cpu.hh revision 5543
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322325SN/A#ifndef __CPU_O3_CPU_HH__ 332325SN/A#define __CPU_O3_CPU_HH__ 341060SN/A 351060SN/A#include <iostream> 361060SN/A#include <list> 372292SN/A#include <queue> 382292SN/A#include <set> 391681SN/A#include <vector> 401060SN/A 412980Sgblack@eecs.umich.edu#include "arch/types.hh" 421060SN/A#include "base/statistics.hh" 431060SN/A#include "base/timebuf.hh" 441858SN/A#include "config/full_system.hh" 454598Sbinkertn@umich.edu#include "config/use_checker.hh" 462325SN/A#include "cpu/activity.hh" 471717SN/A#include "cpu/base.hh" 482683Sktlim@umich.edu#include "cpu/simple_thread.hh" 491717SN/A#include "cpu/o3/comm.hh" 501717SN/A#include "cpu/o3/cpu_policy.hh" 512292SN/A#include "cpu/o3/scoreboard.hh" 522292SN/A#include "cpu/o3/thread_state.hh" 532817Sksewell@umich.edu//#include "cpu/o3/thread_context.hh" 541060SN/A#include "sim/process.hh" 551060SN/A 565529Snate@binkert.org#include "params/DerivO3CPU.hh" 575529Snate@binkert.org 582316SN/Atemplate <class> 592316SN/Aclass Checker; 602680Sktlim@umich.educlass ThreadContext; 612817Sksewell@umich.edutemplate <class> 622817Sksewell@umich.educlass O3ThreadContext; 632843Sktlim@umich.edu 642843Sktlim@umich.educlass Checkpoint; 652669Sktlim@umich.educlass MemObject; 661060SN/Aclass Process; 671060SN/A 685529Snate@binkert.orgclass BaseCPUParams; 695529Snate@binkert.org 702733Sktlim@umich.educlass BaseO3CPU : public BaseCPU 711060SN/A{ 721060SN/A //Stuff that's pretty ISA independent will go here. 731060SN/A public: 745529Snate@binkert.org BaseO3CPU(BaseCPUParams *params); 752292SN/A 762292SN/A void regStats(); 772632Sstever@eecs.umich.edu 782817Sksewell@umich.edu /** Sets this CPU's ID. */ 792817Sksewell@umich.edu void setCpuId(int id) { cpu_id = id; } 802817Sksewell@umich.edu 812817Sksewell@umich.edu /** Reads this CPU's ID. */ 822669Sktlim@umich.edu int readCpuId() { return cpu_id; } 831681SN/A 841685SN/A protected: 851681SN/A int cpu_id; 861060SN/A}; 871060SN/A 882348SN/A/** 892348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 902348SN/A * within it, as well as all of the time buffers between stages. The 912348SN/A * tick() function for the CPU is defined here. 922348SN/A */ 931060SN/Atemplate <class Impl> 942733Sktlim@umich.educlass FullO3CPU : public BaseO3CPU 951060SN/A{ 961060SN/A public: 972325SN/A // Typedefs from the Impl here. 981060SN/A typedef typename Impl::CPUPol CPUPolicy; 991061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1004329Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 1011060SN/A 1022292SN/A typedef O3ThreadState<Impl> Thread; 1032292SN/A 1042292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 1052292SN/A 1062817Sksewell@umich.edu friend class O3ThreadContext<Impl>; 1072829Sksewell@umich.edu 1081060SN/A public: 1091060SN/A enum Status { 1101060SN/A Running, 1111060SN/A Idle, 1121060SN/A Halted, 1132307SN/A Blocked, 1142307SN/A SwitchedOut 1151060SN/A }; 1161060SN/A 1173781Sgblack@eecs.umich.edu TheISA::ITB * itb; 1183781Sgblack@eecs.umich.edu TheISA::DTB * dtb; 1193781Sgblack@eecs.umich.edu 1202292SN/A /** Overall CPU status. */ 1211060SN/A Status _status; 1221060SN/A 1232829Sksewell@umich.edu /** Per-thread status in CPU, used for SMT. */ 1242829Sksewell@umich.edu Status _threadStatus[Impl::MaxThreads]; 1252829Sksewell@umich.edu 1261060SN/A private: 1271060SN/A class TickEvent : public Event 1281060SN/A { 1291060SN/A private: 1302292SN/A /** Pointer to the CPU. */ 1311755SN/A FullO3CPU<Impl> *cpu; 1321060SN/A 1331060SN/A public: 1342292SN/A /** Constructs a tick event. */ 1351755SN/A TickEvent(FullO3CPU<Impl> *c); 1362292SN/A 1372292SN/A /** Processes a tick event, calling tick() on the CPU. */ 1381060SN/A void process(); 1392292SN/A /** Returns the description of the tick event. */ 1405336Shines@cs.fsu.edu const char *description() const; 1411060SN/A }; 1421060SN/A 1432292SN/A /** The tick event used for scheduling CPU ticks. */ 1441060SN/A TickEvent tickEvent; 1451060SN/A 1462292SN/A /** Schedule tick event, regardless of its current state. */ 1471060SN/A void scheduleTickEvent(int delay) 1481060SN/A { 1491060SN/A if (tickEvent.squashed()) 1505100Ssaidi@eecs.umich.edu tickEvent.reschedule(nextCycle(curTick + ticks(delay))); 1511060SN/A else if (!tickEvent.scheduled()) 1525100Ssaidi@eecs.umich.edu tickEvent.schedule(nextCycle(curTick + ticks(delay))); 1531060SN/A } 1541060SN/A 1552292SN/A /** Unschedule tick event, regardless of its current state. */ 1561060SN/A void unscheduleTickEvent() 1571060SN/A { 1581060SN/A if (tickEvent.scheduled()) 1591060SN/A tickEvent.squash(); 1601060SN/A } 1611060SN/A 1622829Sksewell@umich.edu class ActivateThreadEvent : public Event 1632829Sksewell@umich.edu { 1642829Sksewell@umich.edu private: 1652829Sksewell@umich.edu /** Number of Thread to Activate */ 1662829Sksewell@umich.edu int tid; 1672829Sksewell@umich.edu 1682829Sksewell@umich.edu /** Pointer to the CPU. */ 1692829Sksewell@umich.edu FullO3CPU<Impl> *cpu; 1702829Sksewell@umich.edu 1712829Sksewell@umich.edu public: 1722829Sksewell@umich.edu /** Constructs the event. */ 1732829Sksewell@umich.edu ActivateThreadEvent(); 1742829Sksewell@umich.edu 1752829Sksewell@umich.edu /** Initialize Event */ 1762829Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 1772829Sksewell@umich.edu 1782829Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 1792829Sksewell@umich.edu void process(); 1802829Sksewell@umich.edu 1812829Sksewell@umich.edu /** Returns the description of the event. */ 1825336Shines@cs.fsu.edu const char *description() const; 1832829Sksewell@umich.edu }; 1842829Sksewell@umich.edu 1852829Sksewell@umich.edu /** Schedule thread to activate , regardless of its current state. */ 1862829Sksewell@umich.edu void scheduleActivateThreadEvent(int tid, int delay) 1872829Sksewell@umich.edu { 1882829Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 1892829Sksewell@umich.edu if (activateThreadEvent[tid].squashed()) 1904030Sktlim@umich.edu activateThreadEvent[tid]. 1915100Ssaidi@eecs.umich.edu reschedule(nextCycle(curTick + ticks(delay))); 1922829Sksewell@umich.edu else if (!activateThreadEvent[tid].scheduled()) 1934030Sktlim@umich.edu activateThreadEvent[tid]. 1945100Ssaidi@eecs.umich.edu schedule(nextCycle(curTick + ticks(delay))); 1952829Sksewell@umich.edu } 1962829Sksewell@umich.edu 1972829Sksewell@umich.edu /** Unschedule actiavte thread event, regardless of its current state. */ 1982829Sksewell@umich.edu void unscheduleActivateThreadEvent(int tid) 1992829Sksewell@umich.edu { 2002829Sksewell@umich.edu if (activateThreadEvent[tid].scheduled()) 2012829Sksewell@umich.edu activateThreadEvent[tid].squash(); 2022829Sksewell@umich.edu } 2032829Sksewell@umich.edu 2042829Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2052829Sksewell@umich.edu ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 2062829Sksewell@umich.edu 2072875Sksewell@umich.edu class DeallocateContextEvent : public Event 2082875Sksewell@umich.edu { 2092875Sksewell@umich.edu private: 2103221Sktlim@umich.edu /** Number of Thread to deactivate */ 2112875Sksewell@umich.edu int tid; 2122875Sksewell@umich.edu 2133221Sktlim@umich.edu /** Should the thread be removed from the CPU? */ 2143221Sktlim@umich.edu bool remove; 2153221Sktlim@umich.edu 2162875Sksewell@umich.edu /** Pointer to the CPU. */ 2172875Sksewell@umich.edu FullO3CPU<Impl> *cpu; 2182875Sksewell@umich.edu 2192875Sksewell@umich.edu public: 2202875Sksewell@umich.edu /** Constructs the event. */ 2212875Sksewell@umich.edu DeallocateContextEvent(); 2222875Sksewell@umich.edu 2232875Sksewell@umich.edu /** Initialize Event */ 2242875Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 2252875Sksewell@umich.edu 2262875Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 2272875Sksewell@umich.edu void process(); 2282875Sksewell@umich.edu 2293221Sktlim@umich.edu /** Sets whether the thread should also be removed from the CPU. */ 2303221Sktlim@umich.edu void setRemove(bool _remove) { remove = _remove; } 2313221Sktlim@umich.edu 2322875Sksewell@umich.edu /** Returns the description of the event. */ 2335336Shines@cs.fsu.edu const char *description() const; 2342875Sksewell@umich.edu }; 2352875Sksewell@umich.edu 2362875Sksewell@umich.edu /** Schedule cpu to deallocate thread context.*/ 2373221Sktlim@umich.edu void scheduleDeallocateContextEvent(int tid, bool remove, int delay) 2382875Sksewell@umich.edu { 2392875Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 2402875Sksewell@umich.edu if (deallocateContextEvent[tid].squashed()) 2414030Sktlim@umich.edu deallocateContextEvent[tid]. 2425100Ssaidi@eecs.umich.edu reschedule(nextCycle(curTick + ticks(delay))); 2432875Sksewell@umich.edu else if (!deallocateContextEvent[tid].scheduled()) 2444030Sktlim@umich.edu deallocateContextEvent[tid]. 2455100Ssaidi@eecs.umich.edu schedule(nextCycle(curTick + ticks(delay))); 2462875Sksewell@umich.edu } 2472875Sksewell@umich.edu 2482875Sksewell@umich.edu /** Unschedule thread deallocation in CPU */ 2492875Sksewell@umich.edu void unscheduleDeallocateContextEvent(int tid) 2502875Sksewell@umich.edu { 2512875Sksewell@umich.edu if (deallocateContextEvent[tid].scheduled()) 2522875Sksewell@umich.edu deallocateContextEvent[tid].squash(); 2532875Sksewell@umich.edu } 2542875Sksewell@umich.edu 2552875Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2562875Sksewell@umich.edu DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 2572875Sksewell@umich.edu 2581060SN/A public: 2592292SN/A /** Constructs a CPU with the given parameters. */ 2605529Snate@binkert.org FullO3CPU(O3CPU *o3_cpu, DerivO3CPUParams *params); 2612292SN/A /** Destructor. */ 2621755SN/A ~FullO3CPU(); 2631060SN/A 2642292SN/A /** Registers statistics. */ 2651684SN/A void fullCPURegStats(); 2661684SN/A 2675358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 2685358Sgblack@eecs.umich.edu { 2695358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2705358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2715358Sgblack@eecs.umich.edu } 2725358Sgblack@eecs.umich.edu 2735358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 2745358Sgblack@eecs.umich.edu { 2755358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2765358Sgblack@eecs.umich.edu } 2775358Sgblack@eecs.umich.edu 2785358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 2795358Sgblack@eecs.umich.edu { 2805358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2815358Sgblack@eecs.umich.edu } 2825358Sgblack@eecs.umich.edu 2834988Sgblack@eecs.umich.edu /** Translates instruction requestion. */ 2844988Sgblack@eecs.umich.edu Fault translateInstReq(RequestPtr &req, Thread *thread) 2854988Sgblack@eecs.umich.edu { 2864988Sgblack@eecs.umich.edu return this->itb->translate(req, thread->getTC()); 2874988Sgblack@eecs.umich.edu } 2884988Sgblack@eecs.umich.edu 2894988Sgblack@eecs.umich.edu /** Translates data read request. */ 2904988Sgblack@eecs.umich.edu Fault translateDataReadReq(RequestPtr &req, Thread *thread) 2914988Sgblack@eecs.umich.edu { 2924988Sgblack@eecs.umich.edu return this->dtb->translate(req, thread->getTC(), false); 2934988Sgblack@eecs.umich.edu } 2944988Sgblack@eecs.umich.edu 2954988Sgblack@eecs.umich.edu /** Translates data write request. */ 2964988Sgblack@eecs.umich.edu Fault translateDataWriteReq(RequestPtr &req, Thread *thread) 2974988Sgblack@eecs.umich.edu { 2984988Sgblack@eecs.umich.edu return this->dtb->translate(req, thread->getTC(), true); 2994988Sgblack@eecs.umich.edu } 3004988Sgblack@eecs.umich.edu 3012871Sktlim@umich.edu /** Returns a specific port. */ 3022871Sktlim@umich.edu Port *getPort(const std::string &if_name, int idx); 3032871Sktlim@umich.edu 3042292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 3052292SN/A * activity to see if the CPU should deschedule itself. 3062292SN/A */ 3071684SN/A void tick(); 3081684SN/A 3092292SN/A /** Initialize the CPU */ 3101060SN/A void init(); 3111060SN/A 3122834Sksewell@umich.edu /** Returns the Number of Active Threads in the CPU */ 3132834Sksewell@umich.edu int numActiveThreads() 3142834Sksewell@umich.edu { return activeThreads.size(); } 3152834Sksewell@umich.edu 3162829Sksewell@umich.edu /** Add Thread to Active Threads List */ 3172875Sksewell@umich.edu void activateThread(unsigned tid); 3182875Sksewell@umich.edu 3192875Sksewell@umich.edu /** Remove Thread from Active Threads List */ 3202875Sksewell@umich.edu void deactivateThread(unsigned tid); 3212829Sksewell@umich.edu 3222292SN/A /** Setup CPU to insert a thread's context */ 3232292SN/A void insertThread(unsigned tid); 3241060SN/A 3252292SN/A /** Remove all of a thread's context from CPU */ 3262292SN/A void removeThread(unsigned tid); 3272292SN/A 3282292SN/A /** Count the Total Instructions Committed in the CPU. */ 3292292SN/A virtual Counter totalInstructions() const 3302292SN/A { 3312292SN/A Counter total(0); 3322292SN/A 3332292SN/A for (int i=0; i < thread.size(); i++) 3342292SN/A total += thread[i]->numInst; 3352292SN/A 3362292SN/A return total; 3372292SN/A } 3382292SN/A 3392292SN/A /** Add Thread to Active Threads List. */ 3402292SN/A void activateContext(int tid, int delay); 3412292SN/A 3422292SN/A /** Remove Thread from Active Threads List */ 3432292SN/A void suspendContext(int tid); 3442292SN/A 3452292SN/A /** Remove Thread from Active Threads List && 3463221Sktlim@umich.edu * Possibly Remove Thread Context from CPU. 3472292SN/A */ 3483221Sktlim@umich.edu bool deallocateContext(int tid, bool remove, int delay = 1); 3492292SN/A 3502292SN/A /** Remove Thread from Active Threads List && 3512292SN/A * Remove Thread Context from CPU. 3522292SN/A */ 3532292SN/A void haltContext(int tid); 3542292SN/A 3552292SN/A /** Activate a Thread When CPU Resources are Available. */ 3562292SN/A void activateWhenReady(int tid); 3572292SN/A 3582292SN/A /** Add or Remove a Thread Context in the CPU. */ 3592292SN/A void doContextSwitch(); 3602292SN/A 3612292SN/A /** Update The Order In Which We Process Threads. */ 3622292SN/A void updateThreadPriority(); 3632292SN/A 3642864Sktlim@umich.edu /** Serialize state. */ 3652864Sktlim@umich.edu virtual void serialize(std::ostream &os); 3662864Sktlim@umich.edu 3672864Sktlim@umich.edu /** Unserialize from a checkpoint. */ 3682864Sktlim@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 3692864Sktlim@umich.edu 3702864Sktlim@umich.edu public: 3712292SN/A /** Executes a syscall on this cycle. 3722292SN/A * --------------------------------------- 3732292SN/A * Note: this is a virtual function. CPU-Specific 3742292SN/A * functionality defined in derived classes 3752292SN/A */ 3762325SN/A virtual void syscall(int tid) { panic("Unimplemented!"); } 3772292SN/A 3782843Sktlim@umich.edu /** Starts draining the CPU's pipeline of all instructions in 3792843Sktlim@umich.edu * order to stop all memory accesses. */ 3802905Sktlim@umich.edu virtual unsigned int drain(Event *drain_event); 3812843Sktlim@umich.edu 3822843Sktlim@umich.edu /** Resumes execution after a drain. */ 3832843Sktlim@umich.edu virtual void resume(); 3842292SN/A 3852348SN/A /** Signals to this CPU that a stage has completed switching out. */ 3862843Sktlim@umich.edu void signalDrained(); 3872843Sktlim@umich.edu 3882843Sktlim@umich.edu /** Switches out this CPU. */ 3892843Sktlim@umich.edu virtual void switchOut(); 3902316SN/A 3912348SN/A /** Takes over from another CPU. */ 3922843Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *oldCPU); 3931060SN/A 3941060SN/A /** Get the current instruction sequence number, and increment it. */ 3952316SN/A InstSeqNum getAndIncrementInstSeq() 3962316SN/A { return globalSeqNum++; } 3971060SN/A 3981858SN/A#if FULL_SYSTEM 3994192Sktlim@umich.edu /** Update the Virt and Phys ports of all ThreadContexts to 4004192Sktlim@umich.edu * reflect change in memory connections. */ 4014192Sktlim@umich.edu void updateMemPorts(); 4024192Sktlim@umich.edu 4031060SN/A /** Check if this address is a valid instruction address. */ 4041060SN/A bool validInstAddr(Addr addr) { return true; } 4051060SN/A 4061060SN/A /** Check if this address is a valid data address. */ 4071060SN/A bool validDataAddr(Addr addr) { return true; } 4081060SN/A 4091060SN/A /** Get instruction asid. */ 4102292SN/A int getInstAsid(unsigned tid) 4112292SN/A { return regFile.miscRegs[tid].getInstAsid(); } 4121060SN/A 4131060SN/A /** Get data asid. */ 4142292SN/A int getDataAsid(unsigned tid) 4152292SN/A { return regFile.miscRegs[tid].getDataAsid(); } 4161060SN/A#else 4172292SN/A /** Get instruction asid. */ 4182292SN/A int getInstAsid(unsigned tid) 4192683Sktlim@umich.edu { return thread[tid]->getInstAsid(); } 4201060SN/A 4212292SN/A /** Get data asid. */ 4222292SN/A int getDataAsid(unsigned tid) 4232683Sktlim@umich.edu { return thread[tid]->getDataAsid(); } 4241060SN/A 4251060SN/A#endif 4261060SN/A 4272348SN/A /** Register accessors. Index refers to the physical register index. */ 4281060SN/A uint64_t readIntReg(int reg_idx); 4291060SN/A 4303781Sgblack@eecs.umich.edu TheISA::FloatReg readFloatReg(int reg_idx); 4311060SN/A 4323781Sgblack@eecs.umich.edu TheISA::FloatReg readFloatReg(int reg_idx, int width); 4331060SN/A 4343781Sgblack@eecs.umich.edu TheISA::FloatRegBits readFloatRegBits(int reg_idx); 4352455SN/A 4363781Sgblack@eecs.umich.edu TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width); 4371060SN/A 4381060SN/A void setIntReg(int reg_idx, uint64_t val); 4391060SN/A 4403781Sgblack@eecs.umich.edu void setFloatReg(int reg_idx, TheISA::FloatReg val); 4411060SN/A 4423781Sgblack@eecs.umich.edu void setFloatReg(int reg_idx, TheISA::FloatReg val, int width); 4431060SN/A 4443781Sgblack@eecs.umich.edu void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 4452455SN/A 4463781Sgblack@eecs.umich.edu void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width); 4471060SN/A 4482292SN/A uint64_t readArchIntReg(int reg_idx, unsigned tid); 4491060SN/A 4502292SN/A float readArchFloatRegSingle(int reg_idx, unsigned tid); 4511060SN/A 4522292SN/A double readArchFloatRegDouble(int reg_idx, unsigned tid); 4532292SN/A 4542292SN/A uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 4552292SN/A 4562348SN/A /** Architectural register accessors. Looks up in the commit 4572348SN/A * rename table to obtain the true physical index of the 4582348SN/A * architected register first, then accesses that physical 4592348SN/A * register. 4602348SN/A */ 4612292SN/A void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 4622292SN/A 4632292SN/A void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 4642292SN/A 4652292SN/A void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 4662292SN/A 4672292SN/A void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 4682292SN/A 4692348SN/A /** Reads the commit PC of a specific thread. */ 4704636Sgblack@eecs.umich.edu Addr readPC(unsigned tid); 4712292SN/A 4722348SN/A /** Sets the commit PC of a specific thread. */ 4732348SN/A void setPC(Addr new_PC, unsigned tid); 4742292SN/A 4754636Sgblack@eecs.umich.edu /** Reads the commit micro PC of a specific thread. */ 4764636Sgblack@eecs.umich.edu Addr readMicroPC(unsigned tid); 4774636Sgblack@eecs.umich.edu 4784636Sgblack@eecs.umich.edu /** Sets the commmit micro PC of a specific thread. */ 4794636Sgblack@eecs.umich.edu void setMicroPC(Addr new_microPC, unsigned tid); 4804636Sgblack@eecs.umich.edu 4812348SN/A /** Reads the next PC of a specific thread. */ 4824636Sgblack@eecs.umich.edu Addr readNextPC(unsigned tid); 4832292SN/A 4842348SN/A /** Sets the next PC of a specific thread. */ 4854636Sgblack@eecs.umich.edu void setNextPC(Addr val, unsigned tid); 4861060SN/A 4872756Sksewell@umich.edu /** Reads the next NPC of a specific thread. */ 4884636Sgblack@eecs.umich.edu Addr readNextNPC(unsigned tid); 4892756Sksewell@umich.edu 4902756Sksewell@umich.edu /** Sets the next NPC of a specific thread. */ 4914636Sgblack@eecs.umich.edu void setNextNPC(Addr val, unsigned tid); 4924636Sgblack@eecs.umich.edu 4934636Sgblack@eecs.umich.edu /** Reads the commit next micro PC of a specific thread. */ 4944636Sgblack@eecs.umich.edu Addr readNextMicroPC(unsigned tid); 4954636Sgblack@eecs.umich.edu 4964636Sgblack@eecs.umich.edu /** Sets the commit next micro PC of a specific thread. */ 4974636Sgblack@eecs.umich.edu void setNextMicroPC(Addr val, unsigned tid); 4982756Sksewell@umich.edu 4991060SN/A /** Function to add instruction onto the head of the list of the 5001060SN/A * instructions. Used when new instructions are fetched. 5011060SN/A */ 5022292SN/A ListIt addInst(DynInstPtr &inst); 5031060SN/A 5041060SN/A /** Function to tell the CPU that an instruction has completed. */ 5052292SN/A void instDone(unsigned tid); 5061060SN/A 5072292SN/A /** Add Instructions to the CPU Remove List*/ 5082292SN/A void addToRemoveList(DynInstPtr &inst); 5091060SN/A 5102325SN/A /** Remove an instruction from the front end of the list. There's 5112325SN/A * no restriction on location of the instruction. 5121060SN/A */ 5131061SN/A void removeFrontInst(DynInstPtr &inst); 5141060SN/A 5152935Sksewell@umich.edu /** Remove all instructions that are not currently in the ROB. 5162935Sksewell@umich.edu * There's also an option to not squash delay slot instructions.*/ 5174632Sgblack@eecs.umich.edu void removeInstsNotInROB(unsigned tid); 5181060SN/A 5191062SN/A /** Remove all instructions younger than the given sequence number. */ 5202292SN/A void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 5212292SN/A 5222348SN/A /** Removes the instruction pointed to by the iterator. */ 5232292SN/A inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 5242292SN/A 5252348SN/A /** Cleans up all instructions on the remove list. */ 5262292SN/A void cleanUpRemovedInsts(); 5271062SN/A 5282348SN/A /** Debug function to print all instructions on the list. */ 5291060SN/A void dumpInsts(); 5301060SN/A 5311060SN/A public: 5321060SN/A /** List of all the instructions in flight. */ 5332292SN/A std::list<DynInstPtr> instList; 5341060SN/A 5352292SN/A /** List of all the instructions that will be removed at the end of this 5362292SN/A * cycle. 5372292SN/A */ 5382292SN/A std::queue<ListIt> removeList; 5392292SN/A 5402325SN/A#ifdef DEBUG 5412348SN/A /** Debug structure to keep track of the sequence numbers still in 5422348SN/A * flight. 5432348SN/A */ 5442292SN/A std::set<InstSeqNum> snList; 5452325SN/A#endif 5462292SN/A 5472325SN/A /** Records if instructions need to be removed this cycle due to 5482325SN/A * being retired or squashed. 5492292SN/A */ 5502292SN/A bool removeInstsThisCycle; 5512292SN/A 5521060SN/A protected: 5531060SN/A /** The fetch stage. */ 5541060SN/A typename CPUPolicy::Fetch fetch; 5551060SN/A 5561060SN/A /** The decode stage. */ 5571060SN/A typename CPUPolicy::Decode decode; 5581060SN/A 5591060SN/A /** The dispatch stage. */ 5601060SN/A typename CPUPolicy::Rename rename; 5611060SN/A 5621060SN/A /** The issue/execute/writeback stages. */ 5631060SN/A typename CPUPolicy::IEW iew; 5641060SN/A 5651060SN/A /** The commit stage. */ 5661060SN/A typename CPUPolicy::Commit commit; 5671060SN/A 5681060SN/A /** The register file. */ 5691060SN/A typename CPUPolicy::RegFile regFile; 5701060SN/A 5711060SN/A /** The free list. */ 5721060SN/A typename CPUPolicy::FreeList freeList; 5731060SN/A 5741060SN/A /** The rename map. */ 5752292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 5762292SN/A 5772292SN/A /** The commit rename map. */ 5782292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 5791060SN/A 5801060SN/A /** The re-order buffer. */ 5811060SN/A typename CPUPolicy::ROB rob; 5821060SN/A 5832292SN/A /** Active Threads List */ 5842292SN/A std::list<unsigned> activeThreads; 5852292SN/A 5862292SN/A /** Integer Register Scoreboard */ 5872292SN/A Scoreboard scoreboard; 5882292SN/A 5891060SN/A public: 5902292SN/A /** Enum to give each stage a specific index, so when calling 5912292SN/A * activateStage() or deactivateStage(), they can specify which stage 5922292SN/A * is being activated/deactivated. 5932292SN/A */ 5942292SN/A enum StageIdx { 5952292SN/A FetchIdx, 5962292SN/A DecodeIdx, 5972292SN/A RenameIdx, 5982292SN/A IEWIdx, 5992292SN/A CommitIdx, 6002292SN/A NumStages }; 6012292SN/A 6021060SN/A /** Typedefs from the Impl to get the structs that each of the 6031060SN/A * time buffers should use. 6041060SN/A */ 6051061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 6061060SN/A 6071061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 6081060SN/A 6091061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 6101060SN/A 6111061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 6121060SN/A 6131061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 6141060SN/A 6151060SN/A /** The main time buffer to do backwards communication. */ 6161060SN/A TimeBuffer<TimeStruct> timeBuffer; 6171060SN/A 6181060SN/A /** The fetch stage's instruction queue. */ 6191060SN/A TimeBuffer<FetchStruct> fetchQueue; 6201060SN/A 6211060SN/A /** The decode stage's instruction queue. */ 6221060SN/A TimeBuffer<DecodeStruct> decodeQueue; 6231060SN/A 6241060SN/A /** The rename stage's instruction queue. */ 6251060SN/A TimeBuffer<RenameStruct> renameQueue; 6261060SN/A 6271060SN/A /** The IEW stage's instruction queue. */ 6281060SN/A TimeBuffer<IEWStruct> iewQueue; 6291060SN/A 6302348SN/A private: 6312348SN/A /** The activity recorder; used to tell if the CPU has any 6322348SN/A * activity remaining or if it can go to idle and deschedule 6332348SN/A * itself. 6342348SN/A */ 6352325SN/A ActivityRecorder activityRec; 6361060SN/A 6372348SN/A public: 6382348SN/A /** Records that there was time buffer activity this cycle. */ 6392325SN/A void activityThisCycle() { activityRec.activity(); } 6402292SN/A 6412348SN/A /** Changes a stage's status to active within the activity recorder. */ 6422325SN/A void activateStage(const StageIdx idx) 6432325SN/A { activityRec.activateStage(idx); } 6442292SN/A 6452348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 6462325SN/A void deactivateStage(const StageIdx idx) 6472325SN/A { activityRec.deactivateStage(idx); } 6482292SN/A 6492292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 6502292SN/A void wakeCPU(); 6512260SN/A 6522292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 6532292SN/A int getFreeTid(); 6542292SN/A 6552292SN/A public: 6562680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 6572680Sktlim@umich.edu ThreadContext *tcBase(unsigned tid) 6581681SN/A { 6592680Sktlim@umich.edu return thread[tid]->getTC(); 6602190SN/A } 6612190SN/A 6622292SN/A /** The global sequence number counter. */ 6633093Sksewell@umich.edu InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 6641060SN/A 6654598Sbinkertn@umich.edu#if USE_CHECKER 6662348SN/A /** Pointer to the checker, which can dynamically verify 6672348SN/A * instruction results at run time. This can be set to NULL if it 6682348SN/A * is not being used. 6692348SN/A */ 6702316SN/A Checker<DynInstPtr> *checker; 6714598Sbinkertn@umich.edu#endif 6722316SN/A 6731858SN/A#if FULL_SYSTEM 6742292SN/A /** Pointer to the system. */ 6751060SN/A System *system; 6761060SN/A 6772292SN/A /** Pointer to physical memory. */ 6781060SN/A PhysicalMemory *physmem; 6792292SN/A#endif 6801060SN/A 6812843Sktlim@umich.edu /** Event to call process() on once draining has completed. */ 6822843Sktlim@umich.edu Event *drainEvent; 6832843Sktlim@umich.edu 6842843Sktlim@umich.edu /** Counter of how many stages have completed draining. */ 6852843Sktlim@umich.edu int drainCount; 6862316SN/A 6872348SN/A /** Pointers to all of the threads in the CPU. */ 6882292SN/A std::vector<Thread *> thread; 6892260SN/A 6902292SN/A /** Whether or not the CPU should defer its registration. */ 6911060SN/A bool deferRegistration; 6921060SN/A 6932292SN/A /** Is there a context switch pending? */ 6942292SN/A bool contextSwitch; 6951060SN/A 6962292SN/A /** Threads Scheduled to Enter CPU */ 6972292SN/A std::list<int> cpuWaitList; 6982292SN/A 6992292SN/A /** The cycle that the CPU was last running, used for statistics. */ 7002292SN/A Tick lastRunningCycle; 7012292SN/A 7022829Sksewell@umich.edu /** The cycle that the CPU was last activated by a new thread*/ 7032829Sksewell@umich.edu Tick lastActivatedCycle; 7042829Sksewell@umich.edu 7052292SN/A /** Number of Threads CPU can process */ 7062292SN/A unsigned numThreads; 7072292SN/A 7082292SN/A /** Mapping for system thread id to cpu id */ 7092292SN/A std::map<unsigned,unsigned> threadMap; 7102292SN/A 7112292SN/A /** Available thread ids in the cpu*/ 7122292SN/A std::vector<unsigned> tids; 7132292SN/A 7142292SN/A /** Stat for total number of times the CPU is descheduled. */ 7152292SN/A Stats::Scalar<> timesIdled; 7162292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 7172292SN/A Stats::Scalar<> idleCycles; 7182292SN/A /** Stat for the number of committed instructions per thread. */ 7192292SN/A Stats::Vector<> committedInsts; 7202292SN/A /** Stat for the total number of committed instructions. */ 7212292SN/A Stats::Scalar<> totalCommittedInsts; 7222292SN/A /** Stat for the CPI per thread. */ 7232292SN/A Stats::Formula cpi; 7242292SN/A /** Stat for the total CPI. */ 7252292SN/A Stats::Formula totalCpi; 7262292SN/A /** Stat for the IPC per thread. */ 7272292SN/A Stats::Formula ipc; 7282292SN/A /** Stat for the total IPC. */ 7292292SN/A Stats::Formula totalIpc; 7301060SN/A}; 7311060SN/A 7322325SN/A#endif // __CPU_O3_CPU_HH__ 733