cpu.hh revision 4632
12SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292665Ssaidi@eecs.umich.edu * Korey Sewell 302665Ssaidi@eecs.umich.edu */ 312SN/A 322SN/A#ifndef __CPU_O3_CPU_HH__ 332SN/A#define __CPU_O3_CPU_HH__ 342SN/A 352SN/A#include <iostream> 362SN/A#include <list> 373971Sgblack@eecs.umich.edu#include <queue> 3856SN/A#include <set> 3956SN/A#include <vector> 401158SN/A 41146SN/A#include "arch/types.hh" 421858SN/A#include "base/statistics.hh" 432680Sktlim@umich.edu#include "base/timebuf.hh" 442378SN/A#include "config/full_system.hh" 452522SN/A#include "cpu/activity.hh" 462401SN/A#include "cpu/base.hh" 475154Sgblack@eecs.umich.edu#include "cpu/simple_thread.hh" 484762Snate@binkert.org#include "cpu/o3/comm.hh" 495512SMichael.Adler@intel.com#include "cpu/o3/cpu_policy.hh" 50360SN/A#include "cpu/o3/scoreboard.hh" 514434Ssaidi@eecs.umich.edu#include "cpu/o3/thread_state.hh" 52695SN/A//#include "cpu/o3/thread_context.hh" 532093SN/A#include "sim/process.hh" 542378SN/A 552SN/Atemplate <class> 562715Sstever@eecs.umich.educlass Checker; 572715Sstever@eecs.umich.educlass ThreadContext; 582715Sstever@eecs.umich.edutemplate <class> 592715Sstever@eecs.umich.educlass O3ThreadContext; 602715Sstever@eecs.umich.edu 612715Sstever@eecs.umich.educlass Checkpoint; 622715Sstever@eecs.umich.educlass MemObject; 632715Sstever@eecs.umich.educlass Process; 642715Sstever@eecs.umich.edu 655335Shines@cs.fsu.educlass BaseO3CPU : public BaseCPU 665335Shines@cs.fsu.edu{ 674157Sgblack@eecs.umich.edu //Stuff that's pretty ISA independent will go here. 684166Sgblack@eecs.umich.edu public: 692715Sstever@eecs.umich.edu typedef BaseCPU::Params Params; 702715Sstever@eecs.umich.edu 712715Sstever@eecs.umich.edu BaseO3CPU(Params *params); 722715Sstever@eecs.umich.edu 732715Sstever@eecs.umich.edu void regStats(); 742SN/A 752107SN/A /** Sets this CPU's ID. */ 762SN/A void setCpuId(int id) { cpu_id = id; } 772SN/A 782SN/A /** Reads this CPU's ID. */ 792SN/A int readCpuId() { return cpu_id; } 802SN/A 812SN/A protected: 821858SN/A int cpu_id; 83360SN/A}; 842SN/A 852SN/A/** 862SN/A * FullO3CPU class, has each of the stages (fetch through commit) 872SN/A * within it, as well as all of the time buffers between stages. The 882SN/A * tick() function for the CPU is defined here. 895758Shsul@eecs.umich.edu */ 905771Shsul@eecs.umich.edutemplate <class Impl> 915758Shsul@eecs.umich.educlass FullO3CPU : public BaseO3CPU 925758Shsul@eecs.umich.edu{ 935758Shsul@eecs.umich.edu public: 945758Shsul@eecs.umich.edu // Typedefs from the Impl here. 955758Shsul@eecs.umich.edu typedef typename Impl::CPUPol CPUPolicy; 965771Shsul@eecs.umich.edu typedef typename Impl::Params Params; 975771Shsul@eecs.umich.edu typedef typename Impl::DynInstPtr DynInstPtr; 985758Shsul@eecs.umich.edu typedef typename Impl::O3CPU O3CPU; 995154Sgblack@eecs.umich.edu 1005183Ssaidi@eecs.umich.edu typedef O3ThreadState<Impl> Thread; 1015154Sgblack@eecs.umich.edu 1022SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 1035154Sgblack@eecs.umich.edu 1045154Sgblack@eecs.umich.edu friend class O3ThreadContext<Impl>; 1055514SMichael.Adler@intel.com 1065154Sgblack@eecs.umich.edu public: 1075154Sgblack@eecs.umich.edu enum Status { 1085154Sgblack@eecs.umich.edu Running, 1095154Sgblack@eecs.umich.edu Idle, 1105154Sgblack@eecs.umich.edu Halted, 1115154Sgblack@eecs.umich.edu Blocked, 1125154Sgblack@eecs.umich.edu SwitchedOut 1135154Sgblack@eecs.umich.edu }; 1145154Sgblack@eecs.umich.edu 1155154Sgblack@eecs.umich.edu#if FULL_SYSTEM 1165154Sgblack@eecs.umich.edu TheISA::ITB * itb; 1175154Sgblack@eecs.umich.edu TheISA::DTB * dtb; 1185154Sgblack@eecs.umich.edu#endif 1195154Sgblack@eecs.umich.edu 1205154Sgblack@eecs.umich.edu /** Overall CPU status. */ 1215154Sgblack@eecs.umich.edu Status _status; 1225154Sgblack@eecs.umich.edu 1235154Sgblack@eecs.umich.edu /** Per-thread status in CPU, used for SMT. */ 1245154Sgblack@eecs.umich.edu Status _threadStatus[Impl::MaxThreads]; 1255154Sgblack@eecs.umich.edu 1265514SMichael.Adler@intel.com private: 1275514SMichael.Adler@intel.com class TickEvent : public Event 1285514SMichael.Adler@intel.com { 1295514SMichael.Adler@intel.com private: 1305514SMichael.Adler@intel.com /** Pointer to the CPU. */ 1315514SMichael.Adler@intel.com FullO3CPU<Impl> *cpu; 1325514SMichael.Adler@intel.com 1335514SMichael.Adler@intel.com public: 1345514SMichael.Adler@intel.com /** Constructs a tick event. */ 1355514SMichael.Adler@intel.com TickEvent(FullO3CPU<Impl> *c); 1365154Sgblack@eecs.umich.edu 1374997Sgblack@eecs.umich.edu /** Processes a tick event, calling tick() on the CPU. */ 1382SN/A void process(); 1395282Srstrong@cs.ucsd.edu /** Returns the description of the tick event. */ 1405282Srstrong@cs.ucsd.edu const char *description(); 1415282Srstrong@cs.ucsd.edu }; 1425282Srstrong@cs.ucsd.edu 1435282Srstrong@cs.ucsd.edu /** The tick event used for scheduling CPU ticks. */ 1445282Srstrong@cs.ucsd.edu TickEvent tickEvent; 1455282Srstrong@cs.ucsd.edu 1465282Srstrong@cs.ucsd.edu /** Schedule tick event, regardless of its current state. */ 1475282Srstrong@cs.ucsd.edu void scheduleTickEvent(int delay) 1485282Srstrong@cs.ucsd.edu { 1495282Srstrong@cs.ucsd.edu if (tickEvent.squashed()) 1505282Srstrong@cs.ucsd.edu tickEvent.reschedule(nextCycle(curTick + cycles(delay))); 1515282Srstrong@cs.ucsd.edu else if (!tickEvent.scheduled()) 1525282Srstrong@cs.ucsd.edu tickEvent.schedule(nextCycle(curTick + cycles(delay))); 1535282Srstrong@cs.ucsd.edu } 1545282Srstrong@cs.ucsd.edu 1555514SMichael.Adler@intel.com /** Unschedule tick event, regardless of its current state. */ 1565282Srstrong@cs.ucsd.edu void unscheduleTickEvent() 1575282Srstrong@cs.ucsd.edu { 1585282Srstrong@cs.ucsd.edu if (tickEvent.scheduled()) 1595282Srstrong@cs.ucsd.edu tickEvent.squash(); 1602SN/A } 1612SN/A 1622SN/A class ActivateThreadEvent : public Event 1635282Srstrong@cs.ucsd.edu { 1645282Srstrong@cs.ucsd.edu private: 1652SN/A /** Number of Thread to Activate */ 1662SN/A int tid; 1671450SN/A 1681514SN/A /** Pointer to the CPU. */ 1695184Sgblack@eecs.umich.edu FullO3CPU<Impl> *cpu; 1702SN/A 1712SN/A public: 1722SN/A /** Constructs the event. */ 1732378SN/A ActivateThreadEvent(); 1742SN/A 1752SN/A /** Initialize Event */ 1762SN/A void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 177729SN/A 1782SN/A /** Processes the event, calling activateThread() on the CPU. */ 1792SN/A void process(); 1802SN/A 1812SN/A /** Returns the description of the event. */ 1822SN/A const char *description(); 1832SN/A }; 1842SN/A 1852SN/A /** Schedule thread to activate , regardless of its current state. */ 1862SN/A void scheduleActivateThreadEvent(int tid, int delay) 1872SN/A { 1882SN/A // Schedule thread to activate, regardless of its current state. 1892SN/A if (activateThreadEvent[tid].squashed()) 1902SN/A activateThreadEvent[tid]. 1912SN/A reschedule(nextCycle(curTick + cycles(delay))); 1922SN/A else if (!activateThreadEvent[tid].scheduled()) 1932SN/A activateThreadEvent[tid]. 1942SN/A schedule(nextCycle(curTick + cycles(delay))); 1952SN/A } 1962SN/A 1972SN/A /** Unschedule actiavte thread event, regardless of its current state. */ 1982SN/A void unscheduleActivateThreadEvent(int tid) 1992SN/A { 2002SN/A if (activateThreadEvent[tid].scheduled()) 2012SN/A activateThreadEvent[tid].squash(); 2022SN/A } 2032SN/A 2042SN/A /** The tick event used for scheduling CPU ticks. */ 2052SN/A ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 2065514SMichael.Adler@intel.com 2072SN/A class DeallocateContextEvent : public Event 2082SN/A { 209