cpu.hh revision 2864
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322325SN/A#ifndef __CPU_O3_CPU_HH__ 332325SN/A#define __CPU_O3_CPU_HH__ 341060SN/A 351060SN/A#include <iostream> 361060SN/A#include <list> 372292SN/A#include <queue> 382292SN/A#include <set> 391681SN/A#include <vector> 401060SN/A 412669Sktlim@umich.edu#include "arch/isa_traits.hh" 421060SN/A#include "base/statistics.hh" 431060SN/A#include "base/timebuf.hh" 441858SN/A#include "config/full_system.hh" 452325SN/A#include "cpu/activity.hh" 461717SN/A#include "cpu/base.hh" 472683Sktlim@umich.edu#include "cpu/simple_thread.hh" 481717SN/A#include "cpu/o3/comm.hh" 491717SN/A#include "cpu/o3/cpu_policy.hh" 502292SN/A#include "cpu/o3/scoreboard.hh" 512292SN/A#include "cpu/o3/thread_state.hh" 522817Sksewell@umich.edu//#include "cpu/o3/thread_context.hh" 531060SN/A#include "sim/process.hh" 541060SN/A 552316SN/Atemplate <class> 562316SN/Aclass Checker; 572680Sktlim@umich.educlass ThreadContext; 582817Sksewell@umich.edutemplate <class> 592817Sksewell@umich.educlass O3ThreadContext; 602843Sktlim@umich.edu 612843Sktlim@umich.educlass Checkpoint; 622669Sktlim@umich.educlass MemObject; 631060SN/Aclass Process; 641060SN/A 652733Sktlim@umich.educlass BaseO3CPU : public BaseCPU 661060SN/A{ 671060SN/A //Stuff that's pretty ISA independent will go here. 681060SN/A public: 691464SN/A typedef BaseCPU::Params Params; 701061SN/A 712733Sktlim@umich.edu BaseO3CPU(Params *params); 722292SN/A 732292SN/A void regStats(); 742632Sstever@eecs.umich.edu 752817Sksewell@umich.edu /** Sets this CPU's ID. */ 762817Sksewell@umich.edu void setCpuId(int id) { cpu_id = id; } 772817Sksewell@umich.edu 782817Sksewell@umich.edu /** Reads this CPU's ID. */ 792669Sktlim@umich.edu int readCpuId() { return cpu_id; } 801681SN/A 811685SN/A protected: 821681SN/A int cpu_id; 831060SN/A}; 841060SN/A 852348SN/A/** 862348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 872348SN/A * within it, as well as all of the time buffers between stages. The 882348SN/A * tick() function for the CPU is defined here. 892348SN/A */ 901060SN/Atemplate <class Impl> 912733Sktlim@umich.educlass FullO3CPU : public BaseO3CPU 921060SN/A{ 931060SN/A public: 942669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 952669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 962669Sktlim@umich.edu 972325SN/A // Typedefs from the Impl here. 981060SN/A typedef typename Impl::CPUPol CPUPolicy; 991060SN/A typedef typename Impl::Params Params; 1001061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1011060SN/A 1022292SN/A typedef O3ThreadState<Impl> Thread; 1032292SN/A 1042292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 1052292SN/A 1062817Sksewell@umich.edu friend class O3ThreadContext<Impl>; 1072829Sksewell@umich.edu 1081060SN/A public: 1091060SN/A enum Status { 1101060SN/A Running, 1111060SN/A Idle, 1121060SN/A Halted, 1132307SN/A Blocked, 1142307SN/A SwitchedOut 1151060SN/A }; 1161060SN/A 1172292SN/A /** Overall CPU status. */ 1181060SN/A Status _status; 1191060SN/A 1202829Sksewell@umich.edu /** Per-thread status in CPU, used for SMT. */ 1212829Sksewell@umich.edu Status _threadStatus[Impl::MaxThreads]; 1222829Sksewell@umich.edu 1231060SN/A private: 1241060SN/A class TickEvent : public Event 1251060SN/A { 1261060SN/A private: 1272292SN/A /** Pointer to the CPU. */ 1281755SN/A FullO3CPU<Impl> *cpu; 1291060SN/A 1301060SN/A public: 1312292SN/A /** Constructs a tick event. */ 1321755SN/A TickEvent(FullO3CPU<Impl> *c); 1332292SN/A 1342292SN/A /** Processes a tick event, calling tick() on the CPU. */ 1351060SN/A void process(); 1362292SN/A /** Returns the description of the tick event. */ 1371060SN/A const char *description(); 1381060SN/A }; 1391060SN/A 1402292SN/A /** The tick event used for scheduling CPU ticks. */ 1411060SN/A TickEvent tickEvent; 1421060SN/A 1432292SN/A /** Schedule tick event, regardless of its current state. */ 1441060SN/A void scheduleTickEvent(int delay) 1451060SN/A { 1461060SN/A if (tickEvent.squashed()) 1472307SN/A tickEvent.reschedule(curTick + cycles(delay)); 1481060SN/A else if (!tickEvent.scheduled()) 1492307SN/A tickEvent.schedule(curTick + cycles(delay)); 1501060SN/A } 1511060SN/A 1522292SN/A /** Unschedule tick event, regardless of its current state. */ 1531060SN/A void unscheduleTickEvent() 1541060SN/A { 1551060SN/A if (tickEvent.scheduled()) 1561060SN/A tickEvent.squash(); 1571060SN/A } 1581060SN/A 1592829Sksewell@umich.edu class ActivateThreadEvent : public Event 1602829Sksewell@umich.edu { 1612829Sksewell@umich.edu private: 1622829Sksewell@umich.edu /** Number of Thread to Activate */ 1632829Sksewell@umich.edu int tid; 1642829Sksewell@umich.edu 1652829Sksewell@umich.edu /** Pointer to the CPU. */ 1662829Sksewell@umich.edu FullO3CPU<Impl> *cpu; 1672829Sksewell@umich.edu 1682829Sksewell@umich.edu public: 1692829Sksewell@umich.edu /** Constructs the event. */ 1702829Sksewell@umich.edu ActivateThreadEvent(); 1712829Sksewell@umich.edu 1722829Sksewell@umich.edu /** Initialize Event */ 1732829Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 1742829Sksewell@umich.edu 1752829Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 1762829Sksewell@umich.edu void process(); 1772829Sksewell@umich.edu 1782829Sksewell@umich.edu /** Returns the description of the event. */ 1792829Sksewell@umich.edu const char *description(); 1802829Sksewell@umich.edu }; 1812829Sksewell@umich.edu 1822829Sksewell@umich.edu /** Schedule thread to activate , regardless of its current state. */ 1832829Sksewell@umich.edu void scheduleActivateThreadEvent(int tid, int delay) 1842829Sksewell@umich.edu { 1852829Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 1862829Sksewell@umich.edu if (activateThreadEvent[tid].squashed()) 1872829Sksewell@umich.edu activateThreadEvent[tid].reschedule(curTick + cycles(delay)); 1882829Sksewell@umich.edu else if (!activateThreadEvent[tid].scheduled()) 1892829Sksewell@umich.edu activateThreadEvent[tid].schedule(curTick + cycles(delay)); 1902829Sksewell@umich.edu } 1912829Sksewell@umich.edu 1922829Sksewell@umich.edu /** Unschedule actiavte thread event, regardless of its current state. */ 1932829Sksewell@umich.edu void unscheduleActivateThreadEvent(int tid) 1942829Sksewell@umich.edu { 1952829Sksewell@umich.edu if (activateThreadEvent[tid].scheduled()) 1962829Sksewell@umich.edu activateThreadEvent[tid].squash(); 1972829Sksewell@umich.edu } 1982829Sksewell@umich.edu 1992829Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2002829Sksewell@umich.edu ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 2012829Sksewell@umich.edu 2021060SN/A public: 2032292SN/A /** Constructs a CPU with the given parameters. */ 2042292SN/A FullO3CPU(Params *params); 2052292SN/A /** Destructor. */ 2061755SN/A ~FullO3CPU(); 2071060SN/A 2082292SN/A /** Registers statistics. */ 2091684SN/A void fullCPURegStats(); 2101684SN/A 2112292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 2122292SN/A * activity to see if the CPU should deschedule itself. 2132292SN/A */ 2141684SN/A void tick(); 2151684SN/A 2162292SN/A /** Initialize the CPU */ 2171060SN/A void init(); 2181060SN/A 2192834Sksewell@umich.edu /** Returns the Number of Active Threads in the CPU */ 2202834Sksewell@umich.edu int numActiveThreads() 2212834Sksewell@umich.edu { return activeThreads.size(); } 2222834Sksewell@umich.edu 2232829Sksewell@umich.edu /** Add Thread to Active Threads List */ 2242829Sksewell@umich.edu void activateThread(unsigned int tid); 2252829Sksewell@umich.edu 2262292SN/A /** Setup CPU to insert a thread's context */ 2272292SN/A void insertThread(unsigned tid); 2281060SN/A 2292292SN/A /** Remove all of a thread's context from CPU */ 2302292SN/A void removeThread(unsigned tid); 2312292SN/A 2322292SN/A /** Count the Total Instructions Committed in the CPU. */ 2332292SN/A virtual Counter totalInstructions() const 2342292SN/A { 2352292SN/A Counter total(0); 2362292SN/A 2372292SN/A for (int i=0; i < thread.size(); i++) 2382292SN/A total += thread[i]->numInst; 2392292SN/A 2402292SN/A return total; 2412292SN/A } 2422292SN/A 2432292SN/A /** Add Thread to Active Threads List. */ 2442292SN/A void activateContext(int tid, int delay); 2452292SN/A 2462292SN/A /** Remove Thread from Active Threads List */ 2472292SN/A void suspendContext(int tid); 2482292SN/A 2492292SN/A /** Remove Thread from Active Threads List && 2502292SN/A * Remove Thread Context from CPU. 2512292SN/A */ 2522292SN/A void deallocateContext(int tid); 2532292SN/A 2542292SN/A /** Remove Thread from Active Threads List && 2552292SN/A * Remove Thread Context from CPU. 2562292SN/A */ 2572292SN/A void haltContext(int tid); 2582292SN/A 2592292SN/A /** Activate a Thread When CPU Resources are Available. */ 2602292SN/A void activateWhenReady(int tid); 2612292SN/A 2622292SN/A /** Add or Remove a Thread Context in the CPU. */ 2632292SN/A void doContextSwitch(); 2642292SN/A 2652292SN/A /** Update The Order In Which We Process Threads. */ 2662292SN/A void updateThreadPriority(); 2672292SN/A 2682864Sktlim@umich.edu /** Serialize state. */ 2692864Sktlim@umich.edu virtual void serialize(std::ostream &os); 2702864Sktlim@umich.edu 2712864Sktlim@umich.edu /** Unserialize from a checkpoint. */ 2722864Sktlim@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 2732864Sktlim@umich.edu 2742864Sktlim@umich.edu public: 2752292SN/A /** Executes a syscall on this cycle. 2762292SN/A * --------------------------------------- 2772292SN/A * Note: this is a virtual function. CPU-Specific 2782292SN/A * functionality defined in derived classes 2792292SN/A */ 2802325SN/A virtual void syscall(int tid) { panic("Unimplemented!"); } 2812292SN/A 2822843Sktlim@umich.edu /** Starts draining the CPU's pipeline of all instructions in 2832843Sktlim@umich.edu * order to stop all memory accesses. */ 2842843Sktlim@umich.edu virtual bool drain(Event *drain_event); 2852843Sktlim@umich.edu 2862843Sktlim@umich.edu /** Resumes execution after a drain. */ 2872843Sktlim@umich.edu virtual void resume(); 2882292SN/A 2892348SN/A /** Signals to this CPU that a stage has completed switching out. */ 2902843Sktlim@umich.edu void signalDrained(); 2912843Sktlim@umich.edu 2922843Sktlim@umich.edu /** Switches out this CPU. */ 2932843Sktlim@umich.edu virtual void switchOut(); 2942316SN/A 2952348SN/A /** Takes over from another CPU. */ 2962843Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *oldCPU); 2971060SN/A 2981060SN/A /** Get the current instruction sequence number, and increment it. */ 2992316SN/A InstSeqNum getAndIncrementInstSeq() 3002316SN/A { return globalSeqNum++; } 3011060SN/A 3021858SN/A#if FULL_SYSTEM 3031060SN/A /** Check if this address is a valid instruction address. */ 3041060SN/A bool validInstAddr(Addr addr) { return true; } 3051060SN/A 3061060SN/A /** Check if this address is a valid data address. */ 3071060SN/A bool validDataAddr(Addr addr) { return true; } 3081060SN/A 3091060SN/A /** Get instruction asid. */ 3102292SN/A int getInstAsid(unsigned tid) 3112292SN/A { return regFile.miscRegs[tid].getInstAsid(); } 3121060SN/A 3131060SN/A /** Get data asid. */ 3142292SN/A int getDataAsid(unsigned tid) 3152292SN/A { return regFile.miscRegs[tid].getDataAsid(); } 3161060SN/A#else 3172292SN/A /** Get instruction asid. */ 3182292SN/A int getInstAsid(unsigned tid) 3192683Sktlim@umich.edu { return thread[tid]->getInstAsid(); } 3201060SN/A 3212292SN/A /** Get data asid. */ 3222292SN/A int getDataAsid(unsigned tid) 3232683Sktlim@umich.edu { return thread[tid]->getDataAsid(); } 3241060SN/A 3251060SN/A#endif 3261060SN/A 3272348SN/A /** Register accessors. Index refers to the physical register index. */ 3281060SN/A uint64_t readIntReg(int reg_idx); 3291060SN/A 3302455SN/A FloatReg readFloatReg(int reg_idx); 3311060SN/A 3322455SN/A FloatReg readFloatReg(int reg_idx, int width); 3331060SN/A 3342455SN/A FloatRegBits readFloatRegBits(int reg_idx); 3352455SN/A 3362455SN/A FloatRegBits readFloatRegBits(int reg_idx, int width); 3371060SN/A 3381060SN/A void setIntReg(int reg_idx, uint64_t val); 3391060SN/A 3402669Sktlim@umich.edu void setFloatReg(int reg_idx, FloatReg val); 3411060SN/A 3422455SN/A void setFloatReg(int reg_idx, FloatReg val, int width); 3431060SN/A 3442455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val); 3452455SN/A 3462669Sktlim@umich.edu void setFloatRegBits(int reg_idx, FloatRegBits val, int width); 3471060SN/A 3482292SN/A uint64_t readArchIntReg(int reg_idx, unsigned tid); 3491060SN/A 3502292SN/A float readArchFloatRegSingle(int reg_idx, unsigned tid); 3511060SN/A 3522292SN/A double readArchFloatRegDouble(int reg_idx, unsigned tid); 3532292SN/A 3542292SN/A uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 3552292SN/A 3562348SN/A /** Architectural register accessors. Looks up in the commit 3572348SN/A * rename table to obtain the true physical index of the 3582348SN/A * architected register first, then accesses that physical 3592348SN/A * register. 3602348SN/A */ 3612292SN/A void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 3622292SN/A 3632292SN/A void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 3642292SN/A 3652292SN/A void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 3662292SN/A 3672292SN/A void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 3682292SN/A 3692348SN/A /** Reads the commit PC of a specific thread. */ 3702292SN/A uint64_t readPC(unsigned tid); 3712292SN/A 3722348SN/A /** Sets the commit PC of a specific thread. */ 3732348SN/A void setPC(Addr new_PC, unsigned tid); 3742292SN/A 3752348SN/A /** Reads the next PC of a specific thread. */ 3762292SN/A uint64_t readNextPC(unsigned tid); 3772292SN/A 3782348SN/A /** Sets the next PC of a specific thread. */ 3792348SN/A void setNextPC(uint64_t val, unsigned tid); 3801060SN/A 3812756Sksewell@umich.edu /** Reads the next NPC of a specific thread. */ 3822756Sksewell@umich.edu uint64_t readNextNPC(unsigned tid); 3832756Sksewell@umich.edu 3842756Sksewell@umich.edu /** Sets the next NPC of a specific thread. */ 3852756Sksewell@umich.edu void setNextNPC(uint64_t val, unsigned tid); 3862756Sksewell@umich.edu 3871060SN/A /** Function to add instruction onto the head of the list of the 3881060SN/A * instructions. Used when new instructions are fetched. 3891060SN/A */ 3902292SN/A ListIt addInst(DynInstPtr &inst); 3911060SN/A 3921060SN/A /** Function to tell the CPU that an instruction has completed. */ 3932292SN/A void instDone(unsigned tid); 3941060SN/A 3952292SN/A /** Add Instructions to the CPU Remove List*/ 3962292SN/A void addToRemoveList(DynInstPtr &inst); 3971060SN/A 3982325SN/A /** Remove an instruction from the front end of the list. There's 3992325SN/A * no restriction on location of the instruction. 4001060SN/A */ 4011061SN/A void removeFrontInst(DynInstPtr &inst); 4021060SN/A 4031060SN/A /** Remove all instructions that are not currently in the ROB. */ 4042292SN/A void removeInstsNotInROB(unsigned tid); 4051060SN/A 4061062SN/A /** Remove all instructions younger than the given sequence number. */ 4072292SN/A void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 4082292SN/A 4092348SN/A /** Removes the instruction pointed to by the iterator. */ 4102292SN/A inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 4112292SN/A 4122348SN/A /** Cleans up all instructions on the remove list. */ 4132292SN/A void cleanUpRemovedInsts(); 4141062SN/A 4152348SN/A /** Debug function to print all instructions on the list. */ 4161060SN/A void dumpInsts(); 4171060SN/A 4181060SN/A public: 4191060SN/A /** List of all the instructions in flight. */ 4202292SN/A std::list<DynInstPtr> instList; 4211060SN/A 4222292SN/A /** List of all the instructions that will be removed at the end of this 4232292SN/A * cycle. 4242292SN/A */ 4252292SN/A std::queue<ListIt> removeList; 4262292SN/A 4272325SN/A#ifdef DEBUG 4282348SN/A /** Debug structure to keep track of the sequence numbers still in 4292348SN/A * flight. 4302348SN/A */ 4312292SN/A std::set<InstSeqNum> snList; 4322325SN/A#endif 4332292SN/A 4342325SN/A /** Records if instructions need to be removed this cycle due to 4352325SN/A * being retired or squashed. 4362292SN/A */ 4372292SN/A bool removeInstsThisCycle; 4382292SN/A 4391060SN/A protected: 4401060SN/A /** The fetch stage. */ 4411060SN/A typename CPUPolicy::Fetch fetch; 4421060SN/A 4431060SN/A /** The decode stage. */ 4441060SN/A typename CPUPolicy::Decode decode; 4451060SN/A 4461060SN/A /** The dispatch stage. */ 4471060SN/A typename CPUPolicy::Rename rename; 4481060SN/A 4491060SN/A /** The issue/execute/writeback stages. */ 4501060SN/A typename CPUPolicy::IEW iew; 4511060SN/A 4521060SN/A /** The commit stage. */ 4531060SN/A typename CPUPolicy::Commit commit; 4541060SN/A 4551060SN/A /** The register file. */ 4561060SN/A typename CPUPolicy::RegFile regFile; 4571060SN/A 4581060SN/A /** The free list. */ 4591060SN/A typename CPUPolicy::FreeList freeList; 4601060SN/A 4611060SN/A /** The rename map. */ 4622292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 4632292SN/A 4642292SN/A /** The commit rename map. */ 4652292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 4661060SN/A 4671060SN/A /** The re-order buffer. */ 4681060SN/A typename CPUPolicy::ROB rob; 4691060SN/A 4702292SN/A /** Active Threads List */ 4712292SN/A std::list<unsigned> activeThreads; 4722292SN/A 4732292SN/A /** Integer Register Scoreboard */ 4742292SN/A Scoreboard scoreboard; 4752292SN/A 4761060SN/A public: 4772292SN/A /** Enum to give each stage a specific index, so when calling 4782292SN/A * activateStage() or deactivateStage(), they can specify which stage 4792292SN/A * is being activated/deactivated. 4802292SN/A */ 4812292SN/A enum StageIdx { 4822292SN/A FetchIdx, 4832292SN/A DecodeIdx, 4842292SN/A RenameIdx, 4852292SN/A IEWIdx, 4862292SN/A CommitIdx, 4872292SN/A NumStages }; 4882292SN/A 4891060SN/A /** Typedefs from the Impl to get the structs that each of the 4901060SN/A * time buffers should use. 4911060SN/A */ 4921061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 4931060SN/A 4941061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 4951060SN/A 4961061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 4971060SN/A 4981061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 4991060SN/A 5001061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 5011060SN/A 5021060SN/A /** The main time buffer to do backwards communication. */ 5031060SN/A TimeBuffer<TimeStruct> timeBuffer; 5041060SN/A 5051060SN/A /** The fetch stage's instruction queue. */ 5061060SN/A TimeBuffer<FetchStruct> fetchQueue; 5071060SN/A 5081060SN/A /** The decode stage's instruction queue. */ 5091060SN/A TimeBuffer<DecodeStruct> decodeQueue; 5101060SN/A 5111060SN/A /** The rename stage's instruction queue. */ 5121060SN/A TimeBuffer<RenameStruct> renameQueue; 5131060SN/A 5141060SN/A /** The IEW stage's instruction queue. */ 5151060SN/A TimeBuffer<IEWStruct> iewQueue; 5161060SN/A 5172348SN/A private: 5182348SN/A /** The activity recorder; used to tell if the CPU has any 5192348SN/A * activity remaining or if it can go to idle and deschedule 5202348SN/A * itself. 5212348SN/A */ 5222325SN/A ActivityRecorder activityRec; 5231060SN/A 5242348SN/A public: 5252348SN/A /** Records that there was time buffer activity this cycle. */ 5262325SN/A void activityThisCycle() { activityRec.activity(); } 5272292SN/A 5282348SN/A /** Changes a stage's status to active within the activity recorder. */ 5292325SN/A void activateStage(const StageIdx idx) 5302325SN/A { activityRec.activateStage(idx); } 5312292SN/A 5322348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 5332325SN/A void deactivateStage(const StageIdx idx) 5342325SN/A { activityRec.deactivateStage(idx); } 5352292SN/A 5362292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 5372292SN/A void wakeCPU(); 5382260SN/A 5392292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 5402292SN/A int getFreeTid(); 5412292SN/A 5422292SN/A public: 5432680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 5442680Sktlim@umich.edu ThreadContext *tcBase(unsigned tid) 5451681SN/A { 5462680Sktlim@umich.edu return thread[tid]->getTC(); 5472190SN/A } 5482190SN/A 5492292SN/A /** The global sequence number counter. */ 5501060SN/A InstSeqNum globalSeqNum; 5511060SN/A 5522348SN/A /** Pointer to the checker, which can dynamically verify 5532348SN/A * instruction results at run time. This can be set to NULL if it 5542348SN/A * is not being used. 5552348SN/A */ 5562316SN/A Checker<DynInstPtr> *checker; 5572316SN/A 5581858SN/A#if FULL_SYSTEM 5592292SN/A /** Pointer to the system. */ 5601060SN/A System *system; 5611060SN/A 5622292SN/A /** Pointer to physical memory. */ 5631060SN/A PhysicalMemory *physmem; 5642292SN/A#endif 5651060SN/A 5662316SN/A /** Pointer to memory. */ 5672669Sktlim@umich.edu MemObject *mem; 5681060SN/A 5692843Sktlim@umich.edu /** Event to call process() on once draining has completed. */ 5702843Sktlim@umich.edu Event *drainEvent; 5712843Sktlim@umich.edu 5722843Sktlim@umich.edu /** Counter of how many stages have completed draining. */ 5732843Sktlim@umich.edu int drainCount; 5742316SN/A 5752348SN/A /** Pointers to all of the threads in the CPU. */ 5762292SN/A std::vector<Thread *> thread; 5772260SN/A 5782292SN/A /** Pointer to the icache interface. */ 5791060SN/A MemInterface *icacheInterface; 5802292SN/A /** Pointer to the dcache interface. */ 5811060SN/A MemInterface *dcacheInterface; 5821060SN/A 5832292SN/A /** Whether or not the CPU should defer its registration. */ 5841060SN/A bool deferRegistration; 5851060SN/A 5862292SN/A /** Is there a context switch pending? */ 5872292SN/A bool contextSwitch; 5881060SN/A 5892292SN/A /** Threads Scheduled to Enter CPU */ 5902292SN/A std::list<int> cpuWaitList; 5912292SN/A 5922292SN/A /** The cycle that the CPU was last running, used for statistics. */ 5932292SN/A Tick lastRunningCycle; 5942292SN/A 5952829Sksewell@umich.edu /** The cycle that the CPU was last activated by a new thread*/ 5962829Sksewell@umich.edu Tick lastActivatedCycle; 5972829Sksewell@umich.edu 5982292SN/A /** Number of Threads CPU can process */ 5992292SN/A unsigned numThreads; 6002292SN/A 6012292SN/A /** Mapping for system thread id to cpu id */ 6022292SN/A std::map<unsigned,unsigned> threadMap; 6032292SN/A 6042292SN/A /** Available thread ids in the cpu*/ 6052292SN/A std::vector<unsigned> tids; 6062292SN/A 6072292SN/A /** Stat for total number of times the CPU is descheduled. */ 6082292SN/A Stats::Scalar<> timesIdled; 6092292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 6102292SN/A Stats::Scalar<> idleCycles; 6112292SN/A /** Stat for the number of committed instructions per thread. */ 6122292SN/A Stats::Vector<> committedInsts; 6132292SN/A /** Stat for the total number of committed instructions. */ 6142292SN/A Stats::Scalar<> totalCommittedInsts; 6152292SN/A /** Stat for the CPI per thread. */ 6162292SN/A Stats::Formula cpi; 6172292SN/A /** Stat for the total CPI. */ 6182292SN/A Stats::Formula totalCpi; 6192292SN/A /** Stat for the IPC per thread. */ 6202292SN/A Stats::Formula ipc; 6212292SN/A /** Stat for the total IPC. */ 6222292SN/A Stats::Formula totalIpc; 6231060SN/A}; 6241060SN/A 6252325SN/A#endif // __CPU_O3_CPU_HH__ 626