cpu.hh revision 2840
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322325SN/A#ifndef __CPU_O3_CPU_HH__ 332325SN/A#define __CPU_O3_CPU_HH__ 341060SN/A 351060SN/A#include <iostream> 361060SN/A#include <list> 372292SN/A#include <queue> 382292SN/A#include <set> 391681SN/A#include <vector> 401060SN/A 412669Sktlim@umich.edu#include "arch/isa_traits.hh" 421060SN/A#include "base/statistics.hh" 431060SN/A#include "base/timebuf.hh" 441858SN/A#include "config/full_system.hh" 452325SN/A#include "cpu/activity.hh" 461717SN/A#include "cpu/base.hh" 472683Sktlim@umich.edu#include "cpu/simple_thread.hh" 481717SN/A#include "cpu/o3/comm.hh" 491717SN/A#include "cpu/o3/cpu_policy.hh" 502292SN/A#include "cpu/o3/scoreboard.hh" 512292SN/A#include "cpu/o3/thread_state.hh" 522817Sksewell@umich.edu//#include "cpu/o3/thread_context.hh" 531060SN/A#include "sim/process.hh" 541060SN/A 552316SN/Atemplate <class> 562316SN/Aclass Checker; 572680Sktlim@umich.educlass ThreadContext; 582817Sksewell@umich.edutemplate <class> 592817Sksewell@umich.educlass O3ThreadContext; 602669Sktlim@umich.educlass MemObject; 611060SN/Aclass Process; 621060SN/A 632733Sktlim@umich.educlass BaseO3CPU : public BaseCPU 641060SN/A{ 651060SN/A //Stuff that's pretty ISA independent will go here. 661060SN/A public: 671464SN/A typedef BaseCPU::Params Params; 681061SN/A 692733Sktlim@umich.edu BaseO3CPU(Params *params); 702292SN/A 712292SN/A void regStats(); 722632Sstever@eecs.umich.edu 732817Sksewell@umich.edu /** Sets this CPU's ID. */ 742817Sksewell@umich.edu void setCpuId(int id) { cpu_id = id; } 752817Sksewell@umich.edu 762817Sksewell@umich.edu /** Reads this CPU's ID. */ 772669Sktlim@umich.edu int readCpuId() { return cpu_id; } 781681SN/A 791685SN/A protected: 801681SN/A int cpu_id; 811060SN/A}; 821060SN/A 832348SN/A/** 842348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 852348SN/A * within it, as well as all of the time buffers between stages. The 862348SN/A * tick() function for the CPU is defined here. 872348SN/A */ 881060SN/Atemplate <class Impl> 892733Sktlim@umich.educlass FullO3CPU : public BaseO3CPU 901060SN/A{ 911060SN/A public: 922669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 932669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 942669Sktlim@umich.edu 952325SN/A // Typedefs from the Impl here. 961060SN/A typedef typename Impl::CPUPol CPUPolicy; 971060SN/A typedef typename Impl::Params Params; 981061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 991060SN/A 1002292SN/A typedef O3ThreadState<Impl> Thread; 1012292SN/A 1022292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 1032292SN/A 1042817Sksewell@umich.edu friend class O3ThreadContext<Impl>; 1052829Sksewell@umich.edu 1061060SN/A public: 1071060SN/A enum Status { 1081060SN/A Running, 1091060SN/A Idle, 1101060SN/A Halted, 1112307SN/A Blocked, 1122307SN/A SwitchedOut 1131060SN/A }; 1141060SN/A 1152292SN/A /** Overall CPU status. */ 1161060SN/A Status _status; 1171060SN/A 1182829Sksewell@umich.edu /** Per-thread status in CPU, used for SMT. */ 1192829Sksewell@umich.edu Status _threadStatus[Impl::MaxThreads]; 1202829Sksewell@umich.edu 1211060SN/A private: 1221060SN/A class TickEvent : public Event 1231060SN/A { 1241060SN/A private: 1252292SN/A /** Pointer to the CPU. */ 1261755SN/A FullO3CPU<Impl> *cpu; 1271060SN/A 1281060SN/A public: 1292292SN/A /** Constructs a tick event. */ 1301755SN/A TickEvent(FullO3CPU<Impl> *c); 1312292SN/A 1322292SN/A /** Processes a tick event, calling tick() on the CPU. */ 1331060SN/A void process(); 1342292SN/A /** Returns the description of the tick event. */ 1351060SN/A const char *description(); 1361060SN/A }; 1371060SN/A 1382292SN/A /** The tick event used for scheduling CPU ticks. */ 1391060SN/A TickEvent tickEvent; 1401060SN/A 1412292SN/A /** Schedule tick event, regardless of its current state. */ 1421060SN/A void scheduleTickEvent(int delay) 1431060SN/A { 1441060SN/A if (tickEvent.squashed()) 1452307SN/A tickEvent.reschedule(curTick + cycles(delay)); 1461060SN/A else if (!tickEvent.scheduled()) 1472307SN/A tickEvent.schedule(curTick + cycles(delay)); 1481060SN/A } 1491060SN/A 1502292SN/A /** Unschedule tick event, regardless of its current state. */ 1511060SN/A void unscheduleTickEvent() 1521060SN/A { 1531060SN/A if (tickEvent.scheduled()) 1541060SN/A tickEvent.squash(); 1551060SN/A } 1561060SN/A 1572829Sksewell@umich.edu class ActivateThreadEvent : public Event 1582829Sksewell@umich.edu { 1592829Sksewell@umich.edu private: 1602829Sksewell@umich.edu /** Number of Thread to Activate */ 1612829Sksewell@umich.edu int tid; 1622829Sksewell@umich.edu 1632829Sksewell@umich.edu /** Pointer to the CPU. */ 1642829Sksewell@umich.edu FullO3CPU<Impl> *cpu; 1652829Sksewell@umich.edu 1662829Sksewell@umich.edu public: 1672829Sksewell@umich.edu /** Constructs the event. */ 1682829Sksewell@umich.edu ActivateThreadEvent(); 1692829Sksewell@umich.edu 1702829Sksewell@umich.edu /** Initialize Event */ 1712829Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 1722829Sksewell@umich.edu 1732829Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 1742829Sksewell@umich.edu void process(); 1752829Sksewell@umich.edu 1762829Sksewell@umich.edu /** Returns the description of the event. */ 1772829Sksewell@umich.edu const char *description(); 1782829Sksewell@umich.edu }; 1792829Sksewell@umich.edu 1802829Sksewell@umich.edu /** Schedule thread to activate , regardless of its current state. */ 1812829Sksewell@umich.edu void scheduleActivateThreadEvent(int tid, int delay) 1822829Sksewell@umich.edu { 1832829Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 1842829Sksewell@umich.edu if (activateThreadEvent[tid].squashed()) 1852829Sksewell@umich.edu activateThreadEvent[tid].reschedule(curTick + cycles(delay)); 1862829Sksewell@umich.edu else if (!activateThreadEvent[tid].scheduled()) 1872829Sksewell@umich.edu activateThreadEvent[tid].schedule(curTick + cycles(delay)); 1882829Sksewell@umich.edu } 1892829Sksewell@umich.edu 1902829Sksewell@umich.edu /** Unschedule actiavte thread event, regardless of its current state. */ 1912829Sksewell@umich.edu void unscheduleActivateThreadEvent(int tid) 1922829Sksewell@umich.edu { 1932829Sksewell@umich.edu if (activateThreadEvent[tid].scheduled()) 1942829Sksewell@umich.edu activateThreadEvent[tid].squash(); 1952829Sksewell@umich.edu } 1962829Sksewell@umich.edu 1972829Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 1982829Sksewell@umich.edu ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 1992829Sksewell@umich.edu 2001060SN/A public: 2012292SN/A /** Constructs a CPU with the given parameters. */ 2022292SN/A FullO3CPU(Params *params); 2032292SN/A /** Destructor. */ 2041755SN/A ~FullO3CPU(); 2051060SN/A 2062292SN/A /** Registers statistics. */ 2071684SN/A void fullCPURegStats(); 2081684SN/A 2092292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 2102292SN/A * activity to see if the CPU should deschedule itself. 2112292SN/A */ 2121684SN/A void tick(); 2131684SN/A 2142292SN/A /** Initialize the CPU */ 2151060SN/A void init(); 2161060SN/A 2172834Sksewell@umich.edu /** Returns the Number of Active Threads in the CPU */ 2182834Sksewell@umich.edu int numActiveThreads() 2192834Sksewell@umich.edu { return activeThreads.size(); } 2202834Sksewell@umich.edu 2212829Sksewell@umich.edu /** Add Thread to Active Threads List */ 2222829Sksewell@umich.edu void activateThread(unsigned int tid); 2232829Sksewell@umich.edu 2242292SN/A /** Setup CPU to insert a thread's context */ 2252292SN/A void insertThread(unsigned tid); 2261060SN/A 2272292SN/A /** Remove all of a thread's context from CPU */ 2282292SN/A void removeThread(unsigned tid); 2292292SN/A 2302292SN/A /** Count the Total Instructions Committed in the CPU. */ 2312292SN/A virtual Counter totalInstructions() const 2322292SN/A { 2332292SN/A Counter total(0); 2342292SN/A 2352292SN/A for (int i=0; i < thread.size(); i++) 2362292SN/A total += thread[i]->numInst; 2372292SN/A 2382292SN/A return total; 2392292SN/A } 2402292SN/A 2412292SN/A /** Add Thread to Active Threads List. */ 2422292SN/A void activateContext(int tid, int delay); 2432292SN/A 2442292SN/A /** Remove Thread from Active Threads List */ 2452292SN/A void suspendContext(int tid); 2462292SN/A 2472292SN/A /** Remove Thread from Active Threads List && 2482292SN/A * Remove Thread Context from CPU. 2492292SN/A */ 2502292SN/A void deallocateContext(int tid); 2512292SN/A 2522292SN/A /** Remove Thread from Active Threads List && 2532292SN/A * Remove Thread Context from CPU. 2542292SN/A */ 2552292SN/A void haltContext(int tid); 2562292SN/A 2572292SN/A /** Activate a Thread When CPU Resources are Available. */ 2582292SN/A void activateWhenReady(int tid); 2592292SN/A 2602292SN/A /** Add or Remove a Thread Context in the CPU. */ 2612292SN/A void doContextSwitch(); 2622292SN/A 2632292SN/A /** Update The Order In Which We Process Threads. */ 2642292SN/A void updateThreadPriority(); 2652292SN/A 2662292SN/A /** Executes a syscall on this cycle. 2672292SN/A * --------------------------------------- 2682292SN/A * Note: this is a virtual function. CPU-Specific 2692292SN/A * functionality defined in derived classes 2702292SN/A */ 2712325SN/A virtual void syscall(int tid) { panic("Unimplemented!"); } 2722292SN/A 2732348SN/A /** Switches out this CPU. */ 2742840Sktlim@umich.edu void switchOut(); 2752292SN/A 2762348SN/A /** Signals to this CPU that a stage has completed switching out. */ 2772316SN/A void signalSwitched(); 2782316SN/A 2792348SN/A /** Takes over from another CPU. */ 2801060SN/A void takeOverFrom(BaseCPU *oldCPU); 2811060SN/A 2821060SN/A /** Get the current instruction sequence number, and increment it. */ 2832316SN/A InstSeqNum getAndIncrementInstSeq() 2842316SN/A { return globalSeqNum++; } 2851060SN/A 2861858SN/A#if FULL_SYSTEM 2871060SN/A /** Check if this address is a valid instruction address. */ 2881060SN/A bool validInstAddr(Addr addr) { return true; } 2891060SN/A 2901060SN/A /** Check if this address is a valid data address. */ 2911060SN/A bool validDataAddr(Addr addr) { return true; } 2921060SN/A 2931060SN/A /** Get instruction asid. */ 2942292SN/A int getInstAsid(unsigned tid) 2952292SN/A { return regFile.miscRegs[tid].getInstAsid(); } 2961060SN/A 2971060SN/A /** Get data asid. */ 2982292SN/A int getDataAsid(unsigned tid) 2992292SN/A { return regFile.miscRegs[tid].getDataAsid(); } 3001060SN/A#else 3012292SN/A /** Get instruction asid. */ 3022292SN/A int getInstAsid(unsigned tid) 3032683Sktlim@umich.edu { return thread[tid]->getInstAsid(); } 3041060SN/A 3052292SN/A /** Get data asid. */ 3062292SN/A int getDataAsid(unsigned tid) 3072683Sktlim@umich.edu { return thread[tid]->getDataAsid(); } 3081060SN/A 3091060SN/A#endif 3101060SN/A 3112348SN/A /** Register accessors. Index refers to the physical register index. */ 3121060SN/A uint64_t readIntReg(int reg_idx); 3131060SN/A 3142455SN/A FloatReg readFloatReg(int reg_idx); 3151060SN/A 3162455SN/A FloatReg readFloatReg(int reg_idx, int width); 3171060SN/A 3182455SN/A FloatRegBits readFloatRegBits(int reg_idx); 3192455SN/A 3202455SN/A FloatRegBits readFloatRegBits(int reg_idx, int width); 3211060SN/A 3221060SN/A void setIntReg(int reg_idx, uint64_t val); 3231060SN/A 3242669Sktlim@umich.edu void setFloatReg(int reg_idx, FloatReg val); 3251060SN/A 3262455SN/A void setFloatReg(int reg_idx, FloatReg val, int width); 3271060SN/A 3282455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val); 3292455SN/A 3302669Sktlim@umich.edu void setFloatRegBits(int reg_idx, FloatRegBits val, int width); 3311060SN/A 3322292SN/A uint64_t readArchIntReg(int reg_idx, unsigned tid); 3331060SN/A 3342292SN/A float readArchFloatRegSingle(int reg_idx, unsigned tid); 3351060SN/A 3362292SN/A double readArchFloatRegDouble(int reg_idx, unsigned tid); 3372292SN/A 3382292SN/A uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 3392292SN/A 3402348SN/A /** Architectural register accessors. Looks up in the commit 3412348SN/A * rename table to obtain the true physical index of the 3422348SN/A * architected register first, then accesses that physical 3432348SN/A * register. 3442348SN/A */ 3452292SN/A void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 3462292SN/A 3472292SN/A void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 3482292SN/A 3492292SN/A void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 3502292SN/A 3512292SN/A void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 3522292SN/A 3532348SN/A /** Reads the commit PC of a specific thread. */ 3542292SN/A uint64_t readPC(unsigned tid); 3552292SN/A 3562348SN/A /** Sets the commit PC of a specific thread. */ 3572348SN/A void setPC(Addr new_PC, unsigned tid); 3582292SN/A 3592348SN/A /** Reads the next PC of a specific thread. */ 3602292SN/A uint64_t readNextPC(unsigned tid); 3612292SN/A 3622348SN/A /** Sets the next PC of a specific thread. */ 3632348SN/A void setNextPC(uint64_t val, unsigned tid); 3641060SN/A 3652756Sksewell@umich.edu /** Reads the next NPC of a specific thread. */ 3662756Sksewell@umich.edu uint64_t readNextNPC(unsigned tid); 3672756Sksewell@umich.edu 3682756Sksewell@umich.edu /** Sets the next NPC of a specific thread. */ 3692756Sksewell@umich.edu void setNextNPC(uint64_t val, unsigned tid); 3702756Sksewell@umich.edu 3711060SN/A /** Function to add instruction onto the head of the list of the 3721060SN/A * instructions. Used when new instructions are fetched. 3731060SN/A */ 3742292SN/A ListIt addInst(DynInstPtr &inst); 3751060SN/A 3761060SN/A /** Function to tell the CPU that an instruction has completed. */ 3772292SN/A void instDone(unsigned tid); 3781060SN/A 3792292SN/A /** Add Instructions to the CPU Remove List*/ 3802292SN/A void addToRemoveList(DynInstPtr &inst); 3811060SN/A 3822325SN/A /** Remove an instruction from the front end of the list. There's 3832325SN/A * no restriction on location of the instruction. 3841060SN/A */ 3851061SN/A void removeFrontInst(DynInstPtr &inst); 3861060SN/A 3871060SN/A /** Remove all instructions that are not currently in the ROB. */ 3882292SN/A void removeInstsNotInROB(unsigned tid); 3891060SN/A 3901062SN/A /** Remove all instructions younger than the given sequence number. */ 3912292SN/A void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 3922292SN/A 3932348SN/A /** Removes the instruction pointed to by the iterator. */ 3942292SN/A inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 3952292SN/A 3962348SN/A /** Cleans up all instructions on the remove list. */ 3972292SN/A void cleanUpRemovedInsts(); 3981062SN/A 3992348SN/A /** Debug function to print all instructions on the list. */ 4001060SN/A void dumpInsts(); 4011060SN/A 4021060SN/A public: 4031060SN/A /** List of all the instructions in flight. */ 4042292SN/A std::list<DynInstPtr> instList; 4051060SN/A 4062292SN/A /** List of all the instructions that will be removed at the end of this 4072292SN/A * cycle. 4082292SN/A */ 4092292SN/A std::queue<ListIt> removeList; 4102292SN/A 4112325SN/A#ifdef DEBUG 4122348SN/A /** Debug structure to keep track of the sequence numbers still in 4132348SN/A * flight. 4142348SN/A */ 4152292SN/A std::set<InstSeqNum> snList; 4162325SN/A#endif 4172292SN/A 4182325SN/A /** Records if instructions need to be removed this cycle due to 4192325SN/A * being retired or squashed. 4202292SN/A */ 4212292SN/A bool removeInstsThisCycle; 4222292SN/A 4231060SN/A protected: 4241060SN/A /** The fetch stage. */ 4251060SN/A typename CPUPolicy::Fetch fetch; 4261060SN/A 4271060SN/A /** The decode stage. */ 4281060SN/A typename CPUPolicy::Decode decode; 4291060SN/A 4301060SN/A /** The dispatch stage. */ 4311060SN/A typename CPUPolicy::Rename rename; 4321060SN/A 4331060SN/A /** The issue/execute/writeback stages. */ 4341060SN/A typename CPUPolicy::IEW iew; 4351060SN/A 4361060SN/A /** The commit stage. */ 4371060SN/A typename CPUPolicy::Commit commit; 4381060SN/A 4391060SN/A /** The register file. */ 4401060SN/A typename CPUPolicy::RegFile regFile; 4411060SN/A 4421060SN/A /** The free list. */ 4431060SN/A typename CPUPolicy::FreeList freeList; 4441060SN/A 4451060SN/A /** The rename map. */ 4462292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 4472292SN/A 4482292SN/A /** The commit rename map. */ 4492292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 4501060SN/A 4511060SN/A /** The re-order buffer. */ 4521060SN/A typename CPUPolicy::ROB rob; 4531060SN/A 4542292SN/A /** Active Threads List */ 4552292SN/A std::list<unsigned> activeThreads; 4562292SN/A 4572292SN/A /** Integer Register Scoreboard */ 4582292SN/A Scoreboard scoreboard; 4592292SN/A 4601060SN/A public: 4612292SN/A /** Enum to give each stage a specific index, so when calling 4622292SN/A * activateStage() or deactivateStage(), they can specify which stage 4632292SN/A * is being activated/deactivated. 4642292SN/A */ 4652292SN/A enum StageIdx { 4662292SN/A FetchIdx, 4672292SN/A DecodeIdx, 4682292SN/A RenameIdx, 4692292SN/A IEWIdx, 4702292SN/A CommitIdx, 4712292SN/A NumStages }; 4722292SN/A 4731060SN/A /** Typedefs from the Impl to get the structs that each of the 4741060SN/A * time buffers should use. 4751060SN/A */ 4761061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 4771060SN/A 4781061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 4791060SN/A 4801061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 4811060SN/A 4821061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 4831060SN/A 4841061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 4851060SN/A 4861060SN/A /** The main time buffer to do backwards communication. */ 4871060SN/A TimeBuffer<TimeStruct> timeBuffer; 4881060SN/A 4891060SN/A /** The fetch stage's instruction queue. */ 4901060SN/A TimeBuffer<FetchStruct> fetchQueue; 4911060SN/A 4921060SN/A /** The decode stage's instruction queue. */ 4931060SN/A TimeBuffer<DecodeStruct> decodeQueue; 4941060SN/A 4951060SN/A /** The rename stage's instruction queue. */ 4961060SN/A TimeBuffer<RenameStruct> renameQueue; 4971060SN/A 4981060SN/A /** The IEW stage's instruction queue. */ 4991060SN/A TimeBuffer<IEWStruct> iewQueue; 5001060SN/A 5012348SN/A private: 5022348SN/A /** The activity recorder; used to tell if the CPU has any 5032348SN/A * activity remaining or if it can go to idle and deschedule 5042348SN/A * itself. 5052348SN/A */ 5062325SN/A ActivityRecorder activityRec; 5071060SN/A 5082348SN/A public: 5092348SN/A /** Records that there was time buffer activity this cycle. */ 5102325SN/A void activityThisCycle() { activityRec.activity(); } 5112292SN/A 5122348SN/A /** Changes a stage's status to active within the activity recorder. */ 5132325SN/A void activateStage(const StageIdx idx) 5142325SN/A { activityRec.activateStage(idx); } 5152292SN/A 5162348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 5172325SN/A void deactivateStage(const StageIdx idx) 5182325SN/A { activityRec.deactivateStage(idx); } 5192292SN/A 5202292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 5212292SN/A void wakeCPU(); 5222260SN/A 5232292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 5242292SN/A int getFreeTid(); 5252292SN/A 5262292SN/A public: 5272680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 5282680Sktlim@umich.edu ThreadContext *tcBase(unsigned tid) 5291681SN/A { 5302680Sktlim@umich.edu return thread[tid]->getTC(); 5312190SN/A } 5322190SN/A 5332292SN/A /** The global sequence number counter. */ 5341060SN/A InstSeqNum globalSeqNum; 5351060SN/A 5362348SN/A /** Pointer to the checker, which can dynamically verify 5372348SN/A * instruction results at run time. This can be set to NULL if it 5382348SN/A * is not being used. 5392348SN/A */ 5402316SN/A Checker<DynInstPtr> *checker; 5412316SN/A 5421858SN/A#if FULL_SYSTEM 5432292SN/A /** Pointer to the system. */ 5441060SN/A System *system; 5451060SN/A 5462292SN/A /** Pointer to physical memory. */ 5471060SN/A PhysicalMemory *physmem; 5482292SN/A#endif 5491060SN/A 5502316SN/A /** Pointer to memory. */ 5512669Sktlim@umich.edu MemObject *mem; 5521060SN/A 5532348SN/A /** Counter of how many stages have completed switching out. */ 5542316SN/A int switchCount; 5552316SN/A 5562348SN/A /** Pointers to all of the threads in the CPU. */ 5572292SN/A std::vector<Thread *> thread; 5582260SN/A 5592292SN/A /** Pointer to the icache interface. */ 5601060SN/A MemInterface *icacheInterface; 5612292SN/A /** Pointer to the dcache interface. */ 5621060SN/A MemInterface *dcacheInterface; 5631060SN/A 5642292SN/A /** Whether or not the CPU should defer its registration. */ 5651060SN/A bool deferRegistration; 5661060SN/A 5672292SN/A /** Is there a context switch pending? */ 5682292SN/A bool contextSwitch; 5691060SN/A 5702292SN/A /** Threads Scheduled to Enter CPU */ 5712292SN/A std::list<int> cpuWaitList; 5722292SN/A 5732292SN/A /** The cycle that the CPU was last running, used for statistics. */ 5742292SN/A Tick lastRunningCycle; 5752292SN/A 5762829Sksewell@umich.edu /** The cycle that the CPU was last activated by a new thread*/ 5772829Sksewell@umich.edu Tick lastActivatedCycle; 5782829Sksewell@umich.edu 5792292SN/A /** Number of Threads CPU can process */ 5802292SN/A unsigned numThreads; 5812292SN/A 5822292SN/A /** Mapping for system thread id to cpu id */ 5832292SN/A std::map<unsigned,unsigned> threadMap; 5842292SN/A 5852292SN/A /** Available thread ids in the cpu*/ 5862292SN/A std::vector<unsigned> tids; 5872292SN/A 5882292SN/A /** Stat for total number of times the CPU is descheduled. */ 5892292SN/A Stats::Scalar<> timesIdled; 5902292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 5912292SN/A Stats::Scalar<> idleCycles; 5922292SN/A /** Stat for the number of committed instructions per thread. */ 5932292SN/A Stats::Vector<> committedInsts; 5942292SN/A /** Stat for the total number of committed instructions. */ 5952292SN/A Stats::Scalar<> totalCommittedInsts; 5962292SN/A /** Stat for the CPI per thread. */ 5972292SN/A Stats::Formula cpi; 5982292SN/A /** Stat for the total CPI. */ 5992292SN/A Stats::Formula totalCpi; 6002292SN/A /** Stat for the IPC per thread. */ 6012292SN/A Stats::Formula ipc; 6022292SN/A /** Stat for the total IPC. */ 6032292SN/A Stats::Formula totalIpc; 6041060SN/A}; 6051060SN/A 6062325SN/A#endif // __CPU_O3_CPU_HH__ 607