cpu.hh revision 2683
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 312325SN/A#ifndef __CPU_O3_CPU_HH__ 322325SN/A#define __CPU_O3_CPU_HH__ 331060SN/A 341060SN/A#include <iostream> 351060SN/A#include <list> 362292SN/A#include <queue> 372292SN/A#include <set> 381681SN/A#include <vector> 391060SN/A 402669Sktlim@umich.edu#include "arch/isa_traits.hh" 411060SN/A#include "base/statistics.hh" 421060SN/A#include "base/timebuf.hh" 431858SN/A#include "config/full_system.hh" 442325SN/A#include "cpu/activity.hh" 451717SN/A#include "cpu/base.hh" 462683Sktlim@umich.edu#include "cpu/simple_thread.hh" 471717SN/A#include "cpu/o3/comm.hh" 481717SN/A#include "cpu/o3/cpu_policy.hh" 492292SN/A#include "cpu/o3/scoreboard.hh" 502292SN/A#include "cpu/o3/thread_state.hh" 511060SN/A#include "sim/process.hh" 521060SN/A 532316SN/Atemplate <class> 542316SN/Aclass Checker; 552680Sktlim@umich.educlass ThreadContext; 562669Sktlim@umich.educlass MemObject; 571060SN/Aclass Process; 581060SN/A 591060SN/Aclass BaseFullCPU : public BaseCPU 601060SN/A{ 611060SN/A //Stuff that's pretty ISA independent will go here. 621060SN/A public: 631464SN/A typedef BaseCPU::Params Params; 641061SN/A 652292SN/A BaseFullCPU(Params *params); 662292SN/A 672292SN/A void regStats(); 682632Sstever@eecs.umich.edu 692669Sktlim@umich.edu int readCpuId() { return cpu_id; } 701681SN/A 711685SN/A protected: 721681SN/A int cpu_id; 731060SN/A}; 741060SN/A 752348SN/A/** 762348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 772348SN/A * within it, as well as all of the time buffers between stages. The 782348SN/A * tick() function for the CPU is defined here. 792348SN/A */ 801060SN/Atemplate <class Impl> 811755SN/Aclass FullO3CPU : public BaseFullCPU 821060SN/A{ 831060SN/A public: 842669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 852669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 862669Sktlim@umich.edu 872325SN/A // Typedefs from the Impl here. 881060SN/A typedef typename Impl::CPUPol CPUPolicy; 891060SN/A typedef typename Impl::Params Params; 901061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 911060SN/A 922292SN/A typedef O3ThreadState<Impl> Thread; 932292SN/A 942292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 952292SN/A 961060SN/A public: 971060SN/A enum Status { 981060SN/A Running, 991060SN/A Idle, 1001060SN/A Halted, 1012307SN/A Blocked, 1022307SN/A SwitchedOut 1031060SN/A }; 1041060SN/A 1052292SN/A /** Overall CPU status. */ 1061060SN/A Status _status; 1071060SN/A 1081060SN/A private: 1091060SN/A class TickEvent : public Event 1101060SN/A { 1111060SN/A private: 1122292SN/A /** Pointer to the CPU. */ 1131755SN/A FullO3CPU<Impl> *cpu; 1141060SN/A 1151060SN/A public: 1162292SN/A /** Constructs a tick event. */ 1171755SN/A TickEvent(FullO3CPU<Impl> *c); 1182292SN/A 1192292SN/A /** Processes a tick event, calling tick() on the CPU. */ 1201060SN/A void process(); 1212292SN/A /** Returns the description of the tick event. */ 1221060SN/A const char *description(); 1231060SN/A }; 1241060SN/A 1252292SN/A /** The tick event used for scheduling CPU ticks. */ 1261060SN/A TickEvent tickEvent; 1271060SN/A 1282292SN/A /** Schedule tick event, regardless of its current state. */ 1291060SN/A void scheduleTickEvent(int delay) 1301060SN/A { 1311060SN/A if (tickEvent.squashed()) 1322307SN/A tickEvent.reschedule(curTick + cycles(delay)); 1331060SN/A else if (!tickEvent.scheduled()) 1342307SN/A tickEvent.schedule(curTick + cycles(delay)); 1351060SN/A } 1361060SN/A 1372292SN/A /** Unschedule tick event, regardless of its current state. */ 1381060SN/A void unscheduleTickEvent() 1391060SN/A { 1401060SN/A if (tickEvent.scheduled()) 1411060SN/A tickEvent.squash(); 1421060SN/A } 1431060SN/A 1441060SN/A public: 1452292SN/A /** Constructs a CPU with the given parameters. */ 1462292SN/A FullO3CPU(Params *params); 1472292SN/A /** Destructor. */ 1481755SN/A ~FullO3CPU(); 1491060SN/A 1502292SN/A /** Registers statistics. */ 1511684SN/A void fullCPURegStats(); 1521684SN/A 1532292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 1542292SN/A * activity to see if the CPU should deschedule itself. 1552292SN/A */ 1561684SN/A void tick(); 1571684SN/A 1582292SN/A /** Initialize the CPU */ 1591060SN/A void init(); 1601060SN/A 1612292SN/A /** Setup CPU to insert a thread's context */ 1622292SN/A void insertThread(unsigned tid); 1631060SN/A 1642292SN/A /** Remove all of a thread's context from CPU */ 1652292SN/A void removeThread(unsigned tid); 1662292SN/A 1672292SN/A /** Count the Total Instructions Committed in the CPU. */ 1682292SN/A virtual Counter totalInstructions() const 1692292SN/A { 1702292SN/A Counter total(0); 1712292SN/A 1722292SN/A for (int i=0; i < thread.size(); i++) 1732292SN/A total += thread[i]->numInst; 1742292SN/A 1752292SN/A return total; 1762292SN/A } 1772292SN/A 1782292SN/A /** Add Thread to Active Threads List. */ 1792292SN/A void activateContext(int tid, int delay); 1802292SN/A 1812292SN/A /** Remove Thread from Active Threads List */ 1822292SN/A void suspendContext(int tid); 1832292SN/A 1842292SN/A /** Remove Thread from Active Threads List && 1852292SN/A * Remove Thread Context from CPU. 1862292SN/A */ 1872292SN/A void deallocateContext(int tid); 1882292SN/A 1892292SN/A /** Remove Thread from Active Threads List && 1902292SN/A * Remove Thread Context from CPU. 1912292SN/A */ 1922292SN/A void haltContext(int tid); 1932292SN/A 1942292SN/A /** Activate a Thread When CPU Resources are Available. */ 1952292SN/A void activateWhenReady(int tid); 1962292SN/A 1972292SN/A /** Add or Remove a Thread Context in the CPU. */ 1982292SN/A void doContextSwitch(); 1992292SN/A 2002292SN/A /** Update The Order In Which We Process Threads. */ 2012292SN/A void updateThreadPriority(); 2022292SN/A 2032292SN/A /** Executes a syscall on this cycle. 2042292SN/A * --------------------------------------- 2052292SN/A * Note: this is a virtual function. CPU-Specific 2062292SN/A * functionality defined in derived classes 2072292SN/A */ 2082325SN/A virtual void syscall(int tid) { panic("Unimplemented!"); } 2092292SN/A 2102348SN/A /** Switches out this CPU. */ 2112307SN/A void switchOut(Sampler *sampler); 2122292SN/A 2132348SN/A /** Signals to this CPU that a stage has completed switching out. */ 2142316SN/A void signalSwitched(); 2152316SN/A 2162348SN/A /** Takes over from another CPU. */ 2171060SN/A void takeOverFrom(BaseCPU *oldCPU); 2181060SN/A 2191060SN/A /** Get the current instruction sequence number, and increment it. */ 2202316SN/A InstSeqNum getAndIncrementInstSeq() 2212316SN/A { return globalSeqNum++; } 2221060SN/A 2231858SN/A#if FULL_SYSTEM 2241060SN/A /** Check if this address is a valid instruction address. */ 2251060SN/A bool validInstAddr(Addr addr) { return true; } 2261060SN/A 2271060SN/A /** Check if this address is a valid data address. */ 2281060SN/A bool validDataAddr(Addr addr) { return true; } 2291060SN/A 2301060SN/A /** Get instruction asid. */ 2312292SN/A int getInstAsid(unsigned tid) 2322292SN/A { return regFile.miscRegs[tid].getInstAsid(); } 2331060SN/A 2341060SN/A /** Get data asid. */ 2352292SN/A int getDataAsid(unsigned tid) 2362292SN/A { return regFile.miscRegs[tid].getDataAsid(); } 2371060SN/A#else 2382292SN/A /** Get instruction asid. */ 2392292SN/A int getInstAsid(unsigned tid) 2402683Sktlim@umich.edu { return thread[tid]->getInstAsid(); } 2411060SN/A 2422292SN/A /** Get data asid. */ 2432292SN/A int getDataAsid(unsigned tid) 2442683Sktlim@umich.edu { return thread[tid]->getDataAsid(); } 2451060SN/A 2461060SN/A#endif 2471060SN/A 2482348SN/A /** Register accessors. Index refers to the physical register index. */ 2491060SN/A uint64_t readIntReg(int reg_idx); 2501060SN/A 2512455SN/A FloatReg readFloatReg(int reg_idx); 2521060SN/A 2532455SN/A FloatReg readFloatReg(int reg_idx, int width); 2541060SN/A 2552455SN/A FloatRegBits readFloatRegBits(int reg_idx); 2562455SN/A 2572455SN/A FloatRegBits readFloatRegBits(int reg_idx, int width); 2581060SN/A 2591060SN/A void setIntReg(int reg_idx, uint64_t val); 2601060SN/A 2612669Sktlim@umich.edu void setFloatReg(int reg_idx, FloatReg val); 2621060SN/A 2632455SN/A void setFloatReg(int reg_idx, FloatReg val, int width); 2641060SN/A 2652455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val); 2662455SN/A 2672669Sktlim@umich.edu void setFloatRegBits(int reg_idx, FloatRegBits val, int width); 2681060SN/A 2692292SN/A uint64_t readArchIntReg(int reg_idx, unsigned tid); 2701060SN/A 2712292SN/A float readArchFloatRegSingle(int reg_idx, unsigned tid); 2721060SN/A 2732292SN/A double readArchFloatRegDouble(int reg_idx, unsigned tid); 2742292SN/A 2752292SN/A uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 2762292SN/A 2772348SN/A /** Architectural register accessors. Looks up in the commit 2782348SN/A * rename table to obtain the true physical index of the 2792348SN/A * architected register first, then accesses that physical 2802348SN/A * register. 2812348SN/A */ 2822292SN/A void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 2832292SN/A 2842292SN/A void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 2852292SN/A 2862292SN/A void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 2872292SN/A 2882292SN/A void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 2892292SN/A 2902348SN/A /** Reads the commit PC of a specific thread. */ 2912292SN/A uint64_t readPC(unsigned tid); 2922292SN/A 2932348SN/A /** Sets the commit PC of a specific thread. */ 2942348SN/A void setPC(Addr new_PC, unsigned tid); 2952292SN/A 2962348SN/A /** Reads the next PC of a specific thread. */ 2972292SN/A uint64_t readNextPC(unsigned tid); 2982292SN/A 2992348SN/A /** Sets the next PC of a specific thread. */ 3002348SN/A void setNextPC(uint64_t val, unsigned tid); 3011060SN/A 3021060SN/A /** Function to add instruction onto the head of the list of the 3031060SN/A * instructions. Used when new instructions are fetched. 3041060SN/A */ 3052292SN/A ListIt addInst(DynInstPtr &inst); 3061060SN/A 3071060SN/A /** Function to tell the CPU that an instruction has completed. */ 3082292SN/A void instDone(unsigned tid); 3091060SN/A 3102292SN/A /** Add Instructions to the CPU Remove List*/ 3112292SN/A void addToRemoveList(DynInstPtr &inst); 3121060SN/A 3132325SN/A /** Remove an instruction from the front end of the list. There's 3142325SN/A * no restriction on location of the instruction. 3151060SN/A */ 3161061SN/A void removeFrontInst(DynInstPtr &inst); 3171060SN/A 3181060SN/A /** Remove all instructions that are not currently in the ROB. */ 3192292SN/A void removeInstsNotInROB(unsigned tid); 3201060SN/A 3211062SN/A /** Remove all instructions younger than the given sequence number. */ 3222292SN/A void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 3232292SN/A 3242348SN/A /** Removes the instruction pointed to by the iterator. */ 3252292SN/A inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 3262292SN/A 3272348SN/A /** Cleans up all instructions on the remove list. */ 3282292SN/A void cleanUpRemovedInsts(); 3291062SN/A 3302348SN/A /** Debug function to print all instructions on the list. */ 3311060SN/A void dumpInsts(); 3321060SN/A 3331060SN/A public: 3341060SN/A /** List of all the instructions in flight. */ 3352292SN/A std::list<DynInstPtr> instList; 3361060SN/A 3372292SN/A /** List of all the instructions that will be removed at the end of this 3382292SN/A * cycle. 3392292SN/A */ 3402292SN/A std::queue<ListIt> removeList; 3412292SN/A 3422325SN/A#ifdef DEBUG 3432348SN/A /** Debug structure to keep track of the sequence numbers still in 3442348SN/A * flight. 3452348SN/A */ 3462292SN/A std::set<InstSeqNum> snList; 3472325SN/A#endif 3482292SN/A 3492325SN/A /** Records if instructions need to be removed this cycle due to 3502325SN/A * being retired or squashed. 3512292SN/A */ 3522292SN/A bool removeInstsThisCycle; 3532292SN/A 3541060SN/A protected: 3551060SN/A /** The fetch stage. */ 3561060SN/A typename CPUPolicy::Fetch fetch; 3571060SN/A 3581060SN/A /** The decode stage. */ 3591060SN/A typename CPUPolicy::Decode decode; 3601060SN/A 3611060SN/A /** The dispatch stage. */ 3621060SN/A typename CPUPolicy::Rename rename; 3631060SN/A 3641060SN/A /** The issue/execute/writeback stages. */ 3651060SN/A typename CPUPolicy::IEW iew; 3661060SN/A 3671060SN/A /** The commit stage. */ 3681060SN/A typename CPUPolicy::Commit commit; 3691060SN/A 3701060SN/A /** The register file. */ 3711060SN/A typename CPUPolicy::RegFile regFile; 3721060SN/A 3731060SN/A /** The free list. */ 3741060SN/A typename CPUPolicy::FreeList freeList; 3751060SN/A 3761060SN/A /** The rename map. */ 3772292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 3782292SN/A 3792292SN/A /** The commit rename map. */ 3802292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 3811060SN/A 3821060SN/A /** The re-order buffer. */ 3831060SN/A typename CPUPolicy::ROB rob; 3841060SN/A 3852292SN/A /** Active Threads List */ 3862292SN/A std::list<unsigned> activeThreads; 3872292SN/A 3882292SN/A /** Integer Register Scoreboard */ 3892292SN/A Scoreboard scoreboard; 3902292SN/A 3911060SN/A public: 3922292SN/A /** Enum to give each stage a specific index, so when calling 3932292SN/A * activateStage() or deactivateStage(), they can specify which stage 3942292SN/A * is being activated/deactivated. 3952292SN/A */ 3962292SN/A enum StageIdx { 3972292SN/A FetchIdx, 3982292SN/A DecodeIdx, 3992292SN/A RenameIdx, 4002292SN/A IEWIdx, 4012292SN/A CommitIdx, 4022292SN/A NumStages }; 4032292SN/A 4041060SN/A /** Typedefs from the Impl to get the structs that each of the 4051060SN/A * time buffers should use. 4061060SN/A */ 4071061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 4081060SN/A 4091061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 4101060SN/A 4111061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 4121060SN/A 4131061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 4141060SN/A 4151061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 4161060SN/A 4171060SN/A /** The main time buffer to do backwards communication. */ 4181060SN/A TimeBuffer<TimeStruct> timeBuffer; 4191060SN/A 4201060SN/A /** The fetch stage's instruction queue. */ 4211060SN/A TimeBuffer<FetchStruct> fetchQueue; 4221060SN/A 4231060SN/A /** The decode stage's instruction queue. */ 4241060SN/A TimeBuffer<DecodeStruct> decodeQueue; 4251060SN/A 4261060SN/A /** The rename stage's instruction queue. */ 4271060SN/A TimeBuffer<RenameStruct> renameQueue; 4281060SN/A 4291060SN/A /** The IEW stage's instruction queue. */ 4301060SN/A TimeBuffer<IEWStruct> iewQueue; 4311060SN/A 4322348SN/A private: 4332348SN/A /** The activity recorder; used to tell if the CPU has any 4342348SN/A * activity remaining or if it can go to idle and deschedule 4352348SN/A * itself. 4362348SN/A */ 4372325SN/A ActivityRecorder activityRec; 4381060SN/A 4392348SN/A public: 4402348SN/A /** Records that there was time buffer activity this cycle. */ 4412325SN/A void activityThisCycle() { activityRec.activity(); } 4422292SN/A 4432348SN/A /** Changes a stage's status to active within the activity recorder. */ 4442325SN/A void activateStage(const StageIdx idx) 4452325SN/A { activityRec.activateStage(idx); } 4462292SN/A 4472348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 4482325SN/A void deactivateStage(const StageIdx idx) 4492325SN/A { activityRec.deactivateStage(idx); } 4502292SN/A 4512292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 4522292SN/A void wakeCPU(); 4532260SN/A 4542292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 4552292SN/A int getFreeTid(); 4562292SN/A 4572292SN/A public: 4582680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 4592680Sktlim@umich.edu ThreadContext *tcBase(unsigned tid) 4601681SN/A { 4612680Sktlim@umich.edu return thread[tid]->getTC(); 4622190SN/A } 4632190SN/A 4642292SN/A /** The global sequence number counter. */ 4651060SN/A InstSeqNum globalSeqNum; 4661060SN/A 4672348SN/A /** Pointer to the checker, which can dynamically verify 4682348SN/A * instruction results at run time. This can be set to NULL if it 4692348SN/A * is not being used. 4702348SN/A */ 4712316SN/A Checker<DynInstPtr> *checker; 4722316SN/A 4731858SN/A#if FULL_SYSTEM 4742292SN/A /** Pointer to the system. */ 4751060SN/A System *system; 4761060SN/A 4772292SN/A /** Pointer to the memory controller. */ 4781060SN/A MemoryController *memCtrl; 4792292SN/A /** Pointer to physical memory. */ 4801060SN/A PhysicalMemory *physmem; 4812292SN/A#endif 4821060SN/A 4832316SN/A /** Pointer to memory. */ 4842669Sktlim@umich.edu MemObject *mem; 4851060SN/A 4862348SN/A /** Pointer to the sampler */ 4872316SN/A Sampler *sampler; 4882316SN/A 4892348SN/A /** Counter of how many stages have completed switching out. */ 4902316SN/A int switchCount; 4912316SN/A 4922348SN/A /** Pointers to all of the threads in the CPU. */ 4932292SN/A std::vector<Thread *> thread; 4942260SN/A 4952292SN/A#if 0 4962292SN/A /** Page table pointer. */ 4972292SN/A PageTable *pTable; 4981060SN/A#endif 4991060SN/A 5002292SN/A /** Pointer to the icache interface. */ 5011060SN/A MemInterface *icacheInterface; 5022292SN/A /** Pointer to the dcache interface. */ 5031060SN/A MemInterface *dcacheInterface; 5041060SN/A 5052292SN/A /** Whether or not the CPU should defer its registration. */ 5061060SN/A bool deferRegistration; 5071060SN/A 5082292SN/A /** Is there a context switch pending? */ 5092292SN/A bool contextSwitch; 5101060SN/A 5112292SN/A /** Threads Scheduled to Enter CPU */ 5122292SN/A std::list<int> cpuWaitList; 5132292SN/A 5142292SN/A /** The cycle that the CPU was last running, used for statistics. */ 5152292SN/A Tick lastRunningCycle; 5162292SN/A 5172292SN/A /** Number of Threads CPU can process */ 5182292SN/A unsigned numThreads; 5192292SN/A 5202292SN/A /** Mapping for system thread id to cpu id */ 5212292SN/A std::map<unsigned,unsigned> threadMap; 5222292SN/A 5232292SN/A /** Available thread ids in the cpu*/ 5242292SN/A std::vector<unsigned> tids; 5252292SN/A 5262292SN/A /** Stat for total number of times the CPU is descheduled. */ 5272292SN/A Stats::Scalar<> timesIdled; 5282292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 5292292SN/A Stats::Scalar<> idleCycles; 5302292SN/A /** Stat for the number of committed instructions per thread. */ 5312292SN/A Stats::Vector<> committedInsts; 5322292SN/A /** Stat for the total number of committed instructions. */ 5332292SN/A Stats::Scalar<> totalCommittedInsts; 5342292SN/A /** Stat for the CPI per thread. */ 5352292SN/A Stats::Formula cpi; 5362292SN/A /** Stat for the total CPI. */ 5372292SN/A Stats::Formula totalCpi; 5382292SN/A /** Stat for the IPC per thread. */ 5392292SN/A Stats::Formula ipc; 5402292SN/A /** Stat for the total IPC. */ 5412292SN/A Stats::Formula totalIpc; 5421060SN/A}; 5431060SN/A 5442325SN/A#endif // __CPU_O3_CPU_HH__ 545