cpu.hh revision 2350
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_O3_CPU_HH__ 30#define __CPU_O3_CPU_HH__ 31 32#include <iostream> 33#include <list> 34#include <queue> 35#include <set> 36#include <vector> 37 38#include "base/statistics.hh" 39#include "base/timebuf.hh" 40#include "config/full_system.hh" 41#include "cpu/activity.hh" 42#include "cpu/base.hh" 43#include "cpu/cpu_exec_context.hh" 44#include "cpu/o3/comm.hh" 45#include "cpu/o3/cpu_policy.hh" 46#include "cpu/o3/scoreboard.hh" 47#include "cpu/o3/thread_state.hh" 48#include "sim/process.hh" 49 50template <class> 51class Checker; 52class ExecContext; 53class MemInterface; 54class Process; 55 56class BaseFullCPU : public BaseCPU 57{ 58 //Stuff that's pretty ISA independent will go here. 59 public: 60 typedef BaseCPU::Params Params; 61 62 BaseFullCPU(Params *params); 63 64 void regStats(); 65 66 protected: 67 int cpu_id; 68}; 69 70/** 71 * FullO3CPU class, has each of the stages (fetch through commit) 72 * within it, as well as all of the time buffers between stages. The 73 * tick() function for the CPU is defined here. 74 */ 75template <class Impl> 76class FullO3CPU : public BaseFullCPU 77{ 78 public: 79 // Typedefs from the Impl here. 80 typedef typename Impl::CPUPol CPUPolicy; 81 typedef typename Impl::Params Params; 82 typedef typename Impl::DynInstPtr DynInstPtr; 83 84 typedef O3ThreadState<Impl> Thread; 85 86 typedef typename std::list<DynInstPtr>::iterator ListIt; 87 88 public: 89 enum Status { 90 Running, 91 Idle, 92 Halted, 93 Blocked, 94 SwitchedOut 95 }; 96 97 /** Overall CPU status. */ 98 Status _status; 99 100 private: 101 class TickEvent : public Event 102 { 103 private: 104 /** Pointer to the CPU. */ 105 FullO3CPU<Impl> *cpu; 106 107 public: 108 /** Constructs a tick event. */ 109 TickEvent(FullO3CPU<Impl> *c); 110 111 /** Processes a tick event, calling tick() on the CPU. */ 112 void process(); 113 /** Returns the description of the tick event. */ 114 const char *description(); 115 }; 116 117 /** The tick event used for scheduling CPU ticks. */ 118 TickEvent tickEvent; 119 120 /** Schedule tick event, regardless of its current state. */ 121 void scheduleTickEvent(int delay) 122 { 123 if (tickEvent.squashed()) 124 tickEvent.reschedule(curTick + cycles(delay)); 125 else if (!tickEvent.scheduled()) 126 tickEvent.schedule(curTick + cycles(delay)); 127 } 128 129 /** Unschedule tick event, regardless of its current state. */ 130 void unscheduleTickEvent() 131 { 132 if (tickEvent.scheduled()) 133 tickEvent.squash(); 134 } 135 136 public: 137 /** Constructs a CPU with the given parameters. */ 138 FullO3CPU(Params *params); 139 /** Destructor. */ 140 ~FullO3CPU(); 141 142 /** Registers statistics. */ 143 void fullCPURegStats(); 144 145 /** Ticks CPU, calling tick() on each stage, and checking the overall 146 * activity to see if the CPU should deschedule itself. 147 */ 148 void tick(); 149 150 /** Initialize the CPU */ 151 void init(); 152 153 /** Setup CPU to insert a thread's context */ 154 void insertThread(unsigned tid); 155 156 /** Remove all of a thread's context from CPU */ 157 void removeThread(unsigned tid); 158 159 /** Count the Total Instructions Committed in the CPU. */ 160 virtual Counter totalInstructions() const 161 { 162 Counter total(0); 163 164 for (int i=0; i < thread.size(); i++) 165 total += thread[i]->numInst; 166 167 return total; 168 } 169 170 /** Add Thread to Active Threads List. */ 171 void activateContext(int tid, int delay); 172 173 /** Remove Thread from Active Threads List */ 174 void suspendContext(int tid); 175 176 /** Remove Thread from Active Threads List && 177 * Remove Thread Context from CPU. 178 */ 179 void deallocateContext(int tid); 180 181 /** Remove Thread from Active Threads List && 182 * Remove Thread Context from CPU. 183 */ 184 void haltContext(int tid); 185 186 /** Activate a Thread When CPU Resources are Available. */ 187 void activateWhenReady(int tid); 188 189 /** Add or Remove a Thread Context in the CPU. */ 190 void doContextSwitch(); 191 192 /** Update The Order In Which We Process Threads. */ 193 void updateThreadPriority(); 194 195 /** Executes a syscall on this cycle. 196 * --------------------------------------- 197 * Note: this is a virtual function. CPU-Specific 198 * functionality defined in derived classes 199 */ 200 virtual void syscall(int tid) { panic("Unimplemented!"); } 201 202 /** Switches out this CPU. */ 203 void switchOut(Sampler *sampler); 204 205 /** Signals to this CPU that a stage has completed switching out. */ 206 void signalSwitched(); 207 208 /** Takes over from another CPU. */ 209 void takeOverFrom(BaseCPU *oldCPU); 210 211 /** Get the current instruction sequence number, and increment it. */ 212 InstSeqNum getAndIncrementInstSeq() 213 { return globalSeqNum++; } 214 215#if FULL_SYSTEM 216 /** Check if this address is a valid instruction address. */ 217 bool validInstAddr(Addr addr) { return true; } 218 219 /** Check if this address is a valid data address. */ 220 bool validDataAddr(Addr addr) { return true; } 221 222 /** Get instruction asid. */ 223 int getInstAsid(unsigned tid) 224 { return regFile.miscRegs[tid].getInstAsid(); } 225 226 /** Get data asid. */ 227 int getDataAsid(unsigned tid) 228 { return regFile.miscRegs[tid].getDataAsid(); } 229#else 230 /** Check if this address is a valid instruction address. */ 231 bool validInstAddr(Addr addr,unsigned tid) 232 { return thread[tid]->validInstAddr(addr); } 233 234 /** Check if this address is a valid data address. */ 235 bool validDataAddr(Addr addr,unsigned tid) 236 { return thread[tid]->validDataAddr(addr); } 237 238 /** Get instruction asid. */ 239 int getInstAsid(unsigned tid) 240 { return thread[tid]->asid; } 241 242 /** Get data asid. */ 243 int getDataAsid(unsigned tid) 244 { return thread[tid]->asid; } 245 246#endif 247 248 /** Register accessors. Index refers to the physical register index. */ 249 uint64_t readIntReg(int reg_idx); 250 251 float readFloatRegSingle(int reg_idx); 252 253 double readFloatRegDouble(int reg_idx); 254 255 uint64_t readFloatRegInt(int reg_idx); 256 257 void setIntReg(int reg_idx, uint64_t val); 258 259 void setFloatRegSingle(int reg_idx, float val); 260 261 void setFloatRegDouble(int reg_idx, double val); 262 263 void setFloatRegInt(int reg_idx, uint64_t val); 264 265 uint64_t readArchIntReg(int reg_idx, unsigned tid); 266 267 float readArchFloatRegSingle(int reg_idx, unsigned tid); 268 269 double readArchFloatRegDouble(int reg_idx, unsigned tid); 270 271 uint64_t readArchFloatRegInt(int reg_idx, unsigned tid); 272 273 /** Architectural register accessors. Looks up in the commit 274 * rename table to obtain the true physical index of the 275 * architected register first, then accesses that physical 276 * register. 277 */ 278 void setArchIntReg(int reg_idx, uint64_t val, unsigned tid); 279 280 void setArchFloatRegSingle(int reg_idx, float val, unsigned tid); 281 282 void setArchFloatRegDouble(int reg_idx, double val, unsigned tid); 283 284 void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid); 285 286 /** Reads the commit PC of a specific thread. */ 287 uint64_t readPC(unsigned tid); 288 289 /** Sets the commit PC of a specific thread. */ 290 void setPC(Addr new_PC, unsigned tid); 291 292 /** Reads the next PC of a specific thread. */ 293 uint64_t readNextPC(unsigned tid); 294 295 /** Sets the next PC of a specific thread. */ 296 void setNextPC(uint64_t val, unsigned tid); 297 298 /** Function to add instruction onto the head of the list of the 299 * instructions. Used when new instructions are fetched. 300 */ 301 ListIt addInst(DynInstPtr &inst); 302 303 /** Function to tell the CPU that an instruction has completed. */ 304 void instDone(unsigned tid); 305 306 /** Add Instructions to the CPU Remove List*/ 307 void addToRemoveList(DynInstPtr &inst); 308 309 /** Remove an instruction from the front end of the list. There's 310 * no restriction on location of the instruction. 311 */ 312 void removeFrontInst(DynInstPtr &inst); 313 314 /** Remove all instructions that are not currently in the ROB. */ 315 void removeInstsNotInROB(unsigned tid); 316 317 /** Remove all instructions younger than the given sequence number. */ 318 void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid); 319 320 /** Removes the instruction pointed to by the iterator. */ 321 inline void squashInstIt(const ListIt &instIt, const unsigned &tid); 322 323 /** Cleans up all instructions on the remove list. */ 324 void cleanUpRemovedInsts(); 325 326 /** Debug function to print all instructions on the list. */ 327 void dumpInsts(); 328 329 public: 330 /** List of all the instructions in flight. */ 331 std::list<DynInstPtr> instList; 332 333 /** List of all the instructions that will be removed at the end of this 334 * cycle. 335 */ 336 std::queue<ListIt> removeList; 337 338#ifdef DEBUG 339 /** Debug structure to keep track of the sequence numbers still in 340 * flight. 341 */ 342 std::set<InstSeqNum> snList; 343#endif 344 345 /** Records if instructions need to be removed this cycle due to 346 * being retired or squashed. 347 */ 348 bool removeInstsThisCycle; 349 350 protected: 351 /** The fetch stage. */ 352 typename CPUPolicy::Fetch fetch; 353 354 /** The decode stage. */ 355 typename CPUPolicy::Decode decode; 356 357 /** The dispatch stage. */ 358 typename CPUPolicy::Rename rename; 359 360 /** The issue/execute/writeback stages. */ 361 typename CPUPolicy::IEW iew; 362 363 /** The commit stage. */ 364 typename CPUPolicy::Commit commit; 365 366 /** The register file. */ 367 typename CPUPolicy::RegFile regFile; 368 369 /** The free list. */ 370 typename CPUPolicy::FreeList freeList; 371 372 /** The rename map. */ 373 typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 374 375 /** The commit rename map. */ 376 typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 377 378 /** The re-order buffer. */ 379 typename CPUPolicy::ROB rob; 380 381 /** Active Threads List */ 382 std::list<unsigned> activeThreads; 383 384 /** Integer Register Scoreboard */ 385 Scoreboard scoreboard; 386 387 public: 388 /** Enum to give each stage a specific index, so when calling 389 * activateStage() or deactivateStage(), they can specify which stage 390 * is being activated/deactivated. 391 */ 392 enum StageIdx { 393 FetchIdx, 394 DecodeIdx, 395 RenameIdx, 396 IEWIdx, 397 CommitIdx, 398 NumStages }; 399 400 /** Typedefs from the Impl to get the structs that each of the 401 * time buffers should use. 402 */ 403 typedef typename CPUPolicy::TimeStruct TimeStruct; 404 405 typedef typename CPUPolicy::FetchStruct FetchStruct; 406 407 typedef typename CPUPolicy::DecodeStruct DecodeStruct; 408 409 typedef typename CPUPolicy::RenameStruct RenameStruct; 410 411 typedef typename CPUPolicy::IEWStruct IEWStruct; 412 413 /** The main time buffer to do backwards communication. */ 414 TimeBuffer<TimeStruct> timeBuffer; 415 416 /** The fetch stage's instruction queue. */ 417 TimeBuffer<FetchStruct> fetchQueue; 418 419 /** The decode stage's instruction queue. */ 420 TimeBuffer<DecodeStruct> decodeQueue; 421 422 /** The rename stage's instruction queue. */ 423 TimeBuffer<RenameStruct> renameQueue; 424 425 /** The IEW stage's instruction queue. */ 426 TimeBuffer<IEWStruct> iewQueue; 427 428 private: 429 /** The activity recorder; used to tell if the CPU has any 430 * activity remaining or if it can go to idle and deschedule 431 * itself. 432 */ 433 ActivityRecorder activityRec; 434 435 public: 436 /** Records that there was time buffer activity this cycle. */ 437 void activityThisCycle() { activityRec.activity(); } 438 439 /** Changes a stage's status to active within the activity recorder. */ 440 void activateStage(const StageIdx idx) 441 { activityRec.activateStage(idx); } 442 443 /** Changes a stage's status to inactive within the activity recorder. */ 444 void deactivateStage(const StageIdx idx) 445 { activityRec.deactivateStage(idx); } 446 447 /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 448 void wakeCPU(); 449 450 /** Gets a free thread id. Use if thread ids change across system. */ 451 int getFreeTid(); 452 453 public: 454 /** Returns a pointer to a thread's exec context. */ 455 ExecContext *xcBase(unsigned tid) 456 { 457 return thread[tid]->getXCProxy(); 458 } 459 460 /** The global sequence number counter. */ 461 InstSeqNum globalSeqNum; 462 463 /** Pointer to the checker, which can dynamically verify 464 * instruction results at run time. This can be set to NULL if it 465 * is not being used. 466 */ 467 Checker<DynInstPtr> *checker; 468 469#if FULL_SYSTEM 470 /** Pointer to the system. */ 471 System *system; 472 473 /** Pointer to the memory controller. */ 474 MemoryController *memCtrl; 475 /** Pointer to physical memory. */ 476 PhysicalMemory *physmem; 477#endif 478 479 /** Pointer to memory. */ 480 FunctionalMemory *mem; 481 482 /** Pointer to the sampler */ 483 Sampler *sampler; 484 485 /** Counter of how many stages have completed switching out. */ 486 int switchCount; 487 488 /** Pointers to all of the threads in the CPU. */ 489 std::vector<Thread *> thread; 490 491#if 0 492 /** Page table pointer. */ 493 PageTable *pTable; 494#endif 495 496 /** Pointer to the icache interface. */ 497 MemInterface *icacheInterface; 498 /** Pointer to the dcache interface. */ 499 MemInterface *dcacheInterface; 500 501 /** Whether or not the CPU should defer its registration. */ 502 bool deferRegistration; 503 504 /** Is there a context switch pending? */ 505 bool contextSwitch; 506 507 /** Threads Scheduled to Enter CPU */ 508 std::list<int> cpuWaitList; 509 510 /** The cycle that the CPU was last running, used for statistics. */ 511 Tick lastRunningCycle; 512 513 /** Number of Threads CPU can process */ 514 unsigned numThreads; 515 516 /** Mapping for system thread id to cpu id */ 517 std::map<unsigned,unsigned> threadMap; 518 519 /** Available thread ids in the cpu*/ 520 std::vector<unsigned> tids; 521 522 /** Stat for total number of times the CPU is descheduled. */ 523 Stats::Scalar<> timesIdled; 524 /** Stat for total number of cycles the CPU spends descheduled. */ 525 Stats::Scalar<> idleCycles; 526 /** Stat for the number of committed instructions per thread. */ 527 Stats::Vector<> committedInsts; 528 /** Stat for the total number of committed instructions. */ 529 Stats::Scalar<> totalCommittedInsts; 530 /** Stat for the CPI per thread. */ 531 Stats::Formula cpi; 532 /** Stat for the total CPI. */ 533 Stats::Formula totalCpi; 534 /** Stat for the IPC per thread. */ 535 Stats::Formula ipc; 536 /** Stat for the total IPC. */ 537 Stats::Formula totalIpc; 538}; 539 540#endif // __CPU_O3_CPU_HH__ 541