cpu.hh revision 1684
11689SN/A//Todo: Add in a lot of the functions that are ISA specific.  Also define
21689SN/A//the functions that currently exist within the base cpu class.  Define
31689SN/A//everything for the simobject stuff so it can be serialized and
41689SN/A//instantiated, add in debugging statements everywhere.  Have CPU schedule
51689SN/A//itself properly.  Constructor.  Derived alpha class.  Threads!
61689SN/A// Avoid running stages and advancing queues if idle/stalled.
71689SN/A
81689SN/A#ifndef __CPU_BETA_CPU_FULL_CPU_HH__
91689SN/A#define __CPU_BETA_CPU_FULL_CPU_HH__
101689SN/A
111689SN/A#include <iostream>
121689SN/A#include <list>
131689SN/A#include <vector>
141689SN/A
151689SN/A#include "base/statistics.hh"
161689SN/A#include "base/timebuf.hh"
171689SN/A#include "cpu/base_cpu.hh"
181689SN/A#include "cpu/beta_cpu/comm.hh"
191689SN/A#include "cpu/beta_cpu/cpu_policy.hh"
201689SN/A#include "cpu/exec_context.hh"
211689SN/A#include "sim/process.hh"
221689SN/A
231689SN/A#ifdef FULL_SYSTEM
241689SN/A#include "arch/alpha/ev5.hh"
251689SN/Ausing namespace EV5;
261689SN/A#endif
272665Ssaidi@eecs.umich.edu
282665Ssaidi@eecs.umich.educlass FunctionalMemory;
292756Sksewell@umich.educlass Process;
301689SN/A
311689SN/Aclass BaseFullCPU : public BaseCPU
322325SN/A{
332325SN/A    //Stuff that's pretty ISA independent will go here.
341060SN/A  public:
351060SN/A    typedef BaseCPU::Params Params;
361060SN/A
372292SN/A#ifdef FULL_SYSTEM
382292SN/A    BaseFullCPU(Params &params);
391681SN/A#else
401060SN/A    BaseFullCPU(Params &params);
412980Sgblack@eecs.umich.edu#endif // FULL_SYSTEM
421060SN/A
431060SN/A  private:
441858SN/A    int cpu_id;
454598Sbinkertn@umich.edu};
462325SN/A
471717SN/Atemplate <class Impl>
482683Sktlim@umich.educlass FullBetaCPU : public BaseFullCPU
491717SN/A{
501717SN/A  public:
512292SN/A    //Put typedefs from the Impl here.
522292SN/A    typedef typename Impl::ISA ISA;
532817Sksewell@umich.edu    typedef typename Impl::CPUPol CPUPolicy;
541060SN/A    typedef typename Impl::Params Params;
551060SN/A    typedef typename Impl::DynInstPtr DynInstPtr;
565529Snate@binkert.org
575529Snate@binkert.org  public:
582316SN/A    enum Status {
592316SN/A        Running,
602680Sktlim@umich.edu        Idle,
612817Sksewell@umich.edu        Halted,
622817Sksewell@umich.edu        Blocked // ?
632843Sktlim@umich.edu    };
642843Sktlim@umich.edu
652669Sktlim@umich.edu    Status _status;
661060SN/A
671060SN/A  private:
685529Snate@binkert.org    class TickEvent : public Event
695529Snate@binkert.org    {
702733Sktlim@umich.edu      private:
711060SN/A        FullBetaCPU<Impl> *cpu;
721060SN/A
731060SN/A      public:
745529Snate@binkert.org        TickEvent(FullBetaCPU<Impl> *c);
752292SN/A        void process();
762292SN/A        const char *description();
771060SN/A    };
781060SN/A
792348SN/A    TickEvent tickEvent;
802348SN/A
812348SN/A    /// Schedule tick event, regardless of its current state.
822348SN/A    void scheduleTickEvent(int delay)
832348SN/A    {
841060SN/A        if (tickEvent.squashed())
852733Sktlim@umich.edu            tickEvent.reschedule(curTick + delay);
861060SN/A        else if (!tickEvent.scheduled())
871060SN/A            tickEvent.schedule(curTick + delay);
882325SN/A    }
891060SN/A
901061SN/A    /// Unschedule tick event, regardless of its current state.
914329Sktlim@umich.edu    void unscheduleTickEvent()
921060SN/A    {
935595Sgblack@eecs.umich.edu        if (tickEvent.scheduled())
942292SN/A            tickEvent.squash();
952292SN/A    }
962292SN/A
972292SN/A  public:
982817Sksewell@umich.edu    FullBetaCPU(Params &params);
992829Sksewell@umich.edu    ~FullBetaCPU();
1001060SN/A
1011060SN/A    void fullCPURegStats();
1021060SN/A
1031060SN/A    void tick();
1041060SN/A
1052307SN/A    void init();
1062307SN/A
1071060SN/A    void activateContext(int thread_num, int delay);
1081060SN/A    void suspendContext(int thread_num);
1096022Sgblack@eecs.umich.edu    void deallocateContext(int thread_num);
1106022Sgblack@eecs.umich.edu    void haltContext(int thread_num);
1113781Sgblack@eecs.umich.edu
1122292SN/A    void switchOut();
1131060SN/A    void takeOverFrom(BaseCPU *oldCPU);
1141060SN/A
1152829Sksewell@umich.edu    /** Get the current instruction sequence number, and increment it. */
1162829Sksewell@umich.edu    InstSeqNum getAndIncrementInstSeq();
1172829Sksewell@umich.edu
1181060SN/A#ifdef FULL_SYSTEM
1191060SN/A    /** Check if this address is a valid instruction address. */
1201060SN/A    bool validInstAddr(Addr addr) { return true; }
1211060SN/A
1222292SN/A    /** Check if this address is a valid data address. */
1231755SN/A    bool validDataAddr(Addr addr) { return true; }
1241060SN/A
1251060SN/A    /** Get instruction asid. */
1262292SN/A    int getInstAsid()
1271755SN/A    { return ITB_ASN_ASN(regFile.getIpr()[ISA::IPR_ITB_ASN]); }
1282292SN/A
1292292SN/A    /** Get data asid. */
1301060SN/A    int getDataAsid()
1312292SN/A    { return DTB_ASN_ASN(regFile.getIpr()[ISA::IPR_DTB_ASN]); }
1325336Shines@cs.fsu.edu#else
1331060SN/A    bool validInstAddr(Addr addr)
1341060SN/A    { return thread[0]->validInstAddr(addr); }
1352292SN/A
1361060SN/A    bool validDataAddr(Addr addr)
1371060SN/A    { return thread[0]->validDataAddr(addr); }
1382292SN/A
1391060SN/A    int getInstAsid() { return thread[0]->asid; }
1401060SN/A    int getDataAsid() { return thread[0]->asid; }
1411060SN/A
1425606Snate@binkert.org#endif
1431060SN/A
1445606Snate@binkert.org    //
1451060SN/A    // New accessors for new decoder.
1461060SN/A    //
1472292SN/A    uint64_t readIntReg(int reg_idx);
1481060SN/A
1491060SN/A    float readFloatRegSingle(int reg_idx);
1501060SN/A
1511060SN/A    double readFloatRegDouble(int reg_idx);
1521060SN/A
1531060SN/A    uint64_t readFloatRegInt(int reg_idx);
1542829Sksewell@umich.edu
1552829Sksewell@umich.edu    void setIntReg(int reg_idx, uint64_t val);
1562829Sksewell@umich.edu
1572829Sksewell@umich.edu    void setFloatRegSingle(int reg_idx, float val);
1582829Sksewell@umich.edu
1592829Sksewell@umich.edu    void setFloatRegDouble(int reg_idx, double val);
1602829Sksewell@umich.edu
1612829Sksewell@umich.edu    void setFloatRegInt(int reg_idx, uint64_t val);
1622829Sksewell@umich.edu
1632829Sksewell@umich.edu    uint64_t readPC();
1642829Sksewell@umich.edu
1652829Sksewell@umich.edu    void setNextPC(uint64_t val);
1662829Sksewell@umich.edu
1672829Sksewell@umich.edu    void setPC(Addr new_PC);
1682829Sksewell@umich.edu
1692829Sksewell@umich.edu    /** Function to add instruction onto the head of the list of the
1702829Sksewell@umich.edu     *  instructions.  Used when new instructions are fetched.
1712829Sksewell@umich.edu     */
1722829Sksewell@umich.edu    void addInst(DynInstPtr &inst);
1732829Sksewell@umich.edu
1745336Shines@cs.fsu.edu    /** Function to tell the CPU that an instruction has completed. */
1752829Sksewell@umich.edu    void instDone();
1762829Sksewell@umich.edu
1772829Sksewell@umich.edu    /** Remove all instructions in back of the given instruction, but leave
1782829Sksewell@umich.edu     *  that instruction in the list.  This is useful in a squash, when there
1792829Sksewell@umich.edu     *  are instructions in this list that don't exist in structures such as
1802829Sksewell@umich.edu     *  the ROB.  The instruction doesn't have to be the last instruction in
1812829Sksewell@umich.edu     *  the list, but will be once this function completes.
1825606Snate@binkert.org     *  @todo: Remove only up until that inst?  Squashed inst is most likely
1835606Snate@binkert.org     *  valid.
1842829Sksewell@umich.edu     */
1855606Snate@binkert.org    void removeBackInst(DynInstPtr &inst);
1865606Snate@binkert.org
1872829Sksewell@umich.edu    /** Remove an instruction from the front of the list.  It is expected
1882829Sksewell@umich.edu     *  that there are no instructions in front of it (that is, none are older
1892829Sksewell@umich.edu     *  than the instruction being removed).  Used when retiring instructions.
1902829Sksewell@umich.edu     *  @todo: Remove the argument to this function, and just have it remove
1912829Sksewell@umich.edu     *  last instruction once it's verified that commit has the same ordering
1922829Sksewell@umich.edu     *  as the instruction list.
1932829Sksewell@umich.edu     */
1942829Sksewell@umich.edu    void removeFrontInst(DynInstPtr &inst);
1952829Sksewell@umich.edu
1962829Sksewell@umich.edu    /** Remove all instructions that are not currently in the ROB. */
1972829Sksewell@umich.edu    void removeInstsNotInROB();
1982829Sksewell@umich.edu
1992875Sksewell@umich.edu    /** Remove all instructions younger than the given sequence number. */
2002875Sksewell@umich.edu    void removeInstsUntil(const InstSeqNum &seq_num);
2012875Sksewell@umich.edu
2023221Sktlim@umich.edu    /** Remove all instructions from the list. */
2032875Sksewell@umich.edu    void removeAllInsts();
2042875Sksewell@umich.edu
2053221Sktlim@umich.edu    void dumpInsts();
2063221Sktlim@umich.edu
2073221Sktlim@umich.edu    /** Basically a wrapper function so that instructions executed at
2082875Sksewell@umich.edu     *  commit can tell the instruction queue that they have completed.
2092875Sksewell@umich.edu     *  Eventually this hack should be removed.
2102875Sksewell@umich.edu     */
2112875Sksewell@umich.edu    void wakeDependents(DynInstPtr &inst);
2122875Sksewell@umich.edu
2132875Sksewell@umich.edu  public:
2142875Sksewell@umich.edu    /** List of all the instructions in flight. */
2152875Sksewell@umich.edu    list<DynInstPtr> instList;
2162875Sksewell@umich.edu
2172875Sksewell@umich.edu    //not sure these should be private.
2182875Sksewell@umich.edu  protected:
2192875Sksewell@umich.edu    /** The fetch stage. */
2202875Sksewell@umich.edu    typename CPUPolicy::Fetch fetch;
2213221Sktlim@umich.edu
2223221Sktlim@umich.edu    /** The fetch stage's status. */
2233221Sktlim@umich.edu    typename CPUPolicy::Fetch::Status fetchStatus;
2242875Sksewell@umich.edu
2255336Shines@cs.fsu.edu    /** The decode stage. */
2262875Sksewell@umich.edu    typename CPUPolicy::Decode decode;
2272875Sksewell@umich.edu
2282875Sksewell@umich.edu    /** The decode stage's status. */
2293221Sktlim@umich.edu    typename CPUPolicy::Decode::Status decodeStatus;
2302875Sksewell@umich.edu
2312875Sksewell@umich.edu    /** The dispatch stage. */
2322875Sksewell@umich.edu    typename CPUPolicy::Rename rename;
2335606Snate@binkert.org
2345606Snate@binkert.org    /** The dispatch stage's status. */
2352875Sksewell@umich.edu    typename CPUPolicy::Rename::Status renameStatus;
2365606Snate@binkert.org
2375606Snate@binkert.org    /** The issue/execute/writeback stages. */
2382875Sksewell@umich.edu    typename CPUPolicy::IEW iew;
2392875Sksewell@umich.edu
2402875Sksewell@umich.edu    /** The issue/execute/writeback stage's status. */
2412875Sksewell@umich.edu    typename CPUPolicy::IEW::Status iewStatus;
2422875Sksewell@umich.edu
2432875Sksewell@umich.edu    /** The commit stage. */
2442875Sksewell@umich.edu    typename CPUPolicy::Commit commit;
2452875Sksewell@umich.edu
2462875Sksewell@umich.edu    /** The fetch stage's status. */
2472875Sksewell@umich.edu    typename CPUPolicy::Commit::Status commitStatus;
2482875Sksewell@umich.edu
2492875Sksewell@umich.edu    //Might want to just pass these objects in to the constructors of the
2501060SN/A    //appropriate stage.  regFile is in iew, freeList in dispatch, renameMap
2512292SN/A    //in dispatch, and the rob in commit.
2525595Sgblack@eecs.umich.edu    /** The register file. */
2532292SN/A    typename CPUPolicy::RegFile regFile;
2541755SN/A
2551060SN/A    /** The free list. */
2562292SN/A    typename CPUPolicy::FreeList freeList;
2575595Sgblack@eecs.umich.edu
2581684SN/A    /** The rename map. */
2595358Sgblack@eecs.umich.edu    typename CPUPolicy::RenameMap renameMap;
2605358Sgblack@eecs.umich.edu
2615358Sgblack@eecs.umich.edu    /** The re-order buffer. */
2625358Sgblack@eecs.umich.edu    typename CPUPolicy::ROB rob;
2635358Sgblack@eecs.umich.edu
2645358Sgblack@eecs.umich.edu  public:
2655358Sgblack@eecs.umich.edu    /** Typedefs from the Impl to get the structs that each of the
2665358Sgblack@eecs.umich.edu     *  time buffers should use.
2675358Sgblack@eecs.umich.edu     */
2685358Sgblack@eecs.umich.edu    typedef typename CPUPolicy::TimeStruct TimeStruct;
2695358Sgblack@eecs.umich.edu
2705358Sgblack@eecs.umich.edu    typedef typename CPUPolicy::FetchStruct FetchStruct;
2715358Sgblack@eecs.umich.edu
2725358Sgblack@eecs.umich.edu    typedef typename CPUPolicy::DecodeStruct DecodeStruct;
2735358Sgblack@eecs.umich.edu
2745358Sgblack@eecs.umich.edu    typedef typename CPUPolicy::RenameStruct RenameStruct;
2752871Sktlim@umich.edu
2762871Sktlim@umich.edu    typedef typename CPUPolicy::IEWStruct IEWStruct;
2772871Sktlim@umich.edu
2782292SN/A    /** The main time buffer to do backwards communication. */
2792292SN/A    TimeBuffer<TimeStruct> timeBuffer;
2802292SN/A
2811684SN/A    /** The fetch stage's instruction queue. */
2821684SN/A    TimeBuffer<FetchStruct> fetchQueue;
2832292SN/A
2841060SN/A    /** The decode stage's instruction queue. */
2851060SN/A    TimeBuffer<DecodeStruct> decodeQueue;
2862834Sksewell@umich.edu
2872834Sksewell@umich.edu    /** The rename stage's instruction queue. */
2882834Sksewell@umich.edu    TimeBuffer<RenameStruct> renameQueue;
2892834Sksewell@umich.edu
2902829Sksewell@umich.edu    /** The IEW stage's instruction queue. */
2912875Sksewell@umich.edu    TimeBuffer<IEWStruct> iewQueue;
2922875Sksewell@umich.edu
2932875Sksewell@umich.edu  public:
2942875Sksewell@umich.edu    /** The temporary exec context to support older accessors. */
2952829Sksewell@umich.edu    ExecContext *xc;
2962292SN/A
2972292SN/A    /** Temporary function to get pointer to exec context. */
2981060SN/A    ExecContext *xcBase()
2992292SN/A    {
3002292SN/A#ifdef FULL_SYSTEM
3012292SN/A        return system->execContexts[0];
3022292SN/A#else
3032292SN/A        return thread[0];
3042292SN/A#endif
3052292SN/A    }
3062292SN/A
3072292SN/A    InstSeqNum globalSeqNum;
3082292SN/A
3092292SN/A#ifdef FULL_SYSTEM
3102292SN/A    System *system;
3112292SN/A
3122292SN/A    MemoryController *memCtrl;
3132292SN/A    PhysicalMemory *physmem;
3142292SN/A
3152292SN/A    AlphaITB *itb;
3162292SN/A    AlphaDTB *dtb;
3172292SN/A
3182292SN/A//    SWContext *swCtx;
3192292SN/A#else
3203221Sktlim@umich.edu    std::vector<ExecContext *> thread;
3212292SN/A#endif
3223221Sktlim@umich.edu
3232292SN/A    FunctionalMemory *mem;
3242292SN/A
3252292SN/A    MemInterface *icacheInterface;
3262292SN/A    MemInterface *dcacheInterface;
3272292SN/A
3282292SN/A    bool deferRegistration;
3292292SN/A
3302292SN/A    Counter numInsts;
3312292SN/A
3322292SN/A    Counter funcExeInst;
3332292SN/A};
3342292SN/A
3352292SN/A#endif
3362292SN/A