cpu.hh revision 1464
11060SN/A//Todo: Add in a lot of the functions that are ISA specific. Also define 22702Sktlim@umich.edu//the functions that currently exist within the base cpu class. Define 31060SN/A//everything for the simobject stuff so it can be serialized and 41060SN/A//instantiated, add in debugging statements everywhere. Have CPU schedule 51060SN/A//itself properly. Constructor. Derived alpha class. Threads! 61060SN/A// Avoid running stages and advancing queues if idle/stalled. 71060SN/A 81060SN/A#ifndef __SIMPLE_FULL_CPU_HH__ 91060SN/A#define __SIMPLE_FULL_CPU_HH__ 101060SN/A 111060SN/A#include <iostream> 121060SN/A#include <list> 131060SN/A 141060SN/A#include "cpu/beta_cpu/comm.hh" 151060SN/A 161060SN/A#include "base/statistics.hh" 171060SN/A#include "base/timebuf.hh" 181060SN/A#include "cpu/base_cpu.hh" 191060SN/A#include "cpu/exec_context.hh" 201060SN/A#include "cpu/beta_cpu/cpu_policy.hh" 211060SN/A#include "sim/process.hh" 221060SN/A 231060SN/Aclass FunctionalMemory; 241060SN/Aclass Process; 251060SN/A 261060SN/Aclass BaseFullCPU : public BaseCPU 272665Ssaidi@eecs.umich.edu{ 282665Ssaidi@eecs.umich.edu //Stuff that's pretty ISA independent will go here. 291060SN/A public: 301060SN/A typedef BaseCPU::Params Params; 311464SN/A 321464SN/A#ifdef FULL_SYSTEM 331060SN/A BaseFullCPU(Params ¶ms); 342731Sktlim@umich.edu#else 352292SN/A BaseFullCPU(Params ¶ms); 361464SN/A#endif // FULL_SYSTEM 371060SN/A}; 382669Sktlim@umich.edu 391060SN/Atemplate <class Impl> 401060SN/Aclass FullBetaCPU : public BaseFullCPU 411858SN/A{ 423770Sgblack@eecs.umich.edu public: 431464SN/A //Put typedefs from the Impl here. 441464SN/A typedef typename Impl::CPUPol CPUPolicy; 452669Sktlim@umich.edu typedef typename Impl::Params Params; 461060SN/A typedef typename Impl::DynInstPtr DynInstPtr; 472669Sktlim@umich.edu 482292SN/A public: 496023Snate@binkert.org enum Status { 501060SN/A Running, 511060SN/A Idle, 521060SN/A Halted, 531060SN/A Blocked // ? 541060SN/A }; 551060SN/A 561061SN/A Status _status; 571061SN/A 581060SN/A private: 591060SN/A class TickEvent : public Event 601061SN/A { 611060SN/A private: 621060SN/A FullBetaCPU<Impl> *cpu; 631060SN/A 642733Sktlim@umich.edu public: 652733Sktlim@umich.edu TickEvent(FullBetaCPU<Impl> *c); 661060SN/A void process(); 672292SN/A const char *description(); 682107SN/A }; 692690Sktlim@umich.edu 702107SN/A TickEvent tickEvent; 712690Sktlim@umich.edu 722690Sktlim@umich.edu /// Schedule tick event, regardless of its current state. 731060SN/A void scheduleTickEvent(int delay) 742292SN/A { 752292SN/A if (tickEvent.squashed()) 762292SN/A tickEvent.reschedule(curTick + delay); 772292SN/A else if (!tickEvent.scheduled()) 782292SN/A tickEvent.schedule(curTick + delay); 792292SN/A } 801060SN/A 815543Ssaidi@eecs.umich.edu /// Unschedule tick event, regardless of its current state. 825543Ssaidi@eecs.umich.edu void unscheduleTickEvent() 831060SN/A { 841060SN/A if (tickEvent.scheduled()) 852292SN/A tickEvent.squash(); 862107SN/A } 871060SN/A 881060SN/A public: 891060SN/A void tick(); 901060SN/A 911060SN/A FullBetaCPU(Params ¶ms); 921060SN/A ~FullBetaCPU(); 932292SN/A 941060SN/A void init(); 951060SN/A 965358Sgblack@eecs.umich.edu void fullCPURegStats(); 975358Sgblack@eecs.umich.edu 985358Sgblack@eecs.umich.edu void activateContext(int thread_num, int delay); 995358Sgblack@eecs.umich.edu void suspendContext(int thread_num); 1005358Sgblack@eecs.umich.edu void deallocateContext(int thread_num); 1015358Sgblack@eecs.umich.edu void haltContext(int thread_num); 1025358Sgblack@eecs.umich.edu 1035358Sgblack@eecs.umich.edu void switchOut(); 1045358Sgblack@eecs.umich.edu void takeOverFrom(BaseCPU *oldCPU); 1055358Sgblack@eecs.umich.edu 1065358Sgblack@eecs.umich.edu /** Get the current instruction sequence number, and increment it. */ 1075358Sgblack@eecs.umich.edu InstSeqNum getAndIncrementInstSeq(); 1085358Sgblack@eecs.umich.edu 1092292SN/A#ifdef FULL_SYSTEM 1102292SN/A /** Check if this address is a valid instruction address. */ 1112292SN/A bool validInstAddr(Addr addr) { return true; } 1122292SN/A 1132292SN/A /** Check if this address is a valid data address. */ 1142292SN/A bool validDataAddr(Addr addr) { return true; } 1152292SN/A 1161060SN/A /** Get instruction asid. */ 1172132SN/A int getInstAsid() { return ITB_ASN_ASN(regs.ipr[ISA::IPR_ITB_ASN]); } 1181060SN/A 1192292SN/A /** Get data asid. */ 1202292SN/A int getDataAsid() { return DTB_ASN_ASN(regs.ipr[ISA::IPR_DTB_ASN]); } 1212292SN/A#else 1222292SN/A bool validInstAddr(Addr addr) 1232292SN/A { return process->validInstAddr(addr); } 1242292SN/A 1252292SN/A bool validDataAddr(Addr addr) 1262292SN/A { return process->validDataAddr(addr); } 1271060SN/A 1282132SN/A int getInstAsid() { return asid; } 1291060SN/A int getDataAsid() { return asid; } 1301060SN/A 1311060SN/A#endif 1321060SN/A 1332132SN/A // 1342132SN/A // New accessors for new decoder. 1351060SN/A // 1361684SN/A uint64_t readIntReg(int reg_idx); 1371060SN/A 1381060SN/A float readFloatRegSingle(int reg_idx); 1391060SN/A 1401060SN/A double readFloatRegDouble(int reg_idx); 1412731Sktlim@umich.edu 1422731Sktlim@umich.edu uint64_t readFloatRegInt(int reg_idx); 1432731Sktlim@umich.edu 1442731Sktlim@umich.edu void setIntReg(int reg_idx, uint64_t val); 1452731Sktlim@umich.edu 1462731Sktlim@umich.edu void setFloatRegSingle(int reg_idx, float val); 1472731Sktlim@umich.edu 1482731Sktlim@umich.edu void setFloatRegDouble(int reg_idx, double val); 1492731Sktlim@umich.edu 1502731Sktlim@umich.edu void setFloatRegInt(int reg_idx, uint64_t val); 1512731Sktlim@umich.edu 1522731Sktlim@umich.edu uint64_t readPC(); 1532731Sktlim@umich.edu 1542731Sktlim@umich.edu void setNextPC(uint64_t val); 1552731Sktlim@umich.edu 1562731Sktlim@umich.edu void setPC(Addr new_PC); 1572731Sktlim@umich.edu 1582731Sktlim@umich.edu /** Function to add instruction onto the head of the list of the 1592731Sktlim@umich.edu * instructions. Used when new instructions are fetched. 1602731Sktlim@umich.edu */ 1612731Sktlim@umich.edu void addInst(DynInstPtr &inst); 1622731Sktlim@umich.edu 1632731Sktlim@umich.edu /** Function to tell the CPU that an instruction has completed. */ 1642731Sktlim@umich.edu void instDone(); 1652731Sktlim@umich.edu 1662292SN/A /** Remove all instructions in back of the given instruction, but leave 1672731Sktlim@umich.edu * that instruction in the list. This is useful in a squash, when there 1682731Sktlim@umich.edu * are instructions in this list that don't exist in structures such as 1691060SN/A * the ROB. The instruction doesn't have to be the last instruction in 1701060SN/A * the list, but will be once this function completes. 1711060SN/A * @todo: Remove only up until that inst? Squashed inst is most likely 1721060SN/A * valid. 1731060SN/A */ 1741060SN/A void removeBackInst(DynInstPtr &inst); 1751060SN/A 1762292SN/A /** Remove an instruction from the front of the list. It is expected 1772292SN/A * that there are no instructions in front of it (that is, none are older 1782292SN/A * than the instruction being removed). Used when retiring instructions. 1792733Sktlim@umich.edu * @todo: Remove the argument to this function, and just have it remove 1802733Sktlim@umich.edu * last instruction once it's verified that commit has the same ordering 1811060SN/A * as the instruction list. 1822680Sktlim@umich.edu */ 1832292SN/A void removeFrontInst(DynInstPtr &inst); 1841060SN/A 1851060SN/A /** Remove all instructions that are not currently in the ROB. */ 1862132SN/A void removeInstsNotInROB(); 1871060SN/A 1882702Sktlim@umich.edu /** Remove all instructions younger than the given sequence number. */ 1892669Sktlim@umich.edu void removeInstsUntil(const InstSeqNum &seq_num); 1902292SN/A 1911060SN/A /** Remove all instructions from the list. */ 1921060SN/A void removeAllInsts(); 1931060SN/A 1944032Sktlim@umich.edu void dumpInsts(); 1954032Sktlim@umich.edu 1964032Sktlim@umich.edu /** Basically a wrapper function so that instructions executed at 1971060SN/A * commit can tell the instruction queue that they have completed. 1981060SN/A * Eventually this hack should be removed. 1991060SN/A */ 2001060SN/A void wakeDependents(DynInstPtr &inst); 2011060SN/A 2021060SN/A public: 2031060SN/A /** List of all the instructions in flight. */ 2041060SN/A list<DynInstPtr> instList; 2051060SN/A 2061060SN/A //not sure these should be private. 2071060SN/A protected: 2081060SN/A /** The fetch stage. */ 2091464SN/A typename CPUPolicy::Fetch fetch; 2101464SN/A 2112356SN/A /** The fetch stage's status. */ 2121464SN/A typename CPUPolicy::Fetch::Status fetchStatus; 2131464SN/A 2141060SN/A /** The decode stage. */ 2151464SN/A typename CPUPolicy::Decode decode; 2161464SN/A 2171464SN/A /** The decode stage's status. */ 2181464SN/A typename CPUPolicy::Decode::Status decodeStatus; 2191060SN/A 2203326Sktlim@umich.edu /** The dispatch stage. */ 2213326Sktlim@umich.edu typename CPUPolicy::Rename rename; 2223326Sktlim@umich.edu 2231060SN/A /** The dispatch stage's status. */ 2241060SN/A typename CPUPolicy::Rename::Status renameStatus; 2251060SN/A 2264636Sgblack@eecs.umich.edu /** The issue/execute/writeback stages. */ 2274636Sgblack@eecs.umich.edu typename CPUPolicy::IEW iew; 2284636Sgblack@eecs.umich.edu 2293965Sgblack@eecs.umich.edu /** The issue/execute/writeback stage's status. */ 2301060SN/A typename CPUPolicy::IEW::Status iewStatus; 2311060SN/A 2321060SN/A /** The commit stage. */ 2331060SN/A typename CPUPolicy::Commit commit; 2341060SN/A 2351060SN/A /** The fetch stage's status. */ 2362935Sksewell@umich.edu typename CPUPolicy::Commit::Status commitStatus; 2372935Sksewell@umich.edu 2382935Sksewell@umich.edu //Might want to just pass these objects in to the constructors of the 2394636Sgblack@eecs.umich.edu //appropriate stage. regFile is in iew, freeList in dispatch, renameMap 2404636Sgblack@eecs.umich.edu //in dispatch, and the rob in commit. 2414636Sgblack@eecs.umich.edu /** The register file. */ 2421060SN/A typename CPUPolicy::RegFile regFile; 2431060SN/A 2441060SN/A /** The free list. */ 2453794Sgblack@eecs.umich.edu typename CPUPolicy::FreeList freeList; 2463794Sgblack@eecs.umich.edu 2473794Sgblack@eecs.umich.edu /** The rename map. */ 2484636Sgblack@eecs.umich.edu typename CPUPolicy::RenameMap renameMap; 2494636Sgblack@eecs.umich.edu 2504636Sgblack@eecs.umich.edu /** The re-order buffer. */ 2513794Sgblack@eecs.umich.edu typename CPUPolicy::ROB rob; 2523794Sgblack@eecs.umich.edu 2533794Sgblack@eecs.umich.edu public: 2543965Sgblack@eecs.umich.edu /** Typedefs from the Impl to get the structs that each of the 2553965Sgblack@eecs.umich.edu * time buffers should use. 2562292SN/A */ 2572292SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 2582292SN/A 2592292SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 2602292SN/A 2612292SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 2621060SN/A 2631060SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 2641060SN/A 2653770Sgblack@eecs.umich.edu typedef typename CPUPolicy::IEWStruct IEWStruct; 2663770Sgblack@eecs.umich.edu 2673770Sgblack@eecs.umich.edu /** The main time buffer to do backwards communication. */ 2683770Sgblack@eecs.umich.edu TimeBuffer<TimeStruct> timeBuffer; 2693770Sgblack@eecs.umich.edu 2703770Sgblack@eecs.umich.edu /** The fetch stage's instruction queue. */ 2713770Sgblack@eecs.umich.edu TimeBuffer<FetchStruct> fetchQueue; 2723770Sgblack@eecs.umich.edu 2733770Sgblack@eecs.umich.edu /** The decode stage's instruction queue. */ 2743770Sgblack@eecs.umich.edu TimeBuffer<DecodeStruct> decodeQueue; 2753770Sgblack@eecs.umich.edu 2763770Sgblack@eecs.umich.edu /** The rename stage's instruction queue. */ 2773770Sgblack@eecs.umich.edu TimeBuffer<RenameStruct> renameQueue; 2783770Sgblack@eecs.umich.edu 2793770Sgblack@eecs.umich.edu /** The IEW stage's instruction queue. */ 2803770Sgblack@eecs.umich.edu TimeBuffer<IEWStruct> iewQueue; 2813770Sgblack@eecs.umich.edu 2823770Sgblack@eecs.umich.edu public: 2833770Sgblack@eecs.umich.edu /** The temporary exec context to support older accessors. */ 2843770Sgblack@eecs.umich.edu ExecContext *xc; 2853770Sgblack@eecs.umich.edu 2863770Sgblack@eecs.umich.edu /** Temporary function to get pointer to exec context. */ 2873770Sgblack@eecs.umich.edu ExecContext *xcBase() { return xc; } 2883770Sgblack@eecs.umich.edu 2893770Sgblack@eecs.umich.edu InstSeqNum globalSeqNum; 2903770Sgblack@eecs.umich.edu 2911060SN/A#ifdef FULL_SYSTEM 2923770Sgblack@eecs.umich.edu System *system; 2933770Sgblack@eecs.umich.edu 2943770Sgblack@eecs.umich.edu MemoryController *memCtrl; 2953770Sgblack@eecs.umich.edu PhysicalMemory *physmem; 2963770Sgblack@eecs.umich.edu 2973770Sgblack@eecs.umich.edu AlphaITB *itb; 2983770Sgblack@eecs.umich.edu AlphaDTB *dtb; 2993770Sgblack@eecs.umich.edu 3003770Sgblack@eecs.umich.edu// SWContext *swCtx; 3013770Sgblack@eecs.umich.edu#else 3023770Sgblack@eecs.umich.edu Process *process; 3033770Sgblack@eecs.umich.edu 3043770Sgblack@eecs.umich.edu // Address space ID. Note that this is used for TIMING cache 3053770Sgblack@eecs.umich.edu // simulation only; all functional memory accesses should use 3063770Sgblack@eecs.umich.edu // one of the FunctionalMemory pointers above. 3073770Sgblack@eecs.umich.edu short asid; 3083770Sgblack@eecs.umich.edu#endif 3093770Sgblack@eecs.umich.edu 3103770Sgblack@eecs.umich.edu FunctionalMemory *mem; 3113770Sgblack@eecs.umich.edu 3123770Sgblack@eecs.umich.edu MemInterface *icacheInterface; 3133770Sgblack@eecs.umich.edu MemInterface *dcacheInterface; 3143770Sgblack@eecs.umich.edu 3153770Sgblack@eecs.umich.edu bool deferRegistration; 3163770Sgblack@eecs.umich.edu 3173770Sgblack@eecs.umich.edu Counter numInsts; 3183770Sgblack@eecs.umich.edu 3193770Sgblack@eecs.umich.edu Counter funcExeInst; 3203770Sgblack@eecs.umich.edu}; 3213770Sgblack@eecs.umich.edu 3223770Sgblack@eecs.umich.edu#endif 3233770Sgblack@eecs.umich.edu