cpu.hh revision 12406
11689SN/A/* 212109SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2011-2013, 2016 ARM Limited 39919Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48707Sandreas.hansson@arm.com * All rights reserved 58707Sandreas.hansson@arm.com * 68707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148707Sandreas.hansson@arm.com * 151689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 167897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 171689SN/A * All rights reserved. 181689SN/A * 191689SN/A * Redistribution and use in source and binary forms, with or without 201689SN/A * modification, are permitted provided that the following conditions are 211689SN/A * met: redistributions of source code must retain the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer; 231689SN/A * redistributions in binary form must reproduce the above copyright 241689SN/A * notice, this list of conditions and the following disclaimer in the 251689SN/A * documentation and/or other materials provided with the distribution; 261689SN/A * neither the name of the copyright holders nor the names of its 271689SN/A * contributors may be used to endorse or promote products derived from 281689SN/A * this software without specific prior written permission. 291689SN/A * 301689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 432756Sksewell@umich.edu * Korey Sewell 447897Shestness@cs.utexas.edu * Rick Strong 451689SN/A */ 461689SN/A 472325SN/A#ifndef __CPU_O3_CPU_HH__ 482325SN/A#define __CPU_O3_CPU_HH__ 491060SN/A 501060SN/A#include <iostream> 511060SN/A#include <list> 522292SN/A#include <queue> 532292SN/A#include <set> 541681SN/A#include <vector> 551060SN/A 5612109SRekai.GonzalezAlberquilla@arm.com#include "arch/generic/types.hh" 572980Sgblack@eecs.umich.edu#include "arch/types.hh" 581060SN/A#include "base/statistics.hh" 596658Snate@binkert.org#include "config/the_isa.hh" 601717SN/A#include "cpu/o3/comm.hh" 611717SN/A#include "cpu/o3/cpu_policy.hh" 622292SN/A#include "cpu/o3/scoreboard.hh" 632292SN/A#include "cpu/o3/thread_state.hh" 648229Snate@binkert.org#include "cpu/activity.hh" 658229Snate@binkert.org#include "cpu/base.hh" 668229Snate@binkert.org#include "cpu/simple_thread.hh" 678229Snate@binkert.org#include "cpu/timebuf.hh" 682817Sksewell@umich.edu//#include "cpu/o3/thread_context.hh" 698229Snate@binkert.org#include "params/DerivO3CPU.hh" 701060SN/A#include "sim/process.hh" 711060SN/A 722316SN/Atemplate <class> 732316SN/Aclass Checker; 742680Sktlim@umich.educlass ThreadContext; 752817Sksewell@umich.edutemplate <class> 762817Sksewell@umich.educlass O3ThreadContext; 772843Sktlim@umich.edu 782843Sktlim@umich.educlass Checkpoint; 792669Sktlim@umich.educlass MemObject; 801060SN/Aclass Process; 811060SN/A 828737Skoansin.tan@gmail.comstruct BaseCPUParams; 835529Snate@binkert.org 842733Sktlim@umich.educlass BaseO3CPU : public BaseCPU 851060SN/A{ 861060SN/A //Stuff that's pretty ISA independent will go here. 871060SN/A public: 885529Snate@binkert.org BaseO3CPU(BaseCPUParams *params); 892292SN/A 902292SN/A void regStats(); 911060SN/A}; 921060SN/A 932348SN/A/** 942348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 952348SN/A * within it, as well as all of the time buffers between stages. The 962348SN/A * tick() function for the CPU is defined here. 972348SN/A */ 981060SN/Atemplate <class Impl> 992733Sktlim@umich.educlass FullO3CPU : public BaseO3CPU 1001060SN/A{ 1011060SN/A public: 1022325SN/A // Typedefs from the Impl here. 1031060SN/A typedef typename Impl::CPUPol CPUPolicy; 1041061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1054329Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 1061060SN/A 10712109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 10812109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 10912109SRekai.GonzalezAlberquilla@arm.com 1105595Sgblack@eecs.umich.edu typedef O3ThreadState<Impl> ImplState; 1112292SN/A typedef O3ThreadState<Impl> Thread; 1122292SN/A 1132292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 1142292SN/A 1152817Sksewell@umich.edu friend class O3ThreadContext<Impl>; 1162829Sksewell@umich.edu 1171060SN/A public: 1181060SN/A enum Status { 1191060SN/A Running, 1201060SN/A Idle, 1211060SN/A Halted, 1222307SN/A Blocked, 1232307SN/A SwitchedOut 1241060SN/A }; 1251060SN/A 12612406Sgabeblack@google.com BaseTLB *itb; 12712406Sgabeblack@google.com BaseTLB *dtb; 1283781Sgblack@eecs.umich.edu 1292292SN/A /** Overall CPU status. */ 1301060SN/A Status _status; 1311060SN/A 1321060SN/A private: 1338707Sandreas.hansson@arm.com 1348707Sandreas.hansson@arm.com /** 1358707Sandreas.hansson@arm.com * IcachePort class for instruction fetch. 1368707Sandreas.hansson@arm.com */ 1379608Sandreas.hansson@arm.com class IcachePort : public MasterPort 1388707Sandreas.hansson@arm.com { 1398707Sandreas.hansson@arm.com protected: 1408707Sandreas.hansson@arm.com /** Pointer to fetch. */ 1418707Sandreas.hansson@arm.com DefaultFetch<Impl> *fetch; 1428707Sandreas.hansson@arm.com 1438707Sandreas.hansson@arm.com public: 1448707Sandreas.hansson@arm.com /** Default constructor. */ 1458707Sandreas.hansson@arm.com IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 1469608Sandreas.hansson@arm.com : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) 1478707Sandreas.hansson@arm.com { } 1488707Sandreas.hansson@arm.com 1498707Sandreas.hansson@arm.com protected: 1508707Sandreas.hansson@arm.com 1518707Sandreas.hansson@arm.com /** Timing version of receive. Handles setting fetch to the 1528707Sandreas.hansson@arm.com * proper status to start fetching. */ 1538975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 1548707Sandreas.hansson@arm.com 1558707Sandreas.hansson@arm.com /** Handles doing a retry of a failed fetch. */ 15610713Sandreas.hansson@arm.com virtual void recvReqRetry(); 1578707Sandreas.hansson@arm.com }; 1588707Sandreas.hansson@arm.com 1598707Sandreas.hansson@arm.com /** 1608707Sandreas.hansson@arm.com * DcachePort class for the load/store queue. 1618707Sandreas.hansson@arm.com */ 1629608Sandreas.hansson@arm.com class DcachePort : public MasterPort 1638707Sandreas.hansson@arm.com { 1648707Sandreas.hansson@arm.com protected: 1658707Sandreas.hansson@arm.com 1668707Sandreas.hansson@arm.com /** Pointer to LSQ. */ 1678707Sandreas.hansson@arm.com LSQ<Impl> *lsq; 16810529Smorr@cs.wisc.edu FullO3CPU<Impl> *cpu; 1698707Sandreas.hansson@arm.com 1708707Sandreas.hansson@arm.com public: 1718707Sandreas.hansson@arm.com /** Default constructor. */ 1728707Sandreas.hansson@arm.com DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) 17310529Smorr@cs.wisc.edu : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), 17410529Smorr@cs.wisc.edu cpu(_cpu) 1758707Sandreas.hansson@arm.com { } 1768707Sandreas.hansson@arm.com 1778707Sandreas.hansson@arm.com protected: 1788707Sandreas.hansson@arm.com 1798707Sandreas.hansson@arm.com /** Timing version of receive. Handles writing back and 1808707Sandreas.hansson@arm.com * completing the load or store that has returned from 1818707Sandreas.hansson@arm.com * memory. */ 1828975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 1838975Sandreas.hansson@arm.com virtual void recvTimingSnoopReq(PacketPtr pkt); 1848707Sandreas.hansson@arm.com 1859608Sandreas.hansson@arm.com virtual void recvFunctionalSnoop(PacketPtr pkt) 1869608Sandreas.hansson@arm.com { 1879608Sandreas.hansson@arm.com // @todo: Is there a need for potential invalidation here? 1889608Sandreas.hansson@arm.com } 1899608Sandreas.hansson@arm.com 1908707Sandreas.hansson@arm.com /** Handles doing a retry of the previous send. */ 19110713Sandreas.hansson@arm.com virtual void recvReqRetry(); 1928707Sandreas.hansson@arm.com 1938707Sandreas.hansson@arm.com /** 1948707Sandreas.hansson@arm.com * As this CPU requires snooping to maintain the load store queue 1958707Sandreas.hansson@arm.com * change the behaviour from the base CPU port. 1968707Sandreas.hansson@arm.com * 1978711Sandreas.hansson@arm.com * @return true since we have to snoop 1988707Sandreas.hansson@arm.com */ 1998922Swilliam.wang@arm.com virtual bool isSnooping() const { return true; } 2008707Sandreas.hansson@arm.com }; 2018707Sandreas.hansson@arm.com 2022292SN/A /** The tick event used for scheduling CPU ticks. */ 20312127Sspwilson2@wisc.edu EventFunctionWrapper tickEvent; 2041060SN/A 2052292SN/A /** Schedule tick event, regardless of its current state. */ 2069180Sandreas.hansson@arm.com void scheduleTickEvent(Cycles delay) 2071060SN/A { 2081060SN/A if (tickEvent.squashed()) 2099179Sandreas.hansson@arm.com reschedule(tickEvent, clockEdge(delay)); 2101060SN/A else if (!tickEvent.scheduled()) 2119179Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(delay)); 2121060SN/A } 2131060SN/A 2142292SN/A /** Unschedule tick event, regardless of its current state. */ 2151060SN/A void unscheduleTickEvent() 2161060SN/A { 2171060SN/A if (tickEvent.scheduled()) 2181060SN/A tickEvent.squash(); 2191060SN/A } 2201060SN/A 2219444SAndreas.Sandberg@ARM.com /** 22210913Sandreas.sandberg@arm.com * Check if the pipeline has drained and signal drain done. 2239444SAndreas.Sandberg@ARM.com * 2249444SAndreas.Sandberg@ARM.com * This method checks if a drain has been requested and if the CPU 2259444SAndreas.Sandberg@ARM.com * has drained successfully (i.e., there are no instructions in 2269444SAndreas.Sandberg@ARM.com * the pipeline). If the CPU has drained, it deschedules the tick 2279444SAndreas.Sandberg@ARM.com * event and signals the drain manager. 2289444SAndreas.Sandberg@ARM.com * 2299444SAndreas.Sandberg@ARM.com * @return False if a drain hasn't been requested or the CPU 2309444SAndreas.Sandberg@ARM.com * hasn't drained, true otherwise. 2319444SAndreas.Sandberg@ARM.com */ 2329444SAndreas.Sandberg@ARM.com bool tryDrain(); 2339444SAndreas.Sandberg@ARM.com 2349444SAndreas.Sandberg@ARM.com /** 2359444SAndreas.Sandberg@ARM.com * Perform sanity checks after a drain. 2369444SAndreas.Sandberg@ARM.com * 2379444SAndreas.Sandberg@ARM.com * This method is called from drain() when it has determined that 2389444SAndreas.Sandberg@ARM.com * the CPU is fully drained when gem5 is compiled with the NDEBUG 2399444SAndreas.Sandberg@ARM.com * macro undefined. The intention of this method is to do more 2409444SAndreas.Sandberg@ARM.com * extensive tests than the isDrained() method to weed out any 2419444SAndreas.Sandberg@ARM.com * draining bugs. 2429444SAndreas.Sandberg@ARM.com */ 2439444SAndreas.Sandberg@ARM.com void drainSanityCheck() const; 2449444SAndreas.Sandberg@ARM.com 2459444SAndreas.Sandberg@ARM.com /** Check if a system is in a drained state. */ 2469444SAndreas.Sandberg@ARM.com bool isDrained() const; 2479444SAndreas.Sandberg@ARM.com 2481060SN/A public: 2492292SN/A /** Constructs a CPU with the given parameters. */ 2505595Sgblack@eecs.umich.edu FullO3CPU(DerivO3CPUParams *params); 2512292SN/A /** Destructor. */ 2521755SN/A ~FullO3CPU(); 2531060SN/A 2542292SN/A /** Registers statistics. */ 25511169Sandreas.hansson@arm.com void regStats() override; 2561684SN/A 25710023Smatt.horsnell@ARM.com ProbePointArg<PacketPtr> *ppInstAccessComplete; 25810023Smatt.horsnell@ARM.com ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete; 25910023Smatt.horsnell@ARM.com 26010023Smatt.horsnell@ARM.com /** Register probe points. */ 26111169Sandreas.hansson@arm.com void regProbePoints() override; 26210023Smatt.horsnell@ARM.com 2635358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 2645358Sgblack@eecs.umich.edu { 2655358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2665358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2675358Sgblack@eecs.umich.edu } 2685358Sgblack@eecs.umich.edu 2695358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 2705358Sgblack@eecs.umich.edu { 2715358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2725358Sgblack@eecs.umich.edu } 2735358Sgblack@eecs.umich.edu 2745358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 2755358Sgblack@eecs.umich.edu { 2765358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2775358Sgblack@eecs.umich.edu } 2785358Sgblack@eecs.umich.edu 2792292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 2802292SN/A * activity to see if the CPU should deschedule itself. 2812292SN/A */ 2821684SN/A void tick(); 2831684SN/A 2842292SN/A /** Initialize the CPU */ 28511169Sandreas.hansson@arm.com void init() override; 2861060SN/A 28711169Sandreas.hansson@arm.com void startup() override; 2889427SAndreas.Sandberg@ARM.com 2892834Sksewell@umich.edu /** Returns the Number of Active Threads in the CPU */ 2902834Sksewell@umich.edu int numActiveThreads() 2912834Sksewell@umich.edu { return activeThreads.size(); } 2922834Sksewell@umich.edu 2932829Sksewell@umich.edu /** Add Thread to Active Threads List */ 2946221Snate@binkert.org void activateThread(ThreadID tid); 2952875Sksewell@umich.edu 2962875Sksewell@umich.edu /** Remove Thread from Active Threads List */ 2976221Snate@binkert.org void deactivateThread(ThreadID tid); 2982829Sksewell@umich.edu 2992292SN/A /** Setup CPU to insert a thread's context */ 3006221Snate@binkert.org void insertThread(ThreadID tid); 3011060SN/A 3022292SN/A /** Remove all of a thread's context from CPU */ 3036221Snate@binkert.org void removeThread(ThreadID tid); 3042292SN/A 3052292SN/A /** Count the Total Instructions Committed in the CPU. */ 30611169Sandreas.hansson@arm.com Counter totalInsts() const override; 3078834Satgutier@umich.edu 3088834Satgutier@umich.edu /** Count the Total Ops (including micro ops) committed in the CPU. */ 30911169Sandreas.hansson@arm.com Counter totalOps() const override; 3102292SN/A 3112292SN/A /** Add Thread to Active Threads List. */ 31211169Sandreas.hansson@arm.com void activateContext(ThreadID tid) override; 3132292SN/A 3142292SN/A /** Remove Thread from Active Threads List */ 31511169Sandreas.hansson@arm.com void suspendContext(ThreadID tid) override; 3162292SN/A 3172292SN/A /** Remove Thread from Active Threads List && 3182292SN/A * Remove Thread Context from CPU. 3192292SN/A */ 32011169Sandreas.hansson@arm.com void haltContext(ThreadID tid) override; 3212292SN/A 3222292SN/A /** Update The Order In Which We Process Threads. */ 3232292SN/A void updateThreadPriority(); 3242292SN/A 3259444SAndreas.Sandberg@ARM.com /** Is the CPU draining? */ 32610913Sandreas.sandberg@arm.com bool isDraining() const { return drainState() == DrainState::Draining; } 3279444SAndreas.Sandberg@ARM.com 32811168Sandreas.hansson@arm.com void serializeThread(CheckpointOut &cp, ThreadID tid) const override; 32911168Sandreas.hansson@arm.com void unserializeThread(CheckpointIn &cp, ThreadID tid) override; 3302864Sktlim@umich.edu 3312864Sktlim@umich.edu public: 3325595Sgblack@eecs.umich.edu /** Executes a syscall. 3335595Sgblack@eecs.umich.edu * @todo: Determine if this needs to be virtual. 3342292SN/A */ 33511877Sbrandon.potter@amd.com void syscall(int64_t callnum, ThreadID tid, Fault *fault); 3362292SN/A 3372843Sktlim@umich.edu /** Starts draining the CPU's pipeline of all instructions in 3382843Sktlim@umich.edu * order to stop all memory accesses. */ 33911168Sandreas.hansson@arm.com DrainState drain() override; 3402843Sktlim@umich.edu 3412843Sktlim@umich.edu /** Resumes execution after a drain. */ 34211168Sandreas.hansson@arm.com void drainResume() override; 3432292SN/A 3449444SAndreas.Sandberg@ARM.com /** 3459444SAndreas.Sandberg@ARM.com * Commit has reached a safe point to drain a thread. 3469444SAndreas.Sandberg@ARM.com * 3479444SAndreas.Sandberg@ARM.com * Commit calls this method to inform the pipeline that it has 3489444SAndreas.Sandberg@ARM.com * reached a point where it is not executed microcode and is about 3499444SAndreas.Sandberg@ARM.com * to squash uncommitted instructions to fully drain the pipeline. 3509444SAndreas.Sandberg@ARM.com */ 3519444SAndreas.Sandberg@ARM.com void commitDrained(ThreadID tid); 3522843Sktlim@umich.edu 3532843Sktlim@umich.edu /** Switches out this CPU. */ 35411169Sandreas.hansson@arm.com void switchOut() override; 3552316SN/A 3562348SN/A /** Takes over from another CPU. */ 35711169Sandreas.hansson@arm.com void takeOverFrom(BaseCPU *oldCPU) override; 3581060SN/A 35911169Sandreas.hansson@arm.com void verifyMemoryMode() const override; 3609523SAndreas.Sandberg@ARM.com 3611060SN/A /** Get the current instruction sequence number, and increment it. */ 3622316SN/A InstSeqNum getAndIncrementInstSeq() 3632316SN/A { return globalSeqNum++; } 3641060SN/A 3655595Sgblack@eecs.umich.edu /** Traps to handle given fault. */ 36610417Sandreas.hansson@arm.com void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst); 3675595Sgblack@eecs.umich.edu 3685702Ssaidi@eecs.umich.edu /** HW return from error interrupt. */ 3696221Snate@binkert.org Fault hwrei(ThreadID tid); 3705702Ssaidi@eecs.umich.edu 3716221Snate@binkert.org bool simPalCheck(int palFunc, ThreadID tid); 3725702Ssaidi@eecs.umich.edu 3735595Sgblack@eecs.umich.edu /** Returns the Fault for any valid interrupt. */ 3745595Sgblack@eecs.umich.edu Fault getInterrupts(); 3755595Sgblack@eecs.umich.edu 3765595Sgblack@eecs.umich.edu /** Processes any an interrupt fault. */ 37710379Sandreas.hansson@arm.com void processInterrupts(const Fault &interrupt); 3785595Sgblack@eecs.umich.edu 3795595Sgblack@eecs.umich.edu /** Halts the CPU. */ 3805595Sgblack@eecs.umich.edu void halt() { panic("Halt not implemented!\n"); } 3815595Sgblack@eecs.umich.edu 3822348SN/A /** Register accessors. Index refers to the physical register index. */ 3835595Sgblack@eecs.umich.edu 3845595Sgblack@eecs.umich.edu /** Reads a miscellaneous register. */ 38510698Sandreas.hansson@arm.com TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const; 3865595Sgblack@eecs.umich.edu 3875595Sgblack@eecs.umich.edu /** Reads a misc. register, including any side effects the read 3885595Sgblack@eecs.umich.edu * might have as defined by the architecture. 3895595Sgblack@eecs.umich.edu */ 3906221Snate@binkert.org TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 3915595Sgblack@eecs.umich.edu 3925595Sgblack@eecs.umich.edu /** Sets a miscellaneous register. */ 3936221Snate@binkert.org void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 3946221Snate@binkert.org ThreadID tid); 3955595Sgblack@eecs.umich.edu 3965595Sgblack@eecs.umich.edu /** Sets a misc. register, including any side effects the write 3975595Sgblack@eecs.umich.edu * might have as defined by the architecture. 3985595Sgblack@eecs.umich.edu */ 3995595Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 4006221Snate@binkert.org ThreadID tid); 4015595Sgblack@eecs.umich.edu 40212105Snathanael.premillieu@arm.com uint64_t readIntReg(PhysRegIdPtr phys_reg); 4031060SN/A 40412105Snathanael.premillieu@arm.com TheISA::FloatReg readFloatReg(PhysRegIdPtr phys_reg); 4051060SN/A 40612105Snathanael.premillieu@arm.com TheISA::FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg); 4072455SN/A 40812109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const; 40912109SRekai.GonzalezAlberquilla@arm.com 41012109SRekai.GonzalezAlberquilla@arm.com /** 41112109SRekai.GonzalezAlberquilla@arm.com * Read physical vector register for modification. 41212109SRekai.GonzalezAlberquilla@arm.com */ 41312109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx); 41412109SRekai.GonzalezAlberquilla@arm.com 41512109SRekai.GonzalezAlberquilla@arm.com /** 41612109SRekai.GonzalezAlberquilla@arm.com * Read physical vector register lane 41712109SRekai.GonzalezAlberquilla@arm.com */ 41812109SRekai.GonzalezAlberquilla@arm.com template<typename VecElem, int LaneIdx> 41912109SRekai.GonzalezAlberquilla@arm.com VecLaneT<VecElem, true> 42012109SRekai.GonzalezAlberquilla@arm.com readVecLane(PhysRegIdPtr phys_reg) const 42112109SRekai.GonzalezAlberquilla@arm.com { 42212109SRekai.GonzalezAlberquilla@arm.com vecRegfileReads++; 42312109SRekai.GonzalezAlberquilla@arm.com return regFile.readVecLane<VecElem, LaneIdx>(phys_reg); 42412109SRekai.GonzalezAlberquilla@arm.com } 42512109SRekai.GonzalezAlberquilla@arm.com 42612109SRekai.GonzalezAlberquilla@arm.com /** 42712109SRekai.GonzalezAlberquilla@arm.com * Read physical vector register lane 42812109SRekai.GonzalezAlberquilla@arm.com */ 42912109SRekai.GonzalezAlberquilla@arm.com template<typename VecElem> 43012109SRekai.GonzalezAlberquilla@arm.com VecLaneT<VecElem, true> 43112109SRekai.GonzalezAlberquilla@arm.com readVecLane(PhysRegIdPtr phys_reg) const 43212109SRekai.GonzalezAlberquilla@arm.com { 43312109SRekai.GonzalezAlberquilla@arm.com vecRegfileReads++; 43412109SRekai.GonzalezAlberquilla@arm.com return regFile.readVecLane<VecElem>(phys_reg); 43512109SRekai.GonzalezAlberquilla@arm.com } 43612109SRekai.GonzalezAlberquilla@arm.com 43712109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 43812109SRekai.GonzalezAlberquilla@arm.com template<typename LD> 43912109SRekai.GonzalezAlberquilla@arm.com void 44012109SRekai.GonzalezAlberquilla@arm.com setVecLane(PhysRegIdPtr phys_reg, const LD& val) 44112109SRekai.GonzalezAlberquilla@arm.com { 44212109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites++; 44312109SRekai.GonzalezAlberquilla@arm.com return regFile.setVecLane(phys_reg, val); 44412109SRekai.GonzalezAlberquilla@arm.com } 44512109SRekai.GonzalezAlberquilla@arm.com 44612109SRekai.GonzalezAlberquilla@arm.com const VecElem& readVecElem(PhysRegIdPtr reg_idx) const; 44712109SRekai.GonzalezAlberquilla@arm.com 44812105Snathanael.premillieu@arm.com TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg); 4499920Syasuko.eckert@amd.com 45012105Snathanael.premillieu@arm.com void setIntReg(PhysRegIdPtr phys_reg, uint64_t val); 4511060SN/A 45212105Snathanael.premillieu@arm.com void setFloatReg(PhysRegIdPtr phys_reg, TheISA::FloatReg val); 4531060SN/A 45412105Snathanael.premillieu@arm.com void setFloatRegBits(PhysRegIdPtr phys_reg, TheISA::FloatRegBits val); 4552455SN/A 45612109SRekai.GonzalezAlberquilla@arm.com void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val); 45712109SRekai.GonzalezAlberquilla@arm.com 45812109SRekai.GonzalezAlberquilla@arm.com void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val); 45912109SRekai.GonzalezAlberquilla@arm.com 46012105Snathanael.premillieu@arm.com void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val); 4619920Syasuko.eckert@amd.com 4626221Snate@binkert.org uint64_t readArchIntReg(int reg_idx, ThreadID tid); 4631060SN/A 4646314Sgblack@eecs.umich.edu float readArchFloatReg(int reg_idx, ThreadID tid); 4652292SN/A 4666221Snate@binkert.org uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 4672292SN/A 46812109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const; 46912109SRekai.GonzalezAlberquilla@arm.com /** Read architectural vector register for modification. */ 47012109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid); 47112109SRekai.GonzalezAlberquilla@arm.com 47212109SRekai.GonzalezAlberquilla@arm.com /** Read architectural vector register lane. */ 47312109SRekai.GonzalezAlberquilla@arm.com template<typename VecElem> 47412109SRekai.GonzalezAlberquilla@arm.com VecLaneT<VecElem, true> 47512109SRekai.GonzalezAlberquilla@arm.com readArchVecLane(int reg_idx, int lId, ThreadID tid) const 47612109SRekai.GonzalezAlberquilla@arm.com { 47712109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 47812109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx)); 47912109SRekai.GonzalezAlberquilla@arm.com return readVecLane<VecElem>(phys_reg); 48012109SRekai.GonzalezAlberquilla@arm.com } 48112109SRekai.GonzalezAlberquilla@arm.com 48212109SRekai.GonzalezAlberquilla@arm.com 48312109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 48412109SRekai.GonzalezAlberquilla@arm.com template<typename LD> 48512109SRekai.GonzalezAlberquilla@arm.com void 48612109SRekai.GonzalezAlberquilla@arm.com setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val) 48712109SRekai.GonzalezAlberquilla@arm.com { 48812109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 48912109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx)); 49012109SRekai.GonzalezAlberquilla@arm.com setVecLane(phys_reg, val); 49112109SRekai.GonzalezAlberquilla@arm.com } 49212109SRekai.GonzalezAlberquilla@arm.com 49312109SRekai.GonzalezAlberquilla@arm.com const VecElem& readArchVecElem(const RegIndex& reg_idx, 49412109SRekai.GonzalezAlberquilla@arm.com const ElemIndex& ldx, ThreadID tid) const; 49512109SRekai.GonzalezAlberquilla@arm.com 4969920Syasuko.eckert@amd.com TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid); 4979920Syasuko.eckert@amd.com 4982348SN/A /** Architectural register accessors. Looks up in the commit 4992348SN/A * rename table to obtain the true physical index of the 5002348SN/A * architected register first, then accesses that physical 5012348SN/A * register. 5022348SN/A */ 5036221Snate@binkert.org void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 5042292SN/A 5056314Sgblack@eecs.umich.edu void setArchFloatReg(int reg_idx, float val, ThreadID tid); 5062292SN/A 5076221Snate@binkert.org void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 5082292SN/A 50912109SRekai.GonzalezAlberquilla@arm.com void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid); 51012109SRekai.GonzalezAlberquilla@arm.com 51112109SRekai.GonzalezAlberquilla@arm.com void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 51212109SRekai.GonzalezAlberquilla@arm.com const VecElem& val, ThreadID tid); 51312109SRekai.GonzalezAlberquilla@arm.com 5149920Syasuko.eckert@amd.com void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid); 5159920Syasuko.eckert@amd.com 5167720Sgblack@eecs.umich.edu /** Sets the commit PC state of a specific thread. */ 5177720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &newPCState, ThreadID tid); 5187720Sgblack@eecs.umich.edu 5197720Sgblack@eecs.umich.edu /** Reads the commit PC state of a specific thread. */ 5207720Sgblack@eecs.umich.edu TheISA::PCState pcState(ThreadID tid); 5217720Sgblack@eecs.umich.edu 5222348SN/A /** Reads the commit PC of a specific thread. */ 5237720Sgblack@eecs.umich.edu Addr instAddr(ThreadID tid); 5242292SN/A 5254636Sgblack@eecs.umich.edu /** Reads the commit micro PC of a specific thread. */ 5267720Sgblack@eecs.umich.edu MicroPC microPC(ThreadID tid); 5274636Sgblack@eecs.umich.edu 5282348SN/A /** Reads the next PC of a specific thread. */ 5297720Sgblack@eecs.umich.edu Addr nextInstAddr(ThreadID tid); 5302756Sksewell@umich.edu 5315595Sgblack@eecs.umich.edu /** Initiates a squash of all in-flight instructions for a given 5325595Sgblack@eecs.umich.edu * thread. The source of the squash is an external update of 5335595Sgblack@eecs.umich.edu * state through the TC. 5345595Sgblack@eecs.umich.edu */ 5356221Snate@binkert.org void squashFromTC(ThreadID tid); 5365595Sgblack@eecs.umich.edu 5371060SN/A /** Function to add instruction onto the head of the list of the 5381060SN/A * instructions. Used when new instructions are fetched. 5391060SN/A */ 5402292SN/A ListIt addInst(DynInstPtr &inst); 5411060SN/A 5421060SN/A /** Function to tell the CPU that an instruction has completed. */ 5438834Satgutier@umich.edu void instDone(ThreadID tid, DynInstPtr &inst); 5441060SN/A 5452325SN/A /** Remove an instruction from the front end of the list. There's 5462325SN/A * no restriction on location of the instruction. 5471060SN/A */ 5481061SN/A void removeFrontInst(DynInstPtr &inst); 5491060SN/A 5502935Sksewell@umich.edu /** Remove all instructions that are not currently in the ROB. 5512935Sksewell@umich.edu * There's also an option to not squash delay slot instructions.*/ 5526221Snate@binkert.org void removeInstsNotInROB(ThreadID tid); 5531060SN/A 5541062SN/A /** Remove all instructions younger than the given sequence number. */ 5556221Snate@binkert.org void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 5562292SN/A 5572348SN/A /** Removes the instruction pointed to by the iterator. */ 5586221Snate@binkert.org inline void squashInstIt(const ListIt &instIt, ThreadID tid); 5592292SN/A 5602348SN/A /** Cleans up all instructions on the remove list. */ 5612292SN/A void cleanUpRemovedInsts(); 5621062SN/A 5632348SN/A /** Debug function to print all instructions on the list. */ 5641060SN/A void dumpInsts(); 5651060SN/A 5661060SN/A public: 5675737Scws3k@cs.virginia.edu#ifndef NDEBUG 5685737Scws3k@cs.virginia.edu /** Count of total number of dynamic instructions in flight. */ 5695737Scws3k@cs.virginia.edu int instcount; 5705737Scws3k@cs.virginia.edu#endif 5715737Scws3k@cs.virginia.edu 5721060SN/A /** List of all the instructions in flight. */ 5732292SN/A std::list<DynInstPtr> instList; 5741060SN/A 5752292SN/A /** List of all the instructions that will be removed at the end of this 5762292SN/A * cycle. 5772292SN/A */ 5782292SN/A std::queue<ListIt> removeList; 5792292SN/A 5802325SN/A#ifdef DEBUG 5812348SN/A /** Debug structure to keep track of the sequence numbers still in 5822348SN/A * flight. 5832348SN/A */ 5842292SN/A std::set<InstSeqNum> snList; 5852325SN/A#endif 5862292SN/A 5872325SN/A /** Records if instructions need to be removed this cycle due to 5882325SN/A * being retired or squashed. 5892292SN/A */ 5902292SN/A bool removeInstsThisCycle; 5912292SN/A 5921060SN/A protected: 5931060SN/A /** The fetch stage. */ 5941060SN/A typename CPUPolicy::Fetch fetch; 5951060SN/A 5961060SN/A /** The decode stage. */ 5971060SN/A typename CPUPolicy::Decode decode; 5981060SN/A 5991060SN/A /** The dispatch stage. */ 6001060SN/A typename CPUPolicy::Rename rename; 6011060SN/A 6021060SN/A /** The issue/execute/writeback stages. */ 6031060SN/A typename CPUPolicy::IEW iew; 6041060SN/A 6051060SN/A /** The commit stage. */ 6061060SN/A typename CPUPolicy::Commit commit; 6071060SN/A 60812109SRekai.GonzalezAlberquilla@arm.com /** The rename mode of the vector registers */ 60912109SRekai.GonzalezAlberquilla@arm.com Enums::VecRegRenameMode vecMode; 61012109SRekai.GonzalezAlberquilla@arm.com 6111060SN/A /** The register file. */ 6129919Ssteve.reinhardt@amd.com PhysRegFile regFile; 6131060SN/A 6141060SN/A /** The free list. */ 6151060SN/A typename CPUPolicy::FreeList freeList; 6161060SN/A 6171060SN/A /** The rename map. */ 6182292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 6192292SN/A 6202292SN/A /** The commit rename map. */ 6212292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 6221060SN/A 6231060SN/A /** The re-order buffer. */ 6241060SN/A typename CPUPolicy::ROB rob; 6251060SN/A 6262292SN/A /** Active Threads List */ 6276221Snate@binkert.org std::list<ThreadID> activeThreads; 6282292SN/A 6292292SN/A /** Integer Register Scoreboard */ 6302292SN/A Scoreboard scoreboard; 6312292SN/A 6329384SAndreas.Sandberg@arm.com std::vector<TheISA::ISA *> isa; 6336313Sgblack@eecs.umich.edu 6348707Sandreas.hansson@arm.com /** Instruction port. Note that it has to appear after the fetch stage. */ 6358707Sandreas.hansson@arm.com IcachePort icachePort; 6368707Sandreas.hansson@arm.com 6378707Sandreas.hansson@arm.com /** Data port. Note that it has to appear after the iew stages */ 6388707Sandreas.hansson@arm.com DcachePort dcachePort; 6398707Sandreas.hansson@arm.com 6401060SN/A public: 6412292SN/A /** Enum to give each stage a specific index, so when calling 6422292SN/A * activateStage() or deactivateStage(), they can specify which stage 6432292SN/A * is being activated/deactivated. 6442292SN/A */ 6452292SN/A enum StageIdx { 6462292SN/A FetchIdx, 6472292SN/A DecodeIdx, 6482292SN/A RenameIdx, 6492292SN/A IEWIdx, 6502292SN/A CommitIdx, 6512292SN/A NumStages }; 6522292SN/A 6531060SN/A /** Typedefs from the Impl to get the structs that each of the 6541060SN/A * time buffers should use. 6551060SN/A */ 6561061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 6571060SN/A 6581061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 6591060SN/A 6601061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 6611060SN/A 6621061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 6631060SN/A 6641061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 6651060SN/A 6661060SN/A /** The main time buffer to do backwards communication. */ 6671060SN/A TimeBuffer<TimeStruct> timeBuffer; 6681060SN/A 6691060SN/A /** The fetch stage's instruction queue. */ 6701060SN/A TimeBuffer<FetchStruct> fetchQueue; 6711060SN/A 6721060SN/A /** The decode stage's instruction queue. */ 6731060SN/A TimeBuffer<DecodeStruct> decodeQueue; 6741060SN/A 6751060SN/A /** The rename stage's instruction queue. */ 6761060SN/A TimeBuffer<RenameStruct> renameQueue; 6771060SN/A 6781060SN/A /** The IEW stage's instruction queue. */ 6791060SN/A TimeBuffer<IEWStruct> iewQueue; 6801060SN/A 6812348SN/A private: 6822348SN/A /** The activity recorder; used to tell if the CPU has any 6832348SN/A * activity remaining or if it can go to idle and deschedule 6842348SN/A * itself. 6852348SN/A */ 6862325SN/A ActivityRecorder activityRec; 6871060SN/A 6882348SN/A public: 6892348SN/A /** Records that there was time buffer activity this cycle. */ 6902325SN/A void activityThisCycle() { activityRec.activity(); } 6912292SN/A 6922348SN/A /** Changes a stage's status to active within the activity recorder. */ 6932325SN/A void activateStage(const StageIdx idx) 6942325SN/A { activityRec.activateStage(idx); } 6952292SN/A 6962348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 6972325SN/A void deactivateStage(const StageIdx idx) 6982325SN/A { activityRec.deactivateStage(idx); } 6992292SN/A 7002292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 7012292SN/A void wakeCPU(); 7022260SN/A 70311168Sandreas.hansson@arm.com virtual void wakeup(ThreadID tid) override; 7045807Snate@binkert.org 7052292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 7066221Snate@binkert.org ThreadID getFreeTid(); 7072292SN/A 7082292SN/A public: 7092680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 7106221Snate@binkert.org ThreadContext * 7116221Snate@binkert.org tcBase(ThreadID tid) 7121681SN/A { 7132680Sktlim@umich.edu return thread[tid]->getTC(); 7142190SN/A } 7152190SN/A 7162292SN/A /** The global sequence number counter. */ 7173093Sksewell@umich.edu InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 7181060SN/A 7192348SN/A /** Pointer to the checker, which can dynamically verify 7202348SN/A * instruction results at run time. This can be set to NULL if it 7212348SN/A * is not being used. 7222348SN/A */ 7238733Sgeoffrey.blake@arm.com Checker<Impl> *checker; 7242316SN/A 7252292SN/A /** Pointer to the system. */ 7261060SN/A System *system; 7271060SN/A 7282348SN/A /** Pointers to all of the threads in the CPU. */ 7292292SN/A std::vector<Thread *> thread; 7302260SN/A 7312292SN/A /** Threads Scheduled to Enter CPU */ 7322292SN/A std::list<int> cpuWaitList; 7332292SN/A 7342292SN/A /** The cycle that the CPU was last running, used for statistics. */ 7359180Sandreas.hansson@arm.com Cycles lastRunningCycle; 7362292SN/A 7372829Sksewell@umich.edu /** The cycle that the CPU was last activated by a new thread*/ 7382829Sksewell@umich.edu Tick lastActivatedCycle; 7392829Sksewell@umich.edu 7402292SN/A /** Mapping for system thread id to cpu id */ 7416221Snate@binkert.org std::map<ThreadID, unsigned> threadMap; 7422292SN/A 7432292SN/A /** Available thread ids in the cpu*/ 7446221Snate@binkert.org std::vector<ThreadID> tids; 7452292SN/A 7465595Sgblack@eecs.umich.edu /** CPU read function, forwards read to LSQ. */ 7476974Stjones1@inf.ed.ac.uk Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 74811302Ssteve.reinhardt@amd.com int load_idx) 7495595Sgblack@eecs.umich.edu { 75011302Ssteve.reinhardt@amd.com return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, load_idx); 7515595Sgblack@eecs.umich.edu } 7525595Sgblack@eecs.umich.edu 7535595Sgblack@eecs.umich.edu /** CPU write function, forwards write to LSQ. */ 7546974Stjones1@inf.ed.ac.uk Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 7557520Sgblack@eecs.umich.edu uint8_t *data, int store_idx) 7565595Sgblack@eecs.umich.edu { 7576974Stjones1@inf.ed.ac.uk return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 7586974Stjones1@inf.ed.ac.uk data, store_idx); 7595595Sgblack@eecs.umich.edu } 7605595Sgblack@eecs.umich.edu 7618707Sandreas.hansson@arm.com /** Used by the fetch unit to get a hold of the instruction port. */ 76211169Sandreas.hansson@arm.com MasterPort &getInstPort() override { return icachePort; } 7638707Sandreas.hansson@arm.com 7646974Stjones1@inf.ed.ac.uk /** Get the dcache port (used to find block size for translations). */ 76511169Sandreas.hansson@arm.com MasterPort &getDataPort() override { return dcachePort; } 7666974Stjones1@inf.ed.ac.uk 7672292SN/A /** Stat for total number of times the CPU is descheduled. */ 7685999Snate@binkert.org Stats::Scalar timesIdled; 7692292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 7705999Snate@binkert.org Stats::Scalar idleCycles; 7718627SAli.Saidi@ARM.com /** Stat for total number of cycles the CPU spends descheduled due to a 7728627SAli.Saidi@ARM.com * quiesce operation or waiting for an interrupt. */ 7738627SAli.Saidi@ARM.com Stats::Scalar quiesceCycles; 7742292SN/A /** Stat for the number of committed instructions per thread. */ 7755999Snate@binkert.org Stats::Vector committedInsts; 7768834Satgutier@umich.edu /** Stat for the number of committed ops (including micro ops) per thread. */ 7778834Satgutier@umich.edu Stats::Vector committedOps; 7782292SN/A /** Stat for the CPI per thread. */ 7792292SN/A Stats::Formula cpi; 7802292SN/A /** Stat for the total CPI. */ 7812292SN/A Stats::Formula totalCpi; 7822292SN/A /** Stat for the IPC per thread. */ 7832292SN/A Stats::Formula ipc; 7842292SN/A /** Stat for the total IPC. */ 7852292SN/A Stats::Formula totalIpc; 7867897Shestness@cs.utexas.edu 7877897Shestness@cs.utexas.edu //number of integer register file accesses 7887897Shestness@cs.utexas.edu Stats::Scalar intRegfileReads; 7897897Shestness@cs.utexas.edu Stats::Scalar intRegfileWrites; 7907897Shestness@cs.utexas.edu //number of float register file accesses 7917897Shestness@cs.utexas.edu Stats::Scalar fpRegfileReads; 7927897Shestness@cs.utexas.edu Stats::Scalar fpRegfileWrites; 79312109SRekai.GonzalezAlberquilla@arm.com //number of vector register file accesses 79412109SRekai.GonzalezAlberquilla@arm.com mutable Stats::Scalar vecRegfileReads; 79512109SRekai.GonzalezAlberquilla@arm.com Stats::Scalar vecRegfileWrites; 7969920Syasuko.eckert@amd.com //number of CC register file accesses 7979920Syasuko.eckert@amd.com Stats::Scalar ccRegfileReads; 7989920Syasuko.eckert@amd.com Stats::Scalar ccRegfileWrites; 7997897Shestness@cs.utexas.edu //number of misc 8007897Shestness@cs.utexas.edu Stats::Scalar miscRegfileReads; 8017897Shestness@cs.utexas.edu Stats::Scalar miscRegfileWrites; 8021060SN/A}; 8031060SN/A 8042325SN/A#endif // __CPU_O3_CPU_HH__ 805