cpu.hh revision 10698
11689SN/A/* 29608Sandreas.hansson@arm.com * Copyright (c) 2011-2013 ARM Limited 39919Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48707Sandreas.hansson@arm.com * All rights reserved 58707Sandreas.hansson@arm.com * 68707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148707Sandreas.hansson@arm.com * 151689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 167897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 171689SN/A * All rights reserved. 181689SN/A * 191689SN/A * Redistribution and use in source and binary forms, with or without 201689SN/A * modification, are permitted provided that the following conditions are 211689SN/A * met: redistributions of source code must retain the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer; 231689SN/A * redistributions in binary form must reproduce the above copyright 241689SN/A * notice, this list of conditions and the following disclaimer in the 251689SN/A * documentation and/or other materials provided with the distribution; 261689SN/A * neither the name of the copyright holders nor the names of its 271689SN/A * contributors may be used to endorse or promote products derived from 281689SN/A * this software without specific prior written permission. 291689SN/A * 301689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 432756Sksewell@umich.edu * Korey Sewell 447897Shestness@cs.utexas.edu * Rick Strong 451689SN/A */ 461689SN/A 472325SN/A#ifndef __CPU_O3_CPU_HH__ 482325SN/A#define __CPU_O3_CPU_HH__ 491060SN/A 501060SN/A#include <iostream> 511060SN/A#include <list> 522292SN/A#include <queue> 532292SN/A#include <set> 541681SN/A#include <vector> 551060SN/A 562980Sgblack@eecs.umich.edu#include "arch/types.hh" 571060SN/A#include "base/statistics.hh" 586658Snate@binkert.org#include "config/the_isa.hh" 591717SN/A#include "cpu/o3/comm.hh" 601717SN/A#include "cpu/o3/cpu_policy.hh" 612292SN/A#include "cpu/o3/scoreboard.hh" 622292SN/A#include "cpu/o3/thread_state.hh" 638229Snate@binkert.org#include "cpu/activity.hh" 648229Snate@binkert.org#include "cpu/base.hh" 658229Snate@binkert.org#include "cpu/simple_thread.hh" 668229Snate@binkert.org#include "cpu/timebuf.hh" 672817Sksewell@umich.edu//#include "cpu/o3/thread_context.hh" 688229Snate@binkert.org#include "params/DerivO3CPU.hh" 691060SN/A#include "sim/process.hh" 701060SN/A 712316SN/Atemplate <class> 722316SN/Aclass Checker; 732680Sktlim@umich.educlass ThreadContext; 742817Sksewell@umich.edutemplate <class> 752817Sksewell@umich.educlass O3ThreadContext; 762843Sktlim@umich.edu 772843Sktlim@umich.educlass Checkpoint; 782669Sktlim@umich.educlass MemObject; 791060SN/Aclass Process; 801060SN/A 818737Skoansin.tan@gmail.comstruct BaseCPUParams; 825529Snate@binkert.org 832733Sktlim@umich.educlass BaseO3CPU : public BaseCPU 841060SN/A{ 851060SN/A //Stuff that's pretty ISA independent will go here. 861060SN/A public: 875529Snate@binkert.org BaseO3CPU(BaseCPUParams *params); 882292SN/A 892292SN/A void regStats(); 901060SN/A}; 911060SN/A 922348SN/A/** 932348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 942348SN/A * within it, as well as all of the time buffers between stages. The 952348SN/A * tick() function for the CPU is defined here. 962348SN/A */ 971060SN/Atemplate <class Impl> 982733Sktlim@umich.educlass FullO3CPU : public BaseO3CPU 991060SN/A{ 1001060SN/A public: 1012325SN/A // Typedefs from the Impl here. 1021060SN/A typedef typename Impl::CPUPol CPUPolicy; 1031061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1044329Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 1051060SN/A 1065595Sgblack@eecs.umich.edu typedef O3ThreadState<Impl> ImplState; 1072292SN/A typedef O3ThreadState<Impl> Thread; 1082292SN/A 1092292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 1102292SN/A 1112817Sksewell@umich.edu friend class O3ThreadContext<Impl>; 1122829Sksewell@umich.edu 1131060SN/A public: 1141060SN/A enum Status { 1151060SN/A Running, 1161060SN/A Idle, 1171060SN/A Halted, 1182307SN/A Blocked, 1192307SN/A SwitchedOut 1201060SN/A }; 1211060SN/A 1226022Sgblack@eecs.umich.edu TheISA::TLB * itb; 1236022Sgblack@eecs.umich.edu TheISA::TLB * dtb; 1243781Sgblack@eecs.umich.edu 1252292SN/A /** Overall CPU status. */ 1261060SN/A Status _status; 1271060SN/A 1281060SN/A private: 1298707Sandreas.hansson@arm.com 1308707Sandreas.hansson@arm.com /** 1318707Sandreas.hansson@arm.com * IcachePort class for instruction fetch. 1328707Sandreas.hansson@arm.com */ 1339608Sandreas.hansson@arm.com class IcachePort : public MasterPort 1348707Sandreas.hansson@arm.com { 1358707Sandreas.hansson@arm.com protected: 1368707Sandreas.hansson@arm.com /** Pointer to fetch. */ 1378707Sandreas.hansson@arm.com DefaultFetch<Impl> *fetch; 1388707Sandreas.hansson@arm.com 1398707Sandreas.hansson@arm.com public: 1408707Sandreas.hansson@arm.com /** Default constructor. */ 1418707Sandreas.hansson@arm.com IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 1429608Sandreas.hansson@arm.com : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) 1438707Sandreas.hansson@arm.com { } 1448707Sandreas.hansson@arm.com 1458707Sandreas.hansson@arm.com protected: 1468707Sandreas.hansson@arm.com 1478707Sandreas.hansson@arm.com /** Timing version of receive. Handles setting fetch to the 1488707Sandreas.hansson@arm.com * proper status to start fetching. */ 1498975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 1508975Sandreas.hansson@arm.com virtual void recvTimingSnoopReq(PacketPtr pkt) { } 1518707Sandreas.hansson@arm.com 1528707Sandreas.hansson@arm.com /** Handles doing a retry of a failed fetch. */ 1538707Sandreas.hansson@arm.com virtual void recvRetry(); 1548707Sandreas.hansson@arm.com }; 1558707Sandreas.hansson@arm.com 1568707Sandreas.hansson@arm.com /** 1578707Sandreas.hansson@arm.com * DcachePort class for the load/store queue. 1588707Sandreas.hansson@arm.com */ 1599608Sandreas.hansson@arm.com class DcachePort : public MasterPort 1608707Sandreas.hansson@arm.com { 1618707Sandreas.hansson@arm.com protected: 1628707Sandreas.hansson@arm.com 1638707Sandreas.hansson@arm.com /** Pointer to LSQ. */ 1648707Sandreas.hansson@arm.com LSQ<Impl> *lsq; 16510529Smorr@cs.wisc.edu FullO3CPU<Impl> *cpu; 1668707Sandreas.hansson@arm.com 1678707Sandreas.hansson@arm.com public: 1688707Sandreas.hansson@arm.com /** Default constructor. */ 1698707Sandreas.hansson@arm.com DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) 17010529Smorr@cs.wisc.edu : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), 17110529Smorr@cs.wisc.edu cpu(_cpu) 1728707Sandreas.hansson@arm.com { } 1738707Sandreas.hansson@arm.com 1748707Sandreas.hansson@arm.com protected: 1758707Sandreas.hansson@arm.com 1768707Sandreas.hansson@arm.com /** Timing version of receive. Handles writing back and 1778707Sandreas.hansson@arm.com * completing the load or store that has returned from 1788707Sandreas.hansson@arm.com * memory. */ 1798975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 1808975Sandreas.hansson@arm.com virtual void recvTimingSnoopReq(PacketPtr pkt); 1818707Sandreas.hansson@arm.com 1829608Sandreas.hansson@arm.com virtual void recvFunctionalSnoop(PacketPtr pkt) 1839608Sandreas.hansson@arm.com { 1849608Sandreas.hansson@arm.com // @todo: Is there a need for potential invalidation here? 1859608Sandreas.hansson@arm.com } 1869608Sandreas.hansson@arm.com 1878707Sandreas.hansson@arm.com /** Handles doing a retry of the previous send. */ 1888707Sandreas.hansson@arm.com virtual void recvRetry(); 1898707Sandreas.hansson@arm.com 1908707Sandreas.hansson@arm.com /** 1918707Sandreas.hansson@arm.com * As this CPU requires snooping to maintain the load store queue 1928707Sandreas.hansson@arm.com * change the behaviour from the base CPU port. 1938707Sandreas.hansson@arm.com * 1948711Sandreas.hansson@arm.com * @return true since we have to snoop 1958707Sandreas.hansson@arm.com */ 1968922Swilliam.wang@arm.com virtual bool isSnooping() const { return true; } 1978707Sandreas.hansson@arm.com }; 1988707Sandreas.hansson@arm.com 1991060SN/A class TickEvent : public Event 2001060SN/A { 2011060SN/A private: 2022292SN/A /** Pointer to the CPU. */ 2031755SN/A FullO3CPU<Impl> *cpu; 2041060SN/A 2051060SN/A public: 2062292SN/A /** Constructs a tick event. */ 2071755SN/A TickEvent(FullO3CPU<Impl> *c); 2082292SN/A 2092292SN/A /** Processes a tick event, calling tick() on the CPU. */ 2101060SN/A void process(); 2112292SN/A /** Returns the description of the tick event. */ 2125336Shines@cs.fsu.edu const char *description() const; 2131060SN/A }; 2141060SN/A 2152292SN/A /** The tick event used for scheduling CPU ticks. */ 2161060SN/A TickEvent tickEvent; 2171060SN/A 2182292SN/A /** Schedule tick event, regardless of its current state. */ 2199180Sandreas.hansson@arm.com void scheduleTickEvent(Cycles delay) 2201060SN/A { 2211060SN/A if (tickEvent.squashed()) 2229179Sandreas.hansson@arm.com reschedule(tickEvent, clockEdge(delay)); 2231060SN/A else if (!tickEvent.scheduled()) 2249179Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(delay)); 2251060SN/A } 2261060SN/A 2272292SN/A /** Unschedule tick event, regardless of its current state. */ 2281060SN/A void unscheduleTickEvent() 2291060SN/A { 2301060SN/A if (tickEvent.scheduled()) 2311060SN/A tickEvent.squash(); 2321060SN/A } 2331060SN/A 2349444SAndreas.Sandberg@ARM.com /** 2359444SAndreas.Sandberg@ARM.com * Check if the pipeline has drained and signal the DrainManager. 2369444SAndreas.Sandberg@ARM.com * 2379444SAndreas.Sandberg@ARM.com * This method checks if a drain has been requested and if the CPU 2389444SAndreas.Sandberg@ARM.com * has drained successfully (i.e., there are no instructions in 2399444SAndreas.Sandberg@ARM.com * the pipeline). If the CPU has drained, it deschedules the tick 2409444SAndreas.Sandberg@ARM.com * event and signals the drain manager. 2419444SAndreas.Sandberg@ARM.com * 2429444SAndreas.Sandberg@ARM.com * @return False if a drain hasn't been requested or the CPU 2439444SAndreas.Sandberg@ARM.com * hasn't drained, true otherwise. 2449444SAndreas.Sandberg@ARM.com */ 2459444SAndreas.Sandberg@ARM.com bool tryDrain(); 2469444SAndreas.Sandberg@ARM.com 2479444SAndreas.Sandberg@ARM.com /** 2489444SAndreas.Sandberg@ARM.com * Perform sanity checks after a drain. 2499444SAndreas.Sandberg@ARM.com * 2509444SAndreas.Sandberg@ARM.com * This method is called from drain() when it has determined that 2519444SAndreas.Sandberg@ARM.com * the CPU is fully drained when gem5 is compiled with the NDEBUG 2529444SAndreas.Sandberg@ARM.com * macro undefined. The intention of this method is to do more 2539444SAndreas.Sandberg@ARM.com * extensive tests than the isDrained() method to weed out any 2549444SAndreas.Sandberg@ARM.com * draining bugs. 2559444SAndreas.Sandberg@ARM.com */ 2569444SAndreas.Sandberg@ARM.com void drainSanityCheck() const; 2579444SAndreas.Sandberg@ARM.com 2589444SAndreas.Sandberg@ARM.com /** Check if a system is in a drained state. */ 2599444SAndreas.Sandberg@ARM.com bool isDrained() const; 2609444SAndreas.Sandberg@ARM.com 2611060SN/A public: 2622292SN/A /** Constructs a CPU with the given parameters. */ 2635595Sgblack@eecs.umich.edu FullO3CPU(DerivO3CPUParams *params); 2642292SN/A /** Destructor. */ 2651755SN/A ~FullO3CPU(); 2661060SN/A 2672292SN/A /** Registers statistics. */ 2685595Sgblack@eecs.umich.edu void regStats(); 2691684SN/A 27010023Smatt.horsnell@ARM.com ProbePointArg<PacketPtr> *ppInstAccessComplete; 27110023Smatt.horsnell@ARM.com ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete; 27210023Smatt.horsnell@ARM.com 27310023Smatt.horsnell@ARM.com /** Register probe points. */ 27410023Smatt.horsnell@ARM.com void regProbePoints(); 27510023Smatt.horsnell@ARM.com 2765358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 2775358Sgblack@eecs.umich.edu { 2785358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2795358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2805358Sgblack@eecs.umich.edu } 2815358Sgblack@eecs.umich.edu 2825358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 2835358Sgblack@eecs.umich.edu { 2845358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 2855358Sgblack@eecs.umich.edu } 2865358Sgblack@eecs.umich.edu 2875358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 2885358Sgblack@eecs.umich.edu { 2895358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 2905358Sgblack@eecs.umich.edu } 2915358Sgblack@eecs.umich.edu 2922292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 2932292SN/A * activity to see if the CPU should deschedule itself. 2942292SN/A */ 2951684SN/A void tick(); 2961684SN/A 2972292SN/A /** Initialize the CPU */ 2981060SN/A void init(); 2991060SN/A 3009427SAndreas.Sandberg@ARM.com void startup(); 3019427SAndreas.Sandberg@ARM.com 3022834Sksewell@umich.edu /** Returns the Number of Active Threads in the CPU */ 3032834Sksewell@umich.edu int numActiveThreads() 3042834Sksewell@umich.edu { return activeThreads.size(); } 3052834Sksewell@umich.edu 3062829Sksewell@umich.edu /** Add Thread to Active Threads List */ 3076221Snate@binkert.org void activateThread(ThreadID tid); 3082875Sksewell@umich.edu 3092875Sksewell@umich.edu /** Remove Thread from Active Threads List */ 3106221Snate@binkert.org void deactivateThread(ThreadID tid); 3112829Sksewell@umich.edu 3122292SN/A /** Setup CPU to insert a thread's context */ 3136221Snate@binkert.org void insertThread(ThreadID tid); 3141060SN/A 3152292SN/A /** Remove all of a thread's context from CPU */ 3166221Snate@binkert.org void removeThread(ThreadID tid); 3172292SN/A 3182292SN/A /** Count the Total Instructions Committed in the CPU. */ 3198834Satgutier@umich.edu virtual Counter totalInsts() const; 3208834Satgutier@umich.edu 3218834Satgutier@umich.edu /** Count the Total Ops (including micro ops) committed in the CPU. */ 3228834Satgutier@umich.edu virtual Counter totalOps() const; 3232292SN/A 3242292SN/A /** Add Thread to Active Threads List. */ 32510407Smitch.hayenga@arm.com void activateContext(ThreadID tid); 3262292SN/A 3272292SN/A /** Remove Thread from Active Threads List */ 3286221Snate@binkert.org void suspendContext(ThreadID tid); 3292292SN/A 3302292SN/A /** Remove Thread from Active Threads List && 3312292SN/A * Remove Thread Context from CPU. 3322292SN/A */ 3336221Snate@binkert.org void haltContext(ThreadID tid); 3342292SN/A 3352292SN/A /** Update The Order In Which We Process Threads. */ 3362292SN/A void updateThreadPriority(); 3372292SN/A 3389444SAndreas.Sandberg@ARM.com /** Is the CPU draining? */ 3399444SAndreas.Sandberg@ARM.com bool isDraining() const { return getDrainState() == Drainable::Draining; } 3409444SAndreas.Sandberg@ARM.com 3419448SAndreas.Sandberg@ARM.com void serializeThread(std::ostream &os, ThreadID tid); 3422864Sktlim@umich.edu 3439448SAndreas.Sandberg@ARM.com void unserializeThread(Checkpoint *cp, const std::string §ion, 3449448SAndreas.Sandberg@ARM.com ThreadID tid); 3452864Sktlim@umich.edu 3462864Sktlim@umich.edu public: 3475595Sgblack@eecs.umich.edu /** Executes a syscall. 3485595Sgblack@eecs.umich.edu * @todo: Determine if this needs to be virtual. 3492292SN/A */ 3506221Snate@binkert.org void syscall(int64_t callnum, ThreadID tid); 3512292SN/A 3522843Sktlim@umich.edu /** Starts draining the CPU's pipeline of all instructions in 3532843Sktlim@umich.edu * order to stop all memory accesses. */ 3549342SAndreas.Sandberg@arm.com unsigned int drain(DrainManager *drain_manager); 3552843Sktlim@umich.edu 3562843Sktlim@umich.edu /** Resumes execution after a drain. */ 3579342SAndreas.Sandberg@arm.com void drainResume(); 3582292SN/A 3599444SAndreas.Sandberg@ARM.com /** 3609444SAndreas.Sandberg@ARM.com * Commit has reached a safe point to drain a thread. 3619444SAndreas.Sandberg@ARM.com * 3629444SAndreas.Sandberg@ARM.com * Commit calls this method to inform the pipeline that it has 3639444SAndreas.Sandberg@ARM.com * reached a point where it is not executed microcode and is about 3649444SAndreas.Sandberg@ARM.com * to squash uncommitted instructions to fully drain the pipeline. 3659444SAndreas.Sandberg@ARM.com */ 3669444SAndreas.Sandberg@ARM.com void commitDrained(ThreadID tid); 3672843Sktlim@umich.edu 3682843Sktlim@umich.edu /** Switches out this CPU. */ 3692843Sktlim@umich.edu virtual void switchOut(); 3702316SN/A 3712348SN/A /** Takes over from another CPU. */ 3722843Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *oldCPU); 3731060SN/A 3749523SAndreas.Sandberg@ARM.com void verifyMemoryMode() const; 3759523SAndreas.Sandberg@ARM.com 3761060SN/A /** Get the current instruction sequence number, and increment it. */ 3772316SN/A InstSeqNum getAndIncrementInstSeq() 3782316SN/A { return globalSeqNum++; } 3791060SN/A 3805595Sgblack@eecs.umich.edu /** Traps to handle given fault. */ 38110417Sandreas.hansson@arm.com void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst); 3825595Sgblack@eecs.umich.edu 3835702Ssaidi@eecs.umich.edu /** HW return from error interrupt. */ 3846221Snate@binkert.org Fault hwrei(ThreadID tid); 3855702Ssaidi@eecs.umich.edu 3866221Snate@binkert.org bool simPalCheck(int palFunc, ThreadID tid); 3875702Ssaidi@eecs.umich.edu 3885595Sgblack@eecs.umich.edu /** Returns the Fault for any valid interrupt. */ 3895595Sgblack@eecs.umich.edu Fault getInterrupts(); 3905595Sgblack@eecs.umich.edu 3915595Sgblack@eecs.umich.edu /** Processes any an interrupt fault. */ 39210379Sandreas.hansson@arm.com void processInterrupts(const Fault &interrupt); 3935595Sgblack@eecs.umich.edu 3945595Sgblack@eecs.umich.edu /** Halts the CPU. */ 3955595Sgblack@eecs.umich.edu void halt() { panic("Halt not implemented!\n"); } 3965595Sgblack@eecs.umich.edu 3971060SN/A /** Check if this address is a valid instruction address. */ 3981060SN/A bool validInstAddr(Addr addr) { return true; } 3991060SN/A 4001060SN/A /** Check if this address is a valid data address. */ 4011060SN/A bool validDataAddr(Addr addr) { return true; } 4021060SN/A 4032348SN/A /** Register accessors. Index refers to the physical register index. */ 4045595Sgblack@eecs.umich.edu 4055595Sgblack@eecs.umich.edu /** Reads a miscellaneous register. */ 40610698Sandreas.hansson@arm.com TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const; 4075595Sgblack@eecs.umich.edu 4085595Sgblack@eecs.umich.edu /** Reads a misc. register, including any side effects the read 4095595Sgblack@eecs.umich.edu * might have as defined by the architecture. 4105595Sgblack@eecs.umich.edu */ 4116221Snate@binkert.org TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 4125595Sgblack@eecs.umich.edu 4135595Sgblack@eecs.umich.edu /** Sets a miscellaneous register. */ 4146221Snate@binkert.org void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 4156221Snate@binkert.org ThreadID tid); 4165595Sgblack@eecs.umich.edu 4175595Sgblack@eecs.umich.edu /** Sets a misc. register, including any side effects the write 4185595Sgblack@eecs.umich.edu * might have as defined by the architecture. 4195595Sgblack@eecs.umich.edu */ 4205595Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 4216221Snate@binkert.org ThreadID tid); 4225595Sgblack@eecs.umich.edu 4231060SN/A uint64_t readIntReg(int reg_idx); 4241060SN/A 4253781Sgblack@eecs.umich.edu TheISA::FloatReg readFloatReg(int reg_idx); 4261060SN/A 4273781Sgblack@eecs.umich.edu TheISA::FloatRegBits readFloatRegBits(int reg_idx); 4282455SN/A 4299920Syasuko.eckert@amd.com TheISA::CCReg readCCReg(int reg_idx); 4309920Syasuko.eckert@amd.com 4311060SN/A void setIntReg(int reg_idx, uint64_t val); 4321060SN/A 4333781Sgblack@eecs.umich.edu void setFloatReg(int reg_idx, TheISA::FloatReg val); 4341060SN/A 4353781Sgblack@eecs.umich.edu void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 4362455SN/A 4379920Syasuko.eckert@amd.com void setCCReg(int reg_idx, TheISA::CCReg val); 4389920Syasuko.eckert@amd.com 4396221Snate@binkert.org uint64_t readArchIntReg(int reg_idx, ThreadID tid); 4401060SN/A 4416314Sgblack@eecs.umich.edu float readArchFloatReg(int reg_idx, ThreadID tid); 4422292SN/A 4436221Snate@binkert.org uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 4442292SN/A 4459920Syasuko.eckert@amd.com TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid); 4469920Syasuko.eckert@amd.com 4472348SN/A /** Architectural register accessors. Looks up in the commit 4482348SN/A * rename table to obtain the true physical index of the 4492348SN/A * architected register first, then accesses that physical 4502348SN/A * register. 4512348SN/A */ 4526221Snate@binkert.org void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 4532292SN/A 4546314Sgblack@eecs.umich.edu void setArchFloatReg(int reg_idx, float val, ThreadID tid); 4552292SN/A 4566221Snate@binkert.org void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 4572292SN/A 4589920Syasuko.eckert@amd.com void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid); 4599920Syasuko.eckert@amd.com 4607720Sgblack@eecs.umich.edu /** Sets the commit PC state of a specific thread. */ 4617720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &newPCState, ThreadID tid); 4627720Sgblack@eecs.umich.edu 4637720Sgblack@eecs.umich.edu /** Reads the commit PC state of a specific thread. */ 4647720Sgblack@eecs.umich.edu TheISA::PCState pcState(ThreadID tid); 4657720Sgblack@eecs.umich.edu 4662348SN/A /** Reads the commit PC of a specific thread. */ 4677720Sgblack@eecs.umich.edu Addr instAddr(ThreadID tid); 4682292SN/A 4694636Sgblack@eecs.umich.edu /** Reads the commit micro PC of a specific thread. */ 4707720Sgblack@eecs.umich.edu MicroPC microPC(ThreadID tid); 4714636Sgblack@eecs.umich.edu 4722348SN/A /** Reads the next PC of a specific thread. */ 4737720Sgblack@eecs.umich.edu Addr nextInstAddr(ThreadID tid); 4742756Sksewell@umich.edu 4755595Sgblack@eecs.umich.edu /** Initiates a squash of all in-flight instructions for a given 4765595Sgblack@eecs.umich.edu * thread. The source of the squash is an external update of 4775595Sgblack@eecs.umich.edu * state through the TC. 4785595Sgblack@eecs.umich.edu */ 4796221Snate@binkert.org void squashFromTC(ThreadID tid); 4805595Sgblack@eecs.umich.edu 4811060SN/A /** Function to add instruction onto the head of the list of the 4821060SN/A * instructions. Used when new instructions are fetched. 4831060SN/A */ 4842292SN/A ListIt addInst(DynInstPtr &inst); 4851060SN/A 4861060SN/A /** Function to tell the CPU that an instruction has completed. */ 4878834Satgutier@umich.edu void instDone(ThreadID tid, DynInstPtr &inst); 4881060SN/A 4892325SN/A /** Remove an instruction from the front end of the list. There's 4902325SN/A * no restriction on location of the instruction. 4911060SN/A */ 4921061SN/A void removeFrontInst(DynInstPtr &inst); 4931060SN/A 4942935Sksewell@umich.edu /** Remove all instructions that are not currently in the ROB. 4952935Sksewell@umich.edu * There's also an option to not squash delay slot instructions.*/ 4966221Snate@binkert.org void removeInstsNotInROB(ThreadID tid); 4971060SN/A 4981062SN/A /** Remove all instructions younger than the given sequence number. */ 4996221Snate@binkert.org void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 5002292SN/A 5012348SN/A /** Removes the instruction pointed to by the iterator. */ 5026221Snate@binkert.org inline void squashInstIt(const ListIt &instIt, ThreadID tid); 5032292SN/A 5042348SN/A /** Cleans up all instructions on the remove list. */ 5052292SN/A void cleanUpRemovedInsts(); 5061062SN/A 5072348SN/A /** Debug function to print all instructions on the list. */ 5081060SN/A void dumpInsts(); 5091060SN/A 5101060SN/A public: 5115737Scws3k@cs.virginia.edu#ifndef NDEBUG 5125737Scws3k@cs.virginia.edu /** Count of total number of dynamic instructions in flight. */ 5135737Scws3k@cs.virginia.edu int instcount; 5145737Scws3k@cs.virginia.edu#endif 5155737Scws3k@cs.virginia.edu 5161060SN/A /** List of all the instructions in flight. */ 5172292SN/A std::list<DynInstPtr> instList; 5181060SN/A 5192292SN/A /** List of all the instructions that will be removed at the end of this 5202292SN/A * cycle. 5212292SN/A */ 5222292SN/A std::queue<ListIt> removeList; 5232292SN/A 5242325SN/A#ifdef DEBUG 5252348SN/A /** Debug structure to keep track of the sequence numbers still in 5262348SN/A * flight. 5272348SN/A */ 5282292SN/A std::set<InstSeqNum> snList; 5292325SN/A#endif 5302292SN/A 5312325SN/A /** Records if instructions need to be removed this cycle due to 5322325SN/A * being retired or squashed. 5332292SN/A */ 5342292SN/A bool removeInstsThisCycle; 5352292SN/A 5361060SN/A protected: 5371060SN/A /** The fetch stage. */ 5381060SN/A typename CPUPolicy::Fetch fetch; 5391060SN/A 5401060SN/A /** The decode stage. */ 5411060SN/A typename CPUPolicy::Decode decode; 5421060SN/A 5431060SN/A /** The dispatch stage. */ 5441060SN/A typename CPUPolicy::Rename rename; 5451060SN/A 5461060SN/A /** The issue/execute/writeback stages. */ 5471060SN/A typename CPUPolicy::IEW iew; 5481060SN/A 5491060SN/A /** The commit stage. */ 5501060SN/A typename CPUPolicy::Commit commit; 5511060SN/A 5521060SN/A /** The register file. */ 5539919Ssteve.reinhardt@amd.com PhysRegFile regFile; 5541060SN/A 5551060SN/A /** The free list. */ 5561060SN/A typename CPUPolicy::FreeList freeList; 5571060SN/A 5581060SN/A /** The rename map. */ 5592292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 5602292SN/A 5612292SN/A /** The commit rename map. */ 5622292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 5631060SN/A 5641060SN/A /** The re-order buffer. */ 5651060SN/A typename CPUPolicy::ROB rob; 5661060SN/A 5672292SN/A /** Active Threads List */ 5686221Snate@binkert.org std::list<ThreadID> activeThreads; 5692292SN/A 5702292SN/A /** Integer Register Scoreboard */ 5712292SN/A Scoreboard scoreboard; 5722292SN/A 5739384SAndreas.Sandberg@arm.com std::vector<TheISA::ISA *> isa; 5746313Sgblack@eecs.umich.edu 5758707Sandreas.hansson@arm.com /** Instruction port. Note that it has to appear after the fetch stage. */ 5768707Sandreas.hansson@arm.com IcachePort icachePort; 5778707Sandreas.hansson@arm.com 5788707Sandreas.hansson@arm.com /** Data port. Note that it has to appear after the iew stages */ 5798707Sandreas.hansson@arm.com DcachePort dcachePort; 5808707Sandreas.hansson@arm.com 5811060SN/A public: 5822292SN/A /** Enum to give each stage a specific index, so when calling 5832292SN/A * activateStage() or deactivateStage(), they can specify which stage 5842292SN/A * is being activated/deactivated. 5852292SN/A */ 5862292SN/A enum StageIdx { 5872292SN/A FetchIdx, 5882292SN/A DecodeIdx, 5892292SN/A RenameIdx, 5902292SN/A IEWIdx, 5912292SN/A CommitIdx, 5922292SN/A NumStages }; 5932292SN/A 5941060SN/A /** Typedefs from the Impl to get the structs that each of the 5951060SN/A * time buffers should use. 5961060SN/A */ 5971061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 5981060SN/A 5991061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 6001060SN/A 6011061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 6021060SN/A 6031061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 6041060SN/A 6051061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 6061060SN/A 6071060SN/A /** The main time buffer to do backwards communication. */ 6081060SN/A TimeBuffer<TimeStruct> timeBuffer; 6091060SN/A 6101060SN/A /** The fetch stage's instruction queue. */ 6111060SN/A TimeBuffer<FetchStruct> fetchQueue; 6121060SN/A 6131060SN/A /** The decode stage's instruction queue. */ 6141060SN/A TimeBuffer<DecodeStruct> decodeQueue; 6151060SN/A 6161060SN/A /** The rename stage's instruction queue. */ 6171060SN/A TimeBuffer<RenameStruct> renameQueue; 6181060SN/A 6191060SN/A /** The IEW stage's instruction queue. */ 6201060SN/A TimeBuffer<IEWStruct> iewQueue; 6211060SN/A 6222348SN/A private: 6232348SN/A /** The activity recorder; used to tell if the CPU has any 6242348SN/A * activity remaining or if it can go to idle and deschedule 6252348SN/A * itself. 6262348SN/A */ 6272325SN/A ActivityRecorder activityRec; 6281060SN/A 6292348SN/A public: 6302348SN/A /** Records that there was time buffer activity this cycle. */ 6312325SN/A void activityThisCycle() { activityRec.activity(); } 6322292SN/A 6332348SN/A /** Changes a stage's status to active within the activity recorder. */ 6342325SN/A void activateStage(const StageIdx idx) 6352325SN/A { activityRec.activateStage(idx); } 6362292SN/A 6372348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 6382325SN/A void deactivateStage(const StageIdx idx) 6392325SN/A { activityRec.deactivateStage(idx); } 6402292SN/A 6412292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 6422292SN/A void wakeCPU(); 6432260SN/A 6445807Snate@binkert.org virtual void wakeup(); 6455807Snate@binkert.org 6462292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 6476221Snate@binkert.org ThreadID getFreeTid(); 6482292SN/A 6492292SN/A public: 6502680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 6516221Snate@binkert.org ThreadContext * 6526221Snate@binkert.org tcBase(ThreadID tid) 6531681SN/A { 6542680Sktlim@umich.edu return thread[tid]->getTC(); 6552190SN/A } 6562190SN/A 6572292SN/A /** The global sequence number counter. */ 6583093Sksewell@umich.edu InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 6591060SN/A 6602348SN/A /** Pointer to the checker, which can dynamically verify 6612348SN/A * instruction results at run time. This can be set to NULL if it 6622348SN/A * is not being used. 6632348SN/A */ 6648733Sgeoffrey.blake@arm.com Checker<Impl> *checker; 6652316SN/A 6662292SN/A /** Pointer to the system. */ 6671060SN/A System *system; 6681060SN/A 6699342SAndreas.Sandberg@arm.com /** DrainManager to notify when draining has completed. */ 6709342SAndreas.Sandberg@arm.com DrainManager *drainManager; 6712843Sktlim@umich.edu 6722348SN/A /** Pointers to all of the threads in the CPU. */ 6732292SN/A std::vector<Thread *> thread; 6742260SN/A 6752292SN/A /** Threads Scheduled to Enter CPU */ 6762292SN/A std::list<int> cpuWaitList; 6772292SN/A 6782292SN/A /** The cycle that the CPU was last running, used for statistics. */ 6799180Sandreas.hansson@arm.com Cycles lastRunningCycle; 6802292SN/A 6812829Sksewell@umich.edu /** The cycle that the CPU was last activated by a new thread*/ 6822829Sksewell@umich.edu Tick lastActivatedCycle; 6832829Sksewell@umich.edu 6842292SN/A /** Mapping for system thread id to cpu id */ 6856221Snate@binkert.org std::map<ThreadID, unsigned> threadMap; 6862292SN/A 6872292SN/A /** Available thread ids in the cpu*/ 6886221Snate@binkert.org std::vector<ThreadID> tids; 6892292SN/A 6905595Sgblack@eecs.umich.edu /** CPU read function, forwards read to LSQ. */ 6916974Stjones1@inf.ed.ac.uk Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 6927520Sgblack@eecs.umich.edu uint8_t *data, int load_idx) 6935595Sgblack@eecs.umich.edu { 6946974Stjones1@inf.ed.ac.uk return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, 6956974Stjones1@inf.ed.ac.uk data, load_idx); 6965595Sgblack@eecs.umich.edu } 6975595Sgblack@eecs.umich.edu 6985595Sgblack@eecs.umich.edu /** CPU write function, forwards write to LSQ. */ 6996974Stjones1@inf.ed.ac.uk Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 7007520Sgblack@eecs.umich.edu uint8_t *data, int store_idx) 7015595Sgblack@eecs.umich.edu { 7026974Stjones1@inf.ed.ac.uk return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 7036974Stjones1@inf.ed.ac.uk data, store_idx); 7045595Sgblack@eecs.umich.edu } 7055595Sgblack@eecs.umich.edu 7068707Sandreas.hansson@arm.com /** Used by the fetch unit to get a hold of the instruction port. */ 7079608Sandreas.hansson@arm.com virtual MasterPort &getInstPort() { return icachePort; } 7088707Sandreas.hansson@arm.com 7096974Stjones1@inf.ed.ac.uk /** Get the dcache port (used to find block size for translations). */ 7109608Sandreas.hansson@arm.com virtual MasterPort &getDataPort() { return dcachePort; } 7116974Stjones1@inf.ed.ac.uk 7122292SN/A /** Stat for total number of times the CPU is descheduled. */ 7135999Snate@binkert.org Stats::Scalar timesIdled; 7142292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 7155999Snate@binkert.org Stats::Scalar idleCycles; 7168627SAli.Saidi@ARM.com /** Stat for total number of cycles the CPU spends descheduled due to a 7178627SAli.Saidi@ARM.com * quiesce operation or waiting for an interrupt. */ 7188627SAli.Saidi@ARM.com Stats::Scalar quiesceCycles; 7192292SN/A /** Stat for the number of committed instructions per thread. */ 7205999Snate@binkert.org Stats::Vector committedInsts; 7218834Satgutier@umich.edu /** Stat for the number of committed ops (including micro ops) per thread. */ 7228834Satgutier@umich.edu Stats::Vector committedOps; 7232292SN/A /** Stat for the CPI per thread. */ 7242292SN/A Stats::Formula cpi; 7252292SN/A /** Stat for the total CPI. */ 7262292SN/A Stats::Formula totalCpi; 7272292SN/A /** Stat for the IPC per thread. */ 7282292SN/A Stats::Formula ipc; 7292292SN/A /** Stat for the total IPC. */ 7302292SN/A Stats::Formula totalIpc; 7317897Shestness@cs.utexas.edu 7327897Shestness@cs.utexas.edu //number of integer register file accesses 7337897Shestness@cs.utexas.edu Stats::Scalar intRegfileReads; 7347897Shestness@cs.utexas.edu Stats::Scalar intRegfileWrites; 7357897Shestness@cs.utexas.edu //number of float register file accesses 7367897Shestness@cs.utexas.edu Stats::Scalar fpRegfileReads; 7377897Shestness@cs.utexas.edu Stats::Scalar fpRegfileWrites; 7389920Syasuko.eckert@amd.com //number of CC register file accesses 7399920Syasuko.eckert@amd.com Stats::Scalar ccRegfileReads; 7409920Syasuko.eckert@amd.com Stats::Scalar ccRegfileWrites; 7417897Shestness@cs.utexas.edu //number of misc 7427897Shestness@cs.utexas.edu Stats::Scalar miscRegfileReads; 7437897Shestness@cs.utexas.edu Stats::Scalar miscRegfileWrites; 7441060SN/A}; 7451060SN/A 7462325SN/A#endif // __CPU_O3_CPU_HH__ 747