cpu.hh revision 10023
11689SN/A/* 29608Sandreas.hansson@arm.com * Copyright (c) 2011-2013 ARM Limited 39919Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48707Sandreas.hansson@arm.com * All rights reserved 58707Sandreas.hansson@arm.com * 68707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148707Sandreas.hansson@arm.com * 151689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 167897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 171689SN/A * All rights reserved. 181689SN/A * 191689SN/A * Redistribution and use in source and binary forms, with or without 201689SN/A * modification, are permitted provided that the following conditions are 211689SN/A * met: redistributions of source code must retain the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer; 231689SN/A * redistributions in binary form must reproduce the above copyright 241689SN/A * notice, this list of conditions and the following disclaimer in the 251689SN/A * documentation and/or other materials provided with the distribution; 261689SN/A * neither the name of the copyright holders nor the names of its 271689SN/A * contributors may be used to endorse or promote products derived from 281689SN/A * this software without specific prior written permission. 291689SN/A * 301689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 432756Sksewell@umich.edu * Korey Sewell 447897Shestness@cs.utexas.edu * Rick Strong 451689SN/A */ 461689SN/A 472325SN/A#ifndef __CPU_O3_CPU_HH__ 482325SN/A#define __CPU_O3_CPU_HH__ 491060SN/A 501060SN/A#include <iostream> 511060SN/A#include <list> 522292SN/A#include <queue> 532292SN/A#include <set> 541681SN/A#include <vector> 551060SN/A 562980Sgblack@eecs.umich.edu#include "arch/types.hh" 571060SN/A#include "base/statistics.hh" 586658Snate@binkert.org#include "config/the_isa.hh" 591717SN/A#include "cpu/o3/comm.hh" 601717SN/A#include "cpu/o3/cpu_policy.hh" 612292SN/A#include "cpu/o3/scoreboard.hh" 622292SN/A#include "cpu/o3/thread_state.hh" 638229Snate@binkert.org#include "cpu/activity.hh" 648229Snate@binkert.org#include "cpu/base.hh" 658229Snate@binkert.org#include "cpu/simple_thread.hh" 668229Snate@binkert.org#include "cpu/timebuf.hh" 672817Sksewell@umich.edu//#include "cpu/o3/thread_context.hh" 688229Snate@binkert.org#include "params/DerivO3CPU.hh" 691060SN/A#include "sim/process.hh" 701060SN/A 712316SN/Atemplate <class> 722316SN/Aclass Checker; 732680Sktlim@umich.educlass ThreadContext; 742817Sksewell@umich.edutemplate <class> 752817Sksewell@umich.educlass O3ThreadContext; 762843Sktlim@umich.edu 772843Sktlim@umich.educlass Checkpoint; 782669Sktlim@umich.educlass MemObject; 791060SN/Aclass Process; 801060SN/A 818737Skoansin.tan@gmail.comstruct BaseCPUParams; 825529Snate@binkert.org 832733Sktlim@umich.educlass BaseO3CPU : public BaseCPU 841060SN/A{ 851060SN/A //Stuff that's pretty ISA independent will go here. 861060SN/A public: 875529Snate@binkert.org BaseO3CPU(BaseCPUParams *params); 882292SN/A 892292SN/A void regStats(); 901060SN/A}; 911060SN/A 922348SN/A/** 932348SN/A * FullO3CPU class, has each of the stages (fetch through commit) 942348SN/A * within it, as well as all of the time buffers between stages. The 952348SN/A * tick() function for the CPU is defined here. 962348SN/A */ 971060SN/Atemplate <class Impl> 982733Sktlim@umich.educlass FullO3CPU : public BaseO3CPU 991060SN/A{ 1001060SN/A public: 1012325SN/A // Typedefs from the Impl here. 1021060SN/A typedef typename Impl::CPUPol CPUPolicy; 1031061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1044329Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 1051060SN/A 1065595Sgblack@eecs.umich.edu typedef O3ThreadState<Impl> ImplState; 1072292SN/A typedef O3ThreadState<Impl> Thread; 1082292SN/A 1092292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 1102292SN/A 1112817Sksewell@umich.edu friend class O3ThreadContext<Impl>; 1122829Sksewell@umich.edu 1131060SN/A public: 1141060SN/A enum Status { 1151060SN/A Running, 1161060SN/A Idle, 1171060SN/A Halted, 1182307SN/A Blocked, 1192307SN/A SwitchedOut 1201060SN/A }; 1211060SN/A 1226022Sgblack@eecs.umich.edu TheISA::TLB * itb; 1236022Sgblack@eecs.umich.edu TheISA::TLB * dtb; 1243781Sgblack@eecs.umich.edu 1252292SN/A /** Overall CPU status. */ 1261060SN/A Status _status; 1271060SN/A 1281060SN/A private: 1298707Sandreas.hansson@arm.com 1308707Sandreas.hansson@arm.com /** 1318707Sandreas.hansson@arm.com * IcachePort class for instruction fetch. 1328707Sandreas.hansson@arm.com */ 1339608Sandreas.hansson@arm.com class IcachePort : public MasterPort 1348707Sandreas.hansson@arm.com { 1358707Sandreas.hansson@arm.com protected: 1368707Sandreas.hansson@arm.com /** Pointer to fetch. */ 1378707Sandreas.hansson@arm.com DefaultFetch<Impl> *fetch; 1388707Sandreas.hansson@arm.com 1398707Sandreas.hansson@arm.com public: 1408707Sandreas.hansson@arm.com /** Default constructor. */ 1418707Sandreas.hansson@arm.com IcachePort(DefaultFetch<Impl> *_fetch, FullO3CPU<Impl>* _cpu) 1429608Sandreas.hansson@arm.com : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch) 1438707Sandreas.hansson@arm.com { } 1448707Sandreas.hansson@arm.com 1458707Sandreas.hansson@arm.com protected: 1468707Sandreas.hansson@arm.com 1478707Sandreas.hansson@arm.com /** Timing version of receive. Handles setting fetch to the 1488707Sandreas.hansson@arm.com * proper status to start fetching. */ 1498975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 1508975Sandreas.hansson@arm.com virtual void recvTimingSnoopReq(PacketPtr pkt) { } 1518707Sandreas.hansson@arm.com 1528707Sandreas.hansson@arm.com /** Handles doing a retry of a failed fetch. */ 1538707Sandreas.hansson@arm.com virtual void recvRetry(); 1548707Sandreas.hansson@arm.com }; 1558707Sandreas.hansson@arm.com 1568707Sandreas.hansson@arm.com /** 1578707Sandreas.hansson@arm.com * DcachePort class for the load/store queue. 1588707Sandreas.hansson@arm.com */ 1599608Sandreas.hansson@arm.com class DcachePort : public MasterPort 1608707Sandreas.hansson@arm.com { 1618707Sandreas.hansson@arm.com protected: 1628707Sandreas.hansson@arm.com 1638707Sandreas.hansson@arm.com /** Pointer to LSQ. */ 1648707Sandreas.hansson@arm.com LSQ<Impl> *lsq; 1658707Sandreas.hansson@arm.com 1668707Sandreas.hansson@arm.com public: 1678707Sandreas.hansson@arm.com /** Default constructor. */ 1688707Sandreas.hansson@arm.com DcachePort(LSQ<Impl> *_lsq, FullO3CPU<Impl>* _cpu) 1699608Sandreas.hansson@arm.com : MasterPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq) 1708707Sandreas.hansson@arm.com { } 1718707Sandreas.hansson@arm.com 1728707Sandreas.hansson@arm.com protected: 1738707Sandreas.hansson@arm.com 1748707Sandreas.hansson@arm.com /** Timing version of receive. Handles writing back and 1758707Sandreas.hansson@arm.com * completing the load or store that has returned from 1768707Sandreas.hansson@arm.com * memory. */ 1778975Sandreas.hansson@arm.com virtual bool recvTimingResp(PacketPtr pkt); 1788975Sandreas.hansson@arm.com virtual void recvTimingSnoopReq(PacketPtr pkt); 1798707Sandreas.hansson@arm.com 1809608Sandreas.hansson@arm.com virtual void recvFunctionalSnoop(PacketPtr pkt) 1819608Sandreas.hansson@arm.com { 1829608Sandreas.hansson@arm.com // @todo: Is there a need for potential invalidation here? 1839608Sandreas.hansson@arm.com } 1849608Sandreas.hansson@arm.com 1858707Sandreas.hansson@arm.com /** Handles doing a retry of the previous send. */ 1868707Sandreas.hansson@arm.com virtual void recvRetry(); 1878707Sandreas.hansson@arm.com 1888707Sandreas.hansson@arm.com /** 1898707Sandreas.hansson@arm.com * As this CPU requires snooping to maintain the load store queue 1908707Sandreas.hansson@arm.com * change the behaviour from the base CPU port. 1918707Sandreas.hansson@arm.com * 1928711Sandreas.hansson@arm.com * @return true since we have to snoop 1938707Sandreas.hansson@arm.com */ 1948922Swilliam.wang@arm.com virtual bool isSnooping() const { return true; } 1958707Sandreas.hansson@arm.com }; 1968707Sandreas.hansson@arm.com 1971060SN/A class TickEvent : public Event 1981060SN/A { 1991060SN/A private: 2002292SN/A /** Pointer to the CPU. */ 2011755SN/A FullO3CPU<Impl> *cpu; 2021060SN/A 2031060SN/A public: 2042292SN/A /** Constructs a tick event. */ 2051755SN/A TickEvent(FullO3CPU<Impl> *c); 2062292SN/A 2072292SN/A /** Processes a tick event, calling tick() on the CPU. */ 2081060SN/A void process(); 2092292SN/A /** Returns the description of the tick event. */ 2105336Shines@cs.fsu.edu const char *description() const; 2111060SN/A }; 2121060SN/A 2132292SN/A /** The tick event used for scheduling CPU ticks. */ 2141060SN/A TickEvent tickEvent; 2151060SN/A 2162292SN/A /** Schedule tick event, regardless of its current state. */ 2179180Sandreas.hansson@arm.com void scheduleTickEvent(Cycles delay) 2181060SN/A { 2191060SN/A if (tickEvent.squashed()) 2209179Sandreas.hansson@arm.com reschedule(tickEvent, clockEdge(delay)); 2211060SN/A else if (!tickEvent.scheduled()) 2229179Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(delay)); 2231060SN/A } 2241060SN/A 2252292SN/A /** Unschedule tick event, regardless of its current state. */ 2261060SN/A void unscheduleTickEvent() 2271060SN/A { 2281060SN/A if (tickEvent.scheduled()) 2291060SN/A tickEvent.squash(); 2301060SN/A } 2311060SN/A 2322829Sksewell@umich.edu class ActivateThreadEvent : public Event 2332829Sksewell@umich.edu { 2342829Sksewell@umich.edu private: 2352829Sksewell@umich.edu /** Number of Thread to Activate */ 2366221Snate@binkert.org ThreadID tid; 2372829Sksewell@umich.edu 2382829Sksewell@umich.edu /** Pointer to the CPU. */ 2392829Sksewell@umich.edu FullO3CPU<Impl> *cpu; 2402829Sksewell@umich.edu 2412829Sksewell@umich.edu public: 2422829Sksewell@umich.edu /** Constructs the event. */ 2432829Sksewell@umich.edu ActivateThreadEvent(); 2442829Sksewell@umich.edu 2452829Sksewell@umich.edu /** Initialize Event */ 2462829Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 2472829Sksewell@umich.edu 2482829Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 2492829Sksewell@umich.edu void process(); 2502829Sksewell@umich.edu 2512829Sksewell@umich.edu /** Returns the description of the event. */ 2525336Shines@cs.fsu.edu const char *description() const; 2532829Sksewell@umich.edu }; 2542829Sksewell@umich.edu 2552829Sksewell@umich.edu /** Schedule thread to activate , regardless of its current state. */ 2566221Snate@binkert.org void 2579180Sandreas.hansson@arm.com scheduleActivateThreadEvent(ThreadID tid, Cycles delay) 2582829Sksewell@umich.edu { 2592829Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 2602829Sksewell@umich.edu if (activateThreadEvent[tid].squashed()) 2615606Snate@binkert.org reschedule(activateThreadEvent[tid], 2629179Sandreas.hansson@arm.com clockEdge(delay)); 2638518Sgeoffrey.blake@arm.com else if (!activateThreadEvent[tid].scheduled()) { 2649179Sandreas.hansson@arm.com Tick when = clockEdge(delay); 2658518Sgeoffrey.blake@arm.com 2668518Sgeoffrey.blake@arm.com // Check if the deallocateEvent is also scheduled, and make 2678518Sgeoffrey.blake@arm.com // sure they do not happen at same time causing a sleep that 2688518Sgeoffrey.blake@arm.com // is never woken from. 2698518Sgeoffrey.blake@arm.com if (deallocateContextEvent[tid].scheduled() && 2708518Sgeoffrey.blake@arm.com deallocateContextEvent[tid].when() == when) { 2718518Sgeoffrey.blake@arm.com when++; 2728518Sgeoffrey.blake@arm.com } 2738518Sgeoffrey.blake@arm.com 2748518Sgeoffrey.blake@arm.com schedule(activateThreadEvent[tid], when); 2758518Sgeoffrey.blake@arm.com } 2762829Sksewell@umich.edu } 2772829Sksewell@umich.edu 2782829Sksewell@umich.edu /** Unschedule actiavte thread event, regardless of its current state. */ 2796221Snate@binkert.org void 2806221Snate@binkert.org unscheduleActivateThreadEvent(ThreadID tid) 2812829Sksewell@umich.edu { 2822829Sksewell@umich.edu if (activateThreadEvent[tid].scheduled()) 2832829Sksewell@umich.edu activateThreadEvent[tid].squash(); 2842829Sksewell@umich.edu } 2852829Sksewell@umich.edu 2862829Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 2872829Sksewell@umich.edu ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; 2882829Sksewell@umich.edu 2892875Sksewell@umich.edu class DeallocateContextEvent : public Event 2902875Sksewell@umich.edu { 2912875Sksewell@umich.edu private: 2923221Sktlim@umich.edu /** Number of Thread to deactivate */ 2936221Snate@binkert.org ThreadID tid; 2942875Sksewell@umich.edu 2953221Sktlim@umich.edu /** Should the thread be removed from the CPU? */ 2963221Sktlim@umich.edu bool remove; 2973221Sktlim@umich.edu 2982875Sksewell@umich.edu /** Pointer to the CPU. */ 2992875Sksewell@umich.edu FullO3CPU<Impl> *cpu; 3002875Sksewell@umich.edu 3012875Sksewell@umich.edu public: 3022875Sksewell@umich.edu /** Constructs the event. */ 3032875Sksewell@umich.edu DeallocateContextEvent(); 3042875Sksewell@umich.edu 3052875Sksewell@umich.edu /** Initialize Event */ 3062875Sksewell@umich.edu void init(int thread_num, FullO3CPU<Impl> *thread_cpu); 3072875Sksewell@umich.edu 3082875Sksewell@umich.edu /** Processes the event, calling activateThread() on the CPU. */ 3092875Sksewell@umich.edu void process(); 3102875Sksewell@umich.edu 3113221Sktlim@umich.edu /** Sets whether the thread should also be removed from the CPU. */ 3123221Sktlim@umich.edu void setRemove(bool _remove) { remove = _remove; } 3133221Sktlim@umich.edu 3142875Sksewell@umich.edu /** Returns the description of the event. */ 3155336Shines@cs.fsu.edu const char *description() const; 3162875Sksewell@umich.edu }; 3172875Sksewell@umich.edu 3182875Sksewell@umich.edu /** Schedule cpu to deallocate thread context.*/ 3196221Snate@binkert.org void 3209180Sandreas.hansson@arm.com scheduleDeallocateContextEvent(ThreadID tid, bool remove, Cycles delay) 3212875Sksewell@umich.edu { 3222875Sksewell@umich.edu // Schedule thread to activate, regardless of its current state. 3232875Sksewell@umich.edu if (deallocateContextEvent[tid].squashed()) 3245606Snate@binkert.org reschedule(deallocateContextEvent[tid], 3259179Sandreas.hansson@arm.com clockEdge(delay)); 3262875Sksewell@umich.edu else if (!deallocateContextEvent[tid].scheduled()) 3275606Snate@binkert.org schedule(deallocateContextEvent[tid], 3289179Sandreas.hansson@arm.com clockEdge(delay)); 3292875Sksewell@umich.edu } 3302875Sksewell@umich.edu 3312875Sksewell@umich.edu /** Unschedule thread deallocation in CPU */ 3326221Snate@binkert.org void 3336221Snate@binkert.org unscheduleDeallocateContextEvent(ThreadID tid) 3342875Sksewell@umich.edu { 3352875Sksewell@umich.edu if (deallocateContextEvent[tid].scheduled()) 3362875Sksewell@umich.edu deallocateContextEvent[tid].squash(); 3372875Sksewell@umich.edu } 3382875Sksewell@umich.edu 3392875Sksewell@umich.edu /** The tick event used for scheduling CPU ticks. */ 3402875Sksewell@umich.edu DeallocateContextEvent deallocateContextEvent[Impl::MaxThreads]; 3412875Sksewell@umich.edu 3429444SAndreas.Sandberg@ARM.com /** 3439444SAndreas.Sandberg@ARM.com * Check if the pipeline has drained and signal the DrainManager. 3449444SAndreas.Sandberg@ARM.com * 3459444SAndreas.Sandberg@ARM.com * This method checks if a drain has been requested and if the CPU 3469444SAndreas.Sandberg@ARM.com * has drained successfully (i.e., there are no instructions in 3479444SAndreas.Sandberg@ARM.com * the pipeline). If the CPU has drained, it deschedules the tick 3489444SAndreas.Sandberg@ARM.com * event and signals the drain manager. 3499444SAndreas.Sandberg@ARM.com * 3509444SAndreas.Sandberg@ARM.com * @return False if a drain hasn't been requested or the CPU 3519444SAndreas.Sandberg@ARM.com * hasn't drained, true otherwise. 3529444SAndreas.Sandberg@ARM.com */ 3539444SAndreas.Sandberg@ARM.com bool tryDrain(); 3549444SAndreas.Sandberg@ARM.com 3559444SAndreas.Sandberg@ARM.com /** 3569444SAndreas.Sandberg@ARM.com * Perform sanity checks after a drain. 3579444SAndreas.Sandberg@ARM.com * 3589444SAndreas.Sandberg@ARM.com * This method is called from drain() when it has determined that 3599444SAndreas.Sandberg@ARM.com * the CPU is fully drained when gem5 is compiled with the NDEBUG 3609444SAndreas.Sandberg@ARM.com * macro undefined. The intention of this method is to do more 3619444SAndreas.Sandberg@ARM.com * extensive tests than the isDrained() method to weed out any 3629444SAndreas.Sandberg@ARM.com * draining bugs. 3639444SAndreas.Sandberg@ARM.com */ 3649444SAndreas.Sandberg@ARM.com void drainSanityCheck() const; 3659444SAndreas.Sandberg@ARM.com 3669444SAndreas.Sandberg@ARM.com /** Check if a system is in a drained state. */ 3679444SAndreas.Sandberg@ARM.com bool isDrained() const; 3689444SAndreas.Sandberg@ARM.com 3691060SN/A public: 3702292SN/A /** Constructs a CPU with the given parameters. */ 3715595Sgblack@eecs.umich.edu FullO3CPU(DerivO3CPUParams *params); 3722292SN/A /** Destructor. */ 3731755SN/A ~FullO3CPU(); 3741060SN/A 3752292SN/A /** Registers statistics. */ 3765595Sgblack@eecs.umich.edu void regStats(); 3771684SN/A 37810023Smatt.horsnell@ARM.com ProbePointArg<PacketPtr> *ppInstAccessComplete; 37910023Smatt.horsnell@ARM.com ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete; 38010023Smatt.horsnell@ARM.com 38110023Smatt.horsnell@ARM.com /** Register probe points. */ 38210023Smatt.horsnell@ARM.com void regProbePoints(); 38310023Smatt.horsnell@ARM.com 3845358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 3855358Sgblack@eecs.umich.edu { 3865358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3875358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3885358Sgblack@eecs.umich.edu } 3895358Sgblack@eecs.umich.edu 3905358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3915358Sgblack@eecs.umich.edu { 3925358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3935358Sgblack@eecs.umich.edu } 3945358Sgblack@eecs.umich.edu 3955358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3965358Sgblack@eecs.umich.edu { 3975358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3985358Sgblack@eecs.umich.edu } 3995358Sgblack@eecs.umich.edu 4002292SN/A /** Ticks CPU, calling tick() on each stage, and checking the overall 4012292SN/A * activity to see if the CPU should deschedule itself. 4022292SN/A */ 4031684SN/A void tick(); 4041684SN/A 4052292SN/A /** Initialize the CPU */ 4061060SN/A void init(); 4071060SN/A 4089427SAndreas.Sandberg@ARM.com void startup(); 4099427SAndreas.Sandberg@ARM.com 4102834Sksewell@umich.edu /** Returns the Number of Active Threads in the CPU */ 4112834Sksewell@umich.edu int numActiveThreads() 4122834Sksewell@umich.edu { return activeThreads.size(); } 4132834Sksewell@umich.edu 4142829Sksewell@umich.edu /** Add Thread to Active Threads List */ 4156221Snate@binkert.org void activateThread(ThreadID tid); 4162875Sksewell@umich.edu 4172875Sksewell@umich.edu /** Remove Thread from Active Threads List */ 4186221Snate@binkert.org void deactivateThread(ThreadID tid); 4192829Sksewell@umich.edu 4202292SN/A /** Setup CPU to insert a thread's context */ 4216221Snate@binkert.org void insertThread(ThreadID tid); 4221060SN/A 4232292SN/A /** Remove all of a thread's context from CPU */ 4246221Snate@binkert.org void removeThread(ThreadID tid); 4252292SN/A 4262292SN/A /** Count the Total Instructions Committed in the CPU. */ 4278834Satgutier@umich.edu virtual Counter totalInsts() const; 4288834Satgutier@umich.edu 4298834Satgutier@umich.edu /** Count the Total Ops (including micro ops) committed in the CPU. */ 4308834Satgutier@umich.edu virtual Counter totalOps() const; 4312292SN/A 4322292SN/A /** Add Thread to Active Threads List. */ 4339180Sandreas.hansson@arm.com void activateContext(ThreadID tid, Cycles delay); 4342292SN/A 4352292SN/A /** Remove Thread from Active Threads List */ 4366221Snate@binkert.org void suspendContext(ThreadID tid); 4372292SN/A 4382292SN/A /** Remove Thread from Active Threads List && 4393221Sktlim@umich.edu * Possibly Remove Thread Context from CPU. 4402292SN/A */ 4419180Sandreas.hansson@arm.com bool scheduleDeallocateContext(ThreadID tid, bool remove, 4429180Sandreas.hansson@arm.com Cycles delay = Cycles(1)); 4432292SN/A 4442292SN/A /** Remove Thread from Active Threads List && 4452292SN/A * Remove Thread Context from CPU. 4462292SN/A */ 4476221Snate@binkert.org void haltContext(ThreadID tid); 4482292SN/A 4492292SN/A /** Activate a Thread When CPU Resources are Available. */ 4506221Snate@binkert.org void activateWhenReady(ThreadID tid); 4512292SN/A 4522292SN/A /** Add or Remove a Thread Context in the CPU. */ 4532292SN/A void doContextSwitch(); 4542292SN/A 4552292SN/A /** Update The Order In Which We Process Threads. */ 4562292SN/A void updateThreadPriority(); 4572292SN/A 4589444SAndreas.Sandberg@ARM.com /** Is the CPU draining? */ 4599444SAndreas.Sandberg@ARM.com bool isDraining() const { return getDrainState() == Drainable::Draining; } 4609444SAndreas.Sandberg@ARM.com 4619448SAndreas.Sandberg@ARM.com void serializeThread(std::ostream &os, ThreadID tid); 4622864Sktlim@umich.edu 4639448SAndreas.Sandberg@ARM.com void unserializeThread(Checkpoint *cp, const std::string §ion, 4649448SAndreas.Sandberg@ARM.com ThreadID tid); 4652864Sktlim@umich.edu 4662864Sktlim@umich.edu public: 4675595Sgblack@eecs.umich.edu /** Executes a syscall. 4685595Sgblack@eecs.umich.edu * @todo: Determine if this needs to be virtual. 4692292SN/A */ 4706221Snate@binkert.org void syscall(int64_t callnum, ThreadID tid); 4712292SN/A 4722843Sktlim@umich.edu /** Starts draining the CPU's pipeline of all instructions in 4732843Sktlim@umich.edu * order to stop all memory accesses. */ 4749342SAndreas.Sandberg@arm.com unsigned int drain(DrainManager *drain_manager); 4752843Sktlim@umich.edu 4762843Sktlim@umich.edu /** Resumes execution after a drain. */ 4779342SAndreas.Sandberg@arm.com void drainResume(); 4782292SN/A 4799444SAndreas.Sandberg@ARM.com /** 4809444SAndreas.Sandberg@ARM.com * Commit has reached a safe point to drain a thread. 4819444SAndreas.Sandberg@ARM.com * 4829444SAndreas.Sandberg@ARM.com * Commit calls this method to inform the pipeline that it has 4839444SAndreas.Sandberg@ARM.com * reached a point where it is not executed microcode and is about 4849444SAndreas.Sandberg@ARM.com * to squash uncommitted instructions to fully drain the pipeline. 4859444SAndreas.Sandberg@ARM.com */ 4869444SAndreas.Sandberg@ARM.com void commitDrained(ThreadID tid); 4872843Sktlim@umich.edu 4882843Sktlim@umich.edu /** Switches out this CPU. */ 4892843Sktlim@umich.edu virtual void switchOut(); 4902316SN/A 4912348SN/A /** Takes over from another CPU. */ 4922843Sktlim@umich.edu virtual void takeOverFrom(BaseCPU *oldCPU); 4931060SN/A 4949523SAndreas.Sandberg@ARM.com void verifyMemoryMode() const; 4959523SAndreas.Sandberg@ARM.com 4961060SN/A /** Get the current instruction sequence number, and increment it. */ 4972316SN/A InstSeqNum getAndIncrementInstSeq() 4982316SN/A { return globalSeqNum++; } 4991060SN/A 5005595Sgblack@eecs.umich.edu /** Traps to handle given fault. */ 5017684Sgblack@eecs.umich.edu void trap(Fault fault, ThreadID tid, StaticInstPtr inst); 5025595Sgblack@eecs.umich.edu 5035702Ssaidi@eecs.umich.edu /** HW return from error interrupt. */ 5046221Snate@binkert.org Fault hwrei(ThreadID tid); 5055702Ssaidi@eecs.umich.edu 5066221Snate@binkert.org bool simPalCheck(int palFunc, ThreadID tid); 5075702Ssaidi@eecs.umich.edu 5085595Sgblack@eecs.umich.edu /** Returns the Fault for any valid interrupt. */ 5095595Sgblack@eecs.umich.edu Fault getInterrupts(); 5105595Sgblack@eecs.umich.edu 5115595Sgblack@eecs.umich.edu /** Processes any an interrupt fault. */ 5125595Sgblack@eecs.umich.edu void processInterrupts(Fault interrupt); 5135595Sgblack@eecs.umich.edu 5145595Sgblack@eecs.umich.edu /** Halts the CPU. */ 5155595Sgblack@eecs.umich.edu void halt() { panic("Halt not implemented!\n"); } 5165595Sgblack@eecs.umich.edu 5171060SN/A /** Check if this address is a valid instruction address. */ 5181060SN/A bool validInstAddr(Addr addr) { return true; } 5191060SN/A 5201060SN/A /** Check if this address is a valid data address. */ 5211060SN/A bool validDataAddr(Addr addr) { return true; } 5221060SN/A 5232348SN/A /** Register accessors. Index refers to the physical register index. */ 5245595Sgblack@eecs.umich.edu 5255595Sgblack@eecs.umich.edu /** Reads a miscellaneous register. */ 5266221Snate@binkert.org TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid); 5275595Sgblack@eecs.umich.edu 5285595Sgblack@eecs.umich.edu /** Reads a misc. register, including any side effects the read 5295595Sgblack@eecs.umich.edu * might have as defined by the architecture. 5305595Sgblack@eecs.umich.edu */ 5316221Snate@binkert.org TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid); 5325595Sgblack@eecs.umich.edu 5335595Sgblack@eecs.umich.edu /** Sets a miscellaneous register. */ 5346221Snate@binkert.org void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, 5356221Snate@binkert.org ThreadID tid); 5365595Sgblack@eecs.umich.edu 5375595Sgblack@eecs.umich.edu /** Sets a misc. register, including any side effects the write 5385595Sgblack@eecs.umich.edu * might have as defined by the architecture. 5395595Sgblack@eecs.umich.edu */ 5405595Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const TheISA::MiscReg &val, 5416221Snate@binkert.org ThreadID tid); 5425595Sgblack@eecs.umich.edu 5431060SN/A uint64_t readIntReg(int reg_idx); 5441060SN/A 5453781Sgblack@eecs.umich.edu TheISA::FloatReg readFloatReg(int reg_idx); 5461060SN/A 5473781Sgblack@eecs.umich.edu TheISA::FloatRegBits readFloatRegBits(int reg_idx); 5482455SN/A 5499920Syasuko.eckert@amd.com TheISA::CCReg readCCReg(int reg_idx); 5509920Syasuko.eckert@amd.com 5511060SN/A void setIntReg(int reg_idx, uint64_t val); 5521060SN/A 5533781Sgblack@eecs.umich.edu void setFloatReg(int reg_idx, TheISA::FloatReg val); 5541060SN/A 5553781Sgblack@eecs.umich.edu void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); 5562455SN/A 5579920Syasuko.eckert@amd.com void setCCReg(int reg_idx, TheISA::CCReg val); 5589920Syasuko.eckert@amd.com 5596221Snate@binkert.org uint64_t readArchIntReg(int reg_idx, ThreadID tid); 5601060SN/A 5616314Sgblack@eecs.umich.edu float readArchFloatReg(int reg_idx, ThreadID tid); 5622292SN/A 5636221Snate@binkert.org uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); 5642292SN/A 5659920Syasuko.eckert@amd.com TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid); 5669920Syasuko.eckert@amd.com 5672348SN/A /** Architectural register accessors. Looks up in the commit 5682348SN/A * rename table to obtain the true physical index of the 5692348SN/A * architected register first, then accesses that physical 5702348SN/A * register. 5712348SN/A */ 5726221Snate@binkert.org void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); 5732292SN/A 5746314Sgblack@eecs.umich.edu void setArchFloatReg(int reg_idx, float val, ThreadID tid); 5752292SN/A 5766221Snate@binkert.org void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); 5772292SN/A 5789920Syasuko.eckert@amd.com void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid); 5799920Syasuko.eckert@amd.com 5807720Sgblack@eecs.umich.edu /** Sets the commit PC state of a specific thread. */ 5817720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &newPCState, ThreadID tid); 5827720Sgblack@eecs.umich.edu 5837720Sgblack@eecs.umich.edu /** Reads the commit PC state of a specific thread. */ 5847720Sgblack@eecs.umich.edu TheISA::PCState pcState(ThreadID tid); 5857720Sgblack@eecs.umich.edu 5862348SN/A /** Reads the commit PC of a specific thread. */ 5877720Sgblack@eecs.umich.edu Addr instAddr(ThreadID tid); 5882292SN/A 5894636Sgblack@eecs.umich.edu /** Reads the commit micro PC of a specific thread. */ 5907720Sgblack@eecs.umich.edu MicroPC microPC(ThreadID tid); 5914636Sgblack@eecs.umich.edu 5922348SN/A /** Reads the next PC of a specific thread. */ 5937720Sgblack@eecs.umich.edu Addr nextInstAddr(ThreadID tid); 5942756Sksewell@umich.edu 5955595Sgblack@eecs.umich.edu /** Initiates a squash of all in-flight instructions for a given 5965595Sgblack@eecs.umich.edu * thread. The source of the squash is an external update of 5975595Sgblack@eecs.umich.edu * state through the TC. 5985595Sgblack@eecs.umich.edu */ 5996221Snate@binkert.org void squashFromTC(ThreadID tid); 6005595Sgblack@eecs.umich.edu 6011060SN/A /** Function to add instruction onto the head of the list of the 6021060SN/A * instructions. Used when new instructions are fetched. 6031060SN/A */ 6042292SN/A ListIt addInst(DynInstPtr &inst); 6051060SN/A 6061060SN/A /** Function to tell the CPU that an instruction has completed. */ 6078834Satgutier@umich.edu void instDone(ThreadID tid, DynInstPtr &inst); 6081060SN/A 6092325SN/A /** Remove an instruction from the front end of the list. There's 6102325SN/A * no restriction on location of the instruction. 6111060SN/A */ 6121061SN/A void removeFrontInst(DynInstPtr &inst); 6131060SN/A 6142935Sksewell@umich.edu /** Remove all instructions that are not currently in the ROB. 6152935Sksewell@umich.edu * There's also an option to not squash delay slot instructions.*/ 6166221Snate@binkert.org void removeInstsNotInROB(ThreadID tid); 6171060SN/A 6181062SN/A /** Remove all instructions younger than the given sequence number. */ 6196221Snate@binkert.org void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid); 6202292SN/A 6212348SN/A /** Removes the instruction pointed to by the iterator. */ 6226221Snate@binkert.org inline void squashInstIt(const ListIt &instIt, ThreadID tid); 6232292SN/A 6242348SN/A /** Cleans up all instructions on the remove list. */ 6252292SN/A void cleanUpRemovedInsts(); 6261062SN/A 6272348SN/A /** Debug function to print all instructions on the list. */ 6281060SN/A void dumpInsts(); 6291060SN/A 6301060SN/A public: 6315737Scws3k@cs.virginia.edu#ifndef NDEBUG 6325737Scws3k@cs.virginia.edu /** Count of total number of dynamic instructions in flight. */ 6335737Scws3k@cs.virginia.edu int instcount; 6345737Scws3k@cs.virginia.edu#endif 6355737Scws3k@cs.virginia.edu 6361060SN/A /** List of all the instructions in flight. */ 6372292SN/A std::list<DynInstPtr> instList; 6381060SN/A 6392292SN/A /** List of all the instructions that will be removed at the end of this 6402292SN/A * cycle. 6412292SN/A */ 6422292SN/A std::queue<ListIt> removeList; 6432292SN/A 6442325SN/A#ifdef DEBUG 6452348SN/A /** Debug structure to keep track of the sequence numbers still in 6462348SN/A * flight. 6472348SN/A */ 6482292SN/A std::set<InstSeqNum> snList; 6492325SN/A#endif 6502292SN/A 6512325SN/A /** Records if instructions need to be removed this cycle due to 6522325SN/A * being retired or squashed. 6532292SN/A */ 6542292SN/A bool removeInstsThisCycle; 6552292SN/A 6561060SN/A protected: 6571060SN/A /** The fetch stage. */ 6581060SN/A typename CPUPolicy::Fetch fetch; 6591060SN/A 6601060SN/A /** The decode stage. */ 6611060SN/A typename CPUPolicy::Decode decode; 6621060SN/A 6631060SN/A /** The dispatch stage. */ 6641060SN/A typename CPUPolicy::Rename rename; 6651060SN/A 6661060SN/A /** The issue/execute/writeback stages. */ 6671060SN/A typename CPUPolicy::IEW iew; 6681060SN/A 6691060SN/A /** The commit stage. */ 6701060SN/A typename CPUPolicy::Commit commit; 6711060SN/A 6721060SN/A /** The register file. */ 6739919Ssteve.reinhardt@amd.com PhysRegFile regFile; 6741060SN/A 6751060SN/A /** The free list. */ 6761060SN/A typename CPUPolicy::FreeList freeList; 6771060SN/A 6781060SN/A /** The rename map. */ 6792292SN/A typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads]; 6802292SN/A 6812292SN/A /** The commit rename map. */ 6822292SN/A typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads]; 6831060SN/A 6841060SN/A /** The re-order buffer. */ 6851060SN/A typename CPUPolicy::ROB rob; 6861060SN/A 6872292SN/A /** Active Threads List */ 6886221Snate@binkert.org std::list<ThreadID> activeThreads; 6892292SN/A 6902292SN/A /** Integer Register Scoreboard */ 6912292SN/A Scoreboard scoreboard; 6922292SN/A 6939384SAndreas.Sandberg@arm.com std::vector<TheISA::ISA *> isa; 6946313Sgblack@eecs.umich.edu 6958707Sandreas.hansson@arm.com /** Instruction port. Note that it has to appear after the fetch stage. */ 6968707Sandreas.hansson@arm.com IcachePort icachePort; 6978707Sandreas.hansson@arm.com 6988707Sandreas.hansson@arm.com /** Data port. Note that it has to appear after the iew stages */ 6998707Sandreas.hansson@arm.com DcachePort dcachePort; 7008707Sandreas.hansson@arm.com 7011060SN/A public: 7022292SN/A /** Enum to give each stage a specific index, so when calling 7032292SN/A * activateStage() or deactivateStage(), they can specify which stage 7042292SN/A * is being activated/deactivated. 7052292SN/A */ 7062292SN/A enum StageIdx { 7072292SN/A FetchIdx, 7082292SN/A DecodeIdx, 7092292SN/A RenameIdx, 7102292SN/A IEWIdx, 7112292SN/A CommitIdx, 7122292SN/A NumStages }; 7132292SN/A 7141060SN/A /** Typedefs from the Impl to get the structs that each of the 7151060SN/A * time buffers should use. 7161060SN/A */ 7171061SN/A typedef typename CPUPolicy::TimeStruct TimeStruct; 7181060SN/A 7191061SN/A typedef typename CPUPolicy::FetchStruct FetchStruct; 7201060SN/A 7211061SN/A typedef typename CPUPolicy::DecodeStruct DecodeStruct; 7221060SN/A 7231061SN/A typedef typename CPUPolicy::RenameStruct RenameStruct; 7241060SN/A 7251061SN/A typedef typename CPUPolicy::IEWStruct IEWStruct; 7261060SN/A 7271060SN/A /** The main time buffer to do backwards communication. */ 7281060SN/A TimeBuffer<TimeStruct> timeBuffer; 7291060SN/A 7301060SN/A /** The fetch stage's instruction queue. */ 7311060SN/A TimeBuffer<FetchStruct> fetchQueue; 7321060SN/A 7331060SN/A /** The decode stage's instruction queue. */ 7341060SN/A TimeBuffer<DecodeStruct> decodeQueue; 7351060SN/A 7361060SN/A /** The rename stage's instruction queue. */ 7371060SN/A TimeBuffer<RenameStruct> renameQueue; 7381060SN/A 7391060SN/A /** The IEW stage's instruction queue. */ 7401060SN/A TimeBuffer<IEWStruct> iewQueue; 7411060SN/A 7422348SN/A private: 7432348SN/A /** The activity recorder; used to tell if the CPU has any 7442348SN/A * activity remaining or if it can go to idle and deschedule 7452348SN/A * itself. 7462348SN/A */ 7472325SN/A ActivityRecorder activityRec; 7481060SN/A 7492348SN/A public: 7502348SN/A /** Records that there was time buffer activity this cycle. */ 7512325SN/A void activityThisCycle() { activityRec.activity(); } 7522292SN/A 7532348SN/A /** Changes a stage's status to active within the activity recorder. */ 7542325SN/A void activateStage(const StageIdx idx) 7552325SN/A { activityRec.activateStage(idx); } 7562292SN/A 7572348SN/A /** Changes a stage's status to inactive within the activity recorder. */ 7582325SN/A void deactivateStage(const StageIdx idx) 7592325SN/A { activityRec.deactivateStage(idx); } 7602292SN/A 7612292SN/A /** Wakes the CPU, rescheduling the CPU if it's not already active. */ 7622292SN/A void wakeCPU(); 7632260SN/A 7645807Snate@binkert.org virtual void wakeup(); 7655807Snate@binkert.org 7662292SN/A /** Gets a free thread id. Use if thread ids change across system. */ 7676221Snate@binkert.org ThreadID getFreeTid(); 7682292SN/A 7692292SN/A public: 7702680Sktlim@umich.edu /** Returns a pointer to a thread context. */ 7716221Snate@binkert.org ThreadContext * 7726221Snate@binkert.org tcBase(ThreadID tid) 7731681SN/A { 7742680Sktlim@umich.edu return thread[tid]->getTC(); 7752190SN/A } 7762190SN/A 7772292SN/A /** The global sequence number counter. */ 7783093Sksewell@umich.edu InstSeqNum globalSeqNum;//[Impl::MaxThreads]; 7791060SN/A 7802348SN/A /** Pointer to the checker, which can dynamically verify 7812348SN/A * instruction results at run time. This can be set to NULL if it 7822348SN/A * is not being used. 7832348SN/A */ 7848733Sgeoffrey.blake@arm.com Checker<Impl> *checker; 7852316SN/A 7862292SN/A /** Pointer to the system. */ 7871060SN/A System *system; 7881060SN/A 7899342SAndreas.Sandberg@arm.com /** DrainManager to notify when draining has completed. */ 7909342SAndreas.Sandberg@arm.com DrainManager *drainManager; 7912843Sktlim@umich.edu 7922348SN/A /** Pointers to all of the threads in the CPU. */ 7932292SN/A std::vector<Thread *> thread; 7942260SN/A 7952292SN/A /** Is there a context switch pending? */ 7962292SN/A bool contextSwitch; 7971060SN/A 7982292SN/A /** Threads Scheduled to Enter CPU */ 7992292SN/A std::list<int> cpuWaitList; 8002292SN/A 8012292SN/A /** The cycle that the CPU was last running, used for statistics. */ 8029180Sandreas.hansson@arm.com Cycles lastRunningCycle; 8032292SN/A 8042829Sksewell@umich.edu /** The cycle that the CPU was last activated by a new thread*/ 8052829Sksewell@umich.edu Tick lastActivatedCycle; 8062829Sksewell@umich.edu 8072292SN/A /** Mapping for system thread id to cpu id */ 8086221Snate@binkert.org std::map<ThreadID, unsigned> threadMap; 8092292SN/A 8102292SN/A /** Available thread ids in the cpu*/ 8116221Snate@binkert.org std::vector<ThreadID> tids; 8122292SN/A 8135595Sgblack@eecs.umich.edu /** CPU read function, forwards read to LSQ. */ 8146974Stjones1@inf.ed.ac.uk Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 8157520Sgblack@eecs.umich.edu uint8_t *data, int load_idx) 8165595Sgblack@eecs.umich.edu { 8176974Stjones1@inf.ed.ac.uk return this->iew.ldstQueue.read(req, sreqLow, sreqHigh, 8186974Stjones1@inf.ed.ac.uk data, load_idx); 8195595Sgblack@eecs.umich.edu } 8205595Sgblack@eecs.umich.edu 8215595Sgblack@eecs.umich.edu /** CPU write function, forwards write to LSQ. */ 8226974Stjones1@inf.ed.ac.uk Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh, 8237520Sgblack@eecs.umich.edu uint8_t *data, int store_idx) 8245595Sgblack@eecs.umich.edu { 8256974Stjones1@inf.ed.ac.uk return this->iew.ldstQueue.write(req, sreqLow, sreqHigh, 8266974Stjones1@inf.ed.ac.uk data, store_idx); 8275595Sgblack@eecs.umich.edu } 8285595Sgblack@eecs.umich.edu 8298707Sandreas.hansson@arm.com /** Used by the fetch unit to get a hold of the instruction port. */ 8309608Sandreas.hansson@arm.com virtual MasterPort &getInstPort() { return icachePort; } 8318707Sandreas.hansson@arm.com 8326974Stjones1@inf.ed.ac.uk /** Get the dcache port (used to find block size for translations). */ 8339608Sandreas.hansson@arm.com virtual MasterPort &getDataPort() { return dcachePort; } 8346974Stjones1@inf.ed.ac.uk 8352292SN/A /** Stat for total number of times the CPU is descheduled. */ 8365999Snate@binkert.org Stats::Scalar timesIdled; 8372292SN/A /** Stat for total number of cycles the CPU spends descheduled. */ 8385999Snate@binkert.org Stats::Scalar idleCycles; 8398627SAli.Saidi@ARM.com /** Stat for total number of cycles the CPU spends descheduled due to a 8408627SAli.Saidi@ARM.com * quiesce operation or waiting for an interrupt. */ 8418627SAli.Saidi@ARM.com Stats::Scalar quiesceCycles; 8422292SN/A /** Stat for the number of committed instructions per thread. */ 8435999Snate@binkert.org Stats::Vector committedInsts; 8448834Satgutier@umich.edu /** Stat for the number of committed ops (including micro ops) per thread. */ 8458834Satgutier@umich.edu Stats::Vector committedOps; 8462292SN/A /** Stat for the total number of committed instructions. */ 8475999Snate@binkert.org Stats::Scalar totalCommittedInsts; 8482292SN/A /** Stat for the CPI per thread. */ 8492292SN/A Stats::Formula cpi; 8502292SN/A /** Stat for the total CPI. */ 8512292SN/A Stats::Formula totalCpi; 8522292SN/A /** Stat for the IPC per thread. */ 8532292SN/A Stats::Formula ipc; 8542292SN/A /** Stat for the total IPC. */ 8552292SN/A Stats::Formula totalIpc; 8567897Shestness@cs.utexas.edu 8577897Shestness@cs.utexas.edu //number of integer register file accesses 8587897Shestness@cs.utexas.edu Stats::Scalar intRegfileReads; 8597897Shestness@cs.utexas.edu Stats::Scalar intRegfileWrites; 8607897Shestness@cs.utexas.edu //number of float register file accesses 8617897Shestness@cs.utexas.edu Stats::Scalar fpRegfileReads; 8627897Shestness@cs.utexas.edu Stats::Scalar fpRegfileWrites; 8639920Syasuko.eckert@amd.com //number of CC register file accesses 8649920Syasuko.eckert@amd.com Stats::Scalar ccRegfileReads; 8659920Syasuko.eckert@amd.com Stats::Scalar ccRegfileWrites; 8667897Shestness@cs.utexas.edu //number of misc 8677897Shestness@cs.utexas.edu Stats::Scalar miscRegfileReads; 8687897Shestness@cs.utexas.edu Stats::Scalar miscRegfileWrites; 8691060SN/A}; 8701060SN/A 8712325SN/A#endif // __CPU_O3_CPU_HH__ 872