cpu.cc revision 9428
1/* 2 * Copyright (c) 2011-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Korey Sewell 43 * Rick Strong 44 */ 45 46#include "arch/kernel_stats.hh" 47#include "config/the_isa.hh" 48#include "cpu/checker/cpu.hh" 49#include "cpu/checker/thread_context.hh" 50#include "cpu/o3/cpu.hh" 51#include "cpu/o3/isa_specific.hh" 52#include "cpu/o3/thread_context.hh" 53#include "cpu/activity.hh" 54#include "cpu/quiesce_event.hh" 55#include "cpu/simple_thread.hh" 56#include "cpu/thread_context.hh" 57#include "debug/Activity.hh" 58#include "debug/Drain.hh" 59#include "debug/O3CPU.hh" 60#include "debug/Quiesce.hh" 61#include "enums/MemoryMode.hh" 62#include "sim/core.hh" 63#include "sim/full_system.hh" 64#include "sim/process.hh" 65#include "sim/stat_control.hh" 66#include "sim/system.hh" 67 68#if THE_ISA == ALPHA_ISA 69#include "arch/alpha/osfpal.hh" 70#include "debug/Activity.hh" 71#endif 72 73struct BaseCPUParams; 74 75using namespace TheISA; 76using namespace std; 77 78BaseO3CPU::BaseO3CPU(BaseCPUParams *params) 79 : BaseCPU(params) 80{ 81} 82 83void 84BaseO3CPU::regStats() 85{ 86 BaseCPU::regStats(); 87} 88 89template<class Impl> 90bool 91FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt) 92{ 93 DPRINTF(O3CPU, "Fetch unit received timing\n"); 94 // We shouldn't ever get a block in ownership state 95 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); 96 fetch->processCacheCompletion(pkt); 97 98 return true; 99} 100 101template<class Impl> 102void 103FullO3CPU<Impl>::IcachePort::recvRetry() 104{ 105 fetch->recvRetry(); 106} 107 108template <class Impl> 109bool 110FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt) 111{ 112 return lsq->recvTimingResp(pkt); 113} 114 115template <class Impl> 116void 117FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 118{ 119 lsq->recvTimingSnoopReq(pkt); 120} 121 122template <class Impl> 123void 124FullO3CPU<Impl>::DcachePort::recvRetry() 125{ 126 lsq->recvRetry(); 127} 128 129template <class Impl> 130FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 131 : Event(CPU_Tick_Pri), cpu(c) 132{ 133} 134 135template <class Impl> 136void 137FullO3CPU<Impl>::TickEvent::process() 138{ 139 cpu->tick(); 140} 141 142template <class Impl> 143const char * 144FullO3CPU<Impl>::TickEvent::description() const 145{ 146 return "FullO3CPU tick"; 147} 148 149template <class Impl> 150FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 151 : Event(CPU_Switch_Pri) 152{ 153} 154 155template <class Impl> 156void 157FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 158 FullO3CPU<Impl> *thread_cpu) 159{ 160 tid = thread_num; 161 cpu = thread_cpu; 162} 163 164template <class Impl> 165void 166FullO3CPU<Impl>::ActivateThreadEvent::process() 167{ 168 cpu->activateThread(tid); 169} 170 171template <class Impl> 172const char * 173FullO3CPU<Impl>::ActivateThreadEvent::description() const 174{ 175 return "FullO3CPU \"Activate Thread\""; 176} 177 178template <class Impl> 179FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 180 : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 181{ 182} 183 184template <class Impl> 185void 186FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 187 FullO3CPU<Impl> *thread_cpu) 188{ 189 tid = thread_num; 190 cpu = thread_cpu; 191 remove = false; 192} 193 194template <class Impl> 195void 196FullO3CPU<Impl>::DeallocateContextEvent::process() 197{ 198 cpu->deactivateThread(tid); 199 if (remove) 200 cpu->removeThread(tid); 201} 202 203template <class Impl> 204const char * 205FullO3CPU<Impl>::DeallocateContextEvent::description() const 206{ 207 return "FullO3CPU \"Deallocate Context\""; 208} 209 210template <class Impl> 211FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 212 : BaseO3CPU(params), 213 itb(params->itb), 214 dtb(params->dtb), 215 tickEvent(this), 216#ifndef NDEBUG 217 instcount(0), 218#endif 219 removeInstsThisCycle(false), 220 fetch(this, params), 221 decode(this, params), 222 rename(this, params), 223 iew(this, params), 224 commit(this, params), 225 226 regFile(this, params->numPhysIntRegs, 227 params->numPhysFloatRegs), 228 229 freeList(params->numThreads, 230 TheISA::NumIntRegs, params->numPhysIntRegs, 231 TheISA::NumFloatRegs, params->numPhysFloatRegs), 232 233 rob(this, 234 params->numROBEntries, params->squashWidth, 235 params->smtROBPolicy, params->smtROBThreshold, 236 params->numThreads), 237 238 scoreboard(params->numThreads, 239 TheISA::NumIntRegs, params->numPhysIntRegs, 240 TheISA::NumFloatRegs, params->numPhysFloatRegs, 241 TheISA::NumMiscRegs * numThreads, 242 TheISA::ZeroReg), 243 244 isa(numThreads, NULL), 245 246 icachePort(&fetch, this), 247 dcachePort(&iew.ldstQueue, this), 248 249 timeBuffer(params->backComSize, params->forwardComSize), 250 fetchQueue(params->backComSize, params->forwardComSize), 251 decodeQueue(params->backComSize, params->forwardComSize), 252 renameQueue(params->backComSize, params->forwardComSize), 253 iewQueue(params->backComSize, params->forwardComSize), 254 activityRec(name(), NumStages, 255 params->backComSize + params->forwardComSize, 256 params->activity), 257 258 globalSeqNum(1), 259 system(params->system), 260 drainCount(0), 261 deferRegistration(params->defer_registration), 262 lastRunningCycle(curCycle()) 263{ 264 if (!deferRegistration) { 265 _status = Running; 266 } else { 267 _status = SwitchedOut; 268 } 269 270 if (params->checker) { 271 BaseCPU *temp_checker = params->checker; 272 checker = dynamic_cast<Checker<Impl> *>(temp_checker); 273 checker->setIcachePort(&icachePort); 274 checker->setSystem(params->system); 275 } else { 276 checker = NULL; 277 } 278 279 if (!FullSystem) { 280 thread.resize(numThreads); 281 tids.resize(numThreads); 282 } 283 284 // The stages also need their CPU pointer setup. However this 285 // must be done at the upper level CPU because they have pointers 286 // to the upper level CPU, and not this FullO3CPU. 287 288 // Set up Pointers to the activeThreads list for each stage 289 fetch.setActiveThreads(&activeThreads); 290 decode.setActiveThreads(&activeThreads); 291 rename.setActiveThreads(&activeThreads); 292 iew.setActiveThreads(&activeThreads); 293 commit.setActiveThreads(&activeThreads); 294 295 // Give each of the stages the time buffer they will use. 296 fetch.setTimeBuffer(&timeBuffer); 297 decode.setTimeBuffer(&timeBuffer); 298 rename.setTimeBuffer(&timeBuffer); 299 iew.setTimeBuffer(&timeBuffer); 300 commit.setTimeBuffer(&timeBuffer); 301 302 // Also setup each of the stages' queues. 303 fetch.setFetchQueue(&fetchQueue); 304 decode.setFetchQueue(&fetchQueue); 305 commit.setFetchQueue(&fetchQueue); 306 decode.setDecodeQueue(&decodeQueue); 307 rename.setDecodeQueue(&decodeQueue); 308 rename.setRenameQueue(&renameQueue); 309 iew.setRenameQueue(&renameQueue); 310 iew.setIEWQueue(&iewQueue); 311 commit.setIEWQueue(&iewQueue); 312 commit.setRenameQueue(&renameQueue); 313 314 commit.setIEWStage(&iew); 315 rename.setIEWStage(&iew); 316 rename.setCommitStage(&commit); 317 318 ThreadID active_threads; 319 if (FullSystem) { 320 active_threads = 1; 321 } else { 322 active_threads = params->workload.size(); 323 324 if (active_threads > Impl::MaxThreads) { 325 panic("Workload Size too large. Increase the 'MaxThreads' " 326 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 327 "or edit your workload size."); 328 } 329 } 330 331 //Make Sure That this a Valid Architeture 332 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 333 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 334 335 rename.setScoreboard(&scoreboard); 336 iew.setScoreboard(&scoreboard); 337 338 // Setup the rename map for whichever stages need it. 339 PhysRegIndex lreg_idx = 0; 340 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 341 342 for (ThreadID tid = 0; tid < numThreads; tid++) { 343 bool bindRegs = (tid <= active_threads - 1); 344 345 isa[tid] = params->isa[tid]; 346 347 commitRenameMap[tid].init(TheISA::NumIntRegs, 348 params->numPhysIntRegs, 349 lreg_idx, //Index for Logical. Regs 350 351 TheISA::NumFloatRegs, 352 params->numPhysFloatRegs, 353 freg_idx, //Index for Float Regs 354 355 TheISA::NumMiscRegs, 356 357 TheISA::ZeroReg, 358 TheISA::ZeroReg, 359 360 tid, 361 false); 362 363 renameMap[tid].init(TheISA::NumIntRegs, 364 params->numPhysIntRegs, 365 lreg_idx, //Index for Logical. Regs 366 367 TheISA::NumFloatRegs, 368 params->numPhysFloatRegs, 369 freg_idx, //Index for Float Regs 370 371 TheISA::NumMiscRegs, 372 373 TheISA::ZeroReg, 374 TheISA::ZeroReg, 375 376 tid, 377 bindRegs); 378 379 activateThreadEvent[tid].init(tid, this); 380 deallocateContextEvent[tid].init(tid, this); 381 } 382 383 rename.setRenameMap(renameMap); 384 commit.setRenameMap(commitRenameMap); 385 386 // Give renameMap & rename stage access to the freeList; 387 for (ThreadID tid = 0; tid < numThreads; tid++) 388 renameMap[tid].setFreeList(&freeList); 389 rename.setFreeList(&freeList); 390 391 // Setup the ROB for whichever stages need it. 392 commit.setROB(&rob); 393 394 lastActivatedCycle = 0; 395#if 0 396 // Give renameMap & rename stage access to the freeList; 397 for (ThreadID tid = 0; tid < numThreads; tid++) 398 globalSeqNum[tid] = 1; 399#endif 400 401 contextSwitch = false; 402 DPRINTF(O3CPU, "Creating O3CPU object.\n"); 403 404 // Setup any thread state. 405 this->thread.resize(this->numThreads); 406 407 for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 408 if (FullSystem) { 409 // SMT is not supported in FS mode yet. 410 assert(this->numThreads == 1); 411 this->thread[tid] = new Thread(this, 0, NULL); 412 } else { 413 if (tid < params->workload.size()) { 414 DPRINTF(O3CPU, "Workload[%i] process is %#x", 415 tid, this->thread[tid]); 416 this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 417 (typename Impl::O3CPU *)(this), 418 tid, params->workload[tid]); 419 420 //usedTids[tid] = true; 421 //threadMap[tid] = tid; 422 } else { 423 //Allocate Empty thread so M5 can use later 424 //when scheduling threads to CPU 425 Process* dummy_proc = NULL; 426 427 this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 428 (typename Impl::O3CPU *)(this), 429 tid, dummy_proc); 430 //usedTids[tid] = false; 431 } 432 } 433 434 ThreadContext *tc; 435 436 // Setup the TC that will serve as the interface to the threads/CPU. 437 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 438 439 tc = o3_tc; 440 441 // If we're using a checker, then the TC should be the 442 // CheckerThreadContext. 443 if (params->checker) { 444 tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 445 o3_tc, this->checker); 446 } 447 448 o3_tc->cpu = (typename Impl::O3CPU *)(this); 449 assert(o3_tc->cpu); 450 o3_tc->thread = this->thread[tid]; 451 452 if (FullSystem) { 453 // Setup quiesce event. 454 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 455 } 456 // Give the thread the TC. 457 this->thread[tid]->tc = tc; 458 459 // Add the TC to the CPU's list of TC's. 460 this->threadContexts.push_back(tc); 461 } 462 463 // FullO3CPU always requires an interrupt controller. 464 if (!params->defer_registration && !interrupts) { 465 fatal("FullO3CPU %s has no interrupt controller.\n" 466 "Ensure createInterruptController() is called.\n", name()); 467 } 468 469 for (ThreadID tid = 0; tid < this->numThreads; tid++) 470 this->thread[tid]->setFuncExeInst(0); 471 472 lockAddr = 0; 473 lockFlag = false; 474} 475 476template <class Impl> 477FullO3CPU<Impl>::~FullO3CPU() 478{ 479} 480 481template <class Impl> 482void 483FullO3CPU<Impl>::regStats() 484{ 485 BaseO3CPU::regStats(); 486 487 // Register any of the O3CPU's stats here. 488 timesIdled 489 .name(name() + ".timesIdled") 490 .desc("Number of times that the entire CPU went into an idle state and" 491 " unscheduled itself") 492 .prereq(timesIdled); 493 494 idleCycles 495 .name(name() + ".idleCycles") 496 .desc("Total number of cycles that the CPU has spent unscheduled due " 497 "to idling") 498 .prereq(idleCycles); 499 500 quiesceCycles 501 .name(name() + ".quiesceCycles") 502 .desc("Total number of cycles that CPU has spent quiesced or waiting " 503 "for an interrupt") 504 .prereq(quiesceCycles); 505 506 // Number of Instructions simulated 507 // -------------------------------- 508 // Should probably be in Base CPU but need templated 509 // MaxThreads so put in here instead 510 committedInsts 511 .init(numThreads) 512 .name(name() + ".committedInsts") 513 .desc("Number of Instructions Simulated"); 514 515 committedOps 516 .init(numThreads) 517 .name(name() + ".committedOps") 518 .desc("Number of Ops (including micro ops) Simulated"); 519 520 totalCommittedInsts 521 .name(name() + ".committedInsts_total") 522 .desc("Number of Instructions Simulated"); 523 524 cpi 525 .name(name() + ".cpi") 526 .desc("CPI: Cycles Per Instruction") 527 .precision(6); 528 cpi = numCycles / committedInsts; 529 530 totalCpi 531 .name(name() + ".cpi_total") 532 .desc("CPI: Total CPI of All Threads") 533 .precision(6); 534 totalCpi = numCycles / totalCommittedInsts; 535 536 ipc 537 .name(name() + ".ipc") 538 .desc("IPC: Instructions Per Cycle") 539 .precision(6); 540 ipc = committedInsts / numCycles; 541 542 totalIpc 543 .name(name() + ".ipc_total") 544 .desc("IPC: Total IPC of All Threads") 545 .precision(6); 546 totalIpc = totalCommittedInsts / numCycles; 547 548 this->fetch.regStats(); 549 this->decode.regStats(); 550 this->rename.regStats(); 551 this->iew.regStats(); 552 this->commit.regStats(); 553 this->rob.regStats(); 554 555 intRegfileReads 556 .name(name() + ".int_regfile_reads") 557 .desc("number of integer regfile reads") 558 .prereq(intRegfileReads); 559 560 intRegfileWrites 561 .name(name() + ".int_regfile_writes") 562 .desc("number of integer regfile writes") 563 .prereq(intRegfileWrites); 564 565 fpRegfileReads 566 .name(name() + ".fp_regfile_reads") 567 .desc("number of floating regfile reads") 568 .prereq(fpRegfileReads); 569 570 fpRegfileWrites 571 .name(name() + ".fp_regfile_writes") 572 .desc("number of floating regfile writes") 573 .prereq(fpRegfileWrites); 574 575 miscRegfileReads 576 .name(name() + ".misc_regfile_reads") 577 .desc("number of misc regfile reads") 578 .prereq(miscRegfileReads); 579 580 miscRegfileWrites 581 .name(name() + ".misc_regfile_writes") 582 .desc("number of misc regfile writes") 583 .prereq(miscRegfileWrites); 584} 585 586template <class Impl> 587void 588FullO3CPU<Impl>::tick() 589{ 590 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 591 592 ++numCycles; 593 594// activity = false; 595 596 //Tick each of the stages 597 fetch.tick(); 598 599 decode.tick(); 600 601 rename.tick(); 602 603 iew.tick(); 604 605 commit.tick(); 606 607 if (!FullSystem) 608 doContextSwitch(); 609 610 // Now advance the time buffers 611 timeBuffer.advance(); 612 613 fetchQueue.advance(); 614 decodeQueue.advance(); 615 renameQueue.advance(); 616 iewQueue.advance(); 617 618 activityRec.advance(); 619 620 if (removeInstsThisCycle) { 621 cleanUpRemovedInsts(); 622 } 623 624 if (!tickEvent.scheduled()) { 625 if (_status == SwitchedOut || 626 getDrainState() == Drainable::Drained) { 627 DPRINTF(O3CPU, "Switched out!\n"); 628 // increment stat 629 lastRunningCycle = curCycle(); 630 } else if (!activityRec.active() || _status == Idle) { 631 DPRINTF(O3CPU, "Idle!\n"); 632 lastRunningCycle = curCycle(); 633 timesIdled++; 634 } else { 635 schedule(tickEvent, clockEdge(Cycles(1))); 636 DPRINTF(O3CPU, "Scheduling next tick!\n"); 637 } 638 } 639 640 if (!FullSystem) 641 updateThreadPriority(); 642} 643 644template <class Impl> 645void 646FullO3CPU<Impl>::init() 647{ 648 BaseCPU::init(); 649 650 if (!params()->defer_registration && 651 system->getMemoryMode() != Enums::timing) { 652 fatal("The O3 CPU requires the memory system to be in " 653 "'timing' mode.\n"); 654 } 655 656 for (ThreadID tid = 0; tid < numThreads; ++tid) { 657 // Set noSquashFromTC so that the CPU doesn't squash when initially 658 // setting up registers. 659 thread[tid]->noSquashFromTC = true; 660 // Initialise the ThreadContext's memory proxies 661 thread[tid]->initMemProxies(thread[tid]->getTC()); 662 } 663 664 // this CPU could still be unconnected if we are restoring from a 665 // checkpoint and this CPU is to be switched in, thus we can only 666 // do this here if the instruction port is actually connected, if 667 // not we have to do it as part of takeOverFrom 668 if (icachePort.isConnected()) 669 fetch.setIcache(); 670 671 if (FullSystem && !params()->defer_registration) { 672 for (ThreadID tid = 0; tid < numThreads; tid++) { 673 ThreadContext *src_tc = threadContexts[tid]; 674 TheISA::initCPU(src_tc, src_tc->contextId()); 675 } 676 } 677 678 // Clear noSquashFromTC. 679 for (int tid = 0; tid < numThreads; ++tid) 680 thread[tid]->noSquashFromTC = false; 681 682 commit.setThreads(thread); 683} 684 685template <class Impl> 686void 687FullO3CPU<Impl>::startup() 688{ 689 fetch.startupStage(); 690 iew.startupStage(); 691 rename.startupStage(); 692 commit.startupStage(); 693} 694 695template <class Impl> 696void 697FullO3CPU<Impl>::activateThread(ThreadID tid) 698{ 699 list<ThreadID>::iterator isActive = 700 std::find(activeThreads.begin(), activeThreads.end(), tid); 701 702 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 703 704 if (isActive == activeThreads.end()) { 705 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 706 tid); 707 708 activeThreads.push_back(tid); 709 } 710} 711 712template <class Impl> 713void 714FullO3CPU<Impl>::deactivateThread(ThreadID tid) 715{ 716 //Remove From Active List, if Active 717 list<ThreadID>::iterator thread_it = 718 std::find(activeThreads.begin(), activeThreads.end(), tid); 719 720 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 721 722 if (thread_it != activeThreads.end()) { 723 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 724 tid); 725 activeThreads.erase(thread_it); 726 } 727} 728 729template <class Impl> 730Counter 731FullO3CPU<Impl>::totalInsts() const 732{ 733 Counter total(0); 734 735 ThreadID size = thread.size(); 736 for (ThreadID i = 0; i < size; i++) 737 total += thread[i]->numInst; 738 739 return total; 740} 741 742template <class Impl> 743Counter 744FullO3CPU<Impl>::totalOps() const 745{ 746 Counter total(0); 747 748 ThreadID size = thread.size(); 749 for (ThreadID i = 0; i < size; i++) 750 total += thread[i]->numOp; 751 752 return total; 753} 754 755template <class Impl> 756void 757FullO3CPU<Impl>::activateContext(ThreadID tid, Cycles delay) 758{ 759 // Needs to set each stage to running as well. 760 if (delay){ 761 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 762 "on cycle %d\n", tid, clockEdge(delay)); 763 scheduleActivateThreadEvent(tid, delay); 764 } else { 765 activateThread(tid); 766 } 767 768 // If we are time 0 or if the last activation time is in the past, 769 // schedule the next tick and wake up the fetch unit 770 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) { 771 scheduleTickEvent(delay); 772 773 // Be sure to signal that there's some activity so the CPU doesn't 774 // deschedule itself. 775 activityRec.activity(); 776 fetch.wakeFromQuiesce(); 777 778 Cycles cycles(curCycle() - lastRunningCycle); 779 // @todo: This is an oddity that is only here to match the stats 780 if (cycles != 0) 781 --cycles; 782 quiesceCycles += cycles; 783 784 lastActivatedCycle = curTick(); 785 786 _status = Running; 787 } 788} 789 790template <class Impl> 791bool 792FullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove, 793 Cycles delay) 794{ 795 // Schedule removal of thread data from CPU 796 if (delay){ 797 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 798 "on tick %d\n", tid, clockEdge(delay)); 799 scheduleDeallocateContextEvent(tid, remove, delay); 800 return false; 801 } else { 802 deactivateThread(tid); 803 if (remove) 804 removeThread(tid); 805 return true; 806 } 807} 808 809template <class Impl> 810void 811FullO3CPU<Impl>::suspendContext(ThreadID tid) 812{ 813 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 814 bool deallocated = scheduleDeallocateContext(tid, false, Cycles(1)); 815 // If this was the last thread then unschedule the tick event. 816 if ((activeThreads.size() == 1 && !deallocated) || 817 activeThreads.size() == 0) 818 unscheduleTickEvent(); 819 820 DPRINTF(Quiesce, "Suspending Context\n"); 821 lastRunningCycle = curCycle(); 822 _status = Idle; 823} 824 825template <class Impl> 826void 827FullO3CPU<Impl>::haltContext(ThreadID tid) 828{ 829 //For now, this is the same as deallocate 830 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 831 scheduleDeallocateContext(tid, true, Cycles(1)); 832} 833 834template <class Impl> 835void 836FullO3CPU<Impl>::insertThread(ThreadID tid) 837{ 838 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 839 // Will change now that the PC and thread state is internal to the CPU 840 // and not in the ThreadContext. 841 ThreadContext *src_tc; 842 if (FullSystem) 843 src_tc = system->threadContexts[tid]; 844 else 845 src_tc = tcBase(tid); 846 847 //Bind Int Regs to Rename Map 848 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 849 PhysRegIndex phys_reg = freeList.getIntReg(); 850 851 renameMap[tid].setEntry(ireg,phys_reg); 852 scoreboard.setReg(phys_reg); 853 } 854 855 //Bind Float Regs to Rename Map 856 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 857 PhysRegIndex phys_reg = freeList.getFloatReg(); 858 859 renameMap[tid].setEntry(freg,phys_reg); 860 scoreboard.setReg(phys_reg); 861 } 862 863 //Copy Thread Data Into RegFile 864 //this->copyFromTC(tid); 865 866 //Set PC/NPC/NNPC 867 pcState(src_tc->pcState(), tid); 868 869 src_tc->setStatus(ThreadContext::Active); 870 871 activateContext(tid, Cycles(1)); 872 873 //Reset ROB/IQ/LSQ Entries 874 commit.rob->resetEntries(); 875 iew.resetEntries(); 876} 877 878template <class Impl> 879void 880FullO3CPU<Impl>::removeThread(ThreadID tid) 881{ 882 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 883 884 // Copy Thread Data From RegFile 885 // If thread is suspended, it might be re-allocated 886 // this->copyToTC(tid); 887 888 889 // @todo: 2-27-2008: Fix how we free up rename mappings 890 // here to alleviate the case for double-freeing registers 891 // in SMT workloads. 892 893 // Unbind Int Regs from Rename Map 894 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 895 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 896 897 scoreboard.unsetReg(phys_reg); 898 freeList.addReg(phys_reg); 899 } 900 901 // Unbind Float Regs from Rename Map 902 for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 903 PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 904 905 scoreboard.unsetReg(phys_reg); 906 freeList.addReg(phys_reg); 907 } 908 909 // Squash Throughout Pipeline 910 DynInstPtr inst = commit.rob->readHeadInst(tid); 911 InstSeqNum squash_seq_num = inst->seqNum; 912 fetch.squash(0, squash_seq_num, inst, tid); 913 decode.squash(tid); 914 rename.squash(squash_seq_num, tid); 915 iew.squash(tid); 916 iew.ldstQueue.squash(squash_seq_num, tid); 917 commit.rob->squash(squash_seq_num, tid); 918 919 920 assert(iew.instQueue.getCount(tid) == 0); 921 assert(iew.ldstQueue.getCount(tid) == 0); 922 923 // Reset ROB/IQ/LSQ Entries 924 925 // Commented out for now. This should be possible to do by 926 // telling all the pipeline stages to drain first, and then 927 // checking until the drain completes. Once the pipeline is 928 // drained, call resetEntries(). - 10-09-06 ktlim 929/* 930 if (activeThreads.size() >= 1) { 931 commit.rob->resetEntries(); 932 iew.resetEntries(); 933 } 934*/ 935} 936 937 938template <class Impl> 939void 940FullO3CPU<Impl>::activateWhenReady(ThreadID tid) 941{ 942 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 943 "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 944 tid); 945 946 bool ready = true; 947 948 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 949 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 950 "Phys. Int. Regs.\n", 951 tid); 952 ready = false; 953 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 954 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 955 "Phys. Float. Regs.\n", 956 tid); 957 ready = false; 958 } else if (commit.rob->numFreeEntries() >= 959 commit.rob->entryAmount(activeThreads.size() + 1)) { 960 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 961 "ROB entries.\n", 962 tid); 963 ready = false; 964 } else if (iew.instQueue.numFreeEntries() >= 965 iew.instQueue.entryAmount(activeThreads.size() + 1)) { 966 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 967 "IQ entries.\n", 968 tid); 969 ready = false; 970 } else if (iew.ldstQueue.numFreeEntries() >= 971 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 972 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 973 "LSQ entries.\n", 974 tid); 975 ready = false; 976 } 977 978 if (ready) { 979 insertThread(tid); 980 981 contextSwitch = false; 982 983 cpuWaitList.remove(tid); 984 } else { 985 suspendContext(tid); 986 987 //blocks fetch 988 contextSwitch = true; 989 990 //@todo: dont always add to waitlist 991 //do waitlist 992 cpuWaitList.push_back(tid); 993 } 994} 995 996template <class Impl> 997Fault 998FullO3CPU<Impl>::hwrei(ThreadID tid) 999{ 1000#if THE_ISA == ALPHA_ISA 1001 // Need to clear the lock flag upon returning from an interrupt. 1002 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 1003 1004 this->thread[tid]->kernelStats->hwrei(); 1005 1006 // FIXME: XXX check for interrupts? XXX 1007#endif 1008 return NoFault; 1009} 1010 1011template <class Impl> 1012bool 1013FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 1014{ 1015#if THE_ISA == ALPHA_ISA 1016 if (this->thread[tid]->kernelStats) 1017 this->thread[tid]->kernelStats->callpal(palFunc, 1018 this->threadContexts[tid]); 1019 1020 switch (palFunc) { 1021 case PAL::halt: 1022 halt(); 1023 if (--System::numSystemsRunning == 0) 1024 exitSimLoop("all cpus halted"); 1025 break; 1026 1027 case PAL::bpt: 1028 case PAL::bugchk: 1029 if (this->system->breakpoint()) 1030 return false; 1031 break; 1032 } 1033#endif 1034 return true; 1035} 1036 1037template <class Impl> 1038Fault 1039FullO3CPU<Impl>::getInterrupts() 1040{ 1041 // Check if there are any outstanding interrupts 1042 return this->interrupts->getInterrupt(this->threadContexts[0]); 1043} 1044 1045template <class Impl> 1046void 1047FullO3CPU<Impl>::processInterrupts(Fault interrupt) 1048{ 1049 // Check for interrupts here. For now can copy the code that 1050 // exists within isa_fullsys_traits.hh. Also assume that thread 0 1051 // is the one that handles the interrupts. 1052 // @todo: Possibly consolidate the interrupt checking code. 1053 // @todo: Allow other threads to handle interrupts. 1054 1055 assert(interrupt != NoFault); 1056 this->interrupts->updateIntrInfo(this->threadContexts[0]); 1057 1058 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 1059 this->trap(interrupt, 0, NULL); 1060} 1061 1062template <class Impl> 1063void 1064FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst) 1065{ 1066 // Pass the thread's TC into the invoke method. 1067 fault->invoke(this->threadContexts[tid], inst); 1068} 1069 1070template <class Impl> 1071void 1072FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 1073{ 1074 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 1075 1076 DPRINTF(Activity,"Activity: syscall() called.\n"); 1077 1078 // Temporarily increase this by one to account for the syscall 1079 // instruction. 1080 ++(this->thread[tid]->funcExeInst); 1081 1082 // Execute the actual syscall. 1083 this->thread[tid]->syscall(callnum); 1084 1085 // Decrease funcExeInst by one as the normal commit will handle 1086 // incrementing it. 1087 --(this->thread[tid]->funcExeInst); 1088} 1089 1090template <class Impl> 1091void 1092FullO3CPU<Impl>::serialize(std::ostream &os) 1093{ 1094 Drainable::State so_state(getDrainState()); 1095 SERIALIZE_ENUM(so_state); 1096 BaseCPU::serialize(os); 1097 nameOut(os, csprintf("%s.tickEvent", name())); 1098 tickEvent.serialize(os); 1099 1100 for (ThreadID i = 0; i < thread.size(); i++) { 1101 nameOut(os, csprintf("%s.xc.%i", name(), i)); 1102 thread[i]->serialize(os); 1103 } 1104} 1105 1106template <class Impl> 1107void 1108FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 1109{ 1110 Drainable::State so_state; 1111 UNSERIALIZE_ENUM(so_state); 1112 BaseCPU::unserialize(cp, section); 1113 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 1114 1115 for (ThreadID i = 0; i < thread.size(); i++) { 1116 thread[i]->unserialize(cp, 1117 csprintf("%s.xc.%i", section, i)); 1118 if (thread[i]->status() == ThreadContext::Active) 1119 activateThread(i); 1120 } 1121} 1122 1123template <class Impl> 1124unsigned int 1125FullO3CPU<Impl>::drain(DrainManager *drain_manager) 1126{ 1127 DPRINTF(O3CPU, "Switching out\n"); 1128 1129 // If the CPU isn't doing anything, then return immediately. 1130 if (_status == SwitchedOut) 1131 return 0; 1132 1133 drainCount = 0; 1134 fetch.drain(); 1135 decode.drain(); 1136 rename.drain(); 1137 iew.drain(); 1138 commit.drain(); 1139 1140 // Wake the CPU and record activity so everything can drain out if 1141 // the CPU was not able to immediately drain. 1142 if (getDrainState() != Drainable::Drained) { 1143 // A bit of a hack...set the drainManager after all the drain() 1144 // calls have been made, that way if all of the stages drain 1145 // immediately, the signalDrained() function knows not to call 1146 // process on the drain event. 1147 drainManager = drain_manager; 1148 1149 wakeCPU(); 1150 activityRec.activity(); 1151 1152 DPRINTF(Drain, "CPU not drained\n"); 1153 1154 return 1; 1155 } else { 1156 return 0; 1157 } 1158} 1159 1160template <class Impl> 1161void 1162FullO3CPU<Impl>::drainResume() 1163{ 1164 fetch.resume(); 1165 decode.resume(); 1166 rename.resume(); 1167 iew.resume(); 1168 commit.resume(); 1169 1170 setDrainState(Drainable::Running); 1171 1172 if (_status == SwitchedOut) 1173 return; 1174 1175 if (system->getMemoryMode() != Enums::timing) { 1176 fatal("The O3 CPU requires the memory system to be in " 1177 "'timing' mode.\n"); 1178 } 1179 1180 if (!tickEvent.scheduled()) 1181 schedule(tickEvent, nextCycle()); 1182 _status = Running; 1183} 1184 1185template <class Impl> 1186void 1187FullO3CPU<Impl>::signalDrained() 1188{ 1189 if (++drainCount == NumStages) { 1190 if (tickEvent.scheduled()) 1191 tickEvent.squash(); 1192 1193 setDrainState(Drainable::Drained); 1194 1195 BaseCPU::switchOut(); 1196 1197 if (drainManager) { 1198 DPRINTF(Drain, "CPU done draining, processing drain event\n"); 1199 drainManager->signalDrainDone(); 1200 drainManager = NULL; 1201 } 1202 } 1203 assert(drainCount <= 5); 1204} 1205 1206template <class Impl> 1207void 1208FullO3CPU<Impl>::switchOut() 1209{ 1210 fetch.switchOut(); 1211 rename.switchOut(); 1212 iew.switchOut(); 1213 commit.switchOut(); 1214 instList.clear(); 1215 while (!removeList.empty()) { 1216 removeList.pop(); 1217 } 1218 1219 _status = SwitchedOut; 1220 1221 if (checker) 1222 checker->switchOut(); 1223 1224 if (tickEvent.scheduled()) 1225 tickEvent.squash(); 1226} 1227 1228template <class Impl> 1229void 1230FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 1231{ 1232 // Flush out any old data from the time buffers. 1233 for (int i = 0; i < timeBuffer.getSize(); ++i) { 1234 timeBuffer.advance(); 1235 fetchQueue.advance(); 1236 decodeQueue.advance(); 1237 renameQueue.advance(); 1238 iewQueue.advance(); 1239 } 1240 1241 activityRec.reset(); 1242 1243 BaseCPU::takeOverFrom(oldCPU); 1244 1245 fetch.takeOverFrom(); 1246 decode.takeOverFrom(); 1247 rename.takeOverFrom(); 1248 iew.takeOverFrom(); 1249 commit.takeOverFrom(); 1250 1251 assert(!tickEvent.scheduled() || tickEvent.squashed()); 1252 1253 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU); 1254 if (oldO3CPU) 1255 globalSeqNum = oldO3CPU->globalSeqNum; 1256 1257 // @todo: Figure out how to properly select the tid to put onto 1258 // the active threads list. 1259 ThreadID tid = 0; 1260 1261 list<ThreadID>::iterator isActive = 1262 std::find(activeThreads.begin(), activeThreads.end(), tid); 1263 1264 if (isActive == activeThreads.end()) { 1265 //May Need to Re-code this if the delay variable is the delay 1266 //needed for thread to activate 1267 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 1268 tid); 1269 1270 activeThreads.push_back(tid); 1271 } 1272 1273 // Set all statuses to active, schedule the CPU's tick event. 1274 // @todo: Fix up statuses so this is handled properly 1275 ThreadID size = threadContexts.size(); 1276 for (ThreadID i = 0; i < size; ++i) { 1277 ThreadContext *tc = threadContexts[i]; 1278 if (tc->status() == ThreadContext::Active && _status != Running) { 1279 _status = Running; 1280 reschedule(tickEvent, nextCycle(), true); 1281 } 1282 } 1283 if (!tickEvent.scheduled()) 1284 schedule(tickEvent, nextCycle()); 1285 1286 lastRunningCycle = curCycle(); 1287} 1288 1289template <class Impl> 1290TheISA::MiscReg 1291FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) 1292{ 1293 return this->isa[tid]->readMiscRegNoEffect(misc_reg); 1294} 1295 1296template <class Impl> 1297TheISA::MiscReg 1298FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 1299{ 1300 miscRegfileReads++; 1301 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); 1302} 1303 1304template <class Impl> 1305void 1306FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 1307 const TheISA::MiscReg &val, ThreadID tid) 1308{ 1309 this->isa[tid]->setMiscRegNoEffect(misc_reg, val); 1310} 1311 1312template <class Impl> 1313void 1314FullO3CPU<Impl>::setMiscReg(int misc_reg, 1315 const TheISA::MiscReg &val, ThreadID tid) 1316{ 1317 miscRegfileWrites++; 1318 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); 1319} 1320 1321template <class Impl> 1322uint64_t 1323FullO3CPU<Impl>::readIntReg(int reg_idx) 1324{ 1325 intRegfileReads++; 1326 return regFile.readIntReg(reg_idx); 1327} 1328 1329template <class Impl> 1330FloatReg 1331FullO3CPU<Impl>::readFloatReg(int reg_idx) 1332{ 1333 fpRegfileReads++; 1334 return regFile.readFloatReg(reg_idx); 1335} 1336 1337template <class Impl> 1338FloatRegBits 1339FullO3CPU<Impl>::readFloatRegBits(int reg_idx) 1340{ 1341 fpRegfileReads++; 1342 return regFile.readFloatRegBits(reg_idx); 1343} 1344 1345template <class Impl> 1346void 1347FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 1348{ 1349 intRegfileWrites++; 1350 regFile.setIntReg(reg_idx, val); 1351} 1352 1353template <class Impl> 1354void 1355FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 1356{ 1357 fpRegfileWrites++; 1358 regFile.setFloatReg(reg_idx, val); 1359} 1360 1361template <class Impl> 1362void 1363FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 1364{ 1365 fpRegfileWrites++; 1366 regFile.setFloatRegBits(reg_idx, val); 1367} 1368 1369template <class Impl> 1370uint64_t 1371FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 1372{ 1373 intRegfileReads++; 1374 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 1375 1376 return regFile.readIntReg(phys_reg); 1377} 1378 1379template <class Impl> 1380float 1381FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 1382{ 1383 fpRegfileReads++; 1384 int idx = reg_idx + TheISA::NumIntRegs; 1385 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1386 1387 return regFile.readFloatReg(phys_reg); 1388} 1389 1390template <class Impl> 1391uint64_t 1392FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 1393{ 1394 fpRegfileReads++; 1395 int idx = reg_idx + TheISA::NumIntRegs; 1396 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1397 1398 return regFile.readFloatRegBits(phys_reg); 1399} 1400 1401template <class Impl> 1402void 1403FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 1404{ 1405 intRegfileWrites++; 1406 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 1407 1408 regFile.setIntReg(phys_reg, val); 1409} 1410 1411template <class Impl> 1412void 1413FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 1414{ 1415 fpRegfileWrites++; 1416 int idx = reg_idx + TheISA::NumIntRegs; 1417 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1418 1419 regFile.setFloatReg(phys_reg, val); 1420} 1421 1422template <class Impl> 1423void 1424FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 1425{ 1426 fpRegfileWrites++; 1427 int idx = reg_idx + TheISA::NumIntRegs; 1428 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1429 1430 regFile.setFloatRegBits(phys_reg, val); 1431} 1432 1433template <class Impl> 1434TheISA::PCState 1435FullO3CPU<Impl>::pcState(ThreadID tid) 1436{ 1437 return commit.pcState(tid); 1438} 1439 1440template <class Impl> 1441void 1442FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 1443{ 1444 commit.pcState(val, tid); 1445} 1446 1447template <class Impl> 1448Addr 1449FullO3CPU<Impl>::instAddr(ThreadID tid) 1450{ 1451 return commit.instAddr(tid); 1452} 1453 1454template <class Impl> 1455Addr 1456FullO3CPU<Impl>::nextInstAddr(ThreadID tid) 1457{ 1458 return commit.nextInstAddr(tid); 1459} 1460 1461template <class Impl> 1462MicroPC 1463FullO3CPU<Impl>::microPC(ThreadID tid) 1464{ 1465 return commit.microPC(tid); 1466} 1467 1468template <class Impl> 1469void 1470FullO3CPU<Impl>::squashFromTC(ThreadID tid) 1471{ 1472 this->thread[tid]->noSquashFromTC = true; 1473 this->commit.generateTCEvent(tid); 1474} 1475 1476template <class Impl> 1477typename FullO3CPU<Impl>::ListIt 1478FullO3CPU<Impl>::addInst(DynInstPtr &inst) 1479{ 1480 instList.push_back(inst); 1481 1482 return --(instList.end()); 1483} 1484 1485template <class Impl> 1486void 1487FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst) 1488{ 1489 // Keep an instruction count. 1490 if (!inst->isMicroop() || inst->isLastMicroop()) { 1491 thread[tid]->numInst++; 1492 thread[tid]->numInsts++; 1493 committedInsts[tid]++; 1494 totalCommittedInsts++; 1495 } 1496 thread[tid]->numOp++; 1497 thread[tid]->numOps++; 1498 committedOps[tid]++; 1499 1500 system->totalNumInsts++; 1501 // Check for instruction-count-based events. 1502 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 1503 system->instEventQueue.serviceEvents(system->totalNumInsts); 1504} 1505 1506template <class Impl> 1507void 1508FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 1509{ 1510 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 1511 "[sn:%lli]\n", 1512 inst->threadNumber, inst->pcState(), inst->seqNum); 1513 1514 removeInstsThisCycle = true; 1515 1516 // Remove the front instruction. 1517 removeList.push(inst->getInstListIt()); 1518} 1519 1520template <class Impl> 1521void 1522FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 1523{ 1524 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 1525 " list.\n", tid); 1526 1527 ListIt end_it; 1528 1529 bool rob_empty = false; 1530 1531 if (instList.empty()) { 1532 return; 1533 } else if (rob.isEmpty(/*tid*/)) { 1534 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 1535 end_it = instList.begin(); 1536 rob_empty = true; 1537 } else { 1538 end_it = (rob.readTailInst(tid))->getInstListIt(); 1539 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 1540 } 1541 1542 removeInstsThisCycle = true; 1543 1544 ListIt inst_it = instList.end(); 1545 1546 inst_it--; 1547 1548 // Walk through the instruction list, removing any instructions 1549 // that were inserted after the given instruction iterator, end_it. 1550 while (inst_it != end_it) { 1551 assert(!instList.empty()); 1552 1553 squashInstIt(inst_it, tid); 1554 1555 inst_it--; 1556 } 1557 1558 // If the ROB was empty, then we actually need to remove the first 1559 // instruction as well. 1560 if (rob_empty) { 1561 squashInstIt(inst_it, tid); 1562 } 1563} 1564 1565template <class Impl> 1566void 1567FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 1568{ 1569 assert(!instList.empty()); 1570 1571 removeInstsThisCycle = true; 1572 1573 ListIt inst_iter = instList.end(); 1574 1575 inst_iter--; 1576 1577 DPRINTF(O3CPU, "Deleting instructions from instruction " 1578 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 1579 tid, seq_num, (*inst_iter)->seqNum); 1580 1581 while ((*inst_iter)->seqNum > seq_num) { 1582 1583 bool break_loop = (inst_iter == instList.begin()); 1584 1585 squashInstIt(inst_iter, tid); 1586 1587 inst_iter--; 1588 1589 if (break_loop) 1590 break; 1591 } 1592} 1593 1594template <class Impl> 1595inline void 1596FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 1597{ 1598 if ((*instIt)->threadNumber == tid) { 1599 DPRINTF(O3CPU, "Squashing instruction, " 1600 "[tid:%i] [sn:%lli] PC %s\n", 1601 (*instIt)->threadNumber, 1602 (*instIt)->seqNum, 1603 (*instIt)->pcState()); 1604 1605 // Mark it as squashed. 1606 (*instIt)->setSquashed(); 1607 1608 // @todo: Formulate a consistent method for deleting 1609 // instructions from the instruction list 1610 // Remove the instruction from the list. 1611 removeList.push(instIt); 1612 } 1613} 1614 1615template <class Impl> 1616void 1617FullO3CPU<Impl>::cleanUpRemovedInsts() 1618{ 1619 while (!removeList.empty()) { 1620 DPRINTF(O3CPU, "Removing instruction, " 1621 "[tid:%i] [sn:%lli] PC %s\n", 1622 (*removeList.front())->threadNumber, 1623 (*removeList.front())->seqNum, 1624 (*removeList.front())->pcState()); 1625 1626 instList.erase(removeList.front()); 1627 1628 removeList.pop(); 1629 } 1630 1631 removeInstsThisCycle = false; 1632} 1633/* 1634template <class Impl> 1635void 1636FullO3CPU<Impl>::removeAllInsts() 1637{ 1638 instList.clear(); 1639} 1640*/ 1641template <class Impl> 1642void 1643FullO3CPU<Impl>::dumpInsts() 1644{ 1645 int num = 0; 1646 1647 ListIt inst_list_it = instList.begin(); 1648 1649 cprintf("Dumping Instruction List\n"); 1650 1651 while (inst_list_it != instList.end()) { 1652 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 1653 "Squashed:%i\n\n", 1654 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 1655 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 1656 (*inst_list_it)->isSquashed()); 1657 inst_list_it++; 1658 ++num; 1659 } 1660} 1661/* 1662template <class Impl> 1663void 1664FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 1665{ 1666 iew.wakeDependents(inst); 1667} 1668*/ 1669template <class Impl> 1670void 1671FullO3CPU<Impl>::wakeCPU() 1672{ 1673 if (activityRec.active() || tickEvent.scheduled()) { 1674 DPRINTF(Activity, "CPU already running.\n"); 1675 return; 1676 } 1677 1678 DPRINTF(Activity, "Waking up CPU\n"); 1679 1680 Cycles cycles(curCycle() - lastRunningCycle); 1681 // @todo: This is an oddity that is only here to match the stats 1682 if (cycles != 0) 1683 --cycles; 1684 idleCycles += cycles; 1685 numCycles += cycles; 1686 1687 schedule(tickEvent, nextCycle()); 1688} 1689 1690template <class Impl> 1691void 1692FullO3CPU<Impl>::wakeup() 1693{ 1694 if (this->thread[0]->status() != ThreadContext::Suspended) 1695 return; 1696 1697 this->wakeCPU(); 1698 1699 DPRINTF(Quiesce, "Suspended Processor woken\n"); 1700 this->threadContexts[0]->activate(); 1701} 1702 1703template <class Impl> 1704ThreadID 1705FullO3CPU<Impl>::getFreeTid() 1706{ 1707 for (ThreadID tid = 0; tid < numThreads; tid++) { 1708 if (!tids[tid]) { 1709 tids[tid] = true; 1710 return tid; 1711 } 1712 } 1713 1714 return InvalidThreadID; 1715} 1716 1717template <class Impl> 1718void 1719FullO3CPU<Impl>::doContextSwitch() 1720{ 1721 if (contextSwitch) { 1722 1723 //ADD CODE TO DEACTIVE THREAD HERE (???) 1724 1725 ThreadID size = cpuWaitList.size(); 1726 for (ThreadID tid = 0; tid < size; tid++) { 1727 activateWhenReady(tid); 1728 } 1729 1730 if (cpuWaitList.size() == 0) 1731 contextSwitch = true; 1732 } 1733} 1734 1735template <class Impl> 1736void 1737FullO3CPU<Impl>::updateThreadPriority() 1738{ 1739 if (activeThreads.size() > 1) { 1740 //DEFAULT TO ROUND ROBIN SCHEME 1741 //e.g. Move highest priority to end of thread list 1742 list<ThreadID>::iterator list_begin = activeThreads.begin(); 1743 1744 unsigned high_thread = *list_begin; 1745 1746 activeThreads.erase(list_begin); 1747 1748 activeThreads.push_back(high_thread); 1749 } 1750} 1751 1752// Forward declaration of FullO3CPU. 1753template class FullO3CPU<O3CPUImpl>; 1754