cpu.cc revision 8834 
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Korey Sewell
43 *          Rick Strong
44 */
45
46#include "arch/kernel_stats.hh"
47#include "config/the_isa.hh"
48#include "config/use_checker.hh"
49#include "cpu/o3/cpu.hh"
50#include "cpu/o3/isa_specific.hh"
51#include "cpu/o3/thread_context.hh"
52#include "cpu/activity.hh"
53#include "cpu/quiesce_event.hh"
54#include "cpu/simple_thread.hh"
55#include "cpu/thread_context.hh"
56#include "debug/Activity.hh"
57#include "debug/O3CPU.hh"
58#include "debug/Quiesce.hh"
59#include "enums/MemoryMode.hh"
60#include "sim/core.hh"
61#include "sim/full_system.hh"
62#include "sim/process.hh"
63#include "sim/stat_control.hh"
64#include "sim/system.hh"
65
66#if USE_CHECKER
67#include "cpu/checker/cpu.hh"
68#include "cpu/checker/thread_context.hh"
69#endif
70
71#if THE_ISA == ALPHA_ISA
72#include "arch/alpha/osfpal.hh"
73#include "debug/Activity.hh"
74#endif
75
76struct BaseCPUParams;
77
78using namespace TheISA;
79using namespace std;
80
81BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
82    : BaseCPU(params)
83{
84}
85
86void
87BaseO3CPU::regStats()
88{
89    BaseCPU::regStats();
90}
91
92template<class Impl>
93bool
94FullO3CPU<Impl>::IcachePort::recvTiming(PacketPtr pkt)
95{
96    DPRINTF(O3CPU, "Fetch unit received timing\n");
97    if (pkt->isResponse()) {
98        // We shouldn't ever get a block in ownership state
99        assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
100
101        fetch->processCacheCompletion(pkt);
102    }
103    //else Snooped a coherence request, just return
104    return true;
105}
106
107template<class Impl>
108void
109FullO3CPU<Impl>::IcachePort::recvRetry()
110{
111    fetch->recvRetry();
112}
113
114template <class Impl>
115bool
116FullO3CPU<Impl>::DcachePort::recvTiming(PacketPtr pkt)
117{
118    return lsq->recvTiming(pkt);
119}
120
121template <class Impl>
122void
123FullO3CPU<Impl>::DcachePort::recvRetry()
124{
125    lsq->recvRetry();
126}
127
128template <class Impl>
129FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
130    : Event(CPU_Tick_Pri), cpu(c)
131{
132}
133
134template <class Impl>
135void
136FullO3CPU<Impl>::TickEvent::process()
137{
138    cpu->tick();
139}
140
141template <class Impl>
142const char *
143FullO3CPU<Impl>::TickEvent::description() const
144{
145    return "FullO3CPU tick";
146}
147
148template <class Impl>
149FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
150    : Event(CPU_Switch_Pri)
151{
152}
153
154template <class Impl>
155void
156FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
157                                           FullO3CPU<Impl> *thread_cpu)
158{
159    tid = thread_num;
160    cpu = thread_cpu;
161}
162
163template <class Impl>
164void
165FullO3CPU<Impl>::ActivateThreadEvent::process()
166{
167    cpu->activateThread(tid);
168}
169
170template <class Impl>
171const char *
172FullO3CPU<Impl>::ActivateThreadEvent::description() const
173{
174    return "FullO3CPU \"Activate Thread\"";
175}
176
177template <class Impl>
178FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
179    : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
180{
181}
182
183template <class Impl>
184void
185FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
186                                              FullO3CPU<Impl> *thread_cpu)
187{
188    tid = thread_num;
189    cpu = thread_cpu;
190    remove = false;
191}
192
193template <class Impl>
194void
195FullO3CPU<Impl>::DeallocateContextEvent::process()
196{
197    cpu->deactivateThread(tid);
198    if (remove)
199        cpu->removeThread(tid);
200}
201
202template <class Impl>
203const char *
204FullO3CPU<Impl>::DeallocateContextEvent::description() const
205{
206    return "FullO3CPU \"Deallocate Context\"";
207}
208
209template <class Impl>
210FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
211    : BaseO3CPU(params),
212      itb(params->itb),
213      dtb(params->dtb),
214      tickEvent(this),
215#ifndef NDEBUG
216      instcount(0),
217#endif
218      removeInstsThisCycle(false),
219      fetch(this, params),
220      decode(this, params),
221      rename(this, params),
222      iew(this, params),
223      commit(this, params),
224
225      regFile(this, params->numPhysIntRegs,
226              params->numPhysFloatRegs),
227
228      freeList(params->numThreads,
229               TheISA::NumIntRegs, params->numPhysIntRegs,
230               TheISA::NumFloatRegs, params->numPhysFloatRegs),
231
232      rob(this,
233          params->numROBEntries, params->squashWidth,
234          params->smtROBPolicy, params->smtROBThreshold,
235          params->numThreads),
236
237      scoreboard(params->numThreads,
238                 TheISA::NumIntRegs, params->numPhysIntRegs,
239                 TheISA::NumFloatRegs, params->numPhysFloatRegs,
240                 TheISA::NumMiscRegs * numThreads,
241                 TheISA::ZeroReg),
242
243      icachePort(&fetch, this),
244      dcachePort(&iew.ldstQueue, this),
245
246      timeBuffer(params->backComSize, params->forwardComSize),
247      fetchQueue(params->backComSize, params->forwardComSize),
248      decodeQueue(params->backComSize, params->forwardComSize),
249      renameQueue(params->backComSize, params->forwardComSize),
250      iewQueue(params->backComSize, params->forwardComSize),
251      activityRec(name(), NumStages,
252                  params->backComSize + params->forwardComSize,
253                  params->activity),
254
255      globalSeqNum(1),
256      system(params->system),
257      drainCount(0),
258      deferRegistration(params->defer_registration)
259{
260    if (!deferRegistration) {
261        _status = Running;
262    } else {
263        _status = Idle;
264    }
265
266#if USE_CHECKER
267    if (params->checker) {
268        BaseCPU *temp_checker = params->checker;
269        checker = dynamic_cast<Checker<Impl> *>(temp_checker);
270        checker->setIcachePort(&icachePort);
271        checker->setSystem(params->system);
272    } else {
273        checker = NULL;
274    }
275#endif // USE_CHECKER
276
277    if (!FullSystem) {
278        thread.resize(numThreads);
279        tids.resize(numThreads);
280    }
281
282    // The stages also need their CPU pointer setup.  However this
283    // must be done at the upper level CPU because they have pointers
284    // to the upper level CPU, and not this FullO3CPU.
285
286    // Set up Pointers to the activeThreads list for each stage
287    fetch.setActiveThreads(&activeThreads);
288    decode.setActiveThreads(&activeThreads);
289    rename.setActiveThreads(&activeThreads);
290    iew.setActiveThreads(&activeThreads);
291    commit.setActiveThreads(&activeThreads);
292
293    // Give each of the stages the time buffer they will use.
294    fetch.setTimeBuffer(&timeBuffer);
295    decode.setTimeBuffer(&timeBuffer);
296    rename.setTimeBuffer(&timeBuffer);
297    iew.setTimeBuffer(&timeBuffer);
298    commit.setTimeBuffer(&timeBuffer);
299
300    // Also setup each of the stages' queues.
301    fetch.setFetchQueue(&fetchQueue);
302    decode.setFetchQueue(&fetchQueue);
303    commit.setFetchQueue(&fetchQueue);
304    decode.setDecodeQueue(&decodeQueue);
305    rename.setDecodeQueue(&decodeQueue);
306    rename.setRenameQueue(&renameQueue);
307    iew.setRenameQueue(&renameQueue);
308    iew.setIEWQueue(&iewQueue);
309    commit.setIEWQueue(&iewQueue);
310    commit.setRenameQueue(&renameQueue);
311
312    commit.setIEWStage(&iew);
313    rename.setIEWStage(&iew);
314    rename.setCommitStage(&commit);
315
316    ThreadID active_threads;
317    if (FullSystem) {
318        active_threads = 1;
319    } else {
320        active_threads = params->workload.size();
321
322        if (active_threads > Impl::MaxThreads) {
323            panic("Workload Size too large. Increase the 'MaxThreads' "
324                  "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
325                  "or edit your workload size.");
326        }
327    }
328
329    //Make Sure That this a Valid Architeture
330    assert(params->numPhysIntRegs   >= numThreads * TheISA::NumIntRegs);
331    assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
332
333    rename.setScoreboard(&scoreboard);
334    iew.setScoreboard(&scoreboard);
335
336    // Setup the rename map for whichever stages need it.
337    PhysRegIndex lreg_idx = 0;
338    PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
339
340    for (ThreadID tid = 0; tid < numThreads; tid++) {
341        bool bindRegs = (tid <= active_threads - 1);
342
343        commitRenameMap[tid].init(TheISA::NumIntRegs,
344                                  params->numPhysIntRegs,
345                                  lreg_idx,            //Index for Logical. Regs
346
347                                  TheISA::NumFloatRegs,
348                                  params->numPhysFloatRegs,
349                                  freg_idx,            //Index for Float Regs
350
351                                  TheISA::NumMiscRegs,
352
353                                  TheISA::ZeroReg,
354                                  TheISA::ZeroReg,
355
356                                  tid,
357                                  false);
358
359        renameMap[tid].init(TheISA::NumIntRegs,
360                            params->numPhysIntRegs,
361                            lreg_idx,                  //Index for Logical. Regs
362
363                            TheISA::NumFloatRegs,
364                            params->numPhysFloatRegs,
365                            freg_idx,                  //Index for Float Regs
366
367                            TheISA::NumMiscRegs,
368
369                            TheISA::ZeroReg,
370                            TheISA::ZeroReg,
371
372                            tid,
373                            bindRegs);
374
375        activateThreadEvent[tid].init(tid, this);
376        deallocateContextEvent[tid].init(tid, this);
377    }
378
379    rename.setRenameMap(renameMap);
380    commit.setRenameMap(commitRenameMap);
381
382    // Give renameMap & rename stage access to the freeList;
383    for (ThreadID tid = 0; tid < numThreads; tid++)
384        renameMap[tid].setFreeList(&freeList);
385    rename.setFreeList(&freeList);
386
387    // Setup the ROB for whichever stages need it.
388    commit.setROB(&rob);
389
390    lastRunningCycle = curTick();
391
392    lastActivatedCycle = -1;
393#if 0
394    // Give renameMap & rename stage access to the freeList;
395    for (ThreadID tid = 0; tid < numThreads; tid++)
396        globalSeqNum[tid] = 1;
397#endif
398
399    contextSwitch = false;
400    DPRINTF(O3CPU, "Creating O3CPU object.\n");
401
402    // Setup any thread state.
403    this->thread.resize(this->numThreads);
404
405    for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
406        if (FullSystem) {
407            // SMT is not supported in FS mode yet.
408            assert(this->numThreads == 1);
409            this->thread[tid] = new Thread(this, 0, NULL);
410        } else {
411            if (tid < params->workload.size()) {
412                DPRINTF(O3CPU, "Workload[%i] process is %#x",
413                        tid, this->thread[tid]);
414                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
415                        (typename Impl::O3CPU *)(this),
416                        tid, params->workload[tid]);
417
418                //usedTids[tid] = true;
419                //threadMap[tid] = tid;
420            } else {
421                //Allocate Empty thread so M5 can use later
422                //when scheduling threads to CPU
423                Process* dummy_proc = NULL;
424
425                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
426                        (typename Impl::O3CPU *)(this),
427                        tid, dummy_proc);
428                //usedTids[tid] = false;
429            }
430        }
431
432        ThreadContext *tc;
433
434        // Setup the TC that will serve as the interface to the threads/CPU.
435        O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
436
437        tc = o3_tc;
438
439        // If we're using a checker, then the TC should be the
440        // CheckerThreadContext.
441#if USE_CHECKER
442        if (params->checker) {
443            tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
444                o3_tc, this->checker);
445        }
446#endif
447
448        o3_tc->cpu = (typename Impl::O3CPU *)(this);
449        assert(o3_tc->cpu);
450        o3_tc->thread = this->thread[tid];
451
452        if (FullSystem) {
453            // Setup quiesce event.
454            this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
455        }
456        // Give the thread the TC.
457        this->thread[tid]->tc = tc;
458
459        // Add the TC to the CPU's list of TC's.
460        this->threadContexts.push_back(tc);
461    }
462
463    for (ThreadID tid = 0; tid < this->numThreads; tid++)
464        this->thread[tid]->setFuncExeInst(0);
465
466    lockAddr = 0;
467    lockFlag = false;
468}
469
470template <class Impl>
471FullO3CPU<Impl>::~FullO3CPU()
472{
473}
474
475template <class Impl>
476void
477FullO3CPU<Impl>::regStats()
478{
479    BaseO3CPU::regStats();
480
481    // Register any of the O3CPU's stats here.
482    timesIdled
483        .name(name() + ".timesIdled")
484        .desc("Number of times that the entire CPU went into an idle state and"
485              " unscheduled itself")
486        .prereq(timesIdled);
487
488    idleCycles
489        .name(name() + ".idleCycles")
490        .desc("Total number of cycles that the CPU has spent unscheduled due "
491              "to idling")
492        .prereq(idleCycles);
493
494    quiesceCycles
495        .name(name() + ".quiesceCycles")
496        .desc("Total number of cycles that CPU has spent quiesced or waiting "
497              "for an interrupt")
498        .prereq(quiesceCycles);
499
500    // Number of Instructions simulated
501    // --------------------------------
502    // Should probably be in Base CPU but need templated
503    // MaxThreads so put in here instead
504    committedInsts
505        .init(numThreads)
506        .name(name() + ".committedInsts")
507        .desc("Number of Instructions Simulated");
508
509    committedOps
510        .init(numThreads)
511        .name(name() + ".committedOps")
512        .desc("Number of Ops (including micro ops) Simulated");
513
514    totalCommittedInsts
515        .name(name() + ".committedInsts_total")
516        .desc("Number of Instructions Simulated");
517
518    cpi
519        .name(name() + ".cpi")
520        .desc("CPI: Cycles Per Instruction")
521        .precision(6);
522    cpi = numCycles / committedInsts;
523
524    totalCpi
525        .name(name() + ".cpi_total")
526        .desc("CPI: Total CPI of All Threads")
527        .precision(6);
528    totalCpi = numCycles / totalCommittedInsts;
529
530    ipc
531        .name(name() + ".ipc")
532        .desc("IPC: Instructions Per Cycle")
533        .precision(6);
534    ipc =  committedInsts / numCycles;
535
536    totalIpc
537        .name(name() + ".ipc_total")
538        .desc("IPC: Total IPC of All Threads")
539        .precision(6);
540    totalIpc =  totalCommittedInsts / numCycles;
541
542    this->fetch.regStats();
543    this->decode.regStats();
544    this->rename.regStats();
545    this->iew.regStats();
546    this->commit.regStats();
547    this->rob.regStats();
548
549    intRegfileReads
550        .name(name() + ".int_regfile_reads")
551        .desc("number of integer regfile reads")
552        .prereq(intRegfileReads);
553
554    intRegfileWrites
555        .name(name() + ".int_regfile_writes")
556        .desc("number of integer regfile writes")
557        .prereq(intRegfileWrites);
558
559    fpRegfileReads
560        .name(name() + ".fp_regfile_reads")
561        .desc("number of floating regfile reads")
562        .prereq(fpRegfileReads);
563
564    fpRegfileWrites
565        .name(name() + ".fp_regfile_writes")
566        .desc("number of floating regfile writes")
567        .prereq(fpRegfileWrites);
568
569    miscRegfileReads
570        .name(name() + ".misc_regfile_reads")
571        .desc("number of misc regfile reads")
572        .prereq(miscRegfileReads);
573
574    miscRegfileWrites
575        .name(name() + ".misc_regfile_writes")
576        .desc("number of misc regfile writes")
577        .prereq(miscRegfileWrites);
578}
579
580template <class Impl>
581Port *
582FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
583{
584    if (if_name == "dcache_port")
585        return &dcachePort;
586    else if (if_name == "icache_port")
587        return &icachePort;
588    else
589        panic("No Such Port\n");
590}
591
592template <class Impl>
593void
594FullO3CPU<Impl>::tick()
595{
596    DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
597
598    ++numCycles;
599
600//    activity = false;
601
602    //Tick each of the stages
603    fetch.tick();
604
605    decode.tick();
606
607    rename.tick();
608
609    iew.tick();
610
611    commit.tick();
612
613    if (!FullSystem)
614        doContextSwitch();
615
616    // Now advance the time buffers
617    timeBuffer.advance();
618
619    fetchQueue.advance();
620    decodeQueue.advance();
621    renameQueue.advance();
622    iewQueue.advance();
623
624    activityRec.advance();
625
626    if (removeInstsThisCycle) {
627        cleanUpRemovedInsts();
628    }
629
630    if (!tickEvent.scheduled()) {
631        if (_status == SwitchedOut ||
632            getState() == SimObject::Drained) {
633            DPRINTF(O3CPU, "Switched out!\n");
634            // increment stat
635            lastRunningCycle = curTick();
636        } else if (!activityRec.active() || _status == Idle) {
637            DPRINTF(O3CPU, "Idle!\n");
638            lastRunningCycle = curTick();
639            timesIdled++;
640        } else {
641            schedule(tickEvent, nextCycle(curTick() + ticks(1)));
642            DPRINTF(O3CPU, "Scheduling next tick!\n");
643        }
644    }
645
646    if (!FullSystem)
647        updateThreadPriority();
648}
649
650template <class Impl>
651void
652FullO3CPU<Impl>::init()
653{
654    BaseCPU::init();
655
656    // Set inSyscall so that the CPU doesn't squash when initially
657    // setting up registers.
658    for (ThreadID tid = 0; tid < numThreads; ++tid)
659        thread[tid]->inSyscall = true;
660
661    // this CPU could still be unconnected if we are restoring from a
662    // checkpoint and this CPU is to be switched in, thus we can only
663    // do this here if the instruction port is actually connected, if
664    // not we have to do it as part of takeOverFrom
665    if (icachePort.isConnected())
666        fetch.setIcache();
667
668    if (FullSystem) {
669        for (ThreadID tid = 0; tid < numThreads; tid++) {
670            ThreadContext *src_tc = threadContexts[tid];
671            TheISA::initCPU(src_tc, src_tc->contextId());
672            // Initialise the ThreadContext's memory proxies
673            thread[tid]->initMemProxies(thread[tid]->getTC());
674        }
675    }
676
677    // Clear inSyscall.
678    for (int tid = 0; tid < numThreads; ++tid)
679        thread[tid]->inSyscall = false;
680
681    // Initialize stages.
682    fetch.initStage();
683    iew.initStage();
684    rename.initStage();
685    commit.initStage();
686
687    commit.setThreads(thread);
688}
689
690template <class Impl>
691void
692FullO3CPU<Impl>::activateThread(ThreadID tid)
693{
694    list<ThreadID>::iterator isActive =
695        std::find(activeThreads.begin(), activeThreads.end(), tid);
696
697    DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
698
699    if (isActive == activeThreads.end()) {
700        DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
701                tid);
702
703        activeThreads.push_back(tid);
704    }
705}
706
707template <class Impl>
708void
709FullO3CPU<Impl>::deactivateThread(ThreadID tid)
710{
711    //Remove From Active List, if Active
712    list<ThreadID>::iterator thread_it =
713        std::find(activeThreads.begin(), activeThreads.end(), tid);
714
715    DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
716
717    if (thread_it != activeThreads.end()) {
718        DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
719                tid);
720        activeThreads.erase(thread_it);
721    }
722}
723
724template <class Impl>
725Counter
726FullO3CPU<Impl>::totalInsts() const
727{
728    Counter total(0);
729
730    ThreadID size = thread.size();
731    for (ThreadID i = 0; i < size; i++)
732        total += thread[i]->numInst;
733
734    return total;
735}
736
737template <class Impl>
738Counter
739FullO3CPU<Impl>::totalOps() const
740{
741    Counter total(0);
742
743    ThreadID size = thread.size();
744    for (ThreadID i = 0; i < size; i++)
745        total += thread[i]->numOp;
746
747    return total;
748}
749
750template <class Impl>
751void
752FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
753{
754    // Needs to set each stage to running as well.
755    if (delay){
756        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
757                "on cycle %d\n", tid, curTick() + ticks(delay));
758        scheduleActivateThreadEvent(tid, delay);
759    } else {
760        activateThread(tid);
761    }
762
763    if (lastActivatedCycle < curTick()) {
764        scheduleTickEvent(delay);
765
766        // Be sure to signal that there's some activity so the CPU doesn't
767        // deschedule itself.
768        activityRec.activity();
769        fetch.wakeFromQuiesce();
770
771        quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
772
773        lastActivatedCycle = curTick();
774
775        _status = Running;
776    }
777}
778
779template <class Impl>
780bool
781FullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove,
782                                           int delay)
783{
784    // Schedule removal of thread data from CPU
785    if (delay){
786        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
787                "on cycle %d\n", tid, curTick() + ticks(delay));
788        scheduleDeallocateContextEvent(tid, remove, delay);
789        return false;
790    } else {
791        deactivateThread(tid);
792        if (remove)
793            removeThread(tid);
794        return true;
795    }
796}
797
798template <class Impl>
799void
800FullO3CPU<Impl>::suspendContext(ThreadID tid)
801{
802    DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
803    bool deallocated = scheduleDeallocateContext(tid, false, 1);
804    // If this was the last thread then unschedule the tick event.
805    if ((activeThreads.size() == 1 && !deallocated) ||
806        activeThreads.size() == 0)
807        unscheduleTickEvent();
808
809    DPRINTF(Quiesce, "Suspending Context\n");
810    lastRunningCycle = curTick();
811    _status = Idle;
812}
813
814template <class Impl>
815void
816FullO3CPU<Impl>::haltContext(ThreadID tid)
817{
818    //For now, this is the same as deallocate
819    DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
820    scheduleDeallocateContext(tid, true, 1);
821}
822
823template <class Impl>
824void
825FullO3CPU<Impl>::insertThread(ThreadID tid)
826{
827    DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
828    // Will change now that the PC and thread state is internal to the CPU
829    // and not in the ThreadContext.
830    ThreadContext *src_tc;
831    if (FullSystem)
832        src_tc = system->threadContexts[tid];
833    else
834        src_tc = tcBase(tid);
835
836    //Bind Int Regs to Rename Map
837    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
838        PhysRegIndex phys_reg = freeList.getIntReg();
839
840        renameMap[tid].setEntry(ireg,phys_reg);
841        scoreboard.setReg(phys_reg);
842    }
843
844    //Bind Float Regs to Rename Map
845    for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
846        PhysRegIndex phys_reg = freeList.getFloatReg();
847
848        renameMap[tid].setEntry(freg,phys_reg);
849        scoreboard.setReg(phys_reg);
850    }
851
852    //Copy Thread Data Into RegFile
853    //this->copyFromTC(tid);
854
855    //Set PC/NPC/NNPC
856    pcState(src_tc->pcState(), tid);
857
858    src_tc->setStatus(ThreadContext::Active);
859
860    activateContext(tid,1);
861
862    //Reset ROB/IQ/LSQ Entries
863    commit.rob->resetEntries();
864    iew.resetEntries();
865}
866
867template <class Impl>
868void
869FullO3CPU<Impl>::removeThread(ThreadID tid)
870{
871    DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
872
873    // Copy Thread Data From RegFile
874    // If thread is suspended, it might be re-allocated
875    // this->copyToTC(tid);
876
877
878    // @todo: 2-27-2008: Fix how we free up rename mappings
879    // here to alleviate the case for double-freeing registers
880    // in SMT workloads.
881
882    // Unbind Int Regs from Rename Map
883    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
884        PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
885
886        scoreboard.unsetReg(phys_reg);
887        freeList.addReg(phys_reg);
888    }
889
890    // Unbind Float Regs from Rename Map
891    for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) {
892        PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
893
894        scoreboard.unsetReg(phys_reg);
895        freeList.addReg(phys_reg);
896    }
897
898    // Squash Throughout Pipeline
899    DynInstPtr inst = commit.rob->readHeadInst(tid);
900    InstSeqNum squash_seq_num = inst->seqNum;
901    fetch.squash(0, squash_seq_num, inst, tid);
902    decode.squash(tid);
903    rename.squash(squash_seq_num, tid);
904    iew.squash(tid);
905    iew.ldstQueue.squash(squash_seq_num, tid);
906    commit.rob->squash(squash_seq_num, tid);
907
908
909    assert(iew.instQueue.getCount(tid) == 0);
910    assert(iew.ldstQueue.getCount(tid) == 0);
911
912    // Reset ROB/IQ/LSQ Entries
913
914    // Commented out for now.  This should be possible to do by
915    // telling all the pipeline stages to drain first, and then
916    // checking until the drain completes.  Once the pipeline is
917    // drained, call resetEntries(). - 10-09-06 ktlim
918/*
919    if (activeThreads.size() >= 1) {
920        commit.rob->resetEntries();
921        iew.resetEntries();
922    }
923*/
924}
925
926
927template <class Impl>
928void
929FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
930{
931    DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
932            "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
933            tid);
934
935    bool ready = true;
936
937    if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
938        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
939                "Phys. Int. Regs.\n",
940                tid);
941        ready = false;
942    } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
943        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
944                "Phys. Float. Regs.\n",
945                tid);
946        ready = false;
947    } else if (commit.rob->numFreeEntries() >=
948               commit.rob->entryAmount(activeThreads.size() + 1)) {
949        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
950                "ROB entries.\n",
951                tid);
952        ready = false;
953    } else if (iew.instQueue.numFreeEntries() >=
954               iew.instQueue.entryAmount(activeThreads.size() + 1)) {
955        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
956                "IQ entries.\n",
957                tid);
958        ready = false;
959    } else if (iew.ldstQueue.numFreeEntries() >=
960               iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
961        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
962                "LSQ entries.\n",
963                tid);
964        ready = false;
965    }
966
967    if (ready) {
968        insertThread(tid);
969
970        contextSwitch = false;
971
972        cpuWaitList.remove(tid);
973    } else {
974        suspendContext(tid);
975
976        //blocks fetch
977        contextSwitch = true;
978
979        //@todo: dont always add to waitlist
980        //do waitlist
981        cpuWaitList.push_back(tid);
982    }
983}
984
985template <class Impl>
986Fault
987FullO3CPU<Impl>::hwrei(ThreadID tid)
988{
989#if THE_ISA == ALPHA_ISA
990    // Need to clear the lock flag upon returning from an interrupt.
991    this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
992
993    this->thread[tid]->kernelStats->hwrei();
994
995    // FIXME: XXX check for interrupts? XXX
996#endif
997    return NoFault;
998}
999
1000template <class Impl>
1001bool
1002FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
1003{
1004#if THE_ISA == ALPHA_ISA
1005    if (this->thread[tid]->kernelStats)
1006        this->thread[tid]->kernelStats->callpal(palFunc,
1007                                                this->threadContexts[tid]);
1008
1009    switch (palFunc) {
1010      case PAL::halt:
1011        halt();
1012        if (--System::numSystemsRunning == 0)
1013            exitSimLoop("all cpus halted");
1014        break;
1015
1016      case PAL::bpt:
1017      case PAL::bugchk:
1018        if (this->system->breakpoint())
1019            return false;
1020        break;
1021    }
1022#endif
1023    return true;
1024}
1025
1026template <class Impl>
1027Fault
1028FullO3CPU<Impl>::getInterrupts()
1029{
1030    // Check if there are any outstanding interrupts
1031    return this->interrupts->getInterrupt(this->threadContexts[0]);
1032}
1033
1034template <class Impl>
1035void
1036FullO3CPU<Impl>::processInterrupts(Fault interrupt)
1037{
1038    // Check for interrupts here.  For now can copy the code that
1039    // exists within isa_fullsys_traits.hh.  Also assume that thread 0
1040    // is the one that handles the interrupts.
1041    // @todo: Possibly consolidate the interrupt checking code.
1042    // @todo: Allow other threads to handle interrupts.
1043
1044    assert(interrupt != NoFault);
1045    this->interrupts->updateIntrInfo(this->threadContexts[0]);
1046
1047    DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
1048    this->trap(interrupt, 0, NULL);
1049}
1050
1051template <class Impl>
1052void
1053FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst)
1054{
1055    // Pass the thread's TC into the invoke method.
1056    fault->invoke(this->threadContexts[tid], inst);
1057}
1058
1059template <class Impl>
1060void
1061FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
1062{
1063    DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
1064
1065    DPRINTF(Activity,"Activity: syscall() called.\n");
1066
1067    // Temporarily increase this by one to account for the syscall
1068    // instruction.
1069    ++(this->thread[tid]->funcExeInst);
1070
1071    // Execute the actual syscall.
1072    this->thread[tid]->syscall(callnum);
1073
1074    // Decrease funcExeInst by one as the normal commit will handle
1075    // incrementing it.
1076    --(this->thread[tid]->funcExeInst);
1077}
1078
1079template <class Impl>
1080void
1081FullO3CPU<Impl>::serialize(std::ostream &os)
1082{
1083    SimObject::State so_state = SimObject::getState();
1084    SERIALIZE_ENUM(so_state);
1085    BaseCPU::serialize(os);
1086    nameOut(os, csprintf("%s.tickEvent", name()));
1087    tickEvent.serialize(os);
1088
1089    // Use SimpleThread's ability to checkpoint to make it easier to
1090    // write out the registers.  Also make this static so it doesn't
1091    // get instantiated multiple times (causes a panic in statistics).
1092    static SimpleThread temp;
1093
1094    ThreadID size = thread.size();
1095    for (ThreadID i = 0; i < size; i++) {
1096        nameOut(os, csprintf("%s.xc.%i", name(), i));
1097        temp.copyTC(thread[i]->getTC());
1098        temp.serialize(os);
1099    }
1100}
1101
1102template <class Impl>
1103void
1104FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
1105{
1106    SimObject::State so_state;
1107    UNSERIALIZE_ENUM(so_state);
1108    BaseCPU::unserialize(cp, section);
1109    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
1110
1111    // Use SimpleThread's ability to checkpoint to make it easier to
1112    // read in the registers.  Also make this static so it doesn't
1113    // get instantiated multiple times (causes a panic in statistics).
1114    static SimpleThread temp;
1115
1116    ThreadID size = thread.size();
1117    for (ThreadID i = 0; i < size; i++) {
1118        temp.copyTC(thread[i]->getTC());
1119        temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
1120        thread[i]->getTC()->copyArchRegs(temp.getTC());
1121    }
1122}
1123
1124template <class Impl>
1125unsigned int
1126FullO3CPU<Impl>::drain(Event *drain_event)
1127{
1128    DPRINTF(O3CPU, "Switching out\n");
1129
1130    // If the CPU isn't doing anything, then return immediately.
1131    if (_status == Idle || _status == SwitchedOut) {
1132        return 0;
1133    }
1134
1135    drainCount = 0;
1136    fetch.drain();
1137    decode.drain();
1138    rename.drain();
1139    iew.drain();
1140    commit.drain();
1141
1142    // Wake the CPU and record activity so everything can drain out if
1143    // the CPU was not able to immediately drain.
1144    if (getState() != SimObject::Drained) {
1145        // A bit of a hack...set the drainEvent after all the drain()
1146        // calls have been made, that way if all of the stages drain
1147        // immediately, the signalDrained() function knows not to call
1148        // process on the drain event.
1149        drainEvent = drain_event;
1150
1151        wakeCPU();
1152        activityRec.activity();
1153
1154        return 1;
1155    } else {
1156        return 0;
1157    }
1158}
1159
1160template <class Impl>
1161void
1162FullO3CPU<Impl>::resume()
1163{
1164    fetch.resume();
1165    decode.resume();
1166    rename.resume();
1167    iew.resume();
1168    commit.resume();
1169
1170    changeState(SimObject::Running);
1171
1172    if (_status == SwitchedOut || _status == Idle)
1173        return;
1174
1175    assert(system->getMemoryMode() == Enums::timing);
1176
1177    if (!tickEvent.scheduled())
1178        schedule(tickEvent, nextCycle());
1179    _status = Running;
1180}
1181
1182template <class Impl>
1183void
1184FullO3CPU<Impl>::signalDrained()
1185{
1186    if (++drainCount == NumStages) {
1187        if (tickEvent.scheduled())
1188            tickEvent.squash();
1189
1190        changeState(SimObject::Drained);
1191
1192        BaseCPU::switchOut();
1193
1194        if (drainEvent) {
1195            drainEvent->process();
1196            drainEvent = NULL;
1197        }
1198    }
1199    assert(drainCount <= 5);
1200}
1201
1202template <class Impl>
1203void
1204FullO3CPU<Impl>::switchOut()
1205{
1206    fetch.switchOut();
1207    rename.switchOut();
1208    iew.switchOut();
1209    commit.switchOut();
1210    instList.clear();
1211    while (!removeList.empty()) {
1212        removeList.pop();
1213    }
1214
1215    _status = SwitchedOut;
1216#if USE_CHECKER
1217    if (checker)
1218        checker->switchOut();
1219#endif
1220    if (tickEvent.scheduled())
1221        tickEvent.squash();
1222}
1223
1224template <class Impl>
1225void
1226FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1227{
1228    // Flush out any old data from the time buffers.
1229    for (int i = 0; i < timeBuffer.getSize(); ++i) {
1230        timeBuffer.advance();
1231        fetchQueue.advance();
1232        decodeQueue.advance();
1233        renameQueue.advance();
1234        iewQueue.advance();
1235    }
1236
1237    activityRec.reset();
1238
1239    BaseCPU::takeOverFrom(oldCPU);
1240
1241    fetch.takeOverFrom();
1242    decode.takeOverFrom();
1243    rename.takeOverFrom();
1244    iew.takeOverFrom();
1245    commit.takeOverFrom();
1246
1247    assert(!tickEvent.scheduled() || tickEvent.squashed());
1248
1249    // @todo: Figure out how to properly select the tid to put onto
1250    // the active threads list.
1251    ThreadID tid = 0;
1252
1253    list<ThreadID>::iterator isActive =
1254        std::find(activeThreads.begin(), activeThreads.end(), tid);
1255
1256    if (isActive == activeThreads.end()) {
1257        //May Need to Re-code this if the delay variable is the delay
1258        //needed for thread to activate
1259        DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
1260                tid);
1261
1262        activeThreads.push_back(tid);
1263    }
1264
1265    // Set all statuses to active, schedule the CPU's tick event.
1266    // @todo: Fix up statuses so this is handled properly
1267    ThreadID size = threadContexts.size();
1268    for (ThreadID i = 0; i < size; ++i) {
1269        ThreadContext *tc = threadContexts[i];
1270        if (tc->status() == ThreadContext::Active && _status != Running) {
1271            _status = Running;
1272            reschedule(tickEvent, nextCycle(), true);
1273        }
1274    }
1275    if (!tickEvent.scheduled())
1276        schedule(tickEvent, nextCycle());
1277
1278    lastRunningCycle = curTick();
1279}
1280
1281template <class Impl>
1282TheISA::MiscReg
1283FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
1284{
1285    return this->isa[tid].readMiscRegNoEffect(misc_reg);
1286}
1287
1288template <class Impl>
1289TheISA::MiscReg
1290FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1291{
1292    miscRegfileReads++;
1293    return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
1294}
1295
1296template <class Impl>
1297void
1298FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
1299        const TheISA::MiscReg &val, ThreadID tid)
1300{
1301    this->isa[tid].setMiscRegNoEffect(misc_reg, val);
1302}
1303
1304template <class Impl>
1305void
1306FullO3CPU<Impl>::setMiscReg(int misc_reg,
1307        const TheISA::MiscReg &val, ThreadID tid)
1308{
1309    miscRegfileWrites++;
1310    this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
1311}
1312
1313template <class Impl>
1314uint64_t
1315FullO3CPU<Impl>::readIntReg(int reg_idx)
1316{
1317    intRegfileReads++;
1318    return regFile.readIntReg(reg_idx);
1319}
1320
1321template <class Impl>
1322FloatReg
1323FullO3CPU<Impl>::readFloatReg(int reg_idx)
1324{
1325    fpRegfileReads++;
1326    return regFile.readFloatReg(reg_idx);
1327}
1328
1329template <class Impl>
1330FloatRegBits
1331FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1332{
1333    fpRegfileReads++;
1334    return regFile.readFloatRegBits(reg_idx);
1335}
1336
1337template <class Impl>
1338void
1339FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1340{
1341    intRegfileWrites++;
1342    regFile.setIntReg(reg_idx, val);
1343}
1344
1345template <class Impl>
1346void
1347FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1348{
1349    fpRegfileWrites++;
1350    regFile.setFloatReg(reg_idx, val);
1351}
1352
1353template <class Impl>
1354void
1355FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1356{
1357    fpRegfileWrites++;
1358    regFile.setFloatRegBits(reg_idx, val);
1359}
1360
1361template <class Impl>
1362uint64_t
1363FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1364{
1365    intRegfileReads++;
1366    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1367
1368    return regFile.readIntReg(phys_reg);
1369}
1370
1371template <class Impl>
1372float
1373FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1374{
1375    fpRegfileReads++;
1376    int idx = reg_idx + TheISA::NumIntRegs;
1377    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1378
1379    return regFile.readFloatReg(phys_reg);
1380}
1381
1382template <class Impl>
1383uint64_t
1384FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
1385{
1386    fpRegfileReads++;
1387    int idx = reg_idx + TheISA::NumIntRegs;
1388    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1389
1390    return regFile.readFloatRegBits(phys_reg);
1391}
1392
1393template <class Impl>
1394void
1395FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
1396{
1397    intRegfileWrites++;
1398    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1399
1400    regFile.setIntReg(phys_reg, val);
1401}
1402
1403template <class Impl>
1404void
1405FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
1406{
1407    fpRegfileWrites++;
1408    int idx = reg_idx + TheISA::NumIntRegs;
1409    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1410
1411    regFile.setFloatReg(phys_reg, val);
1412}
1413
1414template <class Impl>
1415void
1416FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
1417{
1418    fpRegfileWrites++;
1419    int idx = reg_idx + TheISA::NumIntRegs;
1420    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1421
1422    regFile.setFloatRegBits(phys_reg, val);
1423}
1424
1425template <class Impl>
1426TheISA::PCState
1427FullO3CPU<Impl>::pcState(ThreadID tid)
1428{
1429    return commit.pcState(tid);
1430}
1431
1432template <class Impl>
1433void
1434FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1435{
1436    commit.pcState(val, tid);
1437}
1438
1439template <class Impl>
1440Addr
1441FullO3CPU<Impl>::instAddr(ThreadID tid)
1442{
1443    return commit.instAddr(tid);
1444}
1445
1446template <class Impl>
1447Addr
1448FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1449{
1450    return commit.nextInstAddr(tid);
1451}
1452
1453template <class Impl>
1454MicroPC
1455FullO3CPU<Impl>::microPC(ThreadID tid)
1456{
1457    return commit.microPC(tid);
1458}
1459
1460template <class Impl>
1461void
1462FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1463{
1464    this->thread[tid]->inSyscall = true;
1465    this->commit.generateTCEvent(tid);
1466}
1467
1468template <class Impl>
1469typename FullO3CPU<Impl>::ListIt
1470FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1471{
1472    instList.push_back(inst);
1473
1474    return --(instList.end());
1475}
1476
1477template <class Impl>
1478void
1479FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst)
1480{
1481    // Keep an instruction count.
1482    if (!inst->isMicroop() || inst->isLastMicroop()) {
1483        thread[tid]->numInst++;
1484        thread[tid]->numInsts++;
1485        committedInsts[tid]++;
1486        totalCommittedInsts++;
1487    }
1488    thread[tid]->numOp++;
1489    thread[tid]->numOps++;
1490    committedOps[tid]++;
1491
1492    system->totalNumInsts++;
1493    // Check for instruction-count-based events.
1494    comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1495    system->instEventQueue.serviceEvents(system->totalNumInsts);
1496}
1497
1498template <class Impl>
1499void
1500FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1501{
1502    DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1503            "[sn:%lli]\n",
1504            inst->threadNumber, inst->pcState(), inst->seqNum);
1505
1506    removeInstsThisCycle = true;
1507
1508    // Remove the front instruction.
1509    removeList.push(inst->getInstListIt());
1510}
1511
1512template <class Impl>
1513void
1514FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1515{
1516    DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1517            " list.\n", tid);
1518
1519    ListIt end_it;
1520
1521    bool rob_empty = false;
1522
1523    if (instList.empty()) {
1524        return;
1525    } else if (rob.isEmpty(/*tid*/)) {
1526        DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1527        end_it = instList.begin();
1528        rob_empty = true;
1529    } else {
1530        end_it = (rob.readTailInst(tid))->getInstListIt();
1531        DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1532    }
1533
1534    removeInstsThisCycle = true;
1535
1536    ListIt inst_it = instList.end();
1537
1538    inst_it--;
1539
1540    // Walk through the instruction list, removing any instructions
1541    // that were inserted after the given instruction iterator, end_it.
1542    while (inst_it != end_it) {
1543        assert(!instList.empty());
1544
1545        squashInstIt(inst_it, tid);
1546
1547        inst_it--;
1548    }
1549
1550    // If the ROB was empty, then we actually need to remove the first
1551    // instruction as well.
1552    if (rob_empty) {
1553        squashInstIt(inst_it, tid);
1554    }
1555}
1556
1557template <class Impl>
1558void
1559FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1560{
1561    assert(!instList.empty());
1562
1563    removeInstsThisCycle = true;
1564
1565    ListIt inst_iter = instList.end();
1566
1567    inst_iter--;
1568
1569    DPRINTF(O3CPU, "Deleting instructions from instruction "
1570            "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1571            tid, seq_num, (*inst_iter)->seqNum);
1572
1573    while ((*inst_iter)->seqNum > seq_num) {
1574
1575        bool break_loop = (inst_iter == instList.begin());
1576
1577        squashInstIt(inst_iter, tid);
1578
1579        inst_iter--;
1580
1581        if (break_loop)
1582            break;
1583    }
1584}
1585
1586template <class Impl>
1587inline void
1588FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1589{
1590    if ((*instIt)->threadNumber == tid) {
1591        DPRINTF(O3CPU, "Squashing instruction, "
1592                "[tid:%i] [sn:%lli] PC %s\n",
1593                (*instIt)->threadNumber,
1594                (*instIt)->seqNum,
1595                (*instIt)->pcState());
1596
1597        // Mark it as squashed.
1598        (*instIt)->setSquashed();
1599
1600        // @todo: Formulate a consistent method for deleting
1601        // instructions from the instruction list
1602        // Remove the instruction from the list.
1603        removeList.push(instIt);
1604    }
1605}
1606
1607template <class Impl>
1608void
1609FullO3CPU<Impl>::cleanUpRemovedInsts()
1610{
1611    while (!removeList.empty()) {
1612        DPRINTF(O3CPU, "Removing instruction, "
1613                "[tid:%i] [sn:%lli] PC %s\n",
1614                (*removeList.front())->threadNumber,
1615                (*removeList.front())->seqNum,
1616                (*removeList.front())->pcState());
1617
1618        instList.erase(removeList.front());
1619
1620        removeList.pop();
1621    }
1622
1623    removeInstsThisCycle = false;
1624}
1625/*
1626template <class Impl>
1627void
1628FullO3CPU<Impl>::removeAllInsts()
1629{
1630    instList.clear();
1631}
1632*/
1633template <class Impl>
1634void
1635FullO3CPU<Impl>::dumpInsts()
1636{
1637    int num = 0;
1638
1639    ListIt inst_list_it = instList.begin();
1640
1641    cprintf("Dumping Instruction List\n");
1642
1643    while (inst_list_it != instList.end()) {
1644        cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1645                "Squashed:%i\n\n",
1646                num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1647                (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1648                (*inst_list_it)->isSquashed());
1649        inst_list_it++;
1650        ++num;
1651    }
1652}
1653/*
1654template <class Impl>
1655void
1656FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1657{
1658    iew.wakeDependents(inst);
1659}
1660*/
1661template <class Impl>
1662void
1663FullO3CPU<Impl>::wakeCPU()
1664{
1665    if (activityRec.active() || tickEvent.scheduled()) {
1666        DPRINTF(Activity, "CPU already running.\n");
1667        return;
1668    }
1669
1670    DPRINTF(Activity, "Waking up CPU\n");
1671
1672    idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1673    numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
1674
1675    schedule(tickEvent, nextCycle());
1676}
1677
1678template <class Impl>
1679void
1680FullO3CPU<Impl>::wakeup()
1681{
1682    if (this->thread[0]->status() != ThreadContext::Suspended)
1683        return;
1684
1685    this->wakeCPU();
1686
1687    DPRINTF(Quiesce, "Suspended Processor woken\n");
1688    this->threadContexts[0]->activate();
1689}
1690
1691template <class Impl>
1692ThreadID
1693FullO3CPU<Impl>::getFreeTid()
1694{
1695    for (ThreadID tid = 0; tid < numThreads; tid++) {
1696        if (!tids[tid]) {
1697            tids[tid] = true;
1698            return tid;
1699        }
1700    }
1701
1702    return InvalidThreadID;
1703}
1704
1705template <class Impl>
1706void
1707FullO3CPU<Impl>::doContextSwitch()
1708{
1709    if (contextSwitch) {
1710
1711        //ADD CODE TO DEACTIVE THREAD HERE (???)
1712
1713        ThreadID size = cpuWaitList.size();
1714        for (ThreadID tid = 0; tid < size; tid++) {
1715            activateWhenReady(tid);
1716        }
1717
1718        if (cpuWaitList.size() == 0)
1719            contextSwitch = true;
1720    }
1721}
1722
1723template <class Impl>
1724void
1725FullO3CPU<Impl>::updateThreadPriority()
1726{
1727    if (activeThreads.size() > 1) {
1728        //DEFAULT TO ROUND ROBIN SCHEME
1729        //e.g. Move highest priority to end of thread list
1730        list<ThreadID>::iterator list_begin = activeThreads.begin();
1731
1732        unsigned high_thread = *list_begin;
1733
1734        activeThreads.erase(list_begin);
1735
1736        activeThreads.push_back(high_thread);
1737    }
1738}
1739
1740// Forward declaration of FullO3CPU.
1741template class FullO3CPU<O3CPUImpl>;
1742