cpu.cc revision 5958:2d9737bf3c2f
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include "config/full_system.hh" 33#include "config/use_checker.hh" 34 35#include "cpu/activity.hh" 36#include "cpu/simple_thread.hh" 37#include "cpu/thread_context.hh" 38#include "cpu/o3/isa_specific.hh" 39#include "cpu/o3/cpu.hh" 40#include "cpu/o3/thread_context.hh" 41#include "enums/MemoryMode.hh" 42#include "sim/core.hh" 43#include "sim/stat_control.hh" 44 45#if FULL_SYSTEM 46#include "cpu/quiesce_event.hh" 47#include "sim/system.hh" 48#else 49#include "sim/process.hh" 50#endif 51 52#if USE_CHECKER 53#include "cpu/checker/cpu.hh" 54#endif 55 56#if THE_ISA == ALPHA_ISA 57#include "arch/alpha/osfpal.hh" 58#endif 59 60class BaseCPUParams; 61 62using namespace TheISA; 63 64BaseO3CPU::BaseO3CPU(BaseCPUParams *params) 65 : BaseCPU(params) 66{ 67} 68 69void 70BaseO3CPU::regStats() 71{ 72 BaseCPU::regStats(); 73} 74 75template <class Impl> 76FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 77 : Event(CPU_Tick_Pri), cpu(c) 78{ 79} 80 81template <class Impl> 82void 83FullO3CPU<Impl>::TickEvent::process() 84{ 85 cpu->tick(); 86} 87 88template <class Impl> 89const char * 90FullO3CPU<Impl>::TickEvent::description() const 91{ 92 return "FullO3CPU tick"; 93} 94 95template <class Impl> 96FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 97 : Event(CPU_Switch_Pri) 98{ 99} 100 101template <class Impl> 102void 103FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 104 FullO3CPU<Impl> *thread_cpu) 105{ 106 tid = thread_num; 107 cpu = thread_cpu; 108} 109 110template <class Impl> 111void 112FullO3CPU<Impl>::ActivateThreadEvent::process() 113{ 114 cpu->activateThread(tid); 115} 116 117template <class Impl> 118const char * 119FullO3CPU<Impl>::ActivateThreadEvent::description() const 120{ 121 return "FullO3CPU \"Activate Thread\""; 122} 123 124template <class Impl> 125FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 126 : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 127{ 128} 129 130template <class Impl> 131void 132FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 133 FullO3CPU<Impl> *thread_cpu) 134{ 135 tid = thread_num; 136 cpu = thread_cpu; 137 remove = false; 138} 139 140template <class Impl> 141void 142FullO3CPU<Impl>::DeallocateContextEvent::process() 143{ 144 cpu->deactivateThread(tid); 145 if (remove) 146 cpu->removeThread(tid); 147} 148 149template <class Impl> 150const char * 151FullO3CPU<Impl>::DeallocateContextEvent::description() const 152{ 153 return "FullO3CPU \"Deallocate Context\""; 154} 155 156template <class Impl> 157FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 158 : BaseO3CPU(params), 159 itb(params->itb), 160 dtb(params->dtb), 161 tickEvent(this), 162#ifndef NDEBUG 163 instcount(0), 164#endif 165 removeInstsThisCycle(false), 166 fetch(this, params), 167 decode(this, params), 168 rename(this, params), 169 iew(this, params), 170 commit(this, params), 171 172 regFile(this, params->numPhysIntRegs, 173 params->numPhysFloatRegs), 174 175 freeList(params->numThreads, 176 TheISA::NumIntRegs, params->numPhysIntRegs, 177 TheISA::NumFloatRegs, params->numPhysFloatRegs), 178 179 rob(this, 180 params->numROBEntries, params->squashWidth, 181 params->smtROBPolicy, params->smtROBThreshold, 182 params->numThreads), 183 184 scoreboard(params->numThreads, 185 TheISA::NumIntRegs, params->numPhysIntRegs, 186 TheISA::NumFloatRegs, params->numPhysFloatRegs, 187 TheISA::NumMiscRegs * number_of_threads, 188 TheISA::ZeroReg), 189 190 timeBuffer(params->backComSize, params->forwardComSize), 191 fetchQueue(params->backComSize, params->forwardComSize), 192 decodeQueue(params->backComSize, params->forwardComSize), 193 renameQueue(params->backComSize, params->forwardComSize), 194 iewQueue(params->backComSize, params->forwardComSize), 195 activityRec(name(), NumStages, 196 params->backComSize + params->forwardComSize, 197 params->activity), 198 199 globalSeqNum(1), 200#if FULL_SYSTEM 201 system(params->system), 202 physmem(system->physmem), 203#endif // FULL_SYSTEM 204 drainCount(0), 205 deferRegistration(params->defer_registration), 206 numThreads(number_of_threads) 207{ 208 if (!deferRegistration) { 209 _status = Running; 210 } else { 211 _status = Idle; 212 } 213 214#if USE_CHECKER 215 if (params->checker) { 216 BaseCPU *temp_checker = params->checker; 217 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 218#if FULL_SYSTEM 219 checker->setSystem(params->system); 220#endif 221 } else { 222 checker = NULL; 223 } 224#endif // USE_CHECKER 225 226#if !FULL_SYSTEM 227 thread.resize(number_of_threads); 228 tids.resize(number_of_threads); 229#endif 230 231 // The stages also need their CPU pointer setup. However this 232 // must be done at the upper level CPU because they have pointers 233 // to the upper level CPU, and not this FullO3CPU. 234 235 // Set up Pointers to the activeThreads list for each stage 236 fetch.setActiveThreads(&activeThreads); 237 decode.setActiveThreads(&activeThreads); 238 rename.setActiveThreads(&activeThreads); 239 iew.setActiveThreads(&activeThreads); 240 commit.setActiveThreads(&activeThreads); 241 242 // Give each of the stages the time buffer they will use. 243 fetch.setTimeBuffer(&timeBuffer); 244 decode.setTimeBuffer(&timeBuffer); 245 rename.setTimeBuffer(&timeBuffer); 246 iew.setTimeBuffer(&timeBuffer); 247 commit.setTimeBuffer(&timeBuffer); 248 249 // Also setup each of the stages' queues. 250 fetch.setFetchQueue(&fetchQueue); 251 decode.setFetchQueue(&fetchQueue); 252 commit.setFetchQueue(&fetchQueue); 253 decode.setDecodeQueue(&decodeQueue); 254 rename.setDecodeQueue(&decodeQueue); 255 rename.setRenameQueue(&renameQueue); 256 iew.setRenameQueue(&renameQueue); 257 iew.setIEWQueue(&iewQueue); 258 commit.setIEWQueue(&iewQueue); 259 commit.setRenameQueue(&renameQueue); 260 261 commit.setIEWStage(&iew); 262 rename.setIEWStage(&iew); 263 rename.setCommitStage(&commit); 264 265#if !FULL_SYSTEM 266 int active_threads = params->workload.size(); 267 268 if (active_threads > Impl::MaxThreads) { 269 panic("Workload Size too large. Increase the 'MaxThreads'" 270 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 271 "edit your workload size."); 272 } 273#else 274 int active_threads = 1; 275#endif 276 277 //Make Sure That this a Valid Architeture 278 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 279 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 280 281 rename.setScoreboard(&scoreboard); 282 iew.setScoreboard(&scoreboard); 283 284 // Setup the rename map for whichever stages need it. 285 PhysRegIndex lreg_idx = 0; 286 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 287 288 for (int tid=0; tid < numThreads; tid++) { 289 bool bindRegs = (tid <= active_threads - 1); 290 291 commitRenameMap[tid].init(TheISA::NumIntRegs, 292 params->numPhysIntRegs, 293 lreg_idx, //Index for Logical. Regs 294 295 TheISA::NumFloatRegs, 296 params->numPhysFloatRegs, 297 freg_idx, //Index for Float Regs 298 299 TheISA::NumMiscRegs, 300 301 TheISA::ZeroReg, 302 TheISA::ZeroReg, 303 304 tid, 305 false); 306 307 renameMap[tid].init(TheISA::NumIntRegs, 308 params->numPhysIntRegs, 309 lreg_idx, //Index for Logical. Regs 310 311 TheISA::NumFloatRegs, 312 params->numPhysFloatRegs, 313 freg_idx, //Index for Float Regs 314 315 TheISA::NumMiscRegs, 316 317 TheISA::ZeroReg, 318 TheISA::ZeroReg, 319 320 tid, 321 bindRegs); 322 323 activateThreadEvent[tid].init(tid, this); 324 deallocateContextEvent[tid].init(tid, this); 325 } 326 327 rename.setRenameMap(renameMap); 328 commit.setRenameMap(commitRenameMap); 329 330 // Give renameMap & rename stage access to the freeList; 331 for (int i=0; i < numThreads; i++) { 332 renameMap[i].setFreeList(&freeList); 333 } 334 rename.setFreeList(&freeList); 335 336 // Setup the ROB for whichever stages need it. 337 commit.setROB(&rob); 338 339 lastRunningCycle = curTick; 340 341 lastActivatedCycle = -1; 342 343 // Give renameMap & rename stage access to the freeList; 344 //for (int i=0; i < numThreads; i++) { 345 //globalSeqNum[i] = 1; 346 //} 347 348 contextSwitch = false; 349 DPRINTF(O3CPU, "Creating O3CPU object.\n"); 350 351 // Setup any thread state. 352 this->thread.resize(this->numThreads); 353 354 for (int i = 0; i < this->numThreads; ++i) { 355#if FULL_SYSTEM 356 // SMT is not supported in FS mode yet. 357 assert(this->numThreads == 1); 358 this->thread[i] = new Thread(this, 0); 359 this->thread[i]->setStatus(ThreadContext::Suspended); 360#else 361 if (i < params->workload.size()) { 362 DPRINTF(O3CPU, "Workload[%i] process is %#x", 363 i, this->thread[i]); 364 this->thread[i] = new typename FullO3CPU<Impl>::Thread( 365 (typename Impl::O3CPU *)(this), 366 i, params->workload[i], i); 367 368 this->thread[i]->setStatus(ThreadContext::Suspended); 369 370 //usedTids[i] = true; 371 //threadMap[i] = i; 372 } else { 373 //Allocate Empty thread so M5 can use later 374 //when scheduling threads to CPU 375 Process* dummy_proc = NULL; 376 377 this->thread[i] = new typename FullO3CPU<Impl>::Thread( 378 (typename Impl::O3CPU *)(this), 379 i, dummy_proc, i); 380 //usedTids[i] = false; 381 } 382#endif // !FULL_SYSTEM 383 384 ThreadContext *tc; 385 386 // Setup the TC that will serve as the interface to the threads/CPU. 387 O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 388 389 tc = o3_tc; 390 391 // If we're using a checker, then the TC should be the 392 // CheckerThreadContext. 393#if USE_CHECKER 394 if (params->checker) { 395 tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 396 o3_tc, this->checker); 397 } 398#endif 399 400 o3_tc->cpu = (typename Impl::O3CPU *)(this); 401 assert(o3_tc->cpu); 402 o3_tc->thread = this->thread[i]; 403 404#if FULL_SYSTEM 405 // Setup quiesce event. 406 this->thread[i]->quiesceEvent = new EndQuiesceEvent(tc); 407#endif 408 // Give the thread the TC. 409 this->thread[i]->tc = tc; 410 411 // Add the TC to the CPU's list of TC's. 412 this->threadContexts.push_back(tc); 413 } 414 415 for (int i=0; i < this->numThreads; i++) { 416 this->thread[i]->setFuncExeInst(0); 417 } 418 419 lockAddr = 0; 420 lockFlag = false; 421} 422 423template <class Impl> 424FullO3CPU<Impl>::~FullO3CPU() 425{ 426} 427 428template <class Impl> 429void 430FullO3CPU<Impl>::regStats() 431{ 432 BaseO3CPU::regStats(); 433 434 // Register any of the O3CPU's stats here. 435 timesIdled 436 .name(name() + ".timesIdled") 437 .desc("Number of times that the entire CPU went into an idle state and" 438 " unscheduled itself") 439 .prereq(timesIdled); 440 441 idleCycles 442 .name(name() + ".idleCycles") 443 .desc("Total number of cycles that the CPU has spent unscheduled due " 444 "to idling") 445 .prereq(idleCycles); 446 447 // Number of Instructions simulated 448 // -------------------------------- 449 // Should probably be in Base CPU but need templated 450 // MaxThreads so put in here instead 451 committedInsts 452 .init(numThreads) 453 .name(name() + ".committedInsts") 454 .desc("Number of Instructions Simulated"); 455 456 totalCommittedInsts 457 .name(name() + ".committedInsts_total") 458 .desc("Number of Instructions Simulated"); 459 460 cpi 461 .name(name() + ".cpi") 462 .desc("CPI: Cycles Per Instruction") 463 .precision(6); 464 cpi = numCycles / committedInsts; 465 466 totalCpi 467 .name(name() + ".cpi_total") 468 .desc("CPI: Total CPI of All Threads") 469 .precision(6); 470 totalCpi = numCycles / totalCommittedInsts; 471 472 ipc 473 .name(name() + ".ipc") 474 .desc("IPC: Instructions Per Cycle") 475 .precision(6); 476 ipc = committedInsts / numCycles; 477 478 totalIpc 479 .name(name() + ".ipc_total") 480 .desc("IPC: Total IPC of All Threads") 481 .precision(6); 482 totalIpc = totalCommittedInsts / numCycles; 483 484 this->fetch.regStats(); 485 this->decode.regStats(); 486 this->rename.regStats(); 487 this->iew.regStats(); 488 this->commit.regStats(); 489} 490 491template <class Impl> 492Port * 493FullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 494{ 495 if (if_name == "dcache_port") 496 return iew.getDcachePort(); 497 else if (if_name == "icache_port") 498 return fetch.getIcachePort(); 499 else 500 panic("No Such Port\n"); 501} 502 503template <class Impl> 504void 505FullO3CPU<Impl>::tick() 506{ 507 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 508 509 ++numCycles; 510 511// activity = false; 512 513 //Tick each of the stages 514 fetch.tick(); 515 516 decode.tick(); 517 518 rename.tick(); 519 520 iew.tick(); 521 522 commit.tick(); 523 524#if !FULL_SYSTEM 525 doContextSwitch(); 526#endif 527 528 // Now advance the time buffers 529 timeBuffer.advance(); 530 531 fetchQueue.advance(); 532 decodeQueue.advance(); 533 renameQueue.advance(); 534 iewQueue.advance(); 535 536 activityRec.advance(); 537 538 if (removeInstsThisCycle) { 539 cleanUpRemovedInsts(); 540 } 541 542 if (!tickEvent.scheduled()) { 543 if (_status == SwitchedOut || 544 getState() == SimObject::Drained) { 545 DPRINTF(O3CPU, "Switched out!\n"); 546 // increment stat 547 lastRunningCycle = curTick; 548 } else if (!activityRec.active() || _status == Idle) { 549 DPRINTF(O3CPU, "Idle!\n"); 550 lastRunningCycle = curTick; 551 timesIdled++; 552 } else { 553 schedule(tickEvent, nextCycle(curTick + ticks(1))); 554 DPRINTF(O3CPU, "Scheduling next tick!\n"); 555 } 556 } 557 558#if !FULL_SYSTEM 559 updateThreadPriority(); 560#endif 561} 562 563template <class Impl> 564void 565FullO3CPU<Impl>::init() 566{ 567 BaseCPU::init(); 568 569 // Set inSyscall so that the CPU doesn't squash when initially 570 // setting up registers. 571 for (int i = 0; i < number_of_threads; ++i) 572 thread[i]->inSyscall = true; 573 574 for (int tid=0; tid < number_of_threads; tid++) { 575#if FULL_SYSTEM 576 ThreadContext *src_tc = threadContexts[tid]; 577#else 578 ThreadContext *src_tc = thread[tid]->getTC(); 579#endif 580 // Threads start in the Suspended State 581 if (src_tc->status() != ThreadContext::Suspended) { 582 continue; 583 } 584 585#if FULL_SYSTEM 586 TheISA::initCPU(src_tc, src_tc->contextId()); 587#endif 588 } 589 590 // Clear inSyscall. 591 for (int i = 0; i < number_of_threads; ++i) 592 thread[i]->inSyscall = false; 593 594 // Initialize stages. 595 fetch.initStage(); 596 iew.initStage(); 597 rename.initStage(); 598 commit.initStage(); 599 600 commit.setThreads(thread); 601} 602 603template <class Impl> 604void 605FullO3CPU<Impl>::activateThread(unsigned tid) 606{ 607 std::list<unsigned>::iterator isActive = 608 std::find(activeThreads.begin(), activeThreads.end(), tid); 609 610 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 611 612 if (isActive == activeThreads.end()) { 613 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 614 tid); 615 616 activeThreads.push_back(tid); 617 } 618} 619 620template <class Impl> 621void 622FullO3CPU<Impl>::deactivateThread(unsigned tid) 623{ 624 //Remove From Active List, if Active 625 std::list<unsigned>::iterator thread_it = 626 std::find(activeThreads.begin(), activeThreads.end(), tid); 627 628 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 629 630 if (thread_it != activeThreads.end()) { 631 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 632 tid); 633 activeThreads.erase(thread_it); 634 } 635} 636 637template <class Impl> 638void 639FullO3CPU<Impl>::activateContext(int tid, int delay) 640{ 641 // Needs to set each stage to running as well. 642 if (delay){ 643 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 644 "on cycle %d\n", tid, curTick + ticks(delay)); 645 scheduleActivateThreadEvent(tid, delay); 646 } else { 647 activateThread(tid); 648 } 649 650 if (lastActivatedCycle < curTick) { 651 scheduleTickEvent(delay); 652 653 // Be sure to signal that there's some activity so the CPU doesn't 654 // deschedule itself. 655 activityRec.activity(); 656 fetch.wakeFromQuiesce(); 657 658 lastActivatedCycle = curTick; 659 660 _status = Running; 661 } 662} 663 664template <class Impl> 665bool 666FullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay) 667{ 668 // Schedule removal of thread data from CPU 669 if (delay){ 670 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 671 "on cycle %d\n", tid, curTick + ticks(delay)); 672 scheduleDeallocateContextEvent(tid, remove, delay); 673 return false; 674 } else { 675 deactivateThread(tid); 676 if (remove) 677 removeThread(tid); 678 return true; 679 } 680} 681 682template <class Impl> 683void 684FullO3CPU<Impl>::suspendContext(int tid) 685{ 686 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 687 bool deallocated = deallocateContext(tid, false, 1); 688 // If this was the last thread then unschedule the tick event. 689 if ((activeThreads.size() == 1 && !deallocated) || 690 activeThreads.size() == 0) 691 unscheduleTickEvent(); 692 _status = Idle; 693} 694 695template <class Impl> 696void 697FullO3CPU<Impl>::haltContext(int tid) 698{ 699 //For now, this is the same as deallocate 700 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 701 deallocateContext(tid, true, 1); 702} 703 704template <class Impl> 705void 706FullO3CPU<Impl>::insertThread(unsigned tid) 707{ 708 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 709 // Will change now that the PC and thread state is internal to the CPU 710 // and not in the ThreadContext. 711#if FULL_SYSTEM 712 ThreadContext *src_tc = system->threadContexts[tid]; 713#else 714 ThreadContext *src_tc = tcBase(tid); 715#endif 716 717 //Bind Int Regs to Rename Map 718 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 719 PhysRegIndex phys_reg = freeList.getIntReg(); 720 721 renameMap[tid].setEntry(ireg,phys_reg); 722 scoreboard.setReg(phys_reg); 723 } 724 725 //Bind Float Regs to Rename Map 726 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 727 PhysRegIndex phys_reg = freeList.getFloatReg(); 728 729 renameMap[tid].setEntry(freg,phys_reg); 730 scoreboard.setReg(phys_reg); 731 } 732 733 //Copy Thread Data Into RegFile 734 //this->copyFromTC(tid); 735 736 //Set PC/NPC/NNPC 737 setPC(src_tc->readPC(), tid); 738 setNextPC(src_tc->readNextPC(), tid); 739 setNextNPC(src_tc->readNextNPC(), tid); 740 741 src_tc->setStatus(ThreadContext::Active); 742 743 activateContext(tid,1); 744 745 //Reset ROB/IQ/LSQ Entries 746 commit.rob->resetEntries(); 747 iew.resetEntries(); 748} 749 750template <class Impl> 751void 752FullO3CPU<Impl>::removeThread(unsigned tid) 753{ 754 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 755 756 // Copy Thread Data From RegFile 757 // If thread is suspended, it might be re-allocated 758 // this->copyToTC(tid); 759 760 761 // @todo: 2-27-2008: Fix how we free up rename mappings 762 // here to alleviate the case for double-freeing registers 763 // in SMT workloads. 764 765 // Unbind Int Regs from Rename Map 766 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 767 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 768 769 scoreboard.unsetReg(phys_reg); 770 freeList.addReg(phys_reg); 771 } 772 773 // Unbind Float Regs from Rename Map 774 for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 775 PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 776 777 scoreboard.unsetReg(phys_reg); 778 freeList.addReg(phys_reg); 779 } 780 781 // Squash Throughout Pipeline 782 InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; 783 fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid); 784 decode.squash(tid); 785 rename.squash(squash_seq_num, tid); 786 iew.squash(tid); 787 iew.ldstQueue.squash(squash_seq_num, tid); 788 commit.rob->squash(squash_seq_num, tid); 789 790 791 assert(iew.instQueue.getCount(tid) == 0); 792 assert(iew.ldstQueue.getCount(tid) == 0); 793 794 // Reset ROB/IQ/LSQ Entries 795 796 // Commented out for now. This should be possible to do by 797 // telling all the pipeline stages to drain first, and then 798 // checking until the drain completes. Once the pipeline is 799 // drained, call resetEntries(). - 10-09-06 ktlim 800/* 801 if (activeThreads.size() >= 1) { 802 commit.rob->resetEntries(); 803 iew.resetEntries(); 804 } 805*/ 806} 807 808 809template <class Impl> 810void 811FullO3CPU<Impl>::activateWhenReady(int tid) 812{ 813 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 814 "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 815 tid); 816 817 bool ready = true; 818 819 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 820 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 821 "Phys. Int. Regs.\n", 822 tid); 823 ready = false; 824 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 825 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 826 "Phys. Float. Regs.\n", 827 tid); 828 ready = false; 829 } else if (commit.rob->numFreeEntries() >= 830 commit.rob->entryAmount(activeThreads.size() + 1)) { 831 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 832 "ROB entries.\n", 833 tid); 834 ready = false; 835 } else if (iew.instQueue.numFreeEntries() >= 836 iew.instQueue.entryAmount(activeThreads.size() + 1)) { 837 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 838 "IQ entries.\n", 839 tid); 840 ready = false; 841 } else if (iew.ldstQueue.numFreeEntries() >= 842 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 843 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 844 "LSQ entries.\n", 845 tid); 846 ready = false; 847 } 848 849 if (ready) { 850 insertThread(tid); 851 852 contextSwitch = false; 853 854 cpuWaitList.remove(tid); 855 } else { 856 suspendContext(tid); 857 858 //blocks fetch 859 contextSwitch = true; 860 861 //@todo: dont always add to waitlist 862 //do waitlist 863 cpuWaitList.push_back(tid); 864 } 865} 866 867#if FULL_SYSTEM 868template <class Impl> 869Fault 870FullO3CPU<Impl>::hwrei(unsigned tid) 871{ 872#if THE_ISA == ALPHA_ISA 873 // Need to clear the lock flag upon returning from an interrupt. 874 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 875 876 this->thread[tid]->kernelStats->hwrei(); 877 878 // FIXME: XXX check for interrupts? XXX 879#endif 880 return NoFault; 881} 882 883template <class Impl> 884bool 885FullO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid) 886{ 887#if THE_ISA == ALPHA_ISA 888 if (this->thread[tid]->kernelStats) 889 this->thread[tid]->kernelStats->callpal(palFunc, 890 this->threadContexts[tid]); 891 892 switch (palFunc) { 893 case PAL::halt: 894 halt(); 895 if (--System::numSystemsRunning == 0) 896 exitSimLoop("all cpus halted"); 897 break; 898 899 case PAL::bpt: 900 case PAL::bugchk: 901 if (this->system->breakpoint()) 902 return false; 903 break; 904 } 905#endif 906 return true; 907} 908 909template <class Impl> 910Fault 911FullO3CPU<Impl>::getInterrupts() 912{ 913 // Check if there are any outstanding interrupts 914 return this->interrupts->getInterrupt(this->threadContexts[0]); 915} 916 917template <class Impl> 918void 919FullO3CPU<Impl>::processInterrupts(Fault interrupt) 920{ 921 // Check for interrupts here. For now can copy the code that 922 // exists within isa_fullsys_traits.hh. Also assume that thread 0 923 // is the one that handles the interrupts. 924 // @todo: Possibly consolidate the interrupt checking code. 925 // @todo: Allow other threads to handle interrupts. 926 927 assert(interrupt != NoFault); 928 this->interrupts->updateIntrInfo(this->threadContexts[0]); 929 930 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 931 this->trap(interrupt, 0); 932} 933 934template <class Impl> 935void 936FullO3CPU<Impl>::updateMemPorts() 937{ 938 // Update all ThreadContext's memory ports (Functional/Virtual 939 // Ports) 940 for (int i = 0; i < thread.size(); ++i) 941 thread[i]->connectMemPorts(thread[i]->getTC()); 942} 943#endif 944 945template <class Impl> 946void 947FullO3CPU<Impl>::trap(Fault fault, unsigned tid) 948{ 949 // Pass the thread's TC into the invoke method. 950 fault->invoke(this->threadContexts[tid]); 951} 952 953#if !FULL_SYSTEM 954 955template <class Impl> 956void 957FullO3CPU<Impl>::syscall(int64_t callnum, int tid) 958{ 959 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 960 961 DPRINTF(Activity,"Activity: syscall() called.\n"); 962 963 // Temporarily increase this by one to account for the syscall 964 // instruction. 965 ++(this->thread[tid]->funcExeInst); 966 967 // Execute the actual syscall. 968 this->thread[tid]->syscall(callnum); 969 970 // Decrease funcExeInst by one as the normal commit will handle 971 // incrementing it. 972 --(this->thread[tid]->funcExeInst); 973} 974 975#endif 976 977template <class Impl> 978void 979FullO3CPU<Impl>::serialize(std::ostream &os) 980{ 981 SimObject::State so_state = SimObject::getState(); 982 SERIALIZE_ENUM(so_state); 983 BaseCPU::serialize(os); 984 nameOut(os, csprintf("%s.tickEvent", name())); 985 tickEvent.serialize(os); 986 987 // Use SimpleThread's ability to checkpoint to make it easier to 988 // write out the registers. Also make this static so it doesn't 989 // get instantiated multiple times (causes a panic in statistics). 990 static SimpleThread temp; 991 992 for (int i = 0; i < thread.size(); i++) { 993 nameOut(os, csprintf("%s.xc.%i", name(), i)); 994 temp.copyTC(thread[i]->getTC()); 995 temp.serialize(os); 996 } 997} 998 999template <class Impl> 1000void 1001FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 1002{ 1003 SimObject::State so_state; 1004 UNSERIALIZE_ENUM(so_state); 1005 BaseCPU::unserialize(cp, section); 1006 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 1007 1008 // Use SimpleThread's ability to checkpoint to make it easier to 1009 // read in the registers. Also make this static so it doesn't 1010 // get instantiated multiple times (causes a panic in statistics). 1011 static SimpleThread temp; 1012 1013 for (int i = 0; i < thread.size(); i++) { 1014 temp.copyTC(thread[i]->getTC()); 1015 temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 1016 thread[i]->getTC()->copyArchRegs(temp.getTC()); 1017 } 1018} 1019 1020template <class Impl> 1021unsigned int 1022FullO3CPU<Impl>::drain(Event *drain_event) 1023{ 1024 DPRINTF(O3CPU, "Switching out\n"); 1025 1026 // If the CPU isn't doing anything, then return immediately. 1027 if (_status == Idle || _status == SwitchedOut) { 1028 return 0; 1029 } 1030 1031 drainCount = 0; 1032 fetch.drain(); 1033 decode.drain(); 1034 rename.drain(); 1035 iew.drain(); 1036 commit.drain(); 1037 1038 // Wake the CPU and record activity so everything can drain out if 1039 // the CPU was not able to immediately drain. 1040 if (getState() != SimObject::Drained) { 1041 // A bit of a hack...set the drainEvent after all the drain() 1042 // calls have been made, that way if all of the stages drain 1043 // immediately, the signalDrained() function knows not to call 1044 // process on the drain event. 1045 drainEvent = drain_event; 1046 1047 wakeCPU(); 1048 activityRec.activity(); 1049 1050 return 1; 1051 } else { 1052 return 0; 1053 } 1054} 1055 1056template <class Impl> 1057void 1058FullO3CPU<Impl>::resume() 1059{ 1060 fetch.resume(); 1061 decode.resume(); 1062 rename.resume(); 1063 iew.resume(); 1064 commit.resume(); 1065 1066 changeState(SimObject::Running); 1067 1068 if (_status == SwitchedOut || _status == Idle) 1069 return; 1070 1071#if FULL_SYSTEM 1072 assert(system->getMemoryMode() == Enums::timing); 1073#endif 1074 1075 if (!tickEvent.scheduled()) 1076 schedule(tickEvent, nextCycle()); 1077 _status = Running; 1078} 1079 1080template <class Impl> 1081void 1082FullO3CPU<Impl>::signalDrained() 1083{ 1084 if (++drainCount == NumStages) { 1085 if (tickEvent.scheduled()) 1086 tickEvent.squash(); 1087 1088 changeState(SimObject::Drained); 1089 1090 BaseCPU::switchOut(); 1091 1092 if (drainEvent) { 1093 drainEvent->process(); 1094 drainEvent = NULL; 1095 } 1096 } 1097 assert(drainCount <= 5); 1098} 1099 1100template <class Impl> 1101void 1102FullO3CPU<Impl>::switchOut() 1103{ 1104 fetch.switchOut(); 1105 rename.switchOut(); 1106 iew.switchOut(); 1107 commit.switchOut(); 1108 instList.clear(); 1109 while (!removeList.empty()) { 1110 removeList.pop(); 1111 } 1112 1113 _status = SwitchedOut; 1114#if USE_CHECKER 1115 if (checker) 1116 checker->switchOut(); 1117#endif 1118 if (tickEvent.scheduled()) 1119 tickEvent.squash(); 1120} 1121 1122template <class Impl> 1123void 1124FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 1125{ 1126 // Flush out any old data from the time buffers. 1127 for (int i = 0; i < timeBuffer.getSize(); ++i) { 1128 timeBuffer.advance(); 1129 fetchQueue.advance(); 1130 decodeQueue.advance(); 1131 renameQueue.advance(); 1132 iewQueue.advance(); 1133 } 1134 1135 activityRec.reset(); 1136 1137 BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort()); 1138 1139 fetch.takeOverFrom(); 1140 decode.takeOverFrom(); 1141 rename.takeOverFrom(); 1142 iew.takeOverFrom(); 1143 commit.takeOverFrom(); 1144 1145 assert(!tickEvent.scheduled()); 1146 1147 // @todo: Figure out how to properly select the tid to put onto 1148 // the active threads list. 1149 int tid = 0; 1150 1151 std::list<unsigned>::iterator isActive = 1152 std::find(activeThreads.begin(), activeThreads.end(), tid); 1153 1154 if (isActive == activeThreads.end()) { 1155 //May Need to Re-code this if the delay variable is the delay 1156 //needed for thread to activate 1157 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 1158 tid); 1159 1160 activeThreads.push_back(tid); 1161 } 1162 1163 // Set all statuses to active, schedule the CPU's tick event. 1164 // @todo: Fix up statuses so this is handled properly 1165 for (int i = 0; i < threadContexts.size(); ++i) { 1166 ThreadContext *tc = threadContexts[i]; 1167 if (tc->status() == ThreadContext::Active && _status != Running) { 1168 _status = Running; 1169 schedule(tickEvent, nextCycle()); 1170 } 1171 } 1172 if (!tickEvent.scheduled()) 1173 schedule(tickEvent, nextCycle()); 1174} 1175 1176template <class Impl> 1177TheISA::MiscReg 1178FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid) 1179{ 1180 return this->regFile.readMiscRegNoEffect(misc_reg, tid); 1181} 1182 1183template <class Impl> 1184TheISA::MiscReg 1185FullO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) 1186{ 1187 return this->regFile.readMiscReg(misc_reg, tid); 1188} 1189 1190template <class Impl> 1191void 1192FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 1193 const TheISA::MiscReg &val, unsigned tid) 1194{ 1195 this->regFile.setMiscRegNoEffect(misc_reg, val, tid); 1196} 1197 1198template <class Impl> 1199void 1200FullO3CPU<Impl>::setMiscReg(int misc_reg, 1201 const TheISA::MiscReg &val, unsigned tid) 1202{ 1203 this->regFile.setMiscReg(misc_reg, val, tid); 1204} 1205 1206template <class Impl> 1207uint64_t 1208FullO3CPU<Impl>::readIntReg(int reg_idx) 1209{ 1210 return regFile.readIntReg(reg_idx); 1211} 1212 1213template <class Impl> 1214FloatReg 1215FullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 1216{ 1217 return regFile.readFloatReg(reg_idx, width); 1218} 1219 1220template <class Impl> 1221FloatReg 1222FullO3CPU<Impl>::readFloatReg(int reg_idx) 1223{ 1224 return regFile.readFloatReg(reg_idx); 1225} 1226 1227template <class Impl> 1228FloatRegBits 1229FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 1230{ 1231 return regFile.readFloatRegBits(reg_idx, width); 1232} 1233 1234template <class Impl> 1235FloatRegBits 1236FullO3CPU<Impl>::readFloatRegBits(int reg_idx) 1237{ 1238 return regFile.readFloatRegBits(reg_idx); 1239} 1240 1241template <class Impl> 1242void 1243FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 1244{ 1245 regFile.setIntReg(reg_idx, val); 1246} 1247 1248template <class Impl> 1249void 1250FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 1251{ 1252 regFile.setFloatReg(reg_idx, val, width); 1253} 1254 1255template <class Impl> 1256void 1257FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 1258{ 1259 regFile.setFloatReg(reg_idx, val); 1260} 1261 1262template <class Impl> 1263void 1264FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 1265{ 1266 regFile.setFloatRegBits(reg_idx, val, width); 1267} 1268 1269template <class Impl> 1270void 1271FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 1272{ 1273 regFile.setFloatRegBits(reg_idx, val); 1274} 1275 1276template <class Impl> 1277uint64_t 1278FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 1279{ 1280 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 1281 1282 return regFile.readIntReg(phys_reg); 1283} 1284 1285template <class Impl> 1286float 1287FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 1288{ 1289 int idx = reg_idx + TheISA::FP_Base_DepTag; 1290 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1291 1292 return regFile.readFloatReg(phys_reg); 1293} 1294 1295template <class Impl> 1296double 1297FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 1298{ 1299 int idx = reg_idx + TheISA::FP_Base_DepTag; 1300 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1301 1302 return regFile.readFloatReg(phys_reg, 64); 1303} 1304 1305template <class Impl> 1306uint64_t 1307FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 1308{ 1309 int idx = reg_idx + TheISA::FP_Base_DepTag; 1310 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1311 1312 return regFile.readFloatRegBits(phys_reg); 1313} 1314 1315template <class Impl> 1316void 1317FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 1318{ 1319 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 1320 1321 regFile.setIntReg(phys_reg, val); 1322} 1323 1324template <class Impl> 1325void 1326FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 1327{ 1328 int idx = reg_idx + TheISA::FP_Base_DepTag; 1329 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1330 1331 regFile.setFloatReg(phys_reg, val); 1332} 1333 1334template <class Impl> 1335void 1336FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 1337{ 1338 int idx = reg_idx + TheISA::FP_Base_DepTag; 1339 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1340 1341 regFile.setFloatReg(phys_reg, val, 64); 1342} 1343 1344template <class Impl> 1345void 1346FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 1347{ 1348 int idx = reg_idx + TheISA::FP_Base_DepTag; 1349 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 1350 1351 regFile.setFloatRegBits(phys_reg, val); 1352} 1353 1354template <class Impl> 1355uint64_t 1356FullO3CPU<Impl>::readPC(unsigned tid) 1357{ 1358 return commit.readPC(tid); 1359} 1360 1361template <class Impl> 1362void 1363FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 1364{ 1365 commit.setPC(new_PC, tid); 1366} 1367 1368template <class Impl> 1369uint64_t 1370FullO3CPU<Impl>::readMicroPC(unsigned tid) 1371{ 1372 return commit.readMicroPC(tid); 1373} 1374 1375template <class Impl> 1376void 1377FullO3CPU<Impl>::setMicroPC(Addr new_PC,unsigned tid) 1378{ 1379 commit.setMicroPC(new_PC, tid); 1380} 1381 1382template <class Impl> 1383uint64_t 1384FullO3CPU<Impl>::readNextPC(unsigned tid) 1385{ 1386 return commit.readNextPC(tid); 1387} 1388 1389template <class Impl> 1390void 1391FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 1392{ 1393 commit.setNextPC(val, tid); 1394} 1395 1396template <class Impl> 1397uint64_t 1398FullO3CPU<Impl>::readNextNPC(unsigned tid) 1399{ 1400 return commit.readNextNPC(tid); 1401} 1402 1403template <class Impl> 1404void 1405FullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid) 1406{ 1407 commit.setNextNPC(val, tid); 1408} 1409 1410template <class Impl> 1411uint64_t 1412FullO3CPU<Impl>::readNextMicroPC(unsigned tid) 1413{ 1414 return commit.readNextMicroPC(tid); 1415} 1416 1417template <class Impl> 1418void 1419FullO3CPU<Impl>::setNextMicroPC(Addr new_PC,unsigned tid) 1420{ 1421 commit.setNextMicroPC(new_PC, tid); 1422} 1423 1424template <class Impl> 1425void 1426FullO3CPU<Impl>::squashFromTC(unsigned tid) 1427{ 1428 this->thread[tid]->inSyscall = true; 1429 this->commit.generateTCEvent(tid); 1430} 1431 1432template <class Impl> 1433typename FullO3CPU<Impl>::ListIt 1434FullO3CPU<Impl>::addInst(DynInstPtr &inst) 1435{ 1436 instList.push_back(inst); 1437 1438 return --(instList.end()); 1439} 1440 1441template <class Impl> 1442void 1443FullO3CPU<Impl>::instDone(unsigned tid) 1444{ 1445 // Keep an instruction count. 1446 thread[tid]->numInst++; 1447 thread[tid]->numInsts++; 1448 committedInsts[tid]++; 1449 totalCommittedInsts++; 1450 1451 // Check for instruction-count-based events. 1452 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 1453} 1454 1455template <class Impl> 1456void 1457FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 1458{ 1459 removeInstsThisCycle = true; 1460 1461 removeList.push(inst->getInstListIt()); 1462} 1463 1464template <class Impl> 1465void 1466FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 1467{ 1468 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 1469 "[sn:%lli]\n", 1470 inst->threadNumber, inst->readPC(), inst->seqNum); 1471 1472 removeInstsThisCycle = true; 1473 1474 // Remove the front instruction. 1475 removeList.push(inst->getInstListIt()); 1476} 1477 1478template <class Impl> 1479void 1480FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 1481{ 1482 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 1483 " list.\n", tid); 1484 1485 ListIt end_it; 1486 1487 bool rob_empty = false; 1488 1489 if (instList.empty()) { 1490 return; 1491 } else if (rob.isEmpty(/*tid*/)) { 1492 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 1493 end_it = instList.begin(); 1494 rob_empty = true; 1495 } else { 1496 end_it = (rob.readTailInst(tid))->getInstListIt(); 1497 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 1498 } 1499 1500 removeInstsThisCycle = true; 1501 1502 ListIt inst_it = instList.end(); 1503 1504 inst_it--; 1505 1506 // Walk through the instruction list, removing any instructions 1507 // that were inserted after the given instruction iterator, end_it. 1508 while (inst_it != end_it) { 1509 assert(!instList.empty()); 1510 1511 squashInstIt(inst_it, tid); 1512 1513 inst_it--; 1514 } 1515 1516 // If the ROB was empty, then we actually need to remove the first 1517 // instruction as well. 1518 if (rob_empty) { 1519 squashInstIt(inst_it, tid); 1520 } 1521} 1522 1523template <class Impl> 1524void 1525FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 1526 unsigned tid) 1527{ 1528 assert(!instList.empty()); 1529 1530 removeInstsThisCycle = true; 1531 1532 ListIt inst_iter = instList.end(); 1533 1534 inst_iter--; 1535 1536 DPRINTF(O3CPU, "Deleting instructions from instruction " 1537 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 1538 tid, seq_num, (*inst_iter)->seqNum); 1539 1540 while ((*inst_iter)->seqNum > seq_num) { 1541 1542 bool break_loop = (inst_iter == instList.begin()); 1543 1544 squashInstIt(inst_iter, tid); 1545 1546 inst_iter--; 1547 1548 if (break_loop) 1549 break; 1550 } 1551} 1552 1553template <class Impl> 1554inline void 1555FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 1556{ 1557 if ((*instIt)->threadNumber == tid) { 1558 DPRINTF(O3CPU, "Squashing instruction, " 1559 "[tid:%i] [sn:%lli] PC %#x\n", 1560 (*instIt)->threadNumber, 1561 (*instIt)->seqNum, 1562 (*instIt)->readPC()); 1563 1564 // Mark it as squashed. 1565 (*instIt)->setSquashed(); 1566 1567 // @todo: Formulate a consistent method for deleting 1568 // instructions from the instruction list 1569 // Remove the instruction from the list. 1570 removeList.push(instIt); 1571 } 1572} 1573 1574template <class Impl> 1575void 1576FullO3CPU<Impl>::cleanUpRemovedInsts() 1577{ 1578 while (!removeList.empty()) { 1579 DPRINTF(O3CPU, "Removing instruction, " 1580 "[tid:%i] [sn:%lli] PC %#x\n", 1581 (*removeList.front())->threadNumber, 1582 (*removeList.front())->seqNum, 1583 (*removeList.front())->readPC()); 1584 1585 instList.erase(removeList.front()); 1586 1587 removeList.pop(); 1588 } 1589 1590 removeInstsThisCycle = false; 1591} 1592/* 1593template <class Impl> 1594void 1595FullO3CPU<Impl>::removeAllInsts() 1596{ 1597 instList.clear(); 1598} 1599*/ 1600template <class Impl> 1601void 1602FullO3CPU<Impl>::dumpInsts() 1603{ 1604 int num = 0; 1605 1606 ListIt inst_list_it = instList.begin(); 1607 1608 cprintf("Dumping Instruction List\n"); 1609 1610 while (inst_list_it != instList.end()) { 1611 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 1612 "Squashed:%i\n\n", 1613 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 1614 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 1615 (*inst_list_it)->isSquashed()); 1616 inst_list_it++; 1617 ++num; 1618 } 1619} 1620/* 1621template <class Impl> 1622void 1623FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 1624{ 1625 iew.wakeDependents(inst); 1626} 1627*/ 1628template <class Impl> 1629void 1630FullO3CPU<Impl>::wakeCPU() 1631{ 1632 if (activityRec.active() || tickEvent.scheduled()) { 1633 DPRINTF(Activity, "CPU already running.\n"); 1634 return; 1635 } 1636 1637 DPRINTF(Activity, "Waking up CPU\n"); 1638 1639 idleCycles += tickToCycles((curTick - 1) - lastRunningCycle); 1640 numCycles += tickToCycles((curTick - 1) - lastRunningCycle); 1641 1642 schedule(tickEvent, nextCycle()); 1643} 1644 1645#if FULL_SYSTEM 1646template <class Impl> 1647void 1648FullO3CPU<Impl>::wakeup() 1649{ 1650 if (this->thread[0]->status() != ThreadContext::Suspended) 1651 return; 1652 1653 this->wakeCPU(); 1654 1655 DPRINTF(Quiesce, "Suspended Processor woken\n"); 1656 this->threadContexts[0]->activate(); 1657} 1658#endif 1659 1660template <class Impl> 1661int 1662FullO3CPU<Impl>::getFreeTid() 1663{ 1664 for (int i=0; i < numThreads; i++) { 1665 if (!tids[i]) { 1666 tids[i] = true; 1667 return i; 1668 } 1669 } 1670 1671 return -1; 1672} 1673 1674template <class Impl> 1675void 1676FullO3CPU<Impl>::doContextSwitch() 1677{ 1678 if (contextSwitch) { 1679 1680 //ADD CODE TO DEACTIVE THREAD HERE (???) 1681 1682 for (int tid=0; tid < cpuWaitList.size(); tid++) { 1683 activateWhenReady(tid); 1684 } 1685 1686 if (cpuWaitList.size() == 0) 1687 contextSwitch = true; 1688 } 1689} 1690 1691template <class Impl> 1692void 1693FullO3CPU<Impl>::updateThreadPriority() 1694{ 1695 if (activeThreads.size() > 1) 1696 { 1697 //DEFAULT TO ROUND ROBIN SCHEME 1698 //e.g. Move highest priority to end of thread list 1699 std::list<unsigned>::iterator list_begin = activeThreads.begin(); 1700 std::list<unsigned>::iterator list_end = activeThreads.end(); 1701 1702 unsigned high_thread = *list_begin; 1703 1704 activeThreads.erase(list_begin); 1705 1706 activeThreads.push_back(high_thread); 1707 } 1708} 1709 1710// Forward declaration of FullO3CPU. 1711template class FullO3CPU<O3CPUImpl>; 1712