cpu.cc revision 4192:7accc6365bb9 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#if FULL_SYSTEM
36#include "cpu/quiesce_event.hh"
37#include "sim/system.hh"
38#else
39#include "sim/process.hh"
40#endif
41
42#include "cpu/activity.hh"
43#include "cpu/simple_thread.hh"
44#include "cpu/thread_context.hh"
45#include "cpu/o3/isa_specific.hh"
46#include "cpu/o3/cpu.hh"
47
48#include "sim/core.hh"
49#include "sim/stat_control.hh"
50
51#if USE_CHECKER
52#include "cpu/checker/cpu.hh"
53#endif
54
55using namespace std;
56using namespace TheISA;
57
58BaseO3CPU::BaseO3CPU(Params *params)
59    : BaseCPU(params), cpu_id(0)
60{
61}
62
63void
64BaseO3CPU::regStats()
65{
66    BaseCPU::regStats();
67}
68
69template <class Impl>
70FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c)
71    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
72{
73}
74
75template <class Impl>
76void
77FullO3CPU<Impl>::TickEvent::process()
78{
79    cpu->tick();
80}
81
82template <class Impl>
83const char *
84FullO3CPU<Impl>::TickEvent::description()
85{
86    return "FullO3CPU tick event";
87}
88
89template <class Impl>
90FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent()
91    : Event(&mainEventQueue, CPU_Switch_Pri)
92{
93}
94
95template <class Impl>
96void
97FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num,
98                                           FullO3CPU<Impl> *thread_cpu)
99{
100    tid = thread_num;
101    cpu = thread_cpu;
102}
103
104template <class Impl>
105void
106FullO3CPU<Impl>::ActivateThreadEvent::process()
107{
108    cpu->activateThread(tid);
109}
110
111template <class Impl>
112const char *
113FullO3CPU<Impl>::ActivateThreadEvent::description()
114{
115    return "FullO3CPU \"Activate Thread\" event";
116}
117
118template <class Impl>
119FullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent()
120    : Event(&mainEventQueue, CPU_Tick_Pri), tid(0), remove(false), cpu(NULL)
121{
122}
123
124template <class Impl>
125void
126FullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num,
127                                              FullO3CPU<Impl> *thread_cpu)
128{
129    tid = thread_num;
130    cpu = thread_cpu;
131    remove = false;
132}
133
134template <class Impl>
135void
136FullO3CPU<Impl>::DeallocateContextEvent::process()
137{
138    cpu->deactivateThread(tid);
139    if (remove)
140        cpu->removeThread(tid);
141}
142
143template <class Impl>
144const char *
145FullO3CPU<Impl>::DeallocateContextEvent::description()
146{
147    return "FullO3CPU \"Deallocate Context\" event";
148}
149
150template <class Impl>
151FullO3CPU<Impl>::FullO3CPU(Params *params)
152    : BaseO3CPU(params),
153#if FULL_SYSTEM
154      itb(params->itb),
155      dtb(params->dtb),
156#endif
157      tickEvent(this),
158      removeInstsThisCycle(false),
159      fetch(params),
160      decode(params),
161      rename(params),
162      iew(params),
163      commit(params),
164
165      regFile(params->numPhysIntRegs, params->numPhysFloatRegs),
166
167      freeList(params->numberOfThreads,
168               TheISA::NumIntRegs, params->numPhysIntRegs,
169               TheISA::NumFloatRegs, params->numPhysFloatRegs),
170
171      rob(params->numROBEntries, params->squashWidth,
172          params->smtROBPolicy, params->smtROBThreshold,
173          params->numberOfThreads),
174
175      scoreboard(params->numberOfThreads,
176                 TheISA::NumIntRegs, params->numPhysIntRegs,
177                 TheISA::NumFloatRegs, params->numPhysFloatRegs,
178                 TheISA::NumMiscRegs * number_of_threads,
179                 TheISA::ZeroReg),
180
181      timeBuffer(params->backComSize, params->forwardComSize),
182      fetchQueue(params->backComSize, params->forwardComSize),
183      decodeQueue(params->backComSize, params->forwardComSize),
184      renameQueue(params->backComSize, params->forwardComSize),
185      iewQueue(params->backComSize, params->forwardComSize),
186      activityRec(NumStages,
187                  params->backComSize + params->forwardComSize,
188                  params->activity),
189
190      globalSeqNum(1),
191#if FULL_SYSTEM
192      system(params->system),
193      physmem(system->physmem),
194#endif // FULL_SYSTEM
195      drainCount(0),
196      deferRegistration(params->deferRegistration),
197      numThreads(number_of_threads)
198{
199    if (!deferRegistration) {
200        _status = Running;
201    } else {
202        _status = Idle;
203    }
204
205    checker = NULL;
206
207    if (params->checker) {
208#if USE_CHECKER
209        BaseCPU *temp_checker = params->checker;
210        checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
211#if FULL_SYSTEM
212        checker->setSystem(params->system);
213#endif
214#else
215        panic("Checker enabled but not compiled in!");
216#endif // USE_CHECKER
217    }
218
219#if !FULL_SYSTEM
220    thread.resize(number_of_threads);
221    tids.resize(number_of_threads);
222#endif
223
224    // The stages also need their CPU pointer setup.  However this
225    // must be done at the upper level CPU because they have pointers
226    // to the upper level CPU, and not this FullO3CPU.
227
228    // Set up Pointers to the activeThreads list for each stage
229    fetch.setActiveThreads(&activeThreads);
230    decode.setActiveThreads(&activeThreads);
231    rename.setActiveThreads(&activeThreads);
232    iew.setActiveThreads(&activeThreads);
233    commit.setActiveThreads(&activeThreads);
234
235    // Give each of the stages the time buffer they will use.
236    fetch.setTimeBuffer(&timeBuffer);
237    decode.setTimeBuffer(&timeBuffer);
238    rename.setTimeBuffer(&timeBuffer);
239    iew.setTimeBuffer(&timeBuffer);
240    commit.setTimeBuffer(&timeBuffer);
241
242    // Also setup each of the stages' queues.
243    fetch.setFetchQueue(&fetchQueue);
244    decode.setFetchQueue(&fetchQueue);
245    commit.setFetchQueue(&fetchQueue);
246    decode.setDecodeQueue(&decodeQueue);
247    rename.setDecodeQueue(&decodeQueue);
248    rename.setRenameQueue(&renameQueue);
249    iew.setRenameQueue(&renameQueue);
250    iew.setIEWQueue(&iewQueue);
251    commit.setIEWQueue(&iewQueue);
252    commit.setRenameQueue(&renameQueue);
253
254    commit.setIEWStage(&iew);
255    rename.setIEWStage(&iew);
256    rename.setCommitStage(&commit);
257
258#if !FULL_SYSTEM
259    int active_threads = params->workload.size();
260
261    if (active_threads > Impl::MaxThreads) {
262        panic("Workload Size too large. Increase the 'MaxThreads'"
263              "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
264              "edit your workload size.");
265    }
266#else
267    int active_threads = 1;
268#endif
269
270    //Make Sure That this a Valid Architeture
271    assert(params->numPhysIntRegs   >= numThreads * TheISA::NumIntRegs);
272    assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
273
274    rename.setScoreboard(&scoreboard);
275    iew.setScoreboard(&scoreboard);
276
277    // Setup the rename map for whichever stages need it.
278    PhysRegIndex lreg_idx = 0;
279    PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
280
281    for (int tid=0; tid < numThreads; tid++) {
282        bool bindRegs = (tid <= active_threads - 1);
283
284        commitRenameMap[tid].init(TheISA::NumIntRegs,
285                                  params->numPhysIntRegs,
286                                  lreg_idx,            //Index for Logical. Regs
287
288                                  TheISA::NumFloatRegs,
289                                  params->numPhysFloatRegs,
290                                  freg_idx,            //Index for Float Regs
291
292                                  TheISA::NumMiscRegs,
293
294                                  TheISA::ZeroReg,
295                                  TheISA::ZeroReg,
296
297                                  tid,
298                                  false);
299
300        renameMap[tid].init(TheISA::NumIntRegs,
301                            params->numPhysIntRegs,
302                            lreg_idx,                  //Index for Logical. Regs
303
304                            TheISA::NumFloatRegs,
305                            params->numPhysFloatRegs,
306                            freg_idx,                  //Index for Float Regs
307
308                            TheISA::NumMiscRegs,
309
310                            TheISA::ZeroReg,
311                            TheISA::ZeroReg,
312
313                            tid,
314                            bindRegs);
315
316        activateThreadEvent[tid].init(tid, this);
317        deallocateContextEvent[tid].init(tid, this);
318    }
319
320    rename.setRenameMap(renameMap);
321    commit.setRenameMap(commitRenameMap);
322
323    // Give renameMap & rename stage access to the freeList;
324    for (int i=0; i < numThreads; i++) {
325        renameMap[i].setFreeList(&freeList);
326    }
327    rename.setFreeList(&freeList);
328
329    // Setup the ROB for whichever stages need it.
330    commit.setROB(&rob);
331
332    lastRunningCycle = curTick;
333
334    lastActivatedCycle = -1;
335
336    // Give renameMap & rename stage access to the freeList;
337    //for (int i=0; i < numThreads; i++) {
338        //globalSeqNum[i] = 1;
339        //}
340
341    contextSwitch = false;
342}
343
344template <class Impl>
345FullO3CPU<Impl>::~FullO3CPU()
346{
347}
348
349template <class Impl>
350void
351FullO3CPU<Impl>::fullCPURegStats()
352{
353    BaseO3CPU::regStats();
354
355    // Register any of the O3CPU's stats here.
356    timesIdled
357        .name(name() + ".timesIdled")
358        .desc("Number of times that the entire CPU went into an idle state and"
359              " unscheduled itself")
360        .prereq(timesIdled);
361
362    idleCycles
363        .name(name() + ".idleCycles")
364        .desc("Total number of cycles that the CPU has spent unscheduled due "
365              "to idling")
366        .prereq(idleCycles);
367
368    // Number of Instructions simulated
369    // --------------------------------
370    // Should probably be in Base CPU but need templated
371    // MaxThreads so put in here instead
372    committedInsts
373        .init(numThreads)
374        .name(name() + ".committedInsts")
375        .desc("Number of Instructions Simulated");
376
377    totalCommittedInsts
378        .name(name() + ".committedInsts_total")
379        .desc("Number of Instructions Simulated");
380
381    cpi
382        .name(name() + ".cpi")
383        .desc("CPI: Cycles Per Instruction")
384        .precision(6);
385    cpi = simTicks / committedInsts;
386
387    totalCpi
388        .name(name() + ".cpi_total")
389        .desc("CPI: Total CPI of All Threads")
390        .precision(6);
391    totalCpi = simTicks / totalCommittedInsts;
392
393    ipc
394        .name(name() + ".ipc")
395        .desc("IPC: Instructions Per Cycle")
396        .precision(6);
397    ipc =  committedInsts / simTicks;
398
399    totalIpc
400        .name(name() + ".ipc_total")
401        .desc("IPC: Total IPC of All Threads")
402        .precision(6);
403    totalIpc =  totalCommittedInsts / simTicks;
404
405}
406
407template <class Impl>
408Port *
409FullO3CPU<Impl>::getPort(const std::string &if_name, int idx)
410{
411    if (if_name == "dcache_port")
412        return iew.getDcachePort();
413    else if (if_name == "icache_port")
414        return fetch.getIcachePort();
415    else
416        panic("No Such Port\n");
417}
418
419template <class Impl>
420void
421FullO3CPU<Impl>::tick()
422{
423    DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
424
425    ++numCycles;
426
427//    activity = false;
428
429    //Tick each of the stages
430    fetch.tick();
431
432    decode.tick();
433
434    rename.tick();
435
436    iew.tick();
437
438    commit.tick();
439
440#if !FULL_SYSTEM
441    doContextSwitch();
442#endif
443
444    // Now advance the time buffers
445    timeBuffer.advance();
446
447    fetchQueue.advance();
448    decodeQueue.advance();
449    renameQueue.advance();
450    iewQueue.advance();
451
452    activityRec.advance();
453
454    if (removeInstsThisCycle) {
455        cleanUpRemovedInsts();
456    }
457
458    if (!tickEvent.scheduled()) {
459        if (_status == SwitchedOut ||
460            getState() == SimObject::Drained) {
461            DPRINTF(O3CPU, "Switched out!\n");
462            // increment stat
463            lastRunningCycle = curTick;
464        } else if (!activityRec.active() || _status == Idle) {
465            DPRINTF(O3CPU, "Idle!\n");
466            lastRunningCycle = curTick;
467            timesIdled++;
468        } else {
469            tickEvent.schedule(curTick + cycles(1));
470            DPRINTF(O3CPU, "Scheduling next tick!\n");
471        }
472    }
473
474#if !FULL_SYSTEM
475    updateThreadPriority();
476#endif
477
478}
479
480template <class Impl>
481void
482FullO3CPU<Impl>::init()
483{
484    if (!deferRegistration) {
485        registerThreadContexts();
486    }
487
488    // Set inSyscall so that the CPU doesn't squash when initially
489    // setting up registers.
490    for (int i = 0; i < number_of_threads; ++i)
491        thread[i]->inSyscall = true;
492
493    for (int tid=0; tid < number_of_threads; tid++) {
494#if FULL_SYSTEM
495        ThreadContext *src_tc = threadContexts[tid];
496#else
497        ThreadContext *src_tc = thread[tid]->getTC();
498#endif
499        // Threads start in the Suspended State
500        if (src_tc->status() != ThreadContext::Suspended) {
501            continue;
502        }
503
504#if FULL_SYSTEM
505        TheISA::initCPU(src_tc, src_tc->readCpuId());
506#endif
507    }
508
509    // Clear inSyscall.
510    for (int i = 0; i < number_of_threads; ++i)
511        thread[i]->inSyscall = false;
512
513    // Initialize stages.
514    fetch.initStage();
515    iew.initStage();
516    rename.initStage();
517    commit.initStage();
518
519    commit.setThreads(thread);
520}
521
522template <class Impl>
523void
524FullO3CPU<Impl>::activateThread(unsigned tid)
525{
526    list<unsigned>::iterator isActive = find(
527        activeThreads.begin(), activeThreads.end(), tid);
528
529    DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
530
531    if (isActive == activeThreads.end()) {
532        DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
533                tid);
534
535        activeThreads.push_back(tid);
536    }
537}
538
539template <class Impl>
540void
541FullO3CPU<Impl>::deactivateThread(unsigned tid)
542{
543    //Remove From Active List, if Active
544    list<unsigned>::iterator thread_it =
545        find(activeThreads.begin(), activeThreads.end(), tid);
546
547    DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
548
549    if (thread_it != activeThreads.end()) {
550        DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
551                tid);
552        activeThreads.erase(thread_it);
553    }
554}
555
556template <class Impl>
557void
558FullO3CPU<Impl>::activateContext(int tid, int delay)
559{
560    // Needs to set each stage to running as well.
561    if (delay){
562        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
563                "on cycle %d\n", tid, curTick + cycles(delay));
564        scheduleActivateThreadEvent(tid, delay);
565    } else {
566        activateThread(tid);
567    }
568
569    if (lastActivatedCycle < curTick) {
570        scheduleTickEvent(delay);
571
572        // Be sure to signal that there's some activity so the CPU doesn't
573        // deschedule itself.
574        activityRec.activity();
575        fetch.wakeFromQuiesce();
576
577        lastActivatedCycle = curTick;
578
579        _status = Running;
580    }
581}
582
583template <class Impl>
584bool
585FullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay)
586{
587    // Schedule removal of thread data from CPU
588    if (delay){
589        DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
590                "on cycle %d\n", tid, curTick + cycles(delay));
591        scheduleDeallocateContextEvent(tid, remove, delay);
592        return false;
593    } else {
594        deactivateThread(tid);
595        if (remove)
596            removeThread(tid);
597        return true;
598    }
599}
600
601template <class Impl>
602void
603FullO3CPU<Impl>::suspendContext(int tid)
604{
605    DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
606    bool deallocated = deallocateContext(tid, false, 1);
607    // If this was the last thread then unschedule the tick event.
608    if (activeThreads.size() == 1 && !deallocated ||
609        activeThreads.size() == 0)
610        unscheduleTickEvent();
611    _status = Idle;
612}
613
614template <class Impl>
615void
616FullO3CPU<Impl>::haltContext(int tid)
617{
618    //For now, this is the same as deallocate
619    DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
620    deallocateContext(tid, true, 1);
621}
622
623template <class Impl>
624void
625FullO3CPU<Impl>::insertThread(unsigned tid)
626{
627    DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
628    // Will change now that the PC and thread state is internal to the CPU
629    // and not in the ThreadContext.
630#if FULL_SYSTEM
631    ThreadContext *src_tc = system->threadContexts[tid];
632#else
633    ThreadContext *src_tc = tcBase(tid);
634#endif
635
636    //Bind Int Regs to Rename Map
637    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
638        PhysRegIndex phys_reg = freeList.getIntReg();
639
640        renameMap[tid].setEntry(ireg,phys_reg);
641        scoreboard.setReg(phys_reg);
642    }
643
644    //Bind Float Regs to Rename Map
645    for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
646        PhysRegIndex phys_reg = freeList.getFloatReg();
647
648        renameMap[tid].setEntry(freg,phys_reg);
649        scoreboard.setReg(phys_reg);
650    }
651
652    //Copy Thread Data Into RegFile
653    //this->copyFromTC(tid);
654
655    //Set PC/NPC/NNPC
656    setPC(src_tc->readPC(), tid);
657    setNextPC(src_tc->readNextPC(), tid);
658    setNextNPC(src_tc->readNextNPC(), tid);
659
660    src_tc->setStatus(ThreadContext::Active);
661
662    activateContext(tid,1);
663
664    //Reset ROB/IQ/LSQ Entries
665    commit.rob->resetEntries();
666    iew.resetEntries();
667}
668
669template <class Impl>
670void
671FullO3CPU<Impl>::removeThread(unsigned tid)
672{
673    DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
674
675    // Copy Thread Data From RegFile
676    // If thread is suspended, it might be re-allocated
677    //this->copyToTC(tid);
678
679    // Unbind Int Regs from Rename Map
680    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
681        PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
682
683        scoreboard.unsetReg(phys_reg);
684        freeList.addReg(phys_reg);
685    }
686
687    // Unbind Float Regs from Rename Map
688    for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
689        PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
690
691        scoreboard.unsetReg(phys_reg);
692        freeList.addReg(phys_reg);
693    }
694
695    // Squash Throughout Pipeline
696    InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
697    fetch.squash(0, sizeof(TheISA::MachInst), squash_seq_num, true, tid);
698    decode.squash(tid);
699    rename.squash(squash_seq_num, tid);
700    iew.squash(tid);
701    commit.rob->squash(squash_seq_num, tid);
702
703    assert(iew.ldstQueue.getCount(tid) == 0);
704
705    // Reset ROB/IQ/LSQ Entries
706
707    // Commented out for now.  This should be possible to do by
708    // telling all the pipeline stages to drain first, and then
709    // checking until the drain completes.  Once the pipeline is
710    // drained, call resetEntries(). - 10-09-06 ktlim
711/*
712    if (activeThreads.size() >= 1) {
713        commit.rob->resetEntries();
714        iew.resetEntries();
715    }
716*/
717}
718
719
720template <class Impl>
721void
722FullO3CPU<Impl>::activateWhenReady(int tid)
723{
724    DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
725            "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
726            tid);
727
728    bool ready = true;
729
730    if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
731        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
732                "Phys. Int. Regs.\n",
733                tid);
734        ready = false;
735    } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
736        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
737                "Phys. Float. Regs.\n",
738                tid);
739        ready = false;
740    } else if (commit.rob->numFreeEntries() >=
741               commit.rob->entryAmount(activeThreads.size() + 1)) {
742        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
743                "ROB entries.\n",
744                tid);
745        ready = false;
746    } else if (iew.instQueue.numFreeEntries() >=
747               iew.instQueue.entryAmount(activeThreads.size() + 1)) {
748        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
749                "IQ entries.\n",
750                tid);
751        ready = false;
752    } else if (iew.ldstQueue.numFreeEntries() >=
753               iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
754        DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough "
755                "LSQ entries.\n",
756                tid);
757        ready = false;
758    }
759
760    if (ready) {
761        insertThread(tid);
762
763        contextSwitch = false;
764
765        cpuWaitList.remove(tid);
766    } else {
767        suspendContext(tid);
768
769        //blocks fetch
770        contextSwitch = true;
771
772        //@todo: dont always add to waitlist
773        //do waitlist
774        cpuWaitList.push_back(tid);
775    }
776}
777
778#if FULL_SYSTEM
779template <class Impl>
780void
781FullO3CPU<Impl>::updateMemPorts()
782{
783    // Update all ThreadContext's memory ports (Functional/Virtual
784    // Ports)
785    for (int i = 0; i < thread.size(); ++i)
786        thread[i]->connectMemPorts();
787}
788#endif
789
790template <class Impl>
791void
792FullO3CPU<Impl>::serialize(std::ostream &os)
793{
794    SimObject::State so_state = SimObject::getState();
795    SERIALIZE_ENUM(so_state);
796    BaseCPU::serialize(os);
797    nameOut(os, csprintf("%s.tickEvent", name()));
798    tickEvent.serialize(os);
799
800    // Use SimpleThread's ability to checkpoint to make it easier to
801    // write out the registers.  Also make this static so it doesn't
802    // get instantiated multiple times (causes a panic in statistics).
803    static SimpleThread temp;
804
805    for (int i = 0; i < thread.size(); i++) {
806        nameOut(os, csprintf("%s.xc.%i", name(), i));
807        temp.copyTC(thread[i]->getTC());
808        temp.serialize(os);
809    }
810}
811
812template <class Impl>
813void
814FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
815{
816    SimObject::State so_state;
817    UNSERIALIZE_ENUM(so_state);
818    BaseCPU::unserialize(cp, section);
819    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
820
821    // Use SimpleThread's ability to checkpoint to make it easier to
822    // read in the registers.  Also make this static so it doesn't
823    // get instantiated multiple times (causes a panic in statistics).
824    static SimpleThread temp;
825
826    for (int i = 0; i < thread.size(); i++) {
827        temp.copyTC(thread[i]->getTC());
828        temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
829        thread[i]->getTC()->copyArchRegs(temp.getTC());
830    }
831}
832
833template <class Impl>
834unsigned int
835FullO3CPU<Impl>::drain(Event *drain_event)
836{
837    DPRINTF(O3CPU, "Switching out\n");
838
839    // If the CPU isn't doing anything, then return immediately.
840    if (_status == Idle || _status == SwitchedOut) {
841        return 0;
842    }
843
844    drainCount = 0;
845    fetch.drain();
846    decode.drain();
847    rename.drain();
848    iew.drain();
849    commit.drain();
850
851    // Wake the CPU and record activity so everything can drain out if
852    // the CPU was not able to immediately drain.
853    if (getState() != SimObject::Drained) {
854        // A bit of a hack...set the drainEvent after all the drain()
855        // calls have been made, that way if all of the stages drain
856        // immediately, the signalDrained() function knows not to call
857        // process on the drain event.
858        drainEvent = drain_event;
859
860        wakeCPU();
861        activityRec.activity();
862
863        return 1;
864    } else {
865        return 0;
866    }
867}
868
869template <class Impl>
870void
871FullO3CPU<Impl>::resume()
872{
873    fetch.resume();
874    decode.resume();
875    rename.resume();
876    iew.resume();
877    commit.resume();
878
879    changeState(SimObject::Running);
880
881    if (_status == SwitchedOut || _status == Idle)
882        return;
883
884#if FULL_SYSTEM
885    assert(system->getMemoryMode() == System::Timing);
886#endif
887
888    if (!tickEvent.scheduled())
889        tickEvent.schedule(curTick);
890    _status = Running;
891}
892
893template <class Impl>
894void
895FullO3CPU<Impl>::signalDrained()
896{
897    if (++drainCount == NumStages) {
898        if (tickEvent.scheduled())
899            tickEvent.squash();
900
901        changeState(SimObject::Drained);
902
903        BaseCPU::switchOut();
904
905        if (drainEvent) {
906            drainEvent->process();
907            drainEvent = NULL;
908        }
909    }
910    assert(drainCount <= 5);
911}
912
913template <class Impl>
914void
915FullO3CPU<Impl>::switchOut()
916{
917    fetch.switchOut();
918    rename.switchOut();
919    iew.switchOut();
920    commit.switchOut();
921    instList.clear();
922    while (!removeList.empty()) {
923        removeList.pop();
924    }
925
926    _status = SwitchedOut;
927#if USE_CHECKER
928    if (checker)
929        checker->switchOut();
930#endif
931    if (tickEvent.scheduled())
932        tickEvent.squash();
933}
934
935template <class Impl>
936void
937FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
938{
939    // Flush out any old data from the time buffers.
940    for (int i = 0; i < timeBuffer.getSize(); ++i) {
941        timeBuffer.advance();
942        fetchQueue.advance();
943        decodeQueue.advance();
944        renameQueue.advance();
945        iewQueue.advance();
946    }
947
948    activityRec.reset();
949
950    BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort());
951
952    fetch.takeOverFrom();
953    decode.takeOverFrom();
954    rename.takeOverFrom();
955    iew.takeOverFrom();
956    commit.takeOverFrom();
957
958    assert(!tickEvent.scheduled());
959
960    // @todo: Figure out how to properly select the tid to put onto
961    // the active threads list.
962    int tid = 0;
963
964    list<unsigned>::iterator isActive = find(
965        activeThreads.begin(), activeThreads.end(), tid);
966
967    if (isActive == activeThreads.end()) {
968        //May Need to Re-code this if the delay variable is the delay
969        //needed for thread to activate
970        DPRINTF(O3CPU, "Adding Thread %i to active threads list\n",
971                tid);
972
973        activeThreads.push_back(tid);
974    }
975
976    // Set all statuses to active, schedule the CPU's tick event.
977    // @todo: Fix up statuses so this is handled properly
978    for (int i = 0; i < threadContexts.size(); ++i) {
979        ThreadContext *tc = threadContexts[i];
980        if (tc->status() == ThreadContext::Active && _status != Running) {
981            _status = Running;
982            tickEvent.schedule(curTick);
983        }
984    }
985    if (!tickEvent.scheduled())
986        tickEvent.schedule(curTick);
987}
988
989template <class Impl>
990uint64_t
991FullO3CPU<Impl>::readIntReg(int reg_idx)
992{
993    return regFile.readIntReg(reg_idx);
994}
995
996template <class Impl>
997FloatReg
998FullO3CPU<Impl>::readFloatReg(int reg_idx, int width)
999{
1000    return regFile.readFloatReg(reg_idx, width);
1001}
1002
1003template <class Impl>
1004FloatReg
1005FullO3CPU<Impl>::readFloatReg(int reg_idx)
1006{
1007    return regFile.readFloatReg(reg_idx);
1008}
1009
1010template <class Impl>
1011FloatRegBits
1012FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
1013{
1014    return regFile.readFloatRegBits(reg_idx, width);
1015}
1016
1017template <class Impl>
1018FloatRegBits
1019FullO3CPU<Impl>::readFloatRegBits(int reg_idx)
1020{
1021    return regFile.readFloatRegBits(reg_idx);
1022}
1023
1024template <class Impl>
1025void
1026FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val)
1027{
1028    regFile.setIntReg(reg_idx, val);
1029}
1030
1031template <class Impl>
1032void
1033FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
1034{
1035    regFile.setFloatReg(reg_idx, val, width);
1036}
1037
1038template <class Impl>
1039void
1040FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val)
1041{
1042    regFile.setFloatReg(reg_idx, val);
1043}
1044
1045template <class Impl>
1046void
1047FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width)
1048{
1049    regFile.setFloatRegBits(reg_idx, val, width);
1050}
1051
1052template <class Impl>
1053void
1054FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
1055{
1056    regFile.setFloatRegBits(reg_idx, val);
1057}
1058
1059template <class Impl>
1060uint64_t
1061FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid)
1062{
1063    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1064
1065    return regFile.readIntReg(phys_reg);
1066}
1067
1068template <class Impl>
1069float
1070FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid)
1071{
1072    int idx = reg_idx + TheISA::FP_Base_DepTag;
1073    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1074
1075    return regFile.readFloatReg(phys_reg);
1076}
1077
1078template <class Impl>
1079double
1080FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid)
1081{
1082    int idx = reg_idx + TheISA::FP_Base_DepTag;
1083    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1084
1085    return regFile.readFloatReg(phys_reg, 64);
1086}
1087
1088template <class Impl>
1089uint64_t
1090FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid)
1091{
1092    int idx = reg_idx + TheISA::FP_Base_DepTag;
1093    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1094
1095    return regFile.readFloatRegBits(phys_reg);
1096}
1097
1098template <class Impl>
1099void
1100FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid)
1101{
1102    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
1103
1104    regFile.setIntReg(phys_reg, val);
1105}
1106
1107template <class Impl>
1108void
1109FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
1110{
1111    int idx = reg_idx + TheISA::FP_Base_DepTag;
1112    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1113
1114    regFile.setFloatReg(phys_reg, val);
1115}
1116
1117template <class Impl>
1118void
1119FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
1120{
1121    int idx = reg_idx + TheISA::FP_Base_DepTag;
1122    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1123
1124    regFile.setFloatReg(phys_reg, val, 64);
1125}
1126
1127template <class Impl>
1128void
1129FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
1130{
1131    int idx = reg_idx + TheISA::FP_Base_DepTag;
1132    PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
1133
1134    regFile.setFloatRegBits(phys_reg, val);
1135}
1136
1137template <class Impl>
1138uint64_t
1139FullO3CPU<Impl>::readPC(unsigned tid)
1140{
1141    return commit.readPC(tid);
1142}
1143
1144template <class Impl>
1145void
1146FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid)
1147{
1148    commit.setPC(new_PC, tid);
1149}
1150
1151template <class Impl>
1152uint64_t
1153FullO3CPU<Impl>::readNextPC(unsigned tid)
1154{
1155    return commit.readNextPC(tid);
1156}
1157
1158template <class Impl>
1159void
1160FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid)
1161{
1162    commit.setNextPC(val, tid);
1163}
1164
1165template <class Impl>
1166uint64_t
1167FullO3CPU<Impl>::readNextNPC(unsigned tid)
1168{
1169    return commit.readNextNPC(tid);
1170}
1171
1172template <class Impl>
1173void
1174FullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid)
1175{
1176    commit.setNextNPC(val, tid);
1177}
1178
1179template <class Impl>
1180typename FullO3CPU<Impl>::ListIt
1181FullO3CPU<Impl>::addInst(DynInstPtr &inst)
1182{
1183    instList.push_back(inst);
1184
1185    return --(instList.end());
1186}
1187
1188template <class Impl>
1189void
1190FullO3CPU<Impl>::instDone(unsigned tid)
1191{
1192    // Keep an instruction count.
1193    thread[tid]->numInst++;
1194    thread[tid]->numInsts++;
1195    committedInsts[tid]++;
1196    totalCommittedInsts++;
1197
1198    // Check for instruction-count-based events.
1199    comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1200}
1201
1202template <class Impl>
1203void
1204FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst)
1205{
1206    removeInstsThisCycle = true;
1207
1208    removeList.push(inst->getInstListIt());
1209}
1210
1211template <class Impl>
1212void
1213FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
1214{
1215    DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x "
1216            "[sn:%lli]\n",
1217            inst->threadNumber, inst->readPC(), inst->seqNum);
1218
1219    removeInstsThisCycle = true;
1220
1221    // Remove the front instruction.
1222    removeList.push(inst->getInstListIt());
1223}
1224
1225template <class Impl>
1226void
1227FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid,
1228                                     bool squash_delay_slot,
1229                                     const InstSeqNum &delay_slot_seq_num)
1230{
1231    DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1232            " list.\n", tid);
1233
1234    ListIt end_it;
1235
1236    bool rob_empty = false;
1237
1238    if (instList.empty()) {
1239        return;
1240    } else if (rob.isEmpty(/*tid*/)) {
1241        DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1242        end_it = instList.begin();
1243        rob_empty = true;
1244    } else {
1245        end_it = (rob.readTailInst(tid))->getInstListIt();
1246        DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1247    }
1248
1249    removeInstsThisCycle = true;
1250
1251    ListIt inst_it = instList.end();
1252
1253    inst_it--;
1254
1255    // Walk through the instruction list, removing any instructions
1256    // that were inserted after the given instruction iterator, end_it.
1257    while (inst_it != end_it) {
1258        assert(!instList.empty());
1259
1260#if ISA_HAS_DELAY_SLOT
1261        if(!squash_delay_slot &&
1262           delay_slot_seq_num >= (*inst_it)->seqNum) {
1263            break;
1264        }
1265#endif
1266        squashInstIt(inst_it, tid);
1267
1268        inst_it--;
1269    }
1270
1271    // If the ROB was empty, then we actually need to remove the first
1272    // instruction as well.
1273    if (rob_empty) {
1274        squashInstIt(inst_it, tid);
1275    }
1276}
1277
1278template <class Impl>
1279void
1280FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num,
1281                                  unsigned tid)
1282{
1283    assert(!instList.empty());
1284
1285    removeInstsThisCycle = true;
1286
1287    ListIt inst_iter = instList.end();
1288
1289    inst_iter--;
1290
1291    DPRINTF(O3CPU, "Deleting instructions from instruction "
1292            "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1293            tid, seq_num, (*inst_iter)->seqNum);
1294
1295    while ((*inst_iter)->seqNum > seq_num) {
1296
1297        bool break_loop = (inst_iter == instList.begin());
1298
1299        squashInstIt(inst_iter, tid);
1300
1301        inst_iter--;
1302
1303        if (break_loop)
1304            break;
1305    }
1306}
1307
1308template <class Impl>
1309inline void
1310FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid)
1311{
1312    if ((*instIt)->threadNumber == tid) {
1313        DPRINTF(O3CPU, "Squashing instruction, "
1314                "[tid:%i] [sn:%lli] PC %#x\n",
1315                (*instIt)->threadNumber,
1316                (*instIt)->seqNum,
1317                (*instIt)->readPC());
1318
1319        // Mark it as squashed.
1320        (*instIt)->setSquashed();
1321
1322        // @todo: Formulate a consistent method for deleting
1323        // instructions from the instruction list
1324        // Remove the instruction from the list.
1325        removeList.push(instIt);
1326    }
1327}
1328
1329template <class Impl>
1330void
1331FullO3CPU<Impl>::cleanUpRemovedInsts()
1332{
1333    while (!removeList.empty()) {
1334        DPRINTF(O3CPU, "Removing instruction, "
1335                "[tid:%i] [sn:%lli] PC %#x\n",
1336                (*removeList.front())->threadNumber,
1337                (*removeList.front())->seqNum,
1338                (*removeList.front())->readPC());
1339
1340        instList.erase(removeList.front());
1341
1342        removeList.pop();
1343    }
1344
1345    removeInstsThisCycle = false;
1346}
1347/*
1348template <class Impl>
1349void
1350FullO3CPU<Impl>::removeAllInsts()
1351{
1352    instList.clear();
1353}
1354*/
1355template <class Impl>
1356void
1357FullO3CPU<Impl>::dumpInsts()
1358{
1359    int num = 0;
1360
1361    ListIt inst_list_it = instList.begin();
1362
1363    cprintf("Dumping Instruction List\n");
1364
1365    while (inst_list_it != instList.end()) {
1366        cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1367                "Squashed:%i\n\n",
1368                num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber,
1369                (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1370                (*inst_list_it)->isSquashed());
1371        inst_list_it++;
1372        ++num;
1373    }
1374}
1375/*
1376template <class Impl>
1377void
1378FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
1379{
1380    iew.wakeDependents(inst);
1381}
1382*/
1383template <class Impl>
1384void
1385FullO3CPU<Impl>::wakeCPU()
1386{
1387    if (activityRec.active() || tickEvent.scheduled()) {
1388        DPRINTF(Activity, "CPU already running.\n");
1389        return;
1390    }
1391
1392    DPRINTF(Activity, "Waking up CPU\n");
1393
1394    idleCycles += (curTick - 1) - lastRunningCycle;
1395
1396    tickEvent.schedule(curTick);
1397}
1398
1399template <class Impl>
1400int
1401FullO3CPU<Impl>::getFreeTid()
1402{
1403    for (int i=0; i < numThreads; i++) {
1404        if (!tids[i]) {
1405            tids[i] = true;
1406            return i;
1407        }
1408    }
1409
1410    return -1;
1411}
1412
1413template <class Impl>
1414void
1415FullO3CPU<Impl>::doContextSwitch()
1416{
1417    if (contextSwitch) {
1418
1419        //ADD CODE TO DEACTIVE THREAD HERE (???)
1420
1421        for (int tid=0; tid < cpuWaitList.size(); tid++) {
1422            activateWhenReady(tid);
1423        }
1424
1425        if (cpuWaitList.size() == 0)
1426            contextSwitch = true;
1427    }
1428}
1429
1430template <class Impl>
1431void
1432FullO3CPU<Impl>::updateThreadPriority()
1433{
1434    if (activeThreads.size() > 1)
1435    {
1436        //DEFAULT TO ROUND ROBIN SCHEME
1437        //e.g. Move highest priority to end of thread list
1438        list<unsigned>::iterator list_begin = activeThreads.begin();
1439        list<unsigned>::iterator list_end   = activeThreads.end();
1440
1441        unsigned high_thread = *list_begin;
1442
1443        activeThreads.erase(list_begin);
1444
1445        activeThreads.push_back(high_thread);
1446    }
1447}
1448
1449// Forward declaration of FullO3CPU.
1450template class FullO3CPU<O3CPUImpl>;
1451