cpu.cc revision 2831:0a42b294727c
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include "config/full_system.hh" 33#include "config/use_checker.hh" 34 35#if FULL_SYSTEM 36#include "sim/system.hh" 37#else 38#include "sim/process.hh" 39#endif 40 41#include "cpu/activity.hh" 42#include "cpu/simple_thread.hh" 43#include "cpu/thread_context.hh" 44#include "cpu/o3/isa_specific.hh" 45#include "cpu/o3/cpu.hh" 46 47#include "sim/root.hh" 48#include "sim/stat_control.hh" 49 50#if USE_CHECKER 51#include "cpu/checker/cpu.hh" 52#endif 53 54using namespace std; 55using namespace TheISA; 56 57BaseO3CPU::BaseO3CPU(Params *params) 58 : BaseCPU(params), cpu_id(0) 59{ 60} 61 62void 63BaseO3CPU::regStats() 64{ 65 BaseCPU::regStats(); 66} 67 68template <class Impl> 69FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 70 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 71{ 72} 73 74template <class Impl> 75void 76FullO3CPU<Impl>::TickEvent::process() 77{ 78 cpu->tick(); 79} 80 81template <class Impl> 82const char * 83FullO3CPU<Impl>::TickEvent::description() 84{ 85 return "FullO3CPU tick event"; 86} 87 88template <class Impl> 89FullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 90 : Event(&mainEventQueue, CPU_Tick_Pri) 91{ 92} 93 94template <class Impl> 95void 96FullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 97 FullO3CPU<Impl> *thread_cpu) 98{ 99 tid = thread_num; 100 cpu = thread_cpu; 101} 102 103template <class Impl> 104void 105FullO3CPU<Impl>::ActivateThreadEvent::process() 106{ 107 cpu->activateThread(tid); 108} 109 110template <class Impl> 111const char * 112FullO3CPU<Impl>::ActivateThreadEvent::description() 113{ 114 return "FullO3CPU \"Activate Thread\" event"; 115} 116 117template <class Impl> 118FullO3CPU<Impl>::FullO3CPU(Params *params) 119 : BaseO3CPU(params), 120 tickEvent(this), 121 removeInstsThisCycle(false), 122 fetch(params), 123 decode(params), 124 rename(params), 125 iew(params), 126 commit(params), 127 128 regFile(params->numPhysIntRegs, params->numPhysFloatRegs), 129 130 freeList(params->numberOfThreads, 131 TheISA::NumIntRegs, params->numPhysIntRegs, 132 TheISA::NumFloatRegs, params->numPhysFloatRegs), 133 134 rob(params->numROBEntries, params->squashWidth, 135 params->smtROBPolicy, params->smtROBThreshold, 136 params->numberOfThreads), 137 138 scoreboard(params->numberOfThreads, 139 TheISA::NumIntRegs, params->numPhysIntRegs, 140 TheISA::NumFloatRegs, params->numPhysFloatRegs, 141 TheISA::NumMiscRegs * number_of_threads, 142 TheISA::ZeroReg), 143 144 // For now just have these time buffers be pretty big. 145 // @todo: Make these time buffer sizes parameters or derived 146 // from latencies 147 timeBuffer(5, 5), 148 fetchQueue(5, 5), 149 decodeQueue(5, 5), 150 renameQueue(5, 5), 151 iewQueue(5, 5), 152 activityRec(NumStages, 10, params->activity), 153 154 globalSeqNum(1), 155 156#if FULL_SYSTEM 157 system(params->system), 158 physmem(system->physmem), 159#endif // FULL_SYSTEM 160 mem(params->mem), 161 switchCount(0), 162 deferRegistration(params->deferRegistration), 163 numThreads(number_of_threads) 164{ 165 _status = Idle; 166 167 checker = NULL; 168 169 if (params->checker) { 170#if USE_CHECKER 171 BaseCPU *temp_checker = params->checker; 172 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 173 checker->setMemory(mem); 174#if FULL_SYSTEM 175 checker->setSystem(params->system); 176#endif 177#else 178 panic("Checker enabled but not compiled in!"); 179#endif // USE_CHECKER 180 } 181 182#if !FULL_SYSTEM 183 thread.resize(number_of_threads); 184 tids.resize(number_of_threads); 185#endif 186 187 // The stages also need their CPU pointer setup. However this 188 // must be done at the upper level CPU because they have pointers 189 // to the upper level CPU, and not this FullO3CPU. 190 191 // Set up Pointers to the activeThreads list for each stage 192 fetch.setActiveThreads(&activeThreads); 193 decode.setActiveThreads(&activeThreads); 194 rename.setActiveThreads(&activeThreads); 195 iew.setActiveThreads(&activeThreads); 196 commit.setActiveThreads(&activeThreads); 197 198 // Give each of the stages the time buffer they will use. 199 fetch.setTimeBuffer(&timeBuffer); 200 decode.setTimeBuffer(&timeBuffer); 201 rename.setTimeBuffer(&timeBuffer); 202 iew.setTimeBuffer(&timeBuffer); 203 commit.setTimeBuffer(&timeBuffer); 204 205 // Also setup each of the stages' queues. 206 fetch.setFetchQueue(&fetchQueue); 207 decode.setFetchQueue(&fetchQueue); 208 commit.setFetchQueue(&fetchQueue); 209 decode.setDecodeQueue(&decodeQueue); 210 rename.setDecodeQueue(&decodeQueue); 211 rename.setRenameQueue(&renameQueue); 212 iew.setRenameQueue(&renameQueue); 213 iew.setIEWQueue(&iewQueue); 214 commit.setIEWQueue(&iewQueue); 215 commit.setRenameQueue(&renameQueue); 216 217 commit.setFetchStage(&fetch); 218 commit.setIEWStage(&iew); 219 rename.setIEWStage(&iew); 220 rename.setCommitStage(&commit); 221 222#if !FULL_SYSTEM 223 int active_threads = params->workload.size(); 224 225 if (active_threads > Impl::MaxThreads) { 226 panic("Workload Size too large. Increase the 'MaxThreads'" 227 "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 228 "edit your workload size."); 229 } 230#else 231 int active_threads = 1; 232#endif 233 234 //Make Sure That this a Valid Architeture 235 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 236 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 237 238 rename.setScoreboard(&scoreboard); 239 iew.setScoreboard(&scoreboard); 240 241 // Setup the rename map for whichever stages need it. 242 PhysRegIndex lreg_idx = 0; 243 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 244 245 for (int tid=0; tid < numThreads; tid++) { 246 bool bindRegs = (tid <= active_threads - 1); 247 248 commitRenameMap[tid].init(TheISA::NumIntRegs, 249 params->numPhysIntRegs, 250 lreg_idx, //Index for Logical. Regs 251 252 TheISA::NumFloatRegs, 253 params->numPhysFloatRegs, 254 freg_idx, //Index for Float Regs 255 256 TheISA::NumMiscRegs, 257 258 TheISA::ZeroReg, 259 TheISA::ZeroReg, 260 261 tid, 262 false); 263 264 renameMap[tid].init(TheISA::NumIntRegs, 265 params->numPhysIntRegs, 266 lreg_idx, //Index for Logical. Regs 267 268 TheISA::NumFloatRegs, 269 params->numPhysFloatRegs, 270 freg_idx, //Index for Float Regs 271 272 TheISA::NumMiscRegs, 273 274 TheISA::ZeroReg, 275 TheISA::ZeroReg, 276 277 tid, 278 bindRegs); 279 } 280 281 rename.setRenameMap(renameMap); 282 commit.setRenameMap(commitRenameMap); 283 284 // Give renameMap & rename stage access to the freeList; 285 for (int i=0; i < numThreads; i++) { 286 renameMap[i].setFreeList(&freeList); 287 } 288 rename.setFreeList(&freeList); 289 290 // Setup the ROB for whichever stages need it. 291 commit.setROB(&rob); 292 293 lastRunningCycle = curTick; 294 295 lastActivatedCycle = -1; 296 297 contextSwitch = false; 298} 299 300template <class Impl> 301FullO3CPU<Impl>::~FullO3CPU() 302{ 303} 304 305template <class Impl> 306void 307FullO3CPU<Impl>::fullCPURegStats() 308{ 309 BaseO3CPU::regStats(); 310 311 // Register any of the O3CPU's stats here. 312 timesIdled 313 .name(name() + ".timesIdled") 314 .desc("Number of times that the entire CPU went into an idle state and" 315 " unscheduled itself") 316 .prereq(timesIdled); 317 318 idleCycles 319 .name(name() + ".idleCycles") 320 .desc("Total number of cycles that the CPU has spent unscheduled due " 321 "to idling") 322 .prereq(idleCycles); 323 324 // Number of Instructions simulated 325 // -------------------------------- 326 // Should probably be in Base CPU but need templated 327 // MaxThreads so put in here instead 328 committedInsts 329 .init(numThreads) 330 .name(name() + ".committedInsts") 331 .desc("Number of Instructions Simulated"); 332 333 totalCommittedInsts 334 .name(name() + ".committedInsts_total") 335 .desc("Number of Instructions Simulated"); 336 337 cpi 338 .name(name() + ".cpi") 339 .desc("CPI: Cycles Per Instruction") 340 .precision(6); 341 cpi = simTicks / committedInsts; 342 343 totalCpi 344 .name(name() + ".cpi_total") 345 .desc("CPI: Total CPI of All Threads") 346 .precision(6); 347 totalCpi = simTicks / totalCommittedInsts; 348 349 ipc 350 .name(name() + ".ipc") 351 .desc("IPC: Instructions Per Cycle") 352 .precision(6); 353 ipc = committedInsts / simTicks; 354 355 totalIpc 356 .name(name() + ".ipc_total") 357 .desc("IPC: Total IPC of All Threads") 358 .precision(6); 359 totalIpc = totalCommittedInsts / simTicks; 360 361} 362 363template <class Impl> 364void 365FullO3CPU<Impl>::tick() 366{ 367 DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 368 369 ++numCycles; 370 371// activity = false; 372 373 //Tick each of the stages 374 fetch.tick(); 375 376 decode.tick(); 377 378 rename.tick(); 379 380 iew.tick(); 381 382 commit.tick(); 383 384#if !FULL_SYSTEM 385 doContextSwitch(); 386#endif 387 388 // Now advance the time buffers 389 timeBuffer.advance(); 390 391 fetchQueue.advance(); 392 decodeQueue.advance(); 393 renameQueue.advance(); 394 iewQueue.advance(); 395 396 activityRec.advance(); 397 398 if (removeInstsThisCycle) { 399 cleanUpRemovedInsts(); 400 } 401 402 if (!tickEvent.scheduled()) { 403 if (_status == SwitchedOut) { 404 // increment stat 405 lastRunningCycle = curTick; 406 } else if (!activityRec.active()) { 407 lastRunningCycle = curTick; 408 timesIdled++; 409 } else { 410 tickEvent.schedule(curTick + cycles(1)); 411 } 412 } 413 414#if !FULL_SYSTEM 415 updateThreadPriority(); 416#endif 417 418} 419 420template <class Impl> 421void 422FullO3CPU<Impl>::init() 423{ 424 if (!deferRegistration) { 425 registerThreadContexts(); 426 } 427 428 // Set inSyscall so that the CPU doesn't squash when initially 429 // setting up registers. 430 for (int i = 0; i < number_of_threads; ++i) 431 thread[i]->inSyscall = true; 432 433 for (int tid=0; tid < number_of_threads; tid++) { 434#if FULL_SYSTEM 435 ThreadContext *src_tc = threadContexts[tid]; 436#else 437 ThreadContext *src_tc = thread[tid]->getTC(); 438#endif 439 // Threads start in the Suspended State 440 if (src_tc->status() != ThreadContext::Suspended) { 441 continue; 442 } 443 444#if FULL_SYSTEM 445 TheISA::initCPU(src_tc, src_tc->readCpuId()); 446#endif 447 } 448 449 // Clear inSyscall. 450 for (int i = 0; i < number_of_threads; ++i) 451 thread[i]->inSyscall = false; 452 453 // Initialize stages. 454 fetch.initStage(); 455 iew.initStage(); 456 rename.initStage(); 457 commit.initStage(); 458 459 commit.setThreads(thread); 460} 461 462template <class Impl> 463void 464FullO3CPU<Impl>::insertThread(unsigned tid) 465{ 466 DPRINTF(O3CPU,"[tid:%i] Initializing thread data"); 467 // Will change now that the PC and thread state is internal to the CPU 468 // and not in the ThreadContext. 469#if 0 470#if FULL_SYSTEM 471 ThreadContext *src_tc = system->threadContexts[tid]; 472#else 473 ThreadContext *src_tc = thread[tid]; 474#endif 475 476 //Bind Int Regs to Rename Map 477 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 478 PhysRegIndex phys_reg = freeList.getIntReg(); 479 480 renameMap[tid].setEntry(ireg,phys_reg); 481 scoreboard.setReg(phys_reg); 482 } 483 484 //Bind Float Regs to Rename Map 485 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 486 PhysRegIndex phys_reg = freeList.getFloatReg(); 487 488 renameMap[tid].setEntry(freg,phys_reg); 489 scoreboard.setReg(phys_reg); 490 } 491 492 //Copy Thread Data Into RegFile 493 this->copyFromTC(tid); 494 495 //Set PC/NPC 496 regFile.pc[tid] = src_tc->readPC(); 497 regFile.npc[tid] = src_tc->readNextPC(); 498 499 src_tc->setStatus(ThreadContext::Active); 500 501 activateContext(tid,1); 502 503 //Reset ROB/IQ/LSQ Entries 504 commit.rob->resetEntries(); 505 iew.resetEntries(); 506#endif 507} 508 509template <class Impl> 510void 511FullO3CPU<Impl>::removeThread(unsigned tid) 512{ 513 DPRINTF(O3CPU,"[tid:%i] Removing thread data"); 514#if 0 515 //Unbind Int Regs from Rename Map 516 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 517 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 518 519 scoreboard.unsetReg(phys_reg); 520 freeList.addReg(phys_reg); 521 } 522 523 //Unbind Float Regs from Rename Map 524 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 525 PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 526 527 scoreboard.unsetReg(phys_reg); 528 freeList.addReg(phys_reg); 529 } 530 531 //Copy Thread Data From RegFile 532 /* Fix Me: 533 * Do we really need to do this if we are removing a thread 534 * in the sense that it's finished (exiting)? If the thread is just 535 * being suspended we might... 536 */ 537// this->copyToTC(tid); 538 539 //Squash Throughout Pipeline 540 fetch.squash(0,tid); 541 decode.squash(tid); 542 rename.squash(tid); 543 544 assert(iew.ldstQueue.getCount(tid) == 0); 545 546 //Reset ROB/IQ/LSQ Entries 547 if (activeThreads.size() >= 1) { 548 commit.rob->resetEntries(); 549 iew.resetEntries(); 550 } 551#endif 552} 553 554 555template <class Impl> 556void 557FullO3CPU<Impl>::activateWhenReady(int tid) 558{ 559 DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 560 "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 561 tid); 562 563 bool ready = true; 564 565 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 566 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 567 "Phys. Int. Regs.\n", 568 tid); 569 ready = false; 570 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 571 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 572 "Phys. Float. Regs.\n", 573 tid); 574 ready = false; 575 } else if (commit.rob->numFreeEntries() >= 576 commit.rob->entryAmount(activeThreads.size() + 1)) { 577 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 578 "ROB entries.\n", 579 tid); 580 ready = false; 581 } else if (iew.instQueue.numFreeEntries() >= 582 iew.instQueue.entryAmount(activeThreads.size() + 1)) { 583 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 584 "IQ entries.\n", 585 tid); 586 ready = false; 587 } else if (iew.ldstQueue.numFreeEntries() >= 588 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 589 DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 590 "LSQ entries.\n", 591 tid); 592 ready = false; 593 } 594 595 if (ready) { 596 insertThread(tid); 597 598 contextSwitch = false; 599 600 cpuWaitList.remove(tid); 601 } else { 602 suspendContext(tid); 603 604 //blocks fetch 605 contextSwitch = true; 606 607 //do waitlist 608 cpuWaitList.push_back(tid); 609 } 610} 611 612template <class Impl> 613void 614FullO3CPU<Impl>::activateThread(unsigned int tid) 615{ 616 list<unsigned>::iterator isActive = find( 617 activeThreads.begin(), activeThreads.end(), tid); 618 619 if (isActive == activeThreads.end()) { 620 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 621 tid); 622 623 activeThreads.push_back(tid); 624 } 625} 626 627 628template <class Impl> 629void 630FullO3CPU<Impl>::activateContext(int tid, int delay) 631{ 632 // Needs to set each stage to running as well. 633 if (delay){ 634 DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 635 "on cycle %d\n", tid, curTick + cycles(delay)); 636 scheduleActivateThreadEvent(tid, delay); 637 } else { 638 activateThread(tid); 639 } 640 641 if(lastActivatedCycle < curTick) { 642 scheduleTickEvent(delay); 643 644 // Be sure to signal that there's some activity so the CPU doesn't 645 // deschedule itself. 646 activityRec.activity(); 647 fetch.wakeFromQuiesce(); 648 649 lastActivatedCycle = curTick; 650 651 _status = Running; 652 } 653} 654 655template <class Impl> 656void 657FullO3CPU<Impl>::suspendContext(int tid) 658{ 659 DPRINTF(O3CPU,"[tid: %i]: Suspended ...\n", tid); 660 unscheduleTickEvent(); 661 _status = Idle; 662/* 663 //Remove From Active List, if Active 664 list<unsigned>::iterator isActive = find( 665 activeThreads.begin(), activeThreads.end(), tid); 666 667 if (isActive != activeThreads.end()) { 668 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 669 tid); 670 activeThreads.erase(isActive); 671 } 672*/ 673} 674 675template <class Impl> 676void 677FullO3CPU<Impl>::deallocateContext(int tid) 678{ 679 DPRINTF(O3CPU,"[tid:%i]: Deallocating ...", tid); 680/* 681 //Remove From Active List, if Active 682 list<unsigned>::iterator isActive = find( 683 activeThreads.begin(), activeThreads.end(), tid); 684 685 if (isActive != activeThreads.end()) { 686 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 687 tid); 688 activeThreads.erase(isActive); 689 690 removeThread(tid); 691 } 692*/ 693} 694 695template <class Impl> 696void 697FullO3CPU<Impl>::haltContext(int tid) 698{ 699 DPRINTF(O3CPU,"[tid:%i]: Halted ...", tid); 700/* 701 //Remove From Active List, if Active 702 list<unsigned>::iterator isActive = find( 703 activeThreads.begin(), activeThreads.end(), tid); 704 705 if (isActive != activeThreads.end()) { 706 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 707 tid); 708 activeThreads.erase(isActive); 709 710 removeThread(tid); 711 } 712*/ 713} 714 715template <class Impl> 716void 717FullO3CPU<Impl>::switchOut(Sampler *_sampler) 718{ 719 sampler = _sampler; 720 switchCount = 0; 721 fetch.switchOut(); 722 decode.switchOut(); 723 rename.switchOut(); 724 iew.switchOut(); 725 commit.switchOut(); 726 727 // Wake the CPU and record activity so everything can drain out if 728 // the CPU is currently idle. 729 wakeCPU(); 730 activityRec.activity(); 731} 732 733template <class Impl> 734void 735FullO3CPU<Impl>::signalSwitched() 736{ 737 if (++switchCount == NumStages) { 738 fetch.doSwitchOut(); 739 rename.doSwitchOut(); 740 commit.doSwitchOut(); 741 instList.clear(); 742 while (!removeList.empty()) { 743 removeList.pop(); 744 } 745 746#if USE_CHECKER 747 if (checker) 748 checker->switchOut(sampler); 749#endif 750 751 if (tickEvent.scheduled()) 752 tickEvent.squash(); 753 sampler->signalSwitched(); 754 _status = SwitchedOut; 755 } 756 assert(switchCount <= 5); 757} 758 759template <class Impl> 760void 761FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 762{ 763 // Flush out any old data from the time buffers. 764 for (int i = 0; i < 10; ++i) { 765 timeBuffer.advance(); 766 fetchQueue.advance(); 767 decodeQueue.advance(); 768 renameQueue.advance(); 769 iewQueue.advance(); 770 } 771 772 activityRec.reset(); 773 774 BaseCPU::takeOverFrom(oldCPU); 775 776 fetch.takeOverFrom(); 777 decode.takeOverFrom(); 778 rename.takeOverFrom(); 779 iew.takeOverFrom(); 780 commit.takeOverFrom(); 781 782 assert(!tickEvent.scheduled()); 783 784 // @todo: Figure out how to properly select the tid to put onto 785 // the active threads list. 786 int tid = 0; 787 788 list<unsigned>::iterator isActive = find( 789 activeThreads.begin(), activeThreads.end(), tid); 790 791 if (isActive == activeThreads.end()) { 792 //May Need to Re-code this if the delay variable is the delay 793 //needed for thread to activate 794 DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 795 tid); 796 797 activeThreads.push_back(tid); 798 } 799 800 // Set all statuses to active, schedule the CPU's tick event. 801 // @todo: Fix up statuses so this is handled properly 802 for (int i = 0; i < threadContexts.size(); ++i) { 803 ThreadContext *tc = threadContexts[i]; 804 if (tc->status() == ThreadContext::Active && _status != Running) { 805 _status = Running; 806 tickEvent.schedule(curTick); 807 } 808 } 809 if (!tickEvent.scheduled()) 810 tickEvent.schedule(curTick); 811} 812 813template <class Impl> 814uint64_t 815FullO3CPU<Impl>::readIntReg(int reg_idx) 816{ 817 return regFile.readIntReg(reg_idx); 818} 819 820template <class Impl> 821FloatReg 822FullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 823{ 824 return regFile.readFloatReg(reg_idx, width); 825} 826 827template <class Impl> 828FloatReg 829FullO3CPU<Impl>::readFloatReg(int reg_idx) 830{ 831 return regFile.readFloatReg(reg_idx); 832} 833 834template <class Impl> 835FloatRegBits 836FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 837{ 838 return regFile.readFloatRegBits(reg_idx, width); 839} 840 841template <class Impl> 842FloatRegBits 843FullO3CPU<Impl>::readFloatRegBits(int reg_idx) 844{ 845 return regFile.readFloatRegBits(reg_idx); 846} 847 848template <class Impl> 849void 850FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 851{ 852 regFile.setIntReg(reg_idx, val); 853} 854 855template <class Impl> 856void 857FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 858{ 859 regFile.setFloatReg(reg_idx, val, width); 860} 861 862template <class Impl> 863void 864FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 865{ 866 regFile.setFloatReg(reg_idx, val); 867} 868 869template <class Impl> 870void 871FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 872{ 873 regFile.setFloatRegBits(reg_idx, val, width); 874} 875 876template <class Impl> 877void 878FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 879{ 880 regFile.setFloatRegBits(reg_idx, val); 881} 882 883template <class Impl> 884uint64_t 885FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 886{ 887 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 888 889 return regFile.readIntReg(phys_reg); 890} 891 892template <class Impl> 893float 894FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 895{ 896 int idx = reg_idx + TheISA::FP_Base_DepTag; 897 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 898 899 return regFile.readFloatReg(phys_reg); 900} 901 902template <class Impl> 903double 904FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 905{ 906 int idx = reg_idx + TheISA::FP_Base_DepTag; 907 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 908 909 return regFile.readFloatReg(phys_reg, 64); 910} 911 912template <class Impl> 913uint64_t 914FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 915{ 916 int idx = reg_idx + TheISA::FP_Base_DepTag; 917 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 918 919 return regFile.readFloatRegBits(phys_reg); 920} 921 922template <class Impl> 923void 924FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 925{ 926 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 927 928 regFile.setIntReg(phys_reg, val); 929} 930 931template <class Impl> 932void 933FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 934{ 935 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 936 937 regFile.setFloatReg(phys_reg, val); 938} 939 940template <class Impl> 941void 942FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 943{ 944 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 945 946 regFile.setFloatReg(phys_reg, val, 64); 947} 948 949template <class Impl> 950void 951FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 952{ 953 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 954 955 regFile.setFloatRegBits(phys_reg, val); 956} 957 958template <class Impl> 959uint64_t 960FullO3CPU<Impl>::readPC(unsigned tid) 961{ 962 return commit.readPC(tid); 963} 964 965template <class Impl> 966void 967FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 968{ 969 commit.setPC(new_PC, tid); 970} 971 972template <class Impl> 973uint64_t 974FullO3CPU<Impl>::readNextPC(unsigned tid) 975{ 976 return commit.readNextPC(tid); 977} 978 979template <class Impl> 980void 981FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 982{ 983 commit.setNextPC(val, tid); 984} 985 986#if THE_ISA != ALPHA_ISA 987template <class Impl> 988uint64_t 989FullO3CPU<Impl>::readNextNPC(unsigned tid) 990{ 991 return commit.readNextNPC(tid); 992} 993 994template <class Impl> 995void 996FullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid) 997{ 998 commit.setNextNPC(val, tid); 999} 1000#endif 1001 1002template <class Impl> 1003typename FullO3CPU<Impl>::ListIt 1004FullO3CPU<Impl>::addInst(DynInstPtr &inst) 1005{ 1006 instList.push_back(inst); 1007 1008 return --(instList.end()); 1009} 1010 1011template <class Impl> 1012void 1013FullO3CPU<Impl>::instDone(unsigned tid) 1014{ 1015 // Keep an instruction count. 1016 thread[tid]->numInst++; 1017 thread[tid]->numInsts++; 1018 committedInsts[tid]++; 1019 totalCommittedInsts++; 1020 1021 // Check for instruction-count-based events. 1022 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 1023} 1024 1025template <class Impl> 1026void 1027FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 1028{ 1029 removeInstsThisCycle = true; 1030 1031 removeList.push(inst->getInstListIt()); 1032} 1033 1034template <class Impl> 1035void 1036FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 1037{ 1038 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 1039 "[sn:%lli]\n", 1040 inst->threadNumber, inst->readPC(), inst->seqNum); 1041 1042 removeInstsThisCycle = true; 1043 1044 // Remove the front instruction. 1045 removeList.push(inst->getInstListIt()); 1046} 1047 1048template <class Impl> 1049void 1050FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 1051{ 1052 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 1053 " list.\n", tid); 1054 1055 ListIt end_it; 1056 1057 bool rob_empty = false; 1058 1059 if (instList.empty()) { 1060 return; 1061 } else if (rob.isEmpty(/*tid*/)) { 1062 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 1063 end_it = instList.begin(); 1064 rob_empty = true; 1065 } else { 1066 end_it = (rob.readTailInst(tid))->getInstListIt(); 1067 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 1068 } 1069 1070 removeInstsThisCycle = true; 1071 1072 ListIt inst_it = instList.end(); 1073 1074 inst_it--; 1075 1076 // Walk through the instruction list, removing any instructions 1077 // that were inserted after the given instruction iterator, end_it. 1078 while (inst_it != end_it) { 1079 assert(!instList.empty()); 1080 1081 squashInstIt(inst_it, tid); 1082 1083 inst_it--; 1084 } 1085 1086 // If the ROB was empty, then we actually need to remove the first 1087 // instruction as well. 1088 if (rob_empty) { 1089 squashInstIt(inst_it, tid); 1090 } 1091} 1092 1093template <class Impl> 1094void 1095FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 1096 unsigned tid) 1097{ 1098 assert(!instList.empty()); 1099 1100 removeInstsThisCycle = true; 1101 1102 ListIt inst_iter = instList.end(); 1103 1104 inst_iter--; 1105 1106 DPRINTF(O3CPU, "Deleting instructions from instruction " 1107 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 1108 tid, seq_num, (*inst_iter)->seqNum); 1109 1110 while ((*inst_iter)->seqNum > seq_num) { 1111 1112 bool break_loop = (inst_iter == instList.begin()); 1113 1114 squashInstIt(inst_iter, tid); 1115 1116 inst_iter--; 1117 1118 if (break_loop) 1119 break; 1120 } 1121} 1122 1123template <class Impl> 1124inline void 1125FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 1126{ 1127 if ((*instIt)->threadNumber == tid) { 1128 DPRINTF(O3CPU, "Squashing instruction, " 1129 "[tid:%i] [sn:%lli] PC %#x\n", 1130 (*instIt)->threadNumber, 1131 (*instIt)->seqNum, 1132 (*instIt)->readPC()); 1133 1134 // Mark it as squashed. 1135 (*instIt)->setSquashed(); 1136 1137 // @todo: Formulate a consistent method for deleting 1138 // instructions from the instruction list 1139 // Remove the instruction from the list. 1140 removeList.push(instIt); 1141 } 1142} 1143 1144template <class Impl> 1145void 1146FullO3CPU<Impl>::cleanUpRemovedInsts() 1147{ 1148 while (!removeList.empty()) { 1149 DPRINTF(O3CPU, "Removing instruction, " 1150 "[tid:%i] [sn:%lli] PC %#x\n", 1151 (*removeList.front())->threadNumber, 1152 (*removeList.front())->seqNum, 1153 (*removeList.front())->readPC()); 1154 1155 instList.erase(removeList.front()); 1156 1157 removeList.pop(); 1158 } 1159 1160 removeInstsThisCycle = false; 1161} 1162/* 1163template <class Impl> 1164void 1165FullO3CPU<Impl>::removeAllInsts() 1166{ 1167 instList.clear(); 1168} 1169*/ 1170template <class Impl> 1171void 1172FullO3CPU<Impl>::dumpInsts() 1173{ 1174 int num = 0; 1175 1176 ListIt inst_list_it = instList.begin(); 1177 1178 cprintf("Dumping Instruction List\n"); 1179 1180 while (inst_list_it != instList.end()) { 1181 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 1182 "Squashed:%i\n\n", 1183 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 1184 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 1185 (*inst_list_it)->isSquashed()); 1186 inst_list_it++; 1187 ++num; 1188 } 1189} 1190/* 1191template <class Impl> 1192void 1193FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 1194{ 1195 iew.wakeDependents(inst); 1196} 1197*/ 1198template <class Impl> 1199void 1200FullO3CPU<Impl>::wakeCPU() 1201{ 1202 if (activityRec.active() || tickEvent.scheduled()) { 1203 DPRINTF(Activity, "CPU already running.\n"); 1204 return; 1205 } 1206 1207 DPRINTF(Activity, "Waking up CPU\n"); 1208 1209 idleCycles += (curTick - 1) - lastRunningCycle; 1210 1211 tickEvent.schedule(curTick); 1212} 1213 1214template <class Impl> 1215int 1216FullO3CPU<Impl>::getFreeTid() 1217{ 1218 for (int i=0; i < numThreads; i++) { 1219 if (!tids[i]) { 1220 tids[i] = true; 1221 return i; 1222 } 1223 } 1224 1225 return -1; 1226} 1227 1228template <class Impl> 1229void 1230FullO3CPU<Impl>::doContextSwitch() 1231{ 1232 if (contextSwitch) { 1233 1234 //ADD CODE TO DEACTIVE THREAD HERE (???) 1235 1236 for (int tid=0; tid < cpuWaitList.size(); tid++) { 1237 activateWhenReady(tid); 1238 } 1239 1240 if (cpuWaitList.size() == 0) 1241 contextSwitch = true; 1242 } 1243} 1244 1245template <class Impl> 1246void 1247FullO3CPU<Impl>::updateThreadPriority() 1248{ 1249 if (activeThreads.size() > 1) 1250 { 1251 //DEFAULT TO ROUND ROBIN SCHEME 1252 //e.g. Move highest priority to end of thread list 1253 list<unsigned>::iterator list_begin = activeThreads.begin(); 1254 list<unsigned>::iterator list_end = activeThreads.end(); 1255 1256 unsigned high_thread = *list_begin; 1257 1258 activeThreads.erase(list_begin); 1259 1260 activeThreads.push_back(high_thread); 1261 } 1262} 1263 1264// Forward declaration of FullO3CPU. 1265template class FullO3CPU<O3CPUImpl>; 1266