cpu.cc revision 2756
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include "config/full_system.hh" 33 34#if FULL_SYSTEM 35#include "sim/system.hh" 36#else 37#include "sim/process.hh" 38#endif 39 40#include "cpu/activity.hh" 41#include "cpu/checker/cpu.hh" 42#include "cpu/simple_thread.hh" 43#include "cpu/thread_context.hh" 44#include "cpu/o3/alpha_dyn_inst.hh" 45#include "cpu/o3/alpha_impl.hh" 46#include "cpu/o3/cpu.hh" 47 48#include "sim/root.hh" 49#include "sim/stat_control.hh" 50 51using namespace std; 52using namespace TheISA; 53 54BaseFullCPU::BaseFullCPU(Params *params) 55 : BaseCPU(params), cpu_id(0) 56{ 57} 58 59void 60BaseFullCPU::regStats() 61{ 62 BaseCPU::regStats(); 63} 64 65template <class Impl> 66FullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 67 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 68{ 69} 70 71template <class Impl> 72void 73FullO3CPU<Impl>::TickEvent::process() 74{ 75 cpu->tick(); 76} 77 78template <class Impl> 79const char * 80FullO3CPU<Impl>::TickEvent::description() 81{ 82 return "FullO3CPU tick event"; 83} 84 85template <class Impl> 86FullO3CPU<Impl>::FullO3CPU(Params *params) 87 : BaseFullCPU(params), 88 tickEvent(this), 89 removeInstsThisCycle(false), 90 fetch(params), 91 decode(params), 92 rename(params), 93 iew(params), 94 commit(params), 95 96 regFile(params->numPhysIntRegs, params->numPhysFloatRegs), 97 98 freeList(params->numberOfThreads,//number of activeThreads 99 TheISA::NumIntRegs, params->numPhysIntRegs, 100 TheISA::NumFloatRegs, params->numPhysFloatRegs), 101 102 rob(params->numROBEntries, params->squashWidth, 103 params->smtROBPolicy, params->smtROBThreshold, 104 params->numberOfThreads), 105 106 scoreboard(params->numberOfThreads,//number of activeThreads 107 TheISA::NumIntRegs, params->numPhysIntRegs, 108 TheISA::NumFloatRegs, params->numPhysFloatRegs, 109 TheISA::NumMiscRegs * number_of_threads, 110 TheISA::ZeroReg), 111 112 // For now just have these time buffers be pretty big. 113 // @todo: Make these time buffer sizes parameters or derived 114 // from latencies 115 timeBuffer(5, 5), 116 fetchQueue(5, 5), 117 decodeQueue(5, 5), 118 renameQueue(5, 5), 119 iewQueue(5, 5), 120 activityRec(NumStages, 10, params->activity), 121 122 globalSeqNum(1), 123 124#if FULL_SYSTEM 125 system(params->system), 126 physmem(system->physmem), 127#endif // FULL_SYSTEM 128 mem(params->mem), 129 switchCount(0), 130 deferRegistration(params->deferRegistration), 131 numThreads(number_of_threads) 132{ 133 _status = Idle; 134 135 if (params->checker) { 136 BaseCPU *temp_checker = params->checker; 137 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 138 checker->setMemory(mem); 139#if FULL_SYSTEM 140 checker->setSystem(params->system); 141#endif 142 } else { 143 checker = NULL; 144 } 145 146#if !FULL_SYSTEM 147 thread.resize(number_of_threads); 148 tids.resize(number_of_threads); 149#endif 150 151 // The stages also need their CPU pointer setup. However this 152 // must be done at the upper level CPU because they have pointers 153 // to the upper level CPU, and not this FullO3CPU. 154 155 // Set up Pointers to the activeThreads list for each stage 156 fetch.setActiveThreads(&activeThreads); 157 decode.setActiveThreads(&activeThreads); 158 rename.setActiveThreads(&activeThreads); 159 iew.setActiveThreads(&activeThreads); 160 commit.setActiveThreads(&activeThreads); 161 162 // Give each of the stages the time buffer they will use. 163 fetch.setTimeBuffer(&timeBuffer); 164 decode.setTimeBuffer(&timeBuffer); 165 rename.setTimeBuffer(&timeBuffer); 166 iew.setTimeBuffer(&timeBuffer); 167 commit.setTimeBuffer(&timeBuffer); 168 169 // Also setup each of the stages' queues. 170 fetch.setFetchQueue(&fetchQueue); 171 decode.setFetchQueue(&fetchQueue); 172 commit.setFetchQueue(&fetchQueue); 173 decode.setDecodeQueue(&decodeQueue); 174 rename.setDecodeQueue(&decodeQueue); 175 rename.setRenameQueue(&renameQueue); 176 iew.setRenameQueue(&renameQueue); 177 iew.setIEWQueue(&iewQueue); 178 commit.setIEWQueue(&iewQueue); 179 commit.setRenameQueue(&renameQueue); 180 181 commit.setFetchStage(&fetch); 182 commit.setIEWStage(&iew); 183 rename.setIEWStage(&iew); 184 rename.setCommitStage(&commit); 185 186#if !FULL_SYSTEM 187 int active_threads = params->workload.size(); 188#else 189 int active_threads = 1; 190#endif 191 192 //Make Sure That this a Valid Architeture 193 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 194 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 195 196 rename.setScoreboard(&scoreboard); 197 iew.setScoreboard(&scoreboard); 198 199 // Setup the rename map for whichever stages need it. 200 PhysRegIndex lreg_idx = 0; 201 PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 202 203 for (int tid=0; tid < numThreads; tid++) { 204 bool bindRegs = (tid <= active_threads - 1); 205 206 commitRenameMap[tid].init(TheISA::NumIntRegs, 207 params->numPhysIntRegs, 208 lreg_idx, //Index for Logical. Regs 209 210 TheISA::NumFloatRegs, 211 params->numPhysFloatRegs, 212 freg_idx, //Index for Float Regs 213 214 TheISA::NumMiscRegs, 215 216 TheISA::ZeroReg, 217 TheISA::ZeroReg, 218 219 tid, 220 false); 221 222 renameMap[tid].init(TheISA::NumIntRegs, 223 params->numPhysIntRegs, 224 lreg_idx, //Index for Logical. Regs 225 226 TheISA::NumFloatRegs, 227 params->numPhysFloatRegs, 228 freg_idx, //Index for Float Regs 229 230 TheISA::NumMiscRegs, 231 232 TheISA::ZeroReg, 233 TheISA::ZeroReg, 234 235 tid, 236 bindRegs); 237 } 238 239 rename.setRenameMap(renameMap); 240 commit.setRenameMap(commitRenameMap); 241 242 // Give renameMap & rename stage access to the freeList; 243 for (int i=0; i < numThreads; i++) { 244 renameMap[i].setFreeList(&freeList); 245 } 246 rename.setFreeList(&freeList); 247 248 // Setup the ROB for whichever stages need it. 249 commit.setROB(&rob); 250 251 lastRunningCycle = curTick; 252 253 contextSwitch = false; 254} 255 256template <class Impl> 257FullO3CPU<Impl>::~FullO3CPU() 258{ 259} 260 261template <class Impl> 262void 263FullO3CPU<Impl>::fullCPURegStats() 264{ 265 BaseFullCPU::regStats(); 266 267 // Register any of the FullCPU's stats here. 268 timesIdled 269 .name(name() + ".timesIdled") 270 .desc("Number of times that the entire CPU went into an idle state and" 271 " unscheduled itself") 272 .prereq(timesIdled); 273 274 idleCycles 275 .name(name() + ".idleCycles") 276 .desc("Total number of cycles that the CPU has spent unscheduled due " 277 "to idling") 278 .prereq(idleCycles); 279 280 // Number of Instructions simulated 281 // -------------------------------- 282 // Should probably be in Base CPU but need templated 283 // MaxThreads so put in here instead 284 committedInsts 285 .init(numThreads) 286 .name(name() + ".committedInsts") 287 .desc("Number of Instructions Simulated"); 288 289 totalCommittedInsts 290 .name(name() + ".committedInsts_total") 291 .desc("Number of Instructions Simulated"); 292 293 cpi 294 .name(name() + ".cpi") 295 .desc("CPI: Cycles Per Instruction") 296 .precision(6); 297 cpi = simTicks / committedInsts; 298 299 totalCpi 300 .name(name() + ".cpi_total") 301 .desc("CPI: Total CPI of All Threads") 302 .precision(6); 303 totalCpi = simTicks / totalCommittedInsts; 304 305 ipc 306 .name(name() + ".ipc") 307 .desc("IPC: Instructions Per Cycle") 308 .precision(6); 309 ipc = committedInsts / simTicks; 310 311 totalIpc 312 .name(name() + ".ipc_total") 313 .desc("IPC: Total IPC of All Threads") 314 .precision(6); 315 totalIpc = totalCommittedInsts / simTicks; 316 317} 318 319template <class Impl> 320void 321FullO3CPU<Impl>::tick() 322{ 323 DPRINTF(FullCPU, "\n\nFullCPU: Ticking main, FullO3CPU.\n"); 324 325 ++numCycles; 326 327// activity = false; 328 329 //Tick each of the stages 330 fetch.tick(); 331 332 decode.tick(); 333 334 rename.tick(); 335 336 iew.tick(); 337 338 commit.tick(); 339 340#if !FULL_SYSTEM 341 doContextSwitch(); 342#endif 343 344 // Now advance the time buffers 345 timeBuffer.advance(); 346 347 fetchQueue.advance(); 348 decodeQueue.advance(); 349 renameQueue.advance(); 350 iewQueue.advance(); 351 352 activityRec.advance(); 353 354 if (removeInstsThisCycle) { 355 cleanUpRemovedInsts(); 356 } 357 358 if (!tickEvent.scheduled()) { 359 if (_status == SwitchedOut) { 360 // increment stat 361 lastRunningCycle = curTick; 362 } else if (!activityRec.active()) { 363 lastRunningCycle = curTick; 364 timesIdled++; 365 } else { 366 tickEvent.schedule(curTick + cycles(1)); 367 } 368 } 369 370#if !FULL_SYSTEM 371 updateThreadPriority(); 372#endif 373 374} 375 376template <class Impl> 377void 378FullO3CPU<Impl>::init() 379{ 380 if (!deferRegistration) { 381 registerThreadContexts(); 382 } 383 384 // Set inSyscall so that the CPU doesn't squash when initially 385 // setting up registers. 386 for (int i = 0; i < number_of_threads; ++i) 387 thread[i]->inSyscall = true; 388 389 for (int tid=0; tid < number_of_threads; tid++) { 390#if FULL_SYSTEM 391 ThreadContext *src_tc = threadContexts[tid]; 392#else 393 ThreadContext *src_tc = thread[tid]->getTC(); 394#endif 395 // Threads start in the Suspended State 396 if (src_tc->status() != ThreadContext::Suspended) { 397 continue; 398 } 399 400#if FULL_SYSTEM 401 TheISA::initCPU(src_tc, src_tc->readCpuId()); 402#endif 403 } 404 405 // Clear inSyscall. 406 for (int i = 0; i < number_of_threads; ++i) 407 thread[i]->inSyscall = false; 408 409 // Initialize stages. 410 fetch.initStage(); 411 iew.initStage(); 412 rename.initStage(); 413 commit.initStage(); 414 415 commit.setThreads(thread); 416} 417 418template <class Impl> 419void 420FullO3CPU<Impl>::insertThread(unsigned tid) 421{ 422 DPRINTF(FullCPU,"[tid:%i] Initializing thread data"); 423 // Will change now that the PC and thread state is internal to the CPU 424 // and not in the ThreadContext. 425#if 0 426#if FULL_SYSTEM 427 ThreadContext *src_tc = system->threadContexts[tid]; 428#else 429 ThreadContext *src_tc = thread[tid]; 430#endif 431 432 //Bind Int Regs to Rename Map 433 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 434 PhysRegIndex phys_reg = freeList.getIntReg(); 435 436 renameMap[tid].setEntry(ireg,phys_reg); 437 scoreboard.setReg(phys_reg); 438 } 439 440 //Bind Float Regs to Rename Map 441 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 442 PhysRegIndex phys_reg = freeList.getFloatReg(); 443 444 renameMap[tid].setEntry(freg,phys_reg); 445 scoreboard.setReg(phys_reg); 446 } 447 448 //Copy Thread Data Into RegFile 449 this->copyFromTC(tid); 450 451 //Set PC/NPC 452 regFile.pc[tid] = src_tc->readPC(); 453 regFile.npc[tid] = src_tc->readNextPC(); 454 455 src_tc->setStatus(ThreadContext::Active); 456 457 activateContext(tid,1); 458 459 //Reset ROB/IQ/LSQ Entries 460 commit.rob->resetEntries(); 461 iew.resetEntries(); 462#endif 463} 464 465template <class Impl> 466void 467FullO3CPU<Impl>::removeThread(unsigned tid) 468{ 469 DPRINTF(FullCPU,"[tid:%i] Removing thread data"); 470#if 0 471 //Unbind Int Regs from Rename Map 472 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 473 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 474 475 scoreboard.unsetReg(phys_reg); 476 freeList.addReg(phys_reg); 477 } 478 479 //Unbind Float Regs from Rename Map 480 for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 481 PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 482 483 scoreboard.unsetReg(phys_reg); 484 freeList.addReg(phys_reg); 485 } 486 487 //Copy Thread Data From RegFile 488 /* Fix Me: 489 * Do we really need to do this if we are removing a thread 490 * in the sense that it's finished (exiting)? If the thread is just 491 * being suspended we might... 492 */ 493// this->copyToTC(tid); 494 495 //Squash Throughout Pipeline 496 fetch.squash(0,tid); 497 decode.squash(tid); 498 rename.squash(tid); 499 500 assert(iew.ldstQueue.getCount(tid) == 0); 501 502 //Reset ROB/IQ/LSQ Entries 503 if (activeThreads.size() >= 1) { 504 commit.rob->resetEntries(); 505 iew.resetEntries(); 506 } 507#endif 508} 509 510 511template <class Impl> 512void 513FullO3CPU<Impl>::activateWhenReady(int tid) 514{ 515 DPRINTF(FullCPU,"[tid:%i]: Checking if resources are available for incoming" 516 "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 517 tid); 518 519 bool ready = true; 520 521 if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 522 DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " 523 "Phys. Int. Regs.\n", 524 tid); 525 ready = false; 526 } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 527 DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " 528 "Phys. Float. Regs.\n", 529 tid); 530 ready = false; 531 } else if (commit.rob->numFreeEntries() >= 532 commit.rob->entryAmount(activeThreads.size() + 1)) { 533 DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " 534 "ROB entries.\n", 535 tid); 536 ready = false; 537 } else if (iew.instQueue.numFreeEntries() >= 538 iew.instQueue.entryAmount(activeThreads.size() + 1)) { 539 DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " 540 "IQ entries.\n", 541 tid); 542 ready = false; 543 } else if (iew.ldstQueue.numFreeEntries() >= 544 iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 545 DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " 546 "LSQ entries.\n", 547 tid); 548 ready = false; 549 } 550 551 if (ready) { 552 insertThread(tid); 553 554 contextSwitch = false; 555 556 cpuWaitList.remove(tid); 557 } else { 558 suspendContext(tid); 559 560 //blocks fetch 561 contextSwitch = true; 562 563 //do waitlist 564 cpuWaitList.push_back(tid); 565 } 566} 567 568template <class Impl> 569void 570FullO3CPU<Impl>::activateContext(int tid, int delay) 571{ 572 // Needs to set each stage to running as well. 573 list<unsigned>::iterator isActive = find( 574 activeThreads.begin(), activeThreads.end(), tid); 575 576 if (isActive == activeThreads.end()) { 577 //May Need to Re-code this if the delay variable is the 578 //delay needed for thread to activate 579 DPRINTF(FullCPU, "Adding Thread %i to active threads list\n", 580 tid); 581 582 activeThreads.push_back(tid); 583 } 584 585 assert(_status == Idle || _status == SwitchedOut); 586 587 scheduleTickEvent(delay); 588 589 // Be sure to signal that there's some activity so the CPU doesn't 590 // deschedule itself. 591 activityRec.activity(); 592 fetch.wakeFromQuiesce(); 593 594 _status = Running; 595} 596 597template <class Impl> 598void 599FullO3CPU<Impl>::suspendContext(int tid) 600{ 601 DPRINTF(FullCPU,"[tid: %i]: Suspended ...\n", tid); 602 unscheduleTickEvent(); 603 _status = Idle; 604/* 605 //Remove From Active List, if Active 606 list<unsigned>::iterator isActive = find( 607 activeThreads.begin(), activeThreads.end(), tid); 608 609 if (isActive != activeThreads.end()) { 610 DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n", 611 tid); 612 activeThreads.erase(isActive); 613 } 614*/ 615} 616 617template <class Impl> 618void 619FullO3CPU<Impl>::deallocateContext(int tid) 620{ 621 DPRINTF(FullCPU,"[tid:%i]: Deallocating ...", tid); 622/* 623 //Remove From Active List, if Active 624 list<unsigned>::iterator isActive = find( 625 activeThreads.begin(), activeThreads.end(), tid); 626 627 if (isActive != activeThreads.end()) { 628 DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n", 629 tid); 630 activeThreads.erase(isActive); 631 632 removeThread(tid); 633 } 634*/ 635} 636 637template <class Impl> 638void 639FullO3CPU<Impl>::haltContext(int tid) 640{ 641 DPRINTF(FullCPU,"[tid:%i]: Halted ...", tid); 642/* 643 //Remove From Active List, if Active 644 list<unsigned>::iterator isActive = find( 645 activeThreads.begin(), activeThreads.end(), tid); 646 647 if (isActive != activeThreads.end()) { 648 DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n", 649 tid); 650 activeThreads.erase(isActive); 651 652 removeThread(tid); 653 } 654*/ 655} 656 657template <class Impl> 658void 659FullO3CPU<Impl>::switchOut(Sampler *_sampler) 660{ 661 sampler = _sampler; 662 switchCount = 0; 663 fetch.switchOut(); 664 decode.switchOut(); 665 rename.switchOut(); 666 iew.switchOut(); 667 commit.switchOut(); 668 669 // Wake the CPU and record activity so everything can drain out if 670 // the CPU is currently idle. 671 wakeCPU(); 672 activityRec.activity(); 673} 674 675template <class Impl> 676void 677FullO3CPU<Impl>::signalSwitched() 678{ 679 if (++switchCount == NumStages) { 680 fetch.doSwitchOut(); 681 rename.doSwitchOut(); 682 commit.doSwitchOut(); 683 instList.clear(); 684 while (!removeList.empty()) { 685 removeList.pop(); 686 } 687 688 if (checker) 689 checker->switchOut(sampler); 690 691 if (tickEvent.scheduled()) 692 tickEvent.squash(); 693 sampler->signalSwitched(); 694 _status = SwitchedOut; 695 } 696 assert(switchCount <= 5); 697} 698 699template <class Impl> 700void 701FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 702{ 703 // Flush out any old data from the time buffers. 704 for (int i = 0; i < 10; ++i) { 705 timeBuffer.advance(); 706 fetchQueue.advance(); 707 decodeQueue.advance(); 708 renameQueue.advance(); 709 iewQueue.advance(); 710 } 711 712 activityRec.reset(); 713 714 BaseCPU::takeOverFrom(oldCPU); 715 716 fetch.takeOverFrom(); 717 decode.takeOverFrom(); 718 rename.takeOverFrom(); 719 iew.takeOverFrom(); 720 commit.takeOverFrom(); 721 722 assert(!tickEvent.scheduled()); 723 724 // @todo: Figure out how to properly select the tid to put onto 725 // the active threads list. 726 int tid = 0; 727 728 list<unsigned>::iterator isActive = find( 729 activeThreads.begin(), activeThreads.end(), tid); 730 731 if (isActive == activeThreads.end()) { 732 //May Need to Re-code this if the delay variable is the delay 733 //needed for thread to activate 734 DPRINTF(FullCPU, "Adding Thread %i to active threads list\n", 735 tid); 736 737 activeThreads.push_back(tid); 738 } 739 740 // Set all statuses to active, schedule the CPU's tick event. 741 // @todo: Fix up statuses so this is handled properly 742 for (int i = 0; i < threadContexts.size(); ++i) { 743 ThreadContext *tc = threadContexts[i]; 744 if (tc->status() == ThreadContext::Active && _status != Running) { 745 _status = Running; 746 tickEvent.schedule(curTick); 747 } 748 } 749 if (!tickEvent.scheduled()) 750 tickEvent.schedule(curTick); 751} 752 753template <class Impl> 754uint64_t 755FullO3CPU<Impl>::readIntReg(int reg_idx) 756{ 757 return regFile.readIntReg(reg_idx); 758} 759 760template <class Impl> 761FloatReg 762FullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 763{ 764 return regFile.readFloatReg(reg_idx, width); 765} 766 767template <class Impl> 768FloatReg 769FullO3CPU<Impl>::readFloatReg(int reg_idx) 770{ 771 return regFile.readFloatReg(reg_idx); 772} 773 774template <class Impl> 775FloatRegBits 776FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 777{ 778 return regFile.readFloatRegBits(reg_idx, width); 779} 780 781template <class Impl> 782FloatRegBits 783FullO3CPU<Impl>::readFloatRegBits(int reg_idx) 784{ 785 return regFile.readFloatRegBits(reg_idx); 786} 787 788template <class Impl> 789void 790FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 791{ 792 regFile.setIntReg(reg_idx, val); 793} 794 795template <class Impl> 796void 797FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 798{ 799 regFile.setFloatReg(reg_idx, val, width); 800} 801 802template <class Impl> 803void 804FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 805{ 806 regFile.setFloatReg(reg_idx, val); 807} 808 809template <class Impl> 810void 811FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 812{ 813 regFile.setFloatRegBits(reg_idx, val, width); 814} 815 816template <class Impl> 817void 818FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 819{ 820 regFile.setFloatRegBits(reg_idx, val); 821} 822 823template <class Impl> 824uint64_t 825FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 826{ 827 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 828 829 return regFile.readIntReg(phys_reg); 830} 831 832template <class Impl> 833float 834FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 835{ 836 int idx = reg_idx + TheISA::FP_Base_DepTag; 837 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 838 839 return regFile.readFloatReg(phys_reg); 840} 841 842template <class Impl> 843double 844FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 845{ 846 int idx = reg_idx + TheISA::FP_Base_DepTag; 847 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 848 849 return regFile.readFloatReg(phys_reg, 64); 850} 851 852template <class Impl> 853uint64_t 854FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 855{ 856 int idx = reg_idx + TheISA::FP_Base_DepTag; 857 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 858 859 return regFile.readFloatRegBits(phys_reg); 860} 861 862template <class Impl> 863void 864FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 865{ 866 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 867 868 regFile.setIntReg(phys_reg, val); 869} 870 871template <class Impl> 872void 873FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 874{ 875 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 876 877 regFile.setFloatReg(phys_reg, val); 878} 879 880template <class Impl> 881void 882FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 883{ 884 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 885 886 regFile.setFloatReg(phys_reg, val, 64); 887} 888 889template <class Impl> 890void 891FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 892{ 893 PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 894 895 regFile.setFloatRegBits(phys_reg, val); 896} 897 898template <class Impl> 899uint64_t 900FullO3CPU<Impl>::readPC(unsigned tid) 901{ 902 return commit.readPC(tid); 903} 904 905template <class Impl> 906void 907FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 908{ 909 commit.setPC(new_PC, tid); 910} 911 912template <class Impl> 913uint64_t 914FullO3CPU<Impl>::readNextPC(unsigned tid) 915{ 916 return commit.readNextPC(tid); 917} 918 919template <class Impl> 920void 921FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 922{ 923 commit.setNextPC(val, tid); 924} 925 926#if THE_ISA != ALPHA_ISA 927template <class Impl> 928uint64_t 929FullO3CPU<Impl>::readNextNPC(unsigned tid) 930{ 931 return commit.readNextNPC(tid); 932} 933 934template <class Impl> 935void 936FullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid) 937{ 938 commit.setNextNPC(val, tid); 939} 940#endif 941 942template <class Impl> 943typename FullO3CPU<Impl>::ListIt 944FullO3CPU<Impl>::addInst(DynInstPtr &inst) 945{ 946 instList.push_back(inst); 947 948 return --(instList.end()); 949} 950 951template <class Impl> 952void 953FullO3CPU<Impl>::instDone(unsigned tid) 954{ 955 // Keep an instruction count. 956 thread[tid]->numInst++; 957 thread[tid]->numInsts++; 958 committedInsts[tid]++; 959 totalCommittedInsts++; 960 961 // Check for instruction-count-based events. 962 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 963} 964 965template <class Impl> 966void 967FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 968{ 969 removeInstsThisCycle = true; 970 971 removeList.push(inst->getInstListIt()); 972} 973 974template <class Impl> 975void 976FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 977{ 978 DPRINTF(FullCPU, "FullCPU: Removing committed instruction [tid:%i] PC %#x " 979 "[sn:%lli]\n", 980 inst->threadNumber, inst->readPC(), inst->seqNum); 981 982 removeInstsThisCycle = true; 983 984 // Remove the front instruction. 985 removeList.push(inst->getInstListIt()); 986} 987 988template <class Impl> 989void 990FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 991{ 992 DPRINTF(FullCPU, "FullCPU: Thread %i: Deleting instructions from instruction" 993 " list.\n", tid); 994 995 ListIt end_it; 996 997 bool rob_empty = false; 998 999 if (instList.empty()) { 1000 return; 1001 } else if (rob.isEmpty(/*tid*/)) { 1002 DPRINTF(FullCPU, "FullCPU: ROB is empty, squashing all insts.\n"); 1003 end_it = instList.begin(); 1004 rob_empty = true; 1005 } else { 1006 end_it = (rob.readTailInst(tid))->getInstListIt(); 1007 DPRINTF(FullCPU, "FullCPU: ROB is not empty, squashing insts not in ROB.\n"); 1008 } 1009 1010 removeInstsThisCycle = true; 1011 1012 ListIt inst_it = instList.end(); 1013 1014 inst_it--; 1015 1016 // Walk through the instruction list, removing any instructions 1017 // that were inserted after the given instruction iterator, end_it. 1018 while (inst_it != end_it) { 1019 assert(!instList.empty()); 1020 1021 squashInstIt(inst_it, tid); 1022 1023 inst_it--; 1024 } 1025 1026 // If the ROB was empty, then we actually need to remove the first 1027 // instruction as well. 1028 if (rob_empty) { 1029 squashInstIt(inst_it, tid); 1030 } 1031} 1032 1033template <class Impl> 1034void 1035FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 1036 unsigned tid) 1037{ 1038 assert(!instList.empty()); 1039 1040 removeInstsThisCycle = true; 1041 1042 ListIt inst_iter = instList.end(); 1043 1044 inst_iter--; 1045 1046 DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction " 1047 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 1048 tid, seq_num, (*inst_iter)->seqNum); 1049 1050 while ((*inst_iter)->seqNum > seq_num) { 1051 1052 bool break_loop = (inst_iter == instList.begin()); 1053 1054 squashInstIt(inst_iter, tid); 1055 1056 inst_iter--; 1057 1058 if (break_loop) 1059 break; 1060 } 1061} 1062 1063template <class Impl> 1064inline void 1065FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 1066{ 1067 if ((*instIt)->threadNumber == tid) { 1068 DPRINTF(FullCPU, "FullCPU: Squashing instruction, " 1069 "[tid:%i] [sn:%lli] PC %#x\n", 1070 (*instIt)->threadNumber, 1071 (*instIt)->seqNum, 1072 (*instIt)->readPC()); 1073 1074 // Mark it as squashed. 1075 (*instIt)->setSquashed(); 1076 1077 // @todo: Formulate a consistent method for deleting 1078 // instructions from the instruction list 1079 // Remove the instruction from the list. 1080 removeList.push(instIt); 1081 } 1082} 1083 1084template <class Impl> 1085void 1086FullO3CPU<Impl>::cleanUpRemovedInsts() 1087{ 1088 while (!removeList.empty()) { 1089 DPRINTF(FullCPU, "FullCPU: Removing instruction, " 1090 "[tid:%i] [sn:%lli] PC %#x\n", 1091 (*removeList.front())->threadNumber, 1092 (*removeList.front())->seqNum, 1093 (*removeList.front())->readPC()); 1094 1095 instList.erase(removeList.front()); 1096 1097 removeList.pop(); 1098 } 1099 1100 removeInstsThisCycle = false; 1101} 1102/* 1103template <class Impl> 1104void 1105FullO3CPU<Impl>::removeAllInsts() 1106{ 1107 instList.clear(); 1108} 1109*/ 1110template <class Impl> 1111void 1112FullO3CPU<Impl>::dumpInsts() 1113{ 1114 int num = 0; 1115 1116 ListIt inst_list_it = instList.begin(); 1117 1118 cprintf("Dumping Instruction List\n"); 1119 1120 while (inst_list_it != instList.end()) { 1121 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 1122 "Squashed:%i\n\n", 1123 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 1124 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 1125 (*inst_list_it)->isSquashed()); 1126 inst_list_it++; 1127 ++num; 1128 } 1129} 1130/* 1131template <class Impl> 1132void 1133FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 1134{ 1135 iew.wakeDependents(inst); 1136} 1137*/ 1138template <class Impl> 1139void 1140FullO3CPU<Impl>::wakeCPU() 1141{ 1142 if (activityRec.active() || tickEvent.scheduled()) { 1143 DPRINTF(Activity, "CPU already running.\n"); 1144 return; 1145 } 1146 1147 DPRINTF(Activity, "Waking up CPU\n"); 1148 1149 idleCycles += (curTick - 1) - lastRunningCycle; 1150 1151 tickEvent.schedule(curTick); 1152} 1153 1154template <class Impl> 1155int 1156FullO3CPU<Impl>::getFreeTid() 1157{ 1158 for (int i=0; i < numThreads; i++) { 1159 if (!tids[i]) { 1160 tids[i] = true; 1161 return i; 1162 } 1163 } 1164 1165 return -1; 1166} 1167 1168template <class Impl> 1169void 1170FullO3CPU<Impl>::doContextSwitch() 1171{ 1172 if (contextSwitch) { 1173 1174 //ADD CODE TO DEACTIVE THREAD HERE (???) 1175 1176 for (int tid=0; tid < cpuWaitList.size(); tid++) { 1177 activateWhenReady(tid); 1178 } 1179 1180 if (cpuWaitList.size() == 0) 1181 contextSwitch = true; 1182 } 1183} 1184 1185template <class Impl> 1186void 1187FullO3CPU<Impl>::updateThreadPriority() 1188{ 1189 if (activeThreads.size() > 1) 1190 { 1191 //DEFAULT TO ROUND ROBIN SCHEME 1192 //e.g. Move highest priority to end of thread list 1193 list<unsigned>::iterator list_begin = activeThreads.begin(); 1194 list<unsigned>::iterator list_end = activeThreads.end(); 1195 1196 unsigned high_thread = *list_begin; 1197 1198 activeThreads.erase(list_begin); 1199 1200 activeThreads.push_back(high_thread); 1201 } 1202} 1203 1204// Forward declaration of FullO3CPU. 1205template class FullO3CPU<AlphaSimpleImpl>; 1206