cpu.cc revision 13582:989577bf6abc 
1/*
2 * Copyright (c) 2011-2012, 2014, 2016, 2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2011 Regents of the University of California
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 *          Korey Sewell
44 *          Rick Strong
45 */
46
47#include "cpu/o3/cpu.hh"
48
49#include "arch/generic/traits.hh"
50#include "arch/kernel_stats.hh"
51#include "config/the_isa.hh"
52#include "cpu/activity.hh"
53#include "cpu/checker/cpu.hh"
54#include "cpu/checker/thread_context.hh"
55#include "cpu/o3/isa_specific.hh"
56#include "cpu/o3/thread_context.hh"
57#include "cpu/quiesce_event.hh"
58#include "cpu/simple_thread.hh"
59#include "cpu/thread_context.hh"
60#include "debug/Activity.hh"
61#include "debug/Drain.hh"
62#include "debug/O3CPU.hh"
63#include "debug/Quiesce.hh"
64#include "enums/MemoryMode.hh"
65#include "sim/core.hh"
66#include "sim/full_system.hh"
67#include "sim/process.hh"
68#include "sim/stat_control.hh"
69#include "sim/system.hh"
70
71#if THE_ISA == ALPHA_ISA
72#include "arch/alpha/osfpal.hh"
73#include "debug/Activity.hh"
74
75#endif
76
77struct BaseCPUParams;
78
79using namespace TheISA;
80using namespace std;
81
82BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
83    : BaseCPU(params)
84{
85}
86
87void
88BaseO3CPU::regStats()
89{
90    BaseCPU::regStats();
91}
92
93template<class Impl>
94bool
95FullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt)
96{
97    DPRINTF(O3CPU, "Fetch unit received timing\n");
98    // We shouldn't ever get a cacheable block in Modified state
99    assert(pkt->req->isUncacheable() ||
100           !(pkt->cacheResponding() && !pkt->hasSharers()));
101    fetch->processCacheCompletion(pkt);
102
103    return true;
104}
105
106template<class Impl>
107void
108FullO3CPU<Impl>::IcachePort::recvReqRetry()
109{
110    fetch->recvReqRetry();
111}
112
113template <class Impl>
114bool
115FullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt)
116{
117    return lsq->recvTimingResp(pkt);
118}
119
120template <class Impl>
121void
122FullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
123{
124    for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
125        if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
126            cpu->wakeup(tid);
127        }
128    }
129    lsq->recvTimingSnoopReq(pkt);
130}
131
132template <class Impl>
133void
134FullO3CPU<Impl>::DcachePort::recvReqRetry()
135{
136    lsq->recvReqRetry();
137}
138
139template <class Impl>
140FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
141    : BaseO3CPU(params),
142      itb(params->itb),
143      dtb(params->dtb),
144      tickEvent([this]{ tick(); }, "FullO3CPU tick",
145                false, Event::CPU_Tick_Pri),
146#ifndef NDEBUG
147      instcount(0),
148#endif
149      removeInstsThisCycle(false),
150      fetch(this, params),
151      decode(this, params),
152      rename(this, params),
153      iew(this, params),
154      commit(this, params),
155
156      /* It is mandatory that all SMT threads use the same renaming mode as
157       * they are sharing registers and rename */
158      vecMode(initRenameMode<TheISA::ISA>::mode(params->isa[0])),
159      regFile(params->numPhysIntRegs,
160              params->numPhysFloatRegs,
161              params->numPhysVecRegs,
162              params->numPhysCCRegs,
163              vecMode),
164
165      freeList(name() + ".freelist", &regFile),
166
167      rob(this, params),
168
169      scoreboard(name() + ".scoreboard",
170                 regFile.totalNumPhysRegs()),
171
172      isa(numThreads, NULL),
173
174      icachePort(&fetch, this),
175      dcachePort(&iew.ldstQueue, this),
176
177      timeBuffer(params->backComSize, params->forwardComSize),
178      fetchQueue(params->backComSize, params->forwardComSize),
179      decodeQueue(params->backComSize, params->forwardComSize),
180      renameQueue(params->backComSize, params->forwardComSize),
181      iewQueue(params->backComSize, params->forwardComSize),
182      activityRec(name(), NumStages,
183                  params->backComSize + params->forwardComSize,
184                  params->activity),
185
186      globalSeqNum(1),
187      system(params->system),
188      lastRunningCycle(curCycle())
189{
190    if (!params->switched_out) {
191        _status = Running;
192    } else {
193        _status = SwitchedOut;
194    }
195
196    if (params->checker) {
197        BaseCPU *temp_checker = params->checker;
198        checker = dynamic_cast<Checker<Impl> *>(temp_checker);
199        checker->setIcachePort(&icachePort);
200        checker->setSystem(params->system);
201    } else {
202        checker = NULL;
203    }
204
205    if (!FullSystem) {
206        thread.resize(numThreads);
207        tids.resize(numThreads);
208    }
209
210    // The stages also need their CPU pointer setup.  However this
211    // must be done at the upper level CPU because they have pointers
212    // to the upper level CPU, and not this FullO3CPU.
213
214    // Set up Pointers to the activeThreads list for each stage
215    fetch.setActiveThreads(&activeThreads);
216    decode.setActiveThreads(&activeThreads);
217    rename.setActiveThreads(&activeThreads);
218    iew.setActiveThreads(&activeThreads);
219    commit.setActiveThreads(&activeThreads);
220
221    // Give each of the stages the time buffer they will use.
222    fetch.setTimeBuffer(&timeBuffer);
223    decode.setTimeBuffer(&timeBuffer);
224    rename.setTimeBuffer(&timeBuffer);
225    iew.setTimeBuffer(&timeBuffer);
226    commit.setTimeBuffer(&timeBuffer);
227
228    // Also setup each of the stages' queues.
229    fetch.setFetchQueue(&fetchQueue);
230    decode.setFetchQueue(&fetchQueue);
231    commit.setFetchQueue(&fetchQueue);
232    decode.setDecodeQueue(&decodeQueue);
233    rename.setDecodeQueue(&decodeQueue);
234    rename.setRenameQueue(&renameQueue);
235    iew.setRenameQueue(&renameQueue);
236    iew.setIEWQueue(&iewQueue);
237    commit.setIEWQueue(&iewQueue);
238    commit.setRenameQueue(&renameQueue);
239
240    commit.setIEWStage(&iew);
241    rename.setIEWStage(&iew);
242    rename.setCommitStage(&commit);
243
244    ThreadID active_threads;
245    if (FullSystem) {
246        active_threads = 1;
247    } else {
248        active_threads = params->workload.size();
249
250        if (active_threads > Impl::MaxThreads) {
251            panic("Workload Size too large. Increase the 'MaxThreads' "
252                  "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) "
253                  "or edit your workload size.");
254        }
255    }
256
257    //Make Sure That this a Valid Architeture
258    assert(params->numPhysIntRegs   >= numThreads * TheISA::NumIntRegs);
259    assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
260    assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs);
261    assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs);
262
263    rename.setScoreboard(&scoreboard);
264    iew.setScoreboard(&scoreboard);
265
266    // Setup the rename map for whichever stages need it.
267    for (ThreadID tid = 0; tid < numThreads; tid++) {
268        isa[tid] = params->isa[tid];
269        assert(initRenameMode<TheISA::ISA>::equals(isa[tid], isa[0]));
270
271        // Only Alpha has an FP zero register, so for other ISAs we
272        // use an invalid FP register index to avoid special treatment
273        // of any valid FP reg.
274        RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
275        RegIndex fpZeroReg =
276            (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
277
278        commitRenameMap[tid].init(&regFile, TheISA::ZeroReg, fpZeroReg,
279                                  &freeList,
280                                  vecMode);
281
282        renameMap[tid].init(&regFile, TheISA::ZeroReg, fpZeroReg,
283                            &freeList, vecMode);
284    }
285
286    // Initialize rename map to assign physical registers to the
287    // architectural registers for active threads only.
288    for (ThreadID tid = 0; tid < active_threads; tid++) {
289        for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
290            // Note that we can't use the rename() method because we don't
291            // want special treatment for the zero register at this point
292            PhysRegIdPtr phys_reg = freeList.getIntReg();
293            renameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
294            commitRenameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
295        }
296
297        for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
298            PhysRegIdPtr phys_reg = freeList.getFloatReg();
299            renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg);
300            commitRenameMap[tid].setEntry(
301                    RegId(FloatRegClass, ridx), phys_reg);
302        }
303
304        /* Here we need two 'interfaces' the 'whole register' and the
305         * 'register element'. At any point only one of them will be
306         * active. */
307        if (vecMode == Enums::Full) {
308            /* Initialize the full-vector interface */
309            for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
310                RegId rid = RegId(VecRegClass, ridx);
311                PhysRegIdPtr phys_reg = freeList.getVecReg();
312                renameMap[tid].setEntry(rid, phys_reg);
313                commitRenameMap[tid].setEntry(rid, phys_reg);
314            }
315        } else {
316            /* Initialize the vector-element interface */
317            for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) {
318                for (ElemIndex ldx = 0; ldx < TheISA::NumVecElemPerVecReg;
319                        ++ldx) {
320                    RegId lrid = RegId(VecElemClass, ridx, ldx);
321                    PhysRegIdPtr phys_elem = freeList.getVecElem();
322                    renameMap[tid].setEntry(lrid, phys_elem);
323                    commitRenameMap[tid].setEntry(lrid, phys_elem);
324                }
325            }
326        }
327
328        for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) {
329            PhysRegIdPtr phys_reg = freeList.getCCReg();
330            renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
331            commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
332        }
333    }
334
335    rename.setRenameMap(renameMap);
336    commit.setRenameMap(commitRenameMap);
337    rename.setFreeList(&freeList);
338
339    // Setup the ROB for whichever stages need it.
340    commit.setROB(&rob);
341
342    lastActivatedCycle = 0;
343#if 0
344    // Give renameMap & rename stage access to the freeList;
345    for (ThreadID tid = 0; tid < numThreads; tid++)
346        globalSeqNum[tid] = 1;
347#endif
348
349    DPRINTF(O3CPU, "Creating O3CPU object.\n");
350
351    // Setup any thread state.
352    this->thread.resize(this->numThreads);
353
354    for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
355        if (FullSystem) {
356            // SMT is not supported in FS mode yet.
357            assert(this->numThreads == 1);
358            this->thread[tid] = new Thread(this, 0, NULL);
359        } else {
360            if (tid < params->workload.size()) {
361                DPRINTF(O3CPU, "Workload[%i] process is %#x",
362                        tid, this->thread[tid]);
363                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
364                        (typename Impl::O3CPU *)(this),
365                        tid, params->workload[tid]);
366
367                //usedTids[tid] = true;
368                //threadMap[tid] = tid;
369            } else {
370                //Allocate Empty thread so M5 can use later
371                //when scheduling threads to CPU
372                Process* dummy_proc = NULL;
373
374                this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
375                        (typename Impl::O3CPU *)(this),
376                        tid, dummy_proc);
377                //usedTids[tid] = false;
378            }
379        }
380
381        ThreadContext *tc;
382
383        // Setup the TC that will serve as the interface to the threads/CPU.
384        O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>;
385
386        tc = o3_tc;
387
388        // If we're using a checker, then the TC should be the
389        // CheckerThreadContext.
390        if (params->checker) {
391            tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
392                o3_tc, this->checker);
393        }
394
395        o3_tc->cpu = (typename Impl::O3CPU *)(this);
396        assert(o3_tc->cpu);
397        o3_tc->thread = this->thread[tid];
398
399        // Setup quiesce event.
400        this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
401
402        // Give the thread the TC.
403        this->thread[tid]->tc = tc;
404
405        // Add the TC to the CPU's list of TC's.
406        this->threadContexts.push_back(tc);
407    }
408
409    // FullO3CPU always requires an interrupt controller.
410    if (!params->switched_out && interrupts.empty()) {
411        fatal("FullO3CPU %s has no interrupt controller.\n"
412              "Ensure createInterruptController() is called.\n", name());
413    }
414
415    for (ThreadID tid = 0; tid < this->numThreads; tid++)
416        this->thread[tid]->setFuncExeInst(0);
417}
418
419template <class Impl>
420FullO3CPU<Impl>::~FullO3CPU()
421{
422}
423
424template <class Impl>
425void
426FullO3CPU<Impl>::regProbePoints()
427{
428    BaseCPU::regProbePoints();
429
430    ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete");
431    ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete");
432
433    fetch.regProbePoints();
434    rename.regProbePoints();
435    iew.regProbePoints();
436    commit.regProbePoints();
437}
438
439template <class Impl>
440void
441FullO3CPU<Impl>::regStats()
442{
443    BaseO3CPU::regStats();
444
445    // Register any of the O3CPU's stats here.
446    timesIdled
447        .name(name() + ".timesIdled")
448        .desc("Number of times that the entire CPU went into an idle state and"
449              " unscheduled itself")
450        .prereq(timesIdled);
451
452    idleCycles
453        .name(name() + ".idleCycles")
454        .desc("Total number of cycles that the CPU has spent unscheduled due "
455              "to idling")
456        .prereq(idleCycles);
457
458    quiesceCycles
459        .name(name() + ".quiesceCycles")
460        .desc("Total number of cycles that CPU has spent quiesced or waiting "
461              "for an interrupt")
462        .prereq(quiesceCycles);
463
464    // Number of Instructions simulated
465    // --------------------------------
466    // Should probably be in Base CPU but need templated
467    // MaxThreads so put in here instead
468    committedInsts
469        .init(numThreads)
470        .name(name() + ".committedInsts")
471        .desc("Number of Instructions Simulated")
472        .flags(Stats::total);
473
474    committedOps
475        .init(numThreads)
476        .name(name() + ".committedOps")
477        .desc("Number of Ops (including micro ops) Simulated")
478        .flags(Stats::total);
479
480    cpi
481        .name(name() + ".cpi")
482        .desc("CPI: Cycles Per Instruction")
483        .precision(6);
484    cpi = numCycles / committedInsts;
485
486    totalCpi
487        .name(name() + ".cpi_total")
488        .desc("CPI: Total CPI of All Threads")
489        .precision(6);
490    totalCpi = numCycles / sum(committedInsts);
491
492    ipc
493        .name(name() + ".ipc")
494        .desc("IPC: Instructions Per Cycle")
495        .precision(6);
496    ipc =  committedInsts / numCycles;
497
498    totalIpc
499        .name(name() + ".ipc_total")
500        .desc("IPC: Total IPC of All Threads")
501        .precision(6);
502    totalIpc =  sum(committedInsts) / numCycles;
503
504    this->fetch.regStats();
505    this->decode.regStats();
506    this->rename.regStats();
507    this->iew.regStats();
508    this->commit.regStats();
509    this->rob.regStats();
510
511    intRegfileReads
512        .name(name() + ".int_regfile_reads")
513        .desc("number of integer regfile reads")
514        .prereq(intRegfileReads);
515
516    intRegfileWrites
517        .name(name() + ".int_regfile_writes")
518        .desc("number of integer regfile writes")
519        .prereq(intRegfileWrites);
520
521    fpRegfileReads
522        .name(name() + ".fp_regfile_reads")
523        .desc("number of floating regfile reads")
524        .prereq(fpRegfileReads);
525
526    fpRegfileWrites
527        .name(name() + ".fp_regfile_writes")
528        .desc("number of floating regfile writes")
529        .prereq(fpRegfileWrites);
530
531    vecRegfileReads
532        .name(name() + ".vec_regfile_reads")
533        .desc("number of vector regfile reads")
534        .prereq(vecRegfileReads);
535
536    vecRegfileWrites
537        .name(name() + ".vec_regfile_writes")
538        .desc("number of vector regfile writes")
539        .prereq(vecRegfileWrites);
540
541    ccRegfileReads
542        .name(name() + ".cc_regfile_reads")
543        .desc("number of cc regfile reads")
544        .prereq(ccRegfileReads);
545
546    ccRegfileWrites
547        .name(name() + ".cc_regfile_writes")
548        .desc("number of cc regfile writes")
549        .prereq(ccRegfileWrites);
550
551    miscRegfileReads
552        .name(name() + ".misc_regfile_reads")
553        .desc("number of misc regfile reads")
554        .prereq(miscRegfileReads);
555
556    miscRegfileWrites
557        .name(name() + ".misc_regfile_writes")
558        .desc("number of misc regfile writes")
559        .prereq(miscRegfileWrites);
560}
561
562template <class Impl>
563void
564FullO3CPU<Impl>::tick()
565{
566    DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
567    assert(!switchedOut());
568    assert(drainState() != DrainState::Drained);
569
570    ++numCycles;
571    updateCycleCounters(BaseCPU::CPU_STATE_ON);
572
573//    activity = false;
574
575    //Tick each of the stages
576    fetch.tick();
577
578    decode.tick();
579
580    rename.tick();
581
582    iew.tick();
583
584    commit.tick();
585
586    // Now advance the time buffers
587    timeBuffer.advance();
588
589    fetchQueue.advance();
590    decodeQueue.advance();
591    renameQueue.advance();
592    iewQueue.advance();
593
594    activityRec.advance();
595
596    if (removeInstsThisCycle) {
597        cleanUpRemovedInsts();
598    }
599
600    if (!tickEvent.scheduled()) {
601        if (_status == SwitchedOut) {
602            DPRINTF(O3CPU, "Switched out!\n");
603            // increment stat
604            lastRunningCycle = curCycle();
605        } else if (!activityRec.active() || _status == Idle) {
606            DPRINTF(O3CPU, "Idle!\n");
607            lastRunningCycle = curCycle();
608            timesIdled++;
609        } else {
610            schedule(tickEvent, clockEdge(Cycles(1)));
611            DPRINTF(O3CPU, "Scheduling next tick!\n");
612        }
613    }
614
615    if (!FullSystem)
616        updateThreadPriority();
617
618    tryDrain();
619}
620
621template <class Impl>
622void
623FullO3CPU<Impl>::init()
624{
625    BaseCPU::init();
626
627    for (ThreadID tid = 0; tid < numThreads; ++tid) {
628        // Set noSquashFromTC so that the CPU doesn't squash when initially
629        // setting up registers.
630        thread[tid]->noSquashFromTC = true;
631        // Initialise the ThreadContext's memory proxies
632        thread[tid]->initMemProxies(thread[tid]->getTC());
633    }
634
635    if (FullSystem && !params()->switched_out) {
636        for (ThreadID tid = 0; tid < numThreads; tid++) {
637            ThreadContext *src_tc = threadContexts[tid];
638            TheISA::initCPU(src_tc, src_tc->contextId());
639        }
640    }
641
642    // Clear noSquashFromTC.
643    for (int tid = 0; tid < numThreads; ++tid)
644        thread[tid]->noSquashFromTC = false;
645
646    commit.setThreads(thread);
647}
648
649template <class Impl>
650void
651FullO3CPU<Impl>::startup()
652{
653    BaseCPU::startup();
654    for (int tid = 0; tid < numThreads; ++tid)
655        isa[tid]->startup(threadContexts[tid]);
656
657    fetch.startupStage();
658    decode.startupStage();
659    iew.startupStage();
660    rename.startupStage();
661    commit.startupStage();
662}
663
664template <class Impl>
665void
666FullO3CPU<Impl>::activateThread(ThreadID tid)
667{
668    list<ThreadID>::iterator isActive =
669        std::find(activeThreads.begin(), activeThreads.end(), tid);
670
671    DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
672    assert(!switchedOut());
673
674    if (isActive == activeThreads.end()) {
675        DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
676                tid);
677
678        activeThreads.push_back(tid);
679    }
680}
681
682template <class Impl>
683void
684FullO3CPU<Impl>::deactivateThread(ThreadID tid)
685{
686    //Remove From Active List, if Active
687    list<ThreadID>::iterator thread_it =
688        std::find(activeThreads.begin(), activeThreads.end(), tid);
689
690    DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
691    assert(!switchedOut());
692
693    if (thread_it != activeThreads.end()) {
694        DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
695                tid);
696        activeThreads.erase(thread_it);
697    }
698
699    fetch.deactivateThread(tid);
700    commit.deactivateThread(tid);
701}
702
703template <class Impl>
704Counter
705FullO3CPU<Impl>::totalInsts() const
706{
707    Counter total(0);
708
709    ThreadID size = thread.size();
710    for (ThreadID i = 0; i < size; i++)
711        total += thread[i]->numInst;
712
713    return total;
714}
715
716template <class Impl>
717Counter
718FullO3CPU<Impl>::totalOps() const
719{
720    Counter total(0);
721
722    ThreadID size = thread.size();
723    for (ThreadID i = 0; i < size; i++)
724        total += thread[i]->numOp;
725
726    return total;
727}
728
729template <class Impl>
730void
731FullO3CPU<Impl>::activateContext(ThreadID tid)
732{
733    assert(!switchedOut());
734
735    // Needs to set each stage to running as well.
736    activateThread(tid);
737
738    // We don't want to wake the CPU if it is drained. In that case,
739    // we just want to flag the thread as active and schedule the tick
740    // event from drainResume() instead.
741    if (drainState() == DrainState::Drained)
742        return;
743
744    // If we are time 0 or if the last activation time is in the past,
745    // schedule the next tick and wake up the fetch unit
746    if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) {
747        scheduleTickEvent(Cycles(0));
748
749        // Be sure to signal that there's some activity so the CPU doesn't
750        // deschedule itself.
751        activityRec.activity();
752        fetch.wakeFromQuiesce();
753
754        Cycles cycles(curCycle() - lastRunningCycle);
755        // @todo: This is an oddity that is only here to match the stats
756        if (cycles != 0)
757            --cycles;
758        quiesceCycles += cycles;
759
760        lastActivatedCycle = curTick();
761
762        _status = Running;
763
764        BaseCPU::activateContext(tid);
765    }
766}
767
768template <class Impl>
769void
770FullO3CPU<Impl>::suspendContext(ThreadID tid)
771{
772    DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
773    assert(!switchedOut());
774
775    deactivateThread(tid);
776
777    // If this was the last thread then unschedule the tick event.
778    if (activeThreads.size() == 0) {
779        unscheduleTickEvent();
780        lastRunningCycle = curCycle();
781        _status = Idle;
782    }
783
784    DPRINTF(Quiesce, "Suspending Context\n");
785
786    BaseCPU::suspendContext(tid);
787}
788
789template <class Impl>
790void
791FullO3CPU<Impl>::haltContext(ThreadID tid)
792{
793    //For now, this is the same as deallocate
794    DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
795    assert(!switchedOut());
796
797    deactivateThread(tid);
798    removeThread(tid);
799
800    updateCycleCounters(BaseCPU::CPU_STATE_SLEEP);
801}
802
803template <class Impl>
804void
805FullO3CPU<Impl>::insertThread(ThreadID tid)
806{
807    DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
808    // Will change now that the PC and thread state is internal to the CPU
809    // and not in the ThreadContext.
810    ThreadContext *src_tc;
811    if (FullSystem)
812        src_tc = system->threadContexts[tid];
813    else
814        src_tc = tcBase(tid);
815
816    //Bind Int Regs to Rename Map
817
818    for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs;
819         reg_id.index()++) {
820        PhysRegIdPtr phys_reg = freeList.getIntReg();
821        renameMap[tid].setEntry(reg_id, phys_reg);
822        scoreboard.setReg(phys_reg);
823    }
824
825    //Bind Float Regs to Rename Map
826    for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;
827         reg_id.index()++) {
828        PhysRegIdPtr phys_reg = freeList.getFloatReg();
829        renameMap[tid].setEntry(reg_id, phys_reg);
830        scoreboard.setReg(phys_reg);
831    }
832
833    //Bind condition-code Regs to Rename Map
834    for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
835         reg_id.index()++) {
836        PhysRegIdPtr phys_reg = freeList.getCCReg();
837        renameMap[tid].setEntry(reg_id, phys_reg);
838        scoreboard.setReg(phys_reg);
839    }
840
841    //Copy Thread Data Into RegFile
842    //this->copyFromTC(tid);
843
844    //Set PC/NPC/NNPC
845    pcState(src_tc->pcState(), tid);
846
847    src_tc->setStatus(ThreadContext::Active);
848
849    activateContext(tid);
850
851    //Reset ROB/IQ/LSQ Entries
852    commit.rob->resetEntries();
853    iew.resetEntries();
854}
855
856template <class Impl>
857void
858FullO3CPU<Impl>::removeThread(ThreadID tid)
859{
860    DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
861
862    // Copy Thread Data From RegFile
863    // If thread is suspended, it might be re-allocated
864    // this->copyToTC(tid);
865
866
867    // @todo: 2-27-2008: Fix how we free up rename mappings
868    // here to alleviate the case for double-freeing registers
869    // in SMT workloads.
870
871    // Unbind Int Regs from Rename Map
872    for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs;
873         reg_id.index()++) {
874        PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
875        scoreboard.unsetReg(phys_reg);
876        freeList.addReg(phys_reg);
877    }
878
879    // Unbind Float Regs from Rename Map
880    for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;
881         reg_id.index()++) {
882        PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
883        scoreboard.unsetReg(phys_reg);
884        freeList.addReg(phys_reg);
885    }
886
887    // Unbind condition-code Regs from Rename Map
888    for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs;
889         reg_id.index()++) {
890        PhysRegIdPtr phys_reg = renameMap[tid].lookup(reg_id);
891        scoreboard.unsetReg(phys_reg);
892        freeList.addReg(phys_reg);
893    }
894
895    // Squash Throughout Pipeline
896    DynInstPtr inst = commit.rob->readHeadInst(tid);
897    InstSeqNum squash_seq_num = inst->seqNum;
898    fetch.squash(0, squash_seq_num, inst, tid);
899    decode.squash(tid);
900    rename.squash(squash_seq_num, tid);
901    iew.squash(tid);
902    iew.ldstQueue.squash(squash_seq_num, tid);
903    commit.rob->squash(squash_seq_num, tid);
904
905
906    assert(iew.instQueue.getCount(tid) == 0);
907    assert(iew.ldstQueue.getCount(tid) == 0);
908
909    // Reset ROB/IQ/LSQ Entries
910
911    // Commented out for now.  This should be possible to do by
912    // telling all the pipeline stages to drain first, and then
913    // checking until the drain completes.  Once the pipeline is
914    // drained, call resetEntries(). - 10-09-06 ktlim
915/*
916    if (activeThreads.size() >= 1) {
917        commit.rob->resetEntries();
918        iew.resetEntries();
919    }
920*/
921}
922
923template <class Impl>
924Fault
925FullO3CPU<Impl>::hwrei(ThreadID tid)
926{
927#if THE_ISA == ALPHA_ISA
928    // Need to clear the lock flag upon returning from an interrupt.
929    this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
930
931    this->thread[tid]->kernelStats->hwrei();
932
933    // FIXME: XXX check for interrupts? XXX
934#endif
935    return NoFault;
936}
937
938template <class Impl>
939bool
940FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
941{
942#if THE_ISA == ALPHA_ISA
943    if (this->thread[tid]->kernelStats)
944        this->thread[tid]->kernelStats->callpal(palFunc,
945                                                this->threadContexts[tid]);
946
947    switch (palFunc) {
948      case PAL::halt:
949        halt();
950        if (--System::numSystemsRunning == 0)
951            exitSimLoop("all cpus halted");
952        break;
953
954      case PAL::bpt:
955      case PAL::bugchk:
956        if (this->system->breakpoint())
957            return false;
958        break;
959    }
960#endif
961    return true;
962}
963
964template <class Impl>
965Fault
966FullO3CPU<Impl>::getInterrupts()
967{
968    // Check if there are any outstanding interrupts
969    return this->interrupts[0]->getInterrupt(this->threadContexts[0]);
970}
971
972template <class Impl>
973void
974FullO3CPU<Impl>::processInterrupts(const Fault &interrupt)
975{
976    // Check for interrupts here.  For now can copy the code that
977    // exists within isa_fullsys_traits.hh.  Also assume that thread 0
978    // is the one that handles the interrupts.
979    // @todo: Possibly consolidate the interrupt checking code.
980    // @todo: Allow other threads to handle interrupts.
981
982    assert(interrupt != NoFault);
983    this->interrupts[0]->updateIntrInfo(this->threadContexts[0]);
984
985    DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
986    this->trap(interrupt, 0, nullptr);
987}
988
989template <class Impl>
990void
991FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
992                      const StaticInstPtr &inst)
993{
994    // Pass the thread's TC into the invoke method.
995    fault->invoke(this->threadContexts[tid], inst);
996}
997
998template <class Impl>
999void
1000FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid, Fault *fault)
1001{
1002    DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
1003
1004    DPRINTF(Activity,"Activity: syscall() called.\n");
1005
1006    // Temporarily increase this by one to account for the syscall
1007    // instruction.
1008    ++(this->thread[tid]->funcExeInst);
1009
1010    // Execute the actual syscall.
1011    this->thread[tid]->syscall(callnum, fault);
1012
1013    // Decrease funcExeInst by one as the normal commit will handle
1014    // incrementing it.
1015    --(this->thread[tid]->funcExeInst);
1016}
1017
1018template <class Impl>
1019void
1020FullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const
1021{
1022    thread[tid]->serialize(cp);
1023}
1024
1025template <class Impl>
1026void
1027FullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid)
1028{
1029    thread[tid]->unserialize(cp);
1030}
1031
1032template <class Impl>
1033DrainState
1034FullO3CPU<Impl>::drain()
1035{
1036    // Deschedule any power gating event (if any)
1037    deschedulePowerGatingEvent();
1038
1039    // If the CPU isn't doing anything, then return immediately.
1040    if (switchedOut())
1041        return DrainState::Drained;
1042
1043    DPRINTF(Drain, "Draining...\n");
1044
1045    // We only need to signal a drain to the commit stage as this
1046    // initiates squashing controls the draining. Once the commit
1047    // stage commits an instruction where it is safe to stop, it'll
1048    // squash the rest of the instructions in the pipeline and force
1049    // the fetch stage to stall. The pipeline will be drained once all
1050    // in-flight instructions have retired.
1051    commit.drain();
1052
1053    // Wake the CPU and record activity so everything can drain out if
1054    // the CPU was not able to immediately drain.
1055    if (!isDrained())  {
1056        // If a thread is suspended, wake it up so it can be drained
1057        for (auto t : threadContexts) {
1058            if (t->status() == ThreadContext::Suspended){
1059                DPRINTF(Drain, "Currently suspended so activate %i \n",
1060                        t->threadId());
1061                t->activate();
1062                // As the thread is now active, change the power state as well
1063                activateContext(t->threadId());
1064            }
1065        }
1066
1067        wakeCPU();
1068        activityRec.activity();
1069
1070        DPRINTF(Drain, "CPU not drained\n");
1071
1072        return DrainState::Draining;
1073    } else {
1074        DPRINTF(Drain, "CPU is already drained\n");
1075        if (tickEvent.scheduled())
1076            deschedule(tickEvent);
1077
1078        // Flush out any old data from the time buffers.  In
1079        // particular, there might be some data in flight from the
1080        // fetch stage that isn't visible in any of the CPU buffers we
1081        // test in isDrained().
1082        for (int i = 0; i < timeBuffer.getSize(); ++i) {
1083            timeBuffer.advance();
1084            fetchQueue.advance();
1085            decodeQueue.advance();
1086            renameQueue.advance();
1087            iewQueue.advance();
1088        }
1089
1090        drainSanityCheck();
1091        return DrainState::Drained;
1092    }
1093}
1094
1095template <class Impl>
1096bool
1097FullO3CPU<Impl>::tryDrain()
1098{
1099    if (drainState() != DrainState::Draining || !isDrained())
1100        return false;
1101
1102    if (tickEvent.scheduled())
1103        deschedule(tickEvent);
1104
1105    DPRINTF(Drain, "CPU done draining, processing drain event\n");
1106    signalDrainDone();
1107
1108    return true;
1109}
1110
1111template <class Impl>
1112void
1113FullO3CPU<Impl>::drainSanityCheck() const
1114{
1115    assert(isDrained());
1116    fetch.drainSanityCheck();
1117    decode.drainSanityCheck();
1118    rename.drainSanityCheck();
1119    iew.drainSanityCheck();
1120    commit.drainSanityCheck();
1121}
1122
1123template <class Impl>
1124bool
1125FullO3CPU<Impl>::isDrained() const
1126{
1127    bool drained(true);
1128
1129    if (!instList.empty() || !removeList.empty()) {
1130        DPRINTF(Drain, "Main CPU structures not drained.\n");
1131        drained = false;
1132    }
1133
1134    if (!fetch.isDrained()) {
1135        DPRINTF(Drain, "Fetch not drained.\n");
1136        drained = false;
1137    }
1138
1139    if (!decode.isDrained()) {
1140        DPRINTF(Drain, "Decode not drained.\n");
1141        drained = false;
1142    }
1143
1144    if (!rename.isDrained()) {
1145        DPRINTF(Drain, "Rename not drained.\n");
1146        drained = false;
1147    }
1148
1149    if (!iew.isDrained()) {
1150        DPRINTF(Drain, "IEW not drained.\n");
1151        drained = false;
1152    }
1153
1154    if (!commit.isDrained()) {
1155        DPRINTF(Drain, "Commit not drained.\n");
1156        drained = false;
1157    }
1158
1159    return drained;
1160}
1161
1162template <class Impl>
1163void
1164FullO3CPU<Impl>::commitDrained(ThreadID tid)
1165{
1166    fetch.drainStall(tid);
1167}
1168
1169template <class Impl>
1170void
1171FullO3CPU<Impl>::drainResume()
1172{
1173    if (switchedOut())
1174        return;
1175
1176    DPRINTF(Drain, "Resuming...\n");
1177    verifyMemoryMode();
1178
1179    fetch.drainResume();
1180    commit.drainResume();
1181
1182    _status = Idle;
1183    for (ThreadID i = 0; i < thread.size(); i++) {
1184        if (thread[i]->status() == ThreadContext::Active) {
1185            DPRINTF(Drain, "Activating thread: %i\n", i);
1186            activateThread(i);
1187            _status = Running;
1188        }
1189    }
1190
1191    assert(!tickEvent.scheduled());
1192    if (_status == Running)
1193        schedule(tickEvent, nextCycle());
1194
1195    // Reschedule any power gating event (if any)
1196    schedulePowerGatingEvent();
1197}
1198
1199template <class Impl>
1200void
1201FullO3CPU<Impl>::switchOut()
1202{
1203    DPRINTF(O3CPU, "Switching out\n");
1204    BaseCPU::switchOut();
1205
1206    activityRec.reset();
1207
1208    _status = SwitchedOut;
1209
1210    if (checker)
1211        checker->switchOut();
1212}
1213
1214template <class Impl>
1215void
1216FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
1217{
1218    BaseCPU::takeOverFrom(oldCPU);
1219
1220    fetch.takeOverFrom();
1221    decode.takeOverFrom();
1222    rename.takeOverFrom();
1223    iew.takeOverFrom();
1224    commit.takeOverFrom();
1225
1226    assert(!tickEvent.scheduled());
1227
1228    FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU);
1229    if (oldO3CPU)
1230        globalSeqNum = oldO3CPU->globalSeqNum;
1231
1232    lastRunningCycle = curCycle();
1233    _status = Idle;
1234}
1235
1236template <class Impl>
1237void
1238FullO3CPU<Impl>::verifyMemoryMode() const
1239{
1240    if (!system->isTimingMode()) {
1241        fatal("The O3 CPU requires the memory system to be in "
1242              "'timing' mode.\n");
1243    }
1244}
1245
1246template <class Impl>
1247RegVal
1248FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1249{
1250    return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1251}
1252
1253template <class Impl>
1254RegVal
1255FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1256{
1257    miscRegfileReads++;
1258    return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1259}
1260
1261template <class Impl>
1262void
1263FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
1264{
1265    this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1266}
1267
1268template <class Impl>
1269void
1270FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
1271{
1272    miscRegfileWrites++;
1273    this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1274}
1275
1276template <class Impl>
1277RegVal
1278FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg)
1279{
1280    intRegfileReads++;
1281    return regFile.readIntReg(phys_reg);
1282}
1283
1284template <class Impl>
1285RegVal
1286FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg)
1287{
1288    fpRegfileReads++;
1289    return regFile.readFloatRegBits(phys_reg);
1290}
1291
1292template <class Impl>
1293auto
1294FullO3CPU<Impl>::readVecReg(PhysRegIdPtr phys_reg) const
1295        -> const VecRegContainer&
1296{
1297    vecRegfileReads++;
1298    return regFile.readVecReg(phys_reg);
1299}
1300
1301template <class Impl>
1302auto
1303FullO3CPU<Impl>::getWritableVecReg(PhysRegIdPtr phys_reg)
1304        -> VecRegContainer&
1305{
1306    vecRegfileWrites++;
1307    return regFile.getWritableVecReg(phys_reg);
1308}
1309
1310template <class Impl>
1311auto
1312FullO3CPU<Impl>::readVecElem(PhysRegIdPtr phys_reg) const -> const VecElem&
1313{
1314    vecRegfileReads++;
1315    return regFile.readVecElem(phys_reg);
1316}
1317
1318template <class Impl>
1319CCReg
1320FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
1321{
1322    ccRegfileReads++;
1323    return regFile.readCCReg(phys_reg);
1324}
1325
1326template <class Impl>
1327void
1328FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, RegVal val)
1329{
1330    intRegfileWrites++;
1331    regFile.setIntReg(phys_reg, val);
1332}
1333
1334template <class Impl>
1335void
1336FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, RegVal val)
1337{
1338    fpRegfileWrites++;
1339    regFile.setFloatRegBits(phys_reg, val);
1340}
1341
1342template <class Impl>
1343void
1344FullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
1345{
1346    vecRegfileWrites++;
1347    regFile.setVecReg(phys_reg, val);
1348}
1349
1350template <class Impl>
1351void
1352FullO3CPU<Impl>::setVecElem(PhysRegIdPtr phys_reg, const VecElem& val)
1353{
1354    vecRegfileWrites++;
1355    regFile.setVecElem(phys_reg, val);
1356}
1357
1358template <class Impl>
1359void
1360FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
1361{
1362    ccRegfileWrites++;
1363    regFile.setCCReg(phys_reg, val);
1364}
1365
1366template <class Impl>
1367RegVal
1368FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1369{
1370    intRegfileReads++;
1371    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1372            RegId(IntRegClass, reg_idx));
1373
1374    return regFile.readIntReg(phys_reg);
1375}
1376
1377template <class Impl>
1378RegVal
1379FullO3CPU<Impl>::readArchFloatRegBits(int reg_idx, ThreadID tid)
1380{
1381    fpRegfileReads++;
1382    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1383        RegId(FloatRegClass, reg_idx));
1384
1385    return regFile.readFloatRegBits(phys_reg);
1386}
1387
1388template <class Impl>
1389auto
1390FullO3CPU<Impl>::readArchVecReg(int reg_idx, ThreadID tid) const
1391        -> const VecRegContainer&
1392{
1393    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1394                RegId(VecRegClass, reg_idx));
1395    return readVecReg(phys_reg);
1396}
1397
1398template <class Impl>
1399auto
1400FullO3CPU<Impl>::getWritableArchVecReg(int reg_idx, ThreadID tid)
1401        -> VecRegContainer&
1402{
1403    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1404                RegId(VecRegClass, reg_idx));
1405    return getWritableVecReg(phys_reg);
1406}
1407
1408template <class Impl>
1409auto
1410FullO3CPU<Impl>::readArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
1411                                 ThreadID tid) const -> const VecElem&
1412{
1413    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1414                                RegId(VecRegClass, reg_idx, ldx));
1415    return readVecElem(phys_reg);
1416}
1417
1418template <class Impl>
1419CCReg
1420FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1421{
1422    ccRegfileReads++;
1423    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1424        RegId(CCRegClass, reg_idx));
1425
1426    return regFile.readCCReg(phys_reg);
1427}
1428
1429template <class Impl>
1430void
1431FullO3CPU<Impl>::setArchIntReg(int reg_idx, RegVal val, ThreadID tid)
1432{
1433    intRegfileWrites++;
1434    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1435            RegId(IntRegClass, reg_idx));
1436
1437    regFile.setIntReg(phys_reg, val);
1438}
1439
1440template <class Impl>
1441void
1442FullO3CPU<Impl>::setArchFloatRegBits(int reg_idx, RegVal val, ThreadID tid)
1443{
1444    fpRegfileWrites++;
1445    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1446            RegId(FloatRegClass, reg_idx));
1447
1448    regFile.setFloatRegBits(phys_reg, val);
1449}
1450
1451template <class Impl>
1452void
1453FullO3CPU<Impl>::setArchVecReg(int reg_idx, const VecRegContainer& val,
1454                               ThreadID tid)
1455{
1456    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1457                RegId(VecRegClass, reg_idx));
1458    setVecReg(phys_reg, val);
1459}
1460
1461template <class Impl>
1462void
1463FullO3CPU<Impl>::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
1464                                const VecElem& val, ThreadID tid)
1465{
1466    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1467                RegId(VecElemClass, reg_idx, ldx));
1468    setVecElem(phys_reg, val);
1469}
1470
1471template <class Impl>
1472void
1473FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
1474{
1475    ccRegfileWrites++;
1476    PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1477            RegId(CCRegClass, reg_idx));
1478
1479    regFile.setCCReg(phys_reg, val);
1480}
1481
1482template <class Impl>
1483TheISA::PCState
1484FullO3CPU<Impl>::pcState(ThreadID tid)
1485{
1486    return commit.pcState(tid);
1487}
1488
1489template <class Impl>
1490void
1491FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1492{
1493    commit.pcState(val, tid);
1494}
1495
1496template <class Impl>
1497Addr
1498FullO3CPU<Impl>::instAddr(ThreadID tid)
1499{
1500    return commit.instAddr(tid);
1501}
1502
1503template <class Impl>
1504Addr
1505FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1506{
1507    return commit.nextInstAddr(tid);
1508}
1509
1510template <class Impl>
1511MicroPC
1512FullO3CPU<Impl>::microPC(ThreadID tid)
1513{
1514    return commit.microPC(tid);
1515}
1516
1517template <class Impl>
1518void
1519FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1520{
1521    this->thread[tid]->noSquashFromTC = true;
1522    this->commit.generateTCEvent(tid);
1523}
1524
1525template <class Impl>
1526typename FullO3CPU<Impl>::ListIt
1527FullO3CPU<Impl>::addInst(const DynInstPtr &inst)
1528{
1529    instList.push_back(inst);
1530
1531    return --(instList.end());
1532}
1533
1534template <class Impl>
1535void
1536FullO3CPU<Impl>::instDone(ThreadID tid, const DynInstPtr &inst)
1537{
1538    // Keep an instruction count.
1539    if (!inst->isMicroop() || inst->isLastMicroop()) {
1540        thread[tid]->numInst++;
1541        thread[tid]->numInsts++;
1542        committedInsts[tid]++;
1543        system->totalNumInsts++;
1544
1545        // Check for instruction-count-based events.
1546        comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1547        system->instEventQueue.serviceEvents(system->totalNumInsts);
1548    }
1549    thread[tid]->numOp++;
1550    thread[tid]->numOps++;
1551    committedOps[tid]++;
1552
1553    probeInstCommit(inst->staticInst);
1554}
1555
1556template <class Impl>
1557void
1558FullO3CPU<Impl>::removeFrontInst(const DynInstPtr &inst)
1559{
1560    DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1561            "[sn:%lli]\n",
1562            inst->threadNumber, inst->pcState(), inst->seqNum);
1563
1564    removeInstsThisCycle = true;
1565
1566    // Remove the front instruction.
1567    removeList.push(inst->getInstListIt());
1568}
1569
1570template <class Impl>
1571void
1572FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1573{
1574    DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
1575            " list.\n", tid);
1576
1577    ListIt end_it;
1578
1579    bool rob_empty = false;
1580
1581    if (instList.empty()) {
1582        return;
1583    } else if (rob.isEmpty(tid)) {
1584        DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
1585        end_it = instList.begin();
1586        rob_empty = true;
1587    } else {
1588        end_it = (rob.readTailInst(tid))->getInstListIt();
1589        DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n");
1590    }
1591
1592    removeInstsThisCycle = true;
1593
1594    ListIt inst_it = instList.end();
1595
1596    inst_it--;
1597
1598    // Walk through the instruction list, removing any instructions
1599    // that were inserted after the given instruction iterator, end_it.
1600    while (inst_it != end_it) {
1601        assert(!instList.empty());
1602
1603        squashInstIt(inst_it, tid);
1604
1605        inst_it--;
1606    }
1607
1608    // If the ROB was empty, then we actually need to remove the first
1609    // instruction as well.
1610    if (rob_empty) {
1611        squashInstIt(inst_it, tid);
1612    }
1613}
1614
1615template <class Impl>
1616void
1617FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1618{
1619    assert(!instList.empty());
1620
1621    removeInstsThisCycle = true;
1622
1623    ListIt inst_iter = instList.end();
1624
1625    inst_iter--;
1626
1627    DPRINTF(O3CPU, "Deleting instructions from instruction "
1628            "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1629            tid, seq_num, (*inst_iter)->seqNum);
1630
1631    while ((*inst_iter)->seqNum > seq_num) {
1632
1633        bool break_loop = (inst_iter == instList.begin());
1634
1635        squashInstIt(inst_iter, tid);
1636
1637        inst_iter--;
1638
1639        if (break_loop)
1640            break;
1641    }
1642}
1643
1644template <class Impl>
1645inline void
1646FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1647{
1648    if ((*instIt)->threadNumber == tid) {
1649        DPRINTF(O3CPU, "Squashing instruction, "
1650                "[tid:%i] [sn:%lli] PC %s\n",
1651                (*instIt)->threadNumber,
1652                (*instIt)->seqNum,
1653                (*instIt)->pcState());
1654
1655        // Mark it as squashed.
1656        (*instIt)->setSquashed();
1657
1658        // @todo: Formulate a consistent method for deleting
1659        // instructions from the instruction list
1660        // Remove the instruction from the list.
1661        removeList.push(instIt);
1662    }
1663}
1664
1665template <class Impl>
1666void
1667FullO3CPU<Impl>::cleanUpRemovedInsts()
1668{
1669    while (!removeList.empty()) {
1670        DPRINTF(O3CPU, "Removing instruction, "
1671                "[tid:%i] [sn:%lli] PC %s\n",
1672                (*removeList.front())->threadNumber,
1673                (*removeList.front())->seqNum,
1674                (*removeList.front())->pcState());
1675
1676        instList.erase(removeList.front());
1677
1678        removeList.pop();
1679    }
1680
1681    removeInstsThisCycle = false;
1682}
1683/*
1684template <class Impl>
1685void
1686FullO3CPU<Impl>::removeAllInsts()
1687{
1688    instList.clear();
1689}
1690*/
1691template <class Impl>
1692void
1693FullO3CPU<Impl>::dumpInsts()
1694{
1695    int num = 0;
1696
1697    ListIt inst_list_it = instList.begin();
1698
1699    cprintf("Dumping Instruction List\n");
1700
1701    while (inst_list_it != instList.end()) {
1702        cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1703                "Squashed:%i\n\n",
1704                num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber,
1705                (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
1706                (*inst_list_it)->isSquashed());
1707        inst_list_it++;
1708        ++num;
1709    }
1710}
1711/*
1712template <class Impl>
1713void
1714FullO3CPU<Impl>::wakeDependents(const DynInstPtr &inst)
1715{
1716    iew.wakeDependents(inst);
1717}
1718*/
1719template <class Impl>
1720void
1721FullO3CPU<Impl>::wakeCPU()
1722{
1723    if (activityRec.active() || tickEvent.scheduled()) {
1724        DPRINTF(Activity, "CPU already running.\n");
1725        return;
1726    }
1727
1728    DPRINTF(Activity, "Waking up CPU\n");
1729
1730    Cycles cycles(curCycle() - lastRunningCycle);
1731    // @todo: This is an oddity that is only here to match the stats
1732    if (cycles > 1) {
1733        --cycles;
1734        idleCycles += cycles;
1735        numCycles += cycles;
1736    }
1737
1738    schedule(tickEvent, clockEdge());
1739}
1740
1741template <class Impl>
1742void
1743FullO3CPU<Impl>::wakeup(ThreadID tid)
1744{
1745    if (this->thread[tid]->status() != ThreadContext::Suspended)
1746        return;
1747
1748    this->wakeCPU();
1749
1750    DPRINTF(Quiesce, "Suspended Processor woken\n");
1751    this->threadContexts[tid]->activate();
1752}
1753
1754template <class Impl>
1755ThreadID
1756FullO3CPU<Impl>::getFreeTid()
1757{
1758    for (ThreadID tid = 0; tid < numThreads; tid++) {
1759        if (!tids[tid]) {
1760            tids[tid] = true;
1761            return tid;
1762        }
1763    }
1764
1765    return InvalidThreadID;
1766}
1767
1768template <class Impl>
1769void
1770FullO3CPU<Impl>::updateThreadPriority()
1771{
1772    if (activeThreads.size() > 1) {
1773        //DEFAULT TO ROUND ROBIN SCHEME
1774        //e.g. Move highest priority to end of thread list
1775        list<ThreadID>::iterator list_begin = activeThreads.begin();
1776
1777        unsigned high_thread = *list_begin;
1778
1779        activeThreads.erase(list_begin);
1780
1781        activeThreads.push_back(high_thread);
1782    }
1783}
1784
1785// Forward declaration of FullO3CPU.
1786template class FullO3CPU<O3CPUImpl>;
1787