cpu.cc revision 10407:a9023811bf9e
18981Sandreas.hansson@arm.com/* 210744SGeoffrey.Blake@arm.com * Copyright (c) 2011-2012, 2014 ARM Limited 38981Sandreas.hansson@arm.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48981Sandreas.hansson@arm.com * All rights reserved 58981Sandreas.hansson@arm.com * 68981Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78981Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88981Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98981Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108981Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118981Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128981Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138981Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148981Sandreas.hansson@arm.com * 158981Sandreas.hansson@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 168981Sandreas.hansson@arm.com * Copyright (c) 2011 Regents of the University of California 178981Sandreas.hansson@arm.com * All rights reserved. 188981Sandreas.hansson@arm.com * 198981Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 208981Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 218981Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 228981Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 238981Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 248981Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 258981Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 268981Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 278981Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 288981Sandreas.hansson@arm.com * this software without specific prior written permission. 298981Sandreas.hansson@arm.com * 308981Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 318981Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 328981Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 338981Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 348981Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 358981Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 368981Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 378981Sandreas.hansson@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 388981Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 398981Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 408981Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 419398Sandreas.hansson@arm.com * 429398Sandreas.hansson@arm.com * Authors: Kevin Lim 439356Snilay@cs.wisc.edu * Korey Sewell 448981Sandreas.hansson@arm.com * Rick Strong 458981Sandreas.hansson@arm.com */ 469398Sandreas.hansson@arm.com 478981Sandreas.hansson@arm.com#include "arch/kernel_stats.hh" 488981Sandreas.hansson@arm.com#include "config/the_isa.hh" 498981Sandreas.hansson@arm.com#include "cpu/checker/cpu.hh" 508981Sandreas.hansson@arm.com#include "cpu/checker/thread_context.hh" 518981Sandreas.hansson@arm.com#include "cpu/o3/cpu.hh" 528981Sandreas.hansson@arm.com#include "cpu/o3/isa_specific.hh" 538981Sandreas.hansson@arm.com#include "cpu/o3/thread_context.hh" 548981Sandreas.hansson@arm.com#include "cpu/activity.hh" 5510902Sandreas.sandberg@arm.com#include "cpu/quiesce_event.hh" 568981Sandreas.hansson@arm.com#include "cpu/simple_thread.hh" 578981Sandreas.hansson@arm.com#include "cpu/thread_context.hh" 5810615Skanishk.sugand@arm.com#include "debug/Activity.hh" 5910902Sandreas.sandberg@arm.com#include "debug/Drain.hh" 6010902Sandreas.sandberg@arm.com#include "debug/O3CPU.hh" 6110902Sandreas.sandberg@arm.com#include "debug/Quiesce.hh" 628981Sandreas.hansson@arm.com#include "enums/MemoryMode.hh" 6310189Ssascha.bischoff@ARM.com#include "sim/core.hh" 6410189Ssascha.bischoff@ARM.com#include "sim/full_system.hh" 6510189Ssascha.bischoff@ARM.com#include "sim/process.hh" 6610189Ssascha.bischoff@ARM.com#include "sim/stat_control.hh" 6710189Ssascha.bischoff@ARM.com#include "sim/system.hh" 6810189Ssascha.bischoff@ARM.com 6910189Ssascha.bischoff@ARM.com#if THE_ISA == ALPHA_ISA 7010189Ssascha.bischoff@ARM.com#include "arch/alpha/osfpal.hh" 7110189Ssascha.bischoff@ARM.com#include "debug/Activity.hh" 7210189Ssascha.bischoff@ARM.com#endif 7310189Ssascha.bischoff@ARM.com 7410189Ssascha.bischoff@ARM.comstruct BaseCPUParams; 7510189Ssascha.bischoff@ARM.com 7610189Ssascha.bischoff@ARM.comusing namespace TheISA; 7710189Ssascha.bischoff@ARM.comusing namespace std; 7810189Ssascha.bischoff@ARM.com 7910189Ssascha.bischoff@ARM.comBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 8010189Ssascha.bischoff@ARM.com : BaseCPU(params) 8110189Ssascha.bischoff@ARM.com{ 8210189Ssascha.bischoff@ARM.com} 8310189Ssascha.bischoff@ARM.com 8410189Ssascha.bischoff@ARM.comvoid 859398Sandreas.hansson@arm.comBaseO3CPU::regStats() 869398Sandreas.hansson@arm.com{ 879398Sandreas.hansson@arm.com BaseCPU::regStats(); 889398Sandreas.hansson@arm.com} 8910309Snilay@cs.wisc.edu 909398Sandreas.hansson@arm.comtemplate<class Impl> 919398Sandreas.hansson@arm.combool 929398Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt) 939398Sandreas.hansson@arm.com{ 949398Sandreas.hansson@arm.com DPRINTF(O3CPU, "Fetch unit received timing\n"); 959398Sandreas.hansson@arm.com // We shouldn't ever get a block in ownership state 969398Sandreas.hansson@arm.com assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); 979398Sandreas.hansson@arm.com fetch->processCacheCompletion(pkt); 989398Sandreas.hansson@arm.com 999398Sandreas.hansson@arm.com return true; 1009398Sandreas.hansson@arm.com} 1019398Sandreas.hansson@arm.com 1028981Sandreas.hansson@arm.comtemplate<class Impl> 10310064Sandreas.hansson@arm.comvoid 10410902Sandreas.sandberg@arm.comFullO3CPU<Impl>::IcachePort::recvRetry() 1058981Sandreas.hansson@arm.com{ 1068981Sandreas.hansson@arm.com fetch->recvRetry(); 10710412Sandreas.hansson@arm.com} 10810412Sandreas.hansson@arm.com 10910412Sandreas.hansson@arm.comtemplate <class Impl> 11010412Sandreas.hansson@arm.combool 11110412Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt) 11210412Sandreas.hansson@arm.com{ 1139398Sandreas.hansson@arm.com return lsq->recvTimingResp(pkt); 1149398Sandreas.hansson@arm.com} 1159398Sandreas.hansson@arm.com 1169398Sandreas.hansson@arm.comtemplate <class Impl> 1179398Sandreas.hansson@arm.comvoid 1189398Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 1199398Sandreas.hansson@arm.com{ 1208981Sandreas.hansson@arm.com lsq->recvTimingSnoopReq(pkt); 1218981Sandreas.hansson@arm.com} 1228981Sandreas.hansson@arm.com 1238981Sandreas.hansson@arm.comtemplate <class Impl> 1248981Sandreas.hansson@arm.comvoid 1258981Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvRetry() 1268981Sandreas.hansson@arm.com{ 1278981Sandreas.hansson@arm.com lsq->recvRetry(); 1288981Sandreas.hansson@arm.com} 1298981Sandreas.hansson@arm.com 1308981Sandreas.hansson@arm.comtemplate <class Impl> 1318981Sandreas.hansson@arm.comFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 13210129SSascha.Bischoff@ARM.com : Event(CPU_Tick_Pri), cpu(c) 13310129SSascha.Bischoff@ARM.com{ 13410129SSascha.Bischoff@ARM.com} 13510129SSascha.Bischoff@ARM.com 13610129SSascha.Bischoff@ARM.comtemplate <class Impl> 13710129SSascha.Bischoff@ARM.comvoid 13810129SSascha.Bischoff@ARM.comFullO3CPU<Impl>::TickEvent::process() 13910615Skanishk.sugand@arm.com{ 1408981Sandreas.hansson@arm.com cpu->tick(); 1418981Sandreas.hansson@arm.com} 1429294Sandreas.hansson@arm.com 1439294Sandreas.hansson@arm.comtemplate <class Impl> 1448981Sandreas.hansson@arm.comconst char * 1458981Sandreas.hansson@arm.comFullO3CPU<Impl>::TickEvent::description() const 1468981Sandreas.hansson@arm.com{ 1478981Sandreas.hansson@arm.com return "FullO3CPU tick"; 1488981Sandreas.hansson@arm.com} 1498981Sandreas.hansson@arm.com 1508981Sandreas.hansson@arm.comtemplate <class Impl> 1518981Sandreas.hansson@arm.comFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 1529294Sandreas.hansson@arm.com : BaseO3CPU(params), 1539294Sandreas.hansson@arm.com itb(params->itb), 1548981Sandreas.hansson@arm.com dtb(params->dtb), 1558981Sandreas.hansson@arm.com tickEvent(this), 1568981Sandreas.hansson@arm.com#ifndef NDEBUG 1578981Sandreas.hansson@arm.com instcount(0), 1588981Sandreas.hansson@arm.com#endif 1598981Sandreas.hansson@arm.com removeInstsThisCycle(false), 1608981Sandreas.hansson@arm.com fetch(this, params), 1618981Sandreas.hansson@arm.com decode(this, params), 1628981Sandreas.hansson@arm.com rename(this, params), 1638981Sandreas.hansson@arm.com iew(this, params), 1648981Sandreas.hansson@arm.com commit(this, params), 1658981Sandreas.hansson@arm.com 1668981Sandreas.hansson@arm.com regFile(params->numPhysIntRegs, 1678981Sandreas.hansson@arm.com params->numPhysFloatRegs, 1688981Sandreas.hansson@arm.com params->numPhysCCRegs), 1698981Sandreas.hansson@arm.com 1708981Sandreas.hansson@arm.com freeList(name() + ".freelist", ®File), 1718981Sandreas.hansson@arm.com 1728981Sandreas.hansson@arm.com rob(this, params), 1738981Sandreas.hansson@arm.com 1748981Sandreas.hansson@arm.com scoreboard(name() + ".scoreboard", 1758981Sandreas.hansson@arm.com regFile.totalNumPhysRegs(), TheISA::NumMiscRegs, 1768981Sandreas.hansson@arm.com TheISA::ZeroReg, TheISA::ZeroReg), 17710744SGeoffrey.Blake@arm.com 17810615Skanishk.sugand@arm.com isa(numThreads, NULL), 17910615Skanishk.sugand@arm.com 18010615Skanishk.sugand@arm.com icachePort(&fetch, this), 18110902Sandreas.sandberg@arm.com dcachePort(&iew.ldstQueue, this), 18210902Sandreas.sandberg@arm.com 18310902Sandreas.sandberg@arm.com timeBuffer(params->backComSize, params->forwardComSize), 18410744SGeoffrey.Blake@arm.com fetchQueue(params->backComSize, params->forwardComSize), 18510744SGeoffrey.Blake@arm.com decodeQueue(params->backComSize, params->forwardComSize), 18610744SGeoffrey.Blake@arm.com renameQueue(params->backComSize, params->forwardComSize), 18710744SGeoffrey.Blake@arm.com iewQueue(params->backComSize, params->forwardComSize), 18810744SGeoffrey.Blake@arm.com activityRec(name(), NumStages, 18910744SGeoffrey.Blake@arm.com params->backComSize + params->forwardComSize, 19010744SGeoffrey.Blake@arm.com params->activity), 19110744SGeoffrey.Blake@arm.com 19210744SGeoffrey.Blake@arm.com globalSeqNum(1), 19310744SGeoffrey.Blake@arm.com system(params->system), 1948981Sandreas.hansson@arm.com drainManager(NULL), 1958981Sandreas.hansson@arm.com lastRunningCycle(curCycle()) 1968981Sandreas.hansson@arm.com{ 1978981Sandreas.hansson@arm.com if (!params->switched_out) { 1988981Sandreas.hansson@arm.com _status = Running; 1998981Sandreas.hansson@arm.com } else { 2008981Sandreas.hansson@arm.com _status = SwitchedOut; 2018981Sandreas.hansson@arm.com } 2028981Sandreas.hansson@arm.com 2038981Sandreas.hansson@arm.com if (params->checker) { 2048981Sandreas.hansson@arm.com BaseCPU *temp_checker = params->checker; 2058981Sandreas.hansson@arm.com checker = dynamic_cast<Checker<Impl> *>(temp_checker); 2068981Sandreas.hansson@arm.com checker->setIcachePort(&icachePort); 2078981Sandreas.hansson@arm.com checker->setSystem(params->system); 2088981Sandreas.hansson@arm.com } else { 2098981Sandreas.hansson@arm.com checker = NULL; 2108981Sandreas.hansson@arm.com } 2119785Sandreas.hansson@arm.com 2129785Sandreas.hansson@arm.com if (!FullSystem) { 21310615Skanishk.sugand@arm.com thread.resize(numThreads); 21410615Skanishk.sugand@arm.com tids.resize(numThreads); 2159609Sandreas.hansson@arm.com } 2168981Sandreas.hansson@arm.com 2178981Sandreas.hansson@arm.com // The stages also need their CPU pointer setup. However this 2189785Sandreas.hansson@arm.com // must be done at the upper level CPU because they have pointers 2198981Sandreas.hansson@arm.com // to the upper level CPU, and not this FullO3CPU. 2208981Sandreas.hansson@arm.com 2218981Sandreas.hansson@arm.com // Set up Pointers to the activeThreads list for each stage 2228981Sandreas.hansson@arm.com fetch.setActiveThreads(&activeThreads); 2238981Sandreas.hansson@arm.com decode.setActiveThreads(&activeThreads); 2249785Sandreas.hansson@arm.com rename.setActiveThreads(&activeThreads); 2259542Sandreas.hansson@arm.com iew.setActiveThreads(&activeThreads); 2268981Sandreas.hansson@arm.com commit.setActiveThreads(&activeThreads); 2278981Sandreas.hansson@arm.com 2288981Sandreas.hansson@arm.com // Give each of the stages the time buffer they will use. 2298981Sandreas.hansson@arm.com fetch.setTimeBuffer(&timeBuffer); 2308981Sandreas.hansson@arm.com decode.setTimeBuffer(&timeBuffer); 2318981Sandreas.hansson@arm.com rename.setTimeBuffer(&timeBuffer); 2328981Sandreas.hansson@arm.com iew.setTimeBuffer(&timeBuffer); 2339785Sandreas.hansson@arm.com commit.setTimeBuffer(&timeBuffer); 2349542Sandreas.hansson@arm.com 2358981Sandreas.hansson@arm.com // Also setup each of the stages' queues. 2368981Sandreas.hansson@arm.com fetch.setFetchQueue(&fetchQueue); 23710615Skanishk.sugand@arm.com decode.setFetchQueue(&fetchQueue); 23810615Skanishk.sugand@arm.com commit.setFetchQueue(&fetchQueue); 23910615Skanishk.sugand@arm.com decode.setDecodeQueue(&decodeQueue); 24010615Skanishk.sugand@arm.com rename.setDecodeQueue(&decodeQueue); 24110615Skanishk.sugand@arm.com rename.setRenameQueue(&renameQueue); 2429398Sandreas.hansson@arm.com iew.setRenameQueue(&renameQueue); 2439398Sandreas.hansson@arm.com iew.setIEWQueue(&iewQueue); 2449398Sandreas.hansson@arm.com commit.setIEWQueue(&iewQueue); 2459398Sandreas.hansson@arm.com commit.setRenameQueue(&renameQueue); 24610309Snilay@cs.wisc.edu 2479398Sandreas.hansson@arm.com commit.setIEWStage(&iew); 24810615Skanishk.sugand@arm.com rename.setIEWStage(&iew); 2499609Sandreas.hansson@arm.com rename.setCommitStage(&commit); 2509540Sandreas.hansson@armm.com 2519540Sandreas.hansson@armm.com ThreadID active_threads; 2529398Sandreas.hansson@arm.com if (FullSystem) { 2539398Sandreas.hansson@arm.com active_threads = 1; 2549398Sandreas.hansson@arm.com } else { 2559398Sandreas.hansson@arm.com active_threads = params->workload.size(); 2569785Sandreas.hansson@arm.com 2578981Sandreas.hansson@arm.com if (active_threads > Impl::MaxThreads) { 2588981Sandreas.hansson@arm.com panic("Workload Size too large. Increase the 'MaxThreads' " 2598981Sandreas.hansson@arm.com "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 2608981Sandreas.hansson@arm.com "or edit your workload size."); 2618981Sandreas.hansson@arm.com } 2628981Sandreas.hansson@arm.com } 2638981Sandreas.hansson@arm.com 2648981Sandreas.hansson@arm.com //Make Sure That this a Valid Architeture 2658981Sandreas.hansson@arm.com assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2668981Sandreas.hansson@arm.com assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2678981Sandreas.hansson@arm.com assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs); 2688981Sandreas.hansson@arm.com 2698981Sandreas.hansson@arm.com rename.setScoreboard(&scoreboard); 2708981Sandreas.hansson@arm.com iew.setScoreboard(&scoreboard); 2718981Sandreas.hansson@arm.com 2728981Sandreas.hansson@arm.com // Setup the rename map for whichever stages need it. 2738981Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 2748981Sandreas.hansson@arm.com isa[tid] = params->isa[tid]; 2758981Sandreas.hansson@arm.com 2769785Sandreas.hansson@arm.com // Only Alpha has an FP zero register, so for other ISAs we 2778981Sandreas.hansson@arm.com // use an invalid FP register index to avoid special treatment 2788981Sandreas.hansson@arm.com // of any valid FP reg. 2798981Sandreas.hansson@arm.com RegIndex invalidFPReg = TheISA::NumFloatRegs + 1; 2808981Sandreas.hansson@arm.com RegIndex fpZeroReg = 2818981Sandreas.hansson@arm.com (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg; 2828981Sandreas.hansson@arm.com 2838981Sandreas.hansson@arm.com commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 2848981Sandreas.hansson@arm.com &freeList); 2858981Sandreas.hansson@arm.com 2868981Sandreas.hansson@arm.com renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 2878981Sandreas.hansson@arm.com &freeList); 2888981Sandreas.hansson@arm.com } 2898981Sandreas.hansson@arm.com 2908981Sandreas.hansson@arm.com // Initialize rename map to assign physical registers to the 2918981Sandreas.hansson@arm.com // architectural registers for active threads only. 2928981Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < active_threads; tid++) { 2939785Sandreas.hansson@arm.com for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) { 2948981Sandreas.hansson@arm.com // Note that we can't use the rename() method because we don't 2958981Sandreas.hansson@arm.com // want special treatment for the zero register at this point 2968981Sandreas.hansson@arm.com PhysRegIndex phys_reg = freeList.getIntReg(); 2978981Sandreas.hansson@arm.com renameMap[tid].setIntEntry(ridx, phys_reg); 2988981Sandreas.hansson@arm.com commitRenameMap[tid].setIntEntry(ridx, phys_reg); 2998981Sandreas.hansson@arm.com } 3008981Sandreas.hansson@arm.com 3018981Sandreas.hansson@arm.com for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) { 3028981Sandreas.hansson@arm.com PhysRegIndex phys_reg = freeList.getFloatReg(); 3038981Sandreas.hansson@arm.com renameMap[tid].setFloatEntry(ridx, phys_reg); 3048981Sandreas.hansson@arm.com commitRenameMap[tid].setFloatEntry(ridx, phys_reg); 3058981Sandreas.hansson@arm.com } 3068981Sandreas.hansson@arm.com 3078981Sandreas.hansson@arm.com for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) { 3088981Sandreas.hansson@arm.com PhysRegIndex phys_reg = freeList.getCCReg(); 3098981Sandreas.hansson@arm.com renameMap[tid].setCCEntry(ridx, phys_reg); 3108981Sandreas.hansson@arm.com commitRenameMap[tid].setCCEntry(ridx, phys_reg); 3118981Sandreas.hansson@arm.com } 3128981Sandreas.hansson@arm.com } 3138981Sandreas.hansson@arm.com 3148981Sandreas.hansson@arm.com rename.setRenameMap(renameMap); 3158981Sandreas.hansson@arm.com commit.setRenameMap(commitRenameMap); 3169785Sandreas.hansson@arm.com rename.setFreeList(&freeList); 3178981Sandreas.hansson@arm.com 3188981Sandreas.hansson@arm.com // Setup the ROB for whichever stages need it. 3198981Sandreas.hansson@arm.com commit.setROB(&rob); 3208981Sandreas.hansson@arm.com 3218981Sandreas.hansson@arm.com lastActivatedCycle = 0; 3228981Sandreas.hansson@arm.com#if 0 3238981Sandreas.hansson@arm.com // Give renameMap & rename stage access to the freeList; 3248981Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) 3258981Sandreas.hansson@arm.com globalSeqNum[tid] = 1; 3268981Sandreas.hansson@arm.com#endif 3278981Sandreas.hansson@arm.com 3288981Sandreas.hansson@arm.com DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3298981Sandreas.hansson@arm.com 3308981Sandreas.hansson@arm.com // Setup any thread state. 3318981Sandreas.hansson@arm.com this->thread.resize(this->numThreads); 3328981Sandreas.hansson@arm.com 3338981Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 3348981Sandreas.hansson@arm.com if (FullSystem) { 3358981Sandreas.hansson@arm.com // SMT is not supported in FS mode yet. 3368981Sandreas.hansson@arm.com assert(this->numThreads == 1); 3378981Sandreas.hansson@arm.com this->thread[tid] = new Thread(this, 0, NULL); 3388981Sandreas.hansson@arm.com } else { 3398981Sandreas.hansson@arm.com if (tid < params->workload.size()) { 3408981Sandreas.hansson@arm.com DPRINTF(O3CPU, "Workload[%i] process is %#x", 3418981Sandreas.hansson@arm.com tid, this->thread[tid]); 3428981Sandreas.hansson@arm.com this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3438981Sandreas.hansson@arm.com (typename Impl::O3CPU *)(this), 3448981Sandreas.hansson@arm.com tid, params->workload[tid]); 3458981Sandreas.hansson@arm.com 3468981Sandreas.hansson@arm.com //usedTids[tid] = true; 3478981Sandreas.hansson@arm.com //threadMap[tid] = tid; 3489785Sandreas.hansson@arm.com } else { 3499785Sandreas.hansson@arm.com //Allocate Empty thread so M5 can use later 3508981Sandreas.hansson@arm.com //when scheduling threads to CPU 3518981Sandreas.hansson@arm.com Process* dummy_proc = NULL; 3529785Sandreas.hansson@arm.com 3538981Sandreas.hansson@arm.com this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3548981Sandreas.hansson@arm.com (typename Impl::O3CPU *)(this), 3558981Sandreas.hansson@arm.com tid, dummy_proc); 3568981Sandreas.hansson@arm.com //usedTids[tid] = false; 3579785Sandreas.hansson@arm.com } 3588981Sandreas.hansson@arm.com } 3598981Sandreas.hansson@arm.com 3608981Sandreas.hansson@arm.com ThreadContext *tc; 3619785Sandreas.hansson@arm.com 3628981Sandreas.hansson@arm.com // Setup the TC that will serve as the interface to the threads/CPU. 3638981Sandreas.hansson@arm.com O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 3648981Sandreas.hansson@arm.com 3658981Sandreas.hansson@arm.com tc = o3_tc; 3668981Sandreas.hansson@arm.com 3678981Sandreas.hansson@arm.com // If we're using a checker, then the TC should be the 3688981Sandreas.hansson@arm.com // CheckerThreadContext. 3698981Sandreas.hansson@arm.com if (params->checker) { 3708981Sandreas.hansson@arm.com tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 3719785Sandreas.hansson@arm.com o3_tc, this->checker); 3728981Sandreas.hansson@arm.com } 3739785Sandreas.hansson@arm.com 3748981Sandreas.hansson@arm.com o3_tc->cpu = (typename Impl::O3CPU *)(this); 3758981Sandreas.hansson@arm.com assert(o3_tc->cpu); 3768981Sandreas.hansson@arm.com o3_tc->thread = this->thread[tid]; 3779785Sandreas.hansson@arm.com 3788981Sandreas.hansson@arm.com if (FullSystem) { 3798981Sandreas.hansson@arm.com // Setup quiesce event. 3808981Sandreas.hansson@arm.com this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 3819785Sandreas.hansson@arm.com } 3828981Sandreas.hansson@arm.com // Give the thread the TC. 3838981Sandreas.hansson@arm.com this->thread[tid]->tc = tc; 3848981Sandreas.hansson@arm.com 3858981Sandreas.hansson@arm.com // Add the TC to the CPU's list of TC's. 3868981Sandreas.hansson@arm.com this->threadContexts.push_back(tc); 3878981Sandreas.hansson@arm.com } 3888981Sandreas.hansson@arm.com 3898981Sandreas.hansson@arm.com // FullO3CPU always requires an interrupt controller. 3908981Sandreas.hansson@arm.com if (!params->switched_out && !interrupts) { 3918981Sandreas.hansson@arm.com fatal("FullO3CPU %s has no interrupt controller.\n" 3928981Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 3938981Sandreas.hansson@arm.com } 3948981Sandreas.hansson@arm.com 3958981Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < this->numThreads; tid++) 3968981Sandreas.hansson@arm.com this->thread[tid]->setFuncExeInst(0); 3978981Sandreas.hansson@arm.com} 3988981Sandreas.hansson@arm.com 3999785Sandreas.hansson@arm.comtemplate <class Impl> 4008981Sandreas.hansson@arm.comFullO3CPU<Impl>::~FullO3CPU() 4018981Sandreas.hansson@arm.com{ 4028981Sandreas.hansson@arm.com} 4038981Sandreas.hansson@arm.com 4048981Sandreas.hansson@arm.comtemplate <class Impl> 4058981Sandreas.hansson@arm.comvoid 4068981Sandreas.hansson@arm.comFullO3CPU<Impl>::regProbePoints() 4078981Sandreas.hansson@arm.com{ 4088981Sandreas.hansson@arm.com ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete"); 4098981Sandreas.hansson@arm.com ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete"); 4108981Sandreas.hansson@arm.com fetch.regProbePoints(); 4118981Sandreas.hansson@arm.com iew.regProbePoints(); 4128981Sandreas.hansson@arm.com commit.regProbePoints(); 4138981Sandreas.hansson@arm.com} 4148981Sandreas.hansson@arm.com 4158981Sandreas.hansson@arm.comtemplate <class Impl> 4168981Sandreas.hansson@arm.comvoid 4178981Sandreas.hansson@arm.comFullO3CPU<Impl>::regStats() 4188981Sandreas.hansson@arm.com{ 4198981Sandreas.hansson@arm.com BaseO3CPU::regStats(); 4208981Sandreas.hansson@arm.com 4218981Sandreas.hansson@arm.com // Register any of the O3CPU's stats here. 4228981Sandreas.hansson@arm.com timesIdled 4238981Sandreas.hansson@arm.com .name(name() + ".timesIdled") 4248981Sandreas.hansson@arm.com .desc("Number of times that the entire CPU went into an idle state and" 4258981Sandreas.hansson@arm.com " unscheduled itself") 4268981Sandreas.hansson@arm.com .prereq(timesIdled); 4278981Sandreas.hansson@arm.com 4288981Sandreas.hansson@arm.com idleCycles 4298981Sandreas.hansson@arm.com .name(name() + ".idleCycles") 4308981Sandreas.hansson@arm.com .desc("Total number of cycles that the CPU has spent unscheduled due " 4319088Sandreas.hansson@arm.com "to idling") 4329088Sandreas.hansson@arm.com .prereq(idleCycles); 4338981Sandreas.hansson@arm.com 4348981Sandreas.hansson@arm.com quiesceCycles 4358981Sandreas.hansson@arm.com .name(name() + ".quiesceCycles") 4369090Sandreas.hansson@arm.com .desc("Total number of cycles that CPU has spent quiesced or waiting " 4378981Sandreas.hansson@arm.com "for an interrupt") 4389089Sandreas.hansson@arm.com .prereq(quiesceCycles); 4399089Sandreas.hansson@arm.com 4408981Sandreas.hansson@arm.com // Number of Instructions simulated 4418981Sandreas.hansson@arm.com // -------------------------------- 4428981Sandreas.hansson@arm.com // Should probably be in Base CPU but need templated 44310713Sandreas.hansson@arm.com // MaxThreads so put in here instead 4448981Sandreas.hansson@arm.com committedInsts 44510713Sandreas.hansson@arm.com .init(numThreads) 4468981Sandreas.hansson@arm.com .name(name() + ".committedInsts") 4478981Sandreas.hansson@arm.com .desc("Number of Instructions Simulated") 4488981Sandreas.hansson@arm.com .flags(Stats::total); 44910713Sandreas.hansson@arm.com 4508981Sandreas.hansson@arm.com committedOps 45110713Sandreas.hansson@arm.com .init(numThreads) 4528981Sandreas.hansson@arm.com .name(name() + ".committedOps") 4538981Sandreas.hansson@arm.com .desc("Number of Ops (including micro ops) Simulated") 4548981Sandreas.hansson@arm.com .flags(Stats::total); 4558981Sandreas.hansson@arm.com 4568981Sandreas.hansson@arm.com cpi 4578981Sandreas.hansson@arm.com .name(name() + ".cpi") 4588981Sandreas.hansson@arm.com .desc("CPI: Cycles Per Instruction") 4598981Sandreas.hansson@arm.com .precision(6); 4608981Sandreas.hansson@arm.com cpi = numCycles / committedInsts; 4618981Sandreas.hansson@arm.com 4628981Sandreas.hansson@arm.com totalCpi 4638981Sandreas.hansson@arm.com .name(name() + ".cpi_total") 4648981Sandreas.hansson@arm.com .desc("CPI: Total CPI of All Threads") 4658981Sandreas.hansson@arm.com .precision(6); 4668981Sandreas.hansson@arm.com totalCpi = numCycles / sum(committedInsts); 4678981Sandreas.hansson@arm.com 4688981Sandreas.hansson@arm.com ipc 4698981Sandreas.hansson@arm.com .name(name() + ".ipc") 4708981Sandreas.hansson@arm.com .desc("IPC: Instructions Per Cycle") 4718981Sandreas.hansson@arm.com .precision(6); 4728981Sandreas.hansson@arm.com ipc = committedInsts / numCycles; 4738981Sandreas.hansson@arm.com 4748981Sandreas.hansson@arm.com totalIpc 4758981Sandreas.hansson@arm.com .name(name() + ".ipc_total") 4768981Sandreas.hansson@arm.com .desc("IPC: Total IPC of All Threads") 4778981Sandreas.hansson@arm.com .precision(6); 4788981Sandreas.hansson@arm.com totalIpc = sum(committedInsts) / numCycles; 4798981Sandreas.hansson@arm.com 4808981Sandreas.hansson@arm.com this->fetch.regStats(); 4818981Sandreas.hansson@arm.com this->decode.regStats(); 4828981Sandreas.hansson@arm.com this->rename.regStats(); 4838981Sandreas.hansson@arm.com this->iew.regStats(); 4848981Sandreas.hansson@arm.com this->commit.regStats(); 4858981Sandreas.hansson@arm.com this->rob.regStats(); 4868981Sandreas.hansson@arm.com 4878981Sandreas.hansson@arm.com intRegfileReads 4888981Sandreas.hansson@arm.com .name(name() + ".int_regfile_reads") 4898981Sandreas.hansson@arm.com .desc("number of integer regfile reads") 4908981Sandreas.hansson@arm.com .prereq(intRegfileReads); 4918981Sandreas.hansson@arm.com 4928981Sandreas.hansson@arm.com intRegfileWrites 4938981Sandreas.hansson@arm.com .name(name() + ".int_regfile_writes") 4948981Sandreas.hansson@arm.com .desc("number of integer regfile writes") 4958981Sandreas.hansson@arm.com .prereq(intRegfileWrites); 4968981Sandreas.hansson@arm.com 4978981Sandreas.hansson@arm.com fpRegfileReads 4988981Sandreas.hansson@arm.com .name(name() + ".fp_regfile_reads") 4998981Sandreas.hansson@arm.com .desc("number of floating regfile reads") 5008981Sandreas.hansson@arm.com .prereq(fpRegfileReads); 5018981Sandreas.hansson@arm.com 5028981Sandreas.hansson@arm.com fpRegfileWrites 5038981Sandreas.hansson@arm.com .name(name() + ".fp_regfile_writes") 5048981Sandreas.hansson@arm.com .desc("number of floating regfile writes") 5058981Sandreas.hansson@arm.com .prereq(fpRegfileWrites); 5068981Sandreas.hansson@arm.com 5078981Sandreas.hansson@arm.com ccRegfileReads 5088981Sandreas.hansson@arm.com .name(name() + ".cc_regfile_reads") 5098981Sandreas.hansson@arm.com .desc("number of cc regfile reads") 5108981Sandreas.hansson@arm.com .prereq(ccRegfileReads); 5118981Sandreas.hansson@arm.com 5128981Sandreas.hansson@arm.com ccRegfileWrites 5138981Sandreas.hansson@arm.com .name(name() + ".cc_regfile_writes") 5148981Sandreas.hansson@arm.com .desc("number of cc regfile writes") 5158981Sandreas.hansson@arm.com .prereq(ccRegfileWrites); 5168981Sandreas.hansson@arm.com 5178981Sandreas.hansson@arm.com miscRegfileReads 5188981Sandreas.hansson@arm.com .name(name() + ".misc_regfile_reads") 5198981Sandreas.hansson@arm.com .desc("number of misc regfile reads") 5208981Sandreas.hansson@arm.com .prereq(miscRegfileReads); 5218981Sandreas.hansson@arm.com 5228981Sandreas.hansson@arm.com miscRegfileWrites 5238981Sandreas.hansson@arm.com .name(name() + ".misc_regfile_writes") 5248981Sandreas.hansson@arm.com .desc("number of misc regfile writes") 5258981Sandreas.hansson@arm.com .prereq(miscRegfileWrites); 5268981Sandreas.hansson@arm.com} 5278981Sandreas.hansson@arm.com 5288981Sandreas.hansson@arm.comtemplate <class Impl> 5298981Sandreas.hansson@arm.comvoid 5308981Sandreas.hansson@arm.comFullO3CPU<Impl>::tick() 5318981Sandreas.hansson@arm.com{ 5328981Sandreas.hansson@arm.com DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5338981Sandreas.hansson@arm.com assert(!switchedOut()); 5348981Sandreas.hansson@arm.com assert(getDrainState() != Drainable::Drained); 5358981Sandreas.hansson@arm.com 5368981Sandreas.hansson@arm.com ++numCycles; 5378981Sandreas.hansson@arm.com 5388981Sandreas.hansson@arm.com// activity = false; 5398981Sandreas.hansson@arm.com 5408981Sandreas.hansson@arm.com //Tick each of the stages 5418981Sandreas.hansson@arm.com fetch.tick(); 5428981Sandreas.hansson@arm.com 5438981Sandreas.hansson@arm.com decode.tick(); 5448981Sandreas.hansson@arm.com 5458981Sandreas.hansson@arm.com rename.tick(); 5468981Sandreas.hansson@arm.com 5478981Sandreas.hansson@arm.com iew.tick(); 5488981Sandreas.hansson@arm.com 5498981Sandreas.hansson@arm.com commit.tick(); 5508981Sandreas.hansson@arm.com 5518981Sandreas.hansson@arm.com // Now advance the time buffers 5528981Sandreas.hansson@arm.com timeBuffer.advance(); 5538981Sandreas.hansson@arm.com 5548981Sandreas.hansson@arm.com fetchQueue.advance(); 5558981Sandreas.hansson@arm.com decodeQueue.advance(); 5568981Sandreas.hansson@arm.com renameQueue.advance(); 5578981Sandreas.hansson@arm.com iewQueue.advance(); 5588981Sandreas.hansson@arm.com 5598981Sandreas.hansson@arm.com activityRec.advance(); 5608981Sandreas.hansson@arm.com 5618981Sandreas.hansson@arm.com if (removeInstsThisCycle) { 5628981Sandreas.hansson@arm.com cleanUpRemovedInsts(); 5638981Sandreas.hansson@arm.com } 5648981Sandreas.hansson@arm.com 5658981Sandreas.hansson@arm.com if (!tickEvent.scheduled()) { 5668981Sandreas.hansson@arm.com if (_status == SwitchedOut) { 5678981Sandreas.hansson@arm.com DPRINTF(O3CPU, "Switched out!\n"); 5688981Sandreas.hansson@arm.com // increment stat 5698981Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 5708981Sandreas.hansson@arm.com } else if (!activityRec.active() || _status == Idle) { 5718981Sandreas.hansson@arm.com DPRINTF(O3CPU, "Idle!\n"); 5728981Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 5738981Sandreas.hansson@arm.com timesIdled++; 5748981Sandreas.hansson@arm.com } else { 5758981Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(Cycles(1))); 5768981Sandreas.hansson@arm.com DPRINTF(O3CPU, "Scheduling next tick!\n"); 5778981Sandreas.hansson@arm.com } 5788981Sandreas.hansson@arm.com } 5798981Sandreas.hansson@arm.com 5808981Sandreas.hansson@arm.com if (!FullSystem) 5818981Sandreas.hansson@arm.com updateThreadPriority(); 5828981Sandreas.hansson@arm.com 5838981Sandreas.hansson@arm.com tryDrain(); 5848981Sandreas.hansson@arm.com} 5858981Sandreas.hansson@arm.com 5868981Sandreas.hansson@arm.comtemplate <class Impl> 5878981Sandreas.hansson@arm.comvoid 5888981Sandreas.hansson@arm.comFullO3CPU<Impl>::init() 5898981Sandreas.hansson@arm.com{ 5908981Sandreas.hansson@arm.com BaseCPU::init(); 5918981Sandreas.hansson@arm.com 5928981Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 5938981Sandreas.hansson@arm.com // Set noSquashFromTC so that the CPU doesn't squash when initially 5948981Sandreas.hansson@arm.com // setting up registers. 5958981Sandreas.hansson@arm.com thread[tid]->noSquashFromTC = true; 5968981Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 5978981Sandreas.hansson@arm.com thread[tid]->initMemProxies(thread[tid]->getTC()); 5988981Sandreas.hansson@arm.com } 5998981Sandreas.hansson@arm.com 6008981Sandreas.hansson@arm.com if (FullSystem && !params()->switched_out) { 6018981Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 6028981Sandreas.hansson@arm.com ThreadContext *src_tc = threadContexts[tid]; 6038981Sandreas.hansson@arm.com TheISA::initCPU(src_tc, src_tc->contextId()); 6048981Sandreas.hansson@arm.com } 6058981Sandreas.hansson@arm.com } 6068981Sandreas.hansson@arm.com 6078981Sandreas.hansson@arm.com // Clear noSquashFromTC. 6088981Sandreas.hansson@arm.com for (int tid = 0; tid < numThreads; ++tid) 6098981Sandreas.hansson@arm.com thread[tid]->noSquashFromTC = false; 6108981Sandreas.hansson@arm.com 6118981Sandreas.hansson@arm.com commit.setThreads(thread); 6128981Sandreas.hansson@arm.com} 6138981Sandreas.hansson@arm.com 6148981Sandreas.hansson@arm.comtemplate <class Impl> 6158981Sandreas.hansson@arm.comvoid 6168981Sandreas.hansson@arm.comFullO3CPU<Impl>::startup() 6178981Sandreas.hansson@arm.com{ 6188981Sandreas.hansson@arm.com BaseCPU::startup(); 6198981Sandreas.hansson@arm.com for (int tid = 0; tid < numThreads; ++tid) 6208981Sandreas.hansson@arm.com isa[tid]->startup(threadContexts[tid]); 6218981Sandreas.hansson@arm.com 6228981Sandreas.hansson@arm.com fetch.startupStage(); 6238981Sandreas.hansson@arm.com decode.startupStage(); 6248981Sandreas.hansson@arm.com iew.startupStage(); 6258981Sandreas.hansson@arm.com rename.startupStage(); 6268981Sandreas.hansson@arm.com commit.startupStage(); 6278981Sandreas.hansson@arm.com} 6288981Sandreas.hansson@arm.com 629template <class Impl> 630void 631FullO3CPU<Impl>::activateThread(ThreadID tid) 632{ 633 list<ThreadID>::iterator isActive = 634 std::find(activeThreads.begin(), activeThreads.end(), tid); 635 636 DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 637 assert(!switchedOut()); 638 639 if (isActive == activeThreads.end()) { 640 DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 641 tid); 642 643 activeThreads.push_back(tid); 644 } 645} 646 647template <class Impl> 648void 649FullO3CPU<Impl>::deactivateThread(ThreadID tid) 650{ 651 //Remove From Active List, if Active 652 list<ThreadID>::iterator thread_it = 653 std::find(activeThreads.begin(), activeThreads.end(), tid); 654 655 DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 656 assert(!switchedOut()); 657 658 if (thread_it != activeThreads.end()) { 659 DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 660 tid); 661 activeThreads.erase(thread_it); 662 } 663 664 fetch.deactivateThread(tid); 665 commit.deactivateThread(tid); 666} 667 668template <class Impl> 669Counter 670FullO3CPU<Impl>::totalInsts() const 671{ 672 Counter total(0); 673 674 ThreadID size = thread.size(); 675 for (ThreadID i = 0; i < size; i++) 676 total += thread[i]->numInst; 677 678 return total; 679} 680 681template <class Impl> 682Counter 683FullO3CPU<Impl>::totalOps() const 684{ 685 Counter total(0); 686 687 ThreadID size = thread.size(); 688 for (ThreadID i = 0; i < size; i++) 689 total += thread[i]->numOp; 690 691 return total; 692} 693 694template <class Impl> 695void 696FullO3CPU<Impl>::activateContext(ThreadID tid) 697{ 698 assert(!switchedOut()); 699 700 // Needs to set each stage to running as well. 701 activateThread(tid); 702 703 // We don't want to wake the CPU if it is drained. In that case, 704 // we just want to flag the thread as active and schedule the tick 705 // event from drainResume() instead. 706 if (getDrainState() == Drainable::Drained) 707 return; 708 709 // If we are time 0 or if the last activation time is in the past, 710 // schedule the next tick and wake up the fetch unit 711 if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) { 712 scheduleTickEvent(Cycles(0)); 713 714 // Be sure to signal that there's some activity so the CPU doesn't 715 // deschedule itself. 716 activityRec.activity(); 717 fetch.wakeFromQuiesce(); 718 719 Cycles cycles(curCycle() - lastRunningCycle); 720 // @todo: This is an oddity that is only here to match the stats 721 if (cycles != 0) 722 --cycles; 723 quiesceCycles += cycles; 724 725 lastActivatedCycle = curTick(); 726 727 _status = Running; 728 } 729} 730 731template <class Impl> 732void 733FullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove) 734{ 735 deactivateThread(tid); 736 if (remove) 737 removeThread(tid); 738} 739 740template <class Impl> 741void 742FullO3CPU<Impl>::suspendContext(ThreadID tid) 743{ 744 DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 745 assert(!switchedOut()); 746 deallocateContext(tid, false); 747 748 // If this was the last thread then unschedule the tick event. 749 if (activeThreads.size() == 0) 750 unscheduleTickEvent(); 751 752 DPRINTF(Quiesce, "Suspending Context\n"); 753 lastRunningCycle = curCycle(); 754 _status = Idle; 755} 756 757template <class Impl> 758void 759FullO3CPU<Impl>::haltContext(ThreadID tid) 760{ 761 //For now, this is the same as deallocate 762 DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 763 assert(!switchedOut()); 764 deallocateContext(tid, true); 765} 766 767template <class Impl> 768void 769FullO3CPU<Impl>::insertThread(ThreadID tid) 770{ 771 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 772 // Will change now that the PC and thread state is internal to the CPU 773 // and not in the ThreadContext. 774 ThreadContext *src_tc; 775 if (FullSystem) 776 src_tc = system->threadContexts[tid]; 777 else 778 src_tc = tcBase(tid); 779 780 //Bind Int Regs to Rename Map 781 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 782 PhysRegIndex phys_reg = freeList.getIntReg(); 783 784 renameMap[tid].setEntry(ireg,phys_reg); 785 scoreboard.setReg(phys_reg); 786 } 787 788 //Bind Float Regs to Rename Map 789 int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs; 790 for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) { 791 PhysRegIndex phys_reg = freeList.getFloatReg(); 792 793 renameMap[tid].setEntry(freg,phys_reg); 794 scoreboard.setReg(phys_reg); 795 } 796 797 //Bind condition-code Regs to Rename Map 798 max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs; 799 for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs; 800 creg < max_reg; creg++) { 801 PhysRegIndex phys_reg = freeList.getCCReg(); 802 803 renameMap[tid].setEntry(creg,phys_reg); 804 scoreboard.setReg(phys_reg); 805 } 806 807 //Copy Thread Data Into RegFile 808 //this->copyFromTC(tid); 809 810 //Set PC/NPC/NNPC 811 pcState(src_tc->pcState(), tid); 812 813 src_tc->setStatus(ThreadContext::Active); 814 815 activateContext(tid); 816 817 //Reset ROB/IQ/LSQ Entries 818 commit.rob->resetEntries(); 819 iew.resetEntries(); 820} 821 822template <class Impl> 823void 824FullO3CPU<Impl>::removeThread(ThreadID tid) 825{ 826 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 827 828 // Copy Thread Data From RegFile 829 // If thread is suspended, it might be re-allocated 830 // this->copyToTC(tid); 831 832 833 // @todo: 2-27-2008: Fix how we free up rename mappings 834 // here to alleviate the case for double-freeing registers 835 // in SMT workloads. 836 837 // Unbind Int Regs from Rename Map 838 for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 839 PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 840 841 scoreboard.unsetReg(phys_reg); 842 freeList.addReg(phys_reg); 843 } 844 845 // Unbind Float Regs from Rename Map 846 int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs; 847 for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) { 848 PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 849 850 scoreboard.unsetReg(phys_reg); 851 freeList.addReg(phys_reg); 852 } 853 854 // Unbind condition-code Regs from Rename Map 855 max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs; 856 for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs; 857 creg < max_reg; creg++) { 858 PhysRegIndex phys_reg = renameMap[tid].lookup(creg); 859 860 scoreboard.unsetReg(phys_reg); 861 freeList.addReg(phys_reg); 862 } 863 864 // Squash Throughout Pipeline 865 DynInstPtr inst = commit.rob->readHeadInst(tid); 866 InstSeqNum squash_seq_num = inst->seqNum; 867 fetch.squash(0, squash_seq_num, inst, tid); 868 decode.squash(tid); 869 rename.squash(squash_seq_num, tid); 870 iew.squash(tid); 871 iew.ldstQueue.squash(squash_seq_num, tid); 872 commit.rob->squash(squash_seq_num, tid); 873 874 875 assert(iew.instQueue.getCount(tid) == 0); 876 assert(iew.ldstQueue.getCount(tid) == 0); 877 878 // Reset ROB/IQ/LSQ Entries 879 880 // Commented out for now. This should be possible to do by 881 // telling all the pipeline stages to drain first, and then 882 // checking until the drain completes. Once the pipeline is 883 // drained, call resetEntries(). - 10-09-06 ktlim 884/* 885 if (activeThreads.size() >= 1) { 886 commit.rob->resetEntries(); 887 iew.resetEntries(); 888 } 889*/ 890} 891 892template <class Impl> 893Fault 894FullO3CPU<Impl>::hwrei(ThreadID tid) 895{ 896#if THE_ISA == ALPHA_ISA 897 // Need to clear the lock flag upon returning from an interrupt. 898 this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 899 900 this->thread[tid]->kernelStats->hwrei(); 901 902 // FIXME: XXX check for interrupts? XXX 903#endif 904 return NoFault; 905} 906 907template <class Impl> 908bool 909FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 910{ 911#if THE_ISA == ALPHA_ISA 912 if (this->thread[tid]->kernelStats) 913 this->thread[tid]->kernelStats->callpal(palFunc, 914 this->threadContexts[tid]); 915 916 switch (palFunc) { 917 case PAL::halt: 918 halt(); 919 if (--System::numSystemsRunning == 0) 920 exitSimLoop("all cpus halted"); 921 break; 922 923 case PAL::bpt: 924 case PAL::bugchk: 925 if (this->system->breakpoint()) 926 return false; 927 break; 928 } 929#endif 930 return true; 931} 932 933template <class Impl> 934Fault 935FullO3CPU<Impl>::getInterrupts() 936{ 937 // Check if there are any outstanding interrupts 938 return this->interrupts->getInterrupt(this->threadContexts[0]); 939} 940 941template <class Impl> 942void 943FullO3CPU<Impl>::processInterrupts(const Fault &interrupt) 944{ 945 // Check for interrupts here. For now can copy the code that 946 // exists within isa_fullsys_traits.hh. Also assume that thread 0 947 // is the one that handles the interrupts. 948 // @todo: Possibly consolidate the interrupt checking code. 949 // @todo: Allow other threads to handle interrupts. 950 951 assert(interrupt != NoFault); 952 this->interrupts->updateIntrInfo(this->threadContexts[0]); 953 954 DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 955 this->trap(interrupt, 0, NULL); 956} 957 958template <class Impl> 959void 960FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid, StaticInstPtr inst) 961{ 962 // Pass the thread's TC into the invoke method. 963 fault->invoke(this->threadContexts[tid], inst); 964} 965 966template <class Impl> 967void 968FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 969{ 970 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 971 972 DPRINTF(Activity,"Activity: syscall() called.\n"); 973 974 // Temporarily increase this by one to account for the syscall 975 // instruction. 976 ++(this->thread[tid]->funcExeInst); 977 978 // Execute the actual syscall. 979 this->thread[tid]->syscall(callnum); 980 981 // Decrease funcExeInst by one as the normal commit will handle 982 // incrementing it. 983 --(this->thread[tid]->funcExeInst); 984} 985 986template <class Impl> 987void 988FullO3CPU<Impl>::serializeThread(std::ostream &os, ThreadID tid) 989{ 990 thread[tid]->serialize(os); 991} 992 993template <class Impl> 994void 995FullO3CPU<Impl>::unserializeThread(Checkpoint *cp, const std::string §ion, 996 ThreadID tid) 997{ 998 thread[tid]->unserialize(cp, section); 999} 1000 1001template <class Impl> 1002unsigned int 1003FullO3CPU<Impl>::drain(DrainManager *drain_manager) 1004{ 1005 // If the CPU isn't doing anything, then return immediately. 1006 if (switchedOut()) { 1007 setDrainState(Drainable::Drained); 1008 return 0; 1009 } 1010 1011 DPRINTF(Drain, "Draining...\n"); 1012 setDrainState(Drainable::Draining); 1013 1014 // We only need to signal a drain to the commit stage as this 1015 // initiates squashing controls the draining. Once the commit 1016 // stage commits an instruction where it is safe to stop, it'll 1017 // squash the rest of the instructions in the pipeline and force 1018 // the fetch stage to stall. The pipeline will be drained once all 1019 // in-flight instructions have retired. 1020 commit.drain(); 1021 1022 // Wake the CPU and record activity so everything can drain out if 1023 // the CPU was not able to immediately drain. 1024 if (!isDrained()) { 1025 drainManager = drain_manager; 1026 1027 wakeCPU(); 1028 activityRec.activity(); 1029 1030 DPRINTF(Drain, "CPU not drained\n"); 1031 1032 return 1; 1033 } else { 1034 setDrainState(Drainable::Drained); 1035 DPRINTF(Drain, "CPU is already drained\n"); 1036 if (tickEvent.scheduled()) 1037 deschedule(tickEvent); 1038 1039 // Flush out any old data from the time buffers. In 1040 // particular, there might be some data in flight from the 1041 // fetch stage that isn't visible in any of the CPU buffers we 1042 // test in isDrained(). 1043 for (int i = 0; i < timeBuffer.getSize(); ++i) { 1044 timeBuffer.advance(); 1045 fetchQueue.advance(); 1046 decodeQueue.advance(); 1047 renameQueue.advance(); 1048 iewQueue.advance(); 1049 } 1050 1051 drainSanityCheck(); 1052 return 0; 1053 } 1054} 1055 1056template <class Impl> 1057bool 1058FullO3CPU<Impl>::tryDrain() 1059{ 1060 if (!drainManager || !isDrained()) 1061 return false; 1062 1063 if (tickEvent.scheduled()) 1064 deschedule(tickEvent); 1065 1066 DPRINTF(Drain, "CPU done draining, processing drain event\n"); 1067 drainManager->signalDrainDone(); 1068 drainManager = NULL; 1069 1070 return true; 1071} 1072 1073template <class Impl> 1074void 1075FullO3CPU<Impl>::drainSanityCheck() const 1076{ 1077 assert(isDrained()); 1078 fetch.drainSanityCheck(); 1079 decode.drainSanityCheck(); 1080 rename.drainSanityCheck(); 1081 iew.drainSanityCheck(); 1082 commit.drainSanityCheck(); 1083} 1084 1085template <class Impl> 1086bool 1087FullO3CPU<Impl>::isDrained() const 1088{ 1089 bool drained(true); 1090 1091 if (!instList.empty() || !removeList.empty()) { 1092 DPRINTF(Drain, "Main CPU structures not drained.\n"); 1093 drained = false; 1094 } 1095 1096 if (!fetch.isDrained()) { 1097 DPRINTF(Drain, "Fetch not drained.\n"); 1098 drained = false; 1099 } 1100 1101 if (!decode.isDrained()) { 1102 DPRINTF(Drain, "Decode not drained.\n"); 1103 drained = false; 1104 } 1105 1106 if (!rename.isDrained()) { 1107 DPRINTF(Drain, "Rename not drained.\n"); 1108 drained = false; 1109 } 1110 1111 if (!iew.isDrained()) { 1112 DPRINTF(Drain, "IEW not drained.\n"); 1113 drained = false; 1114 } 1115 1116 if (!commit.isDrained()) { 1117 DPRINTF(Drain, "Commit not drained.\n"); 1118 drained = false; 1119 } 1120 1121 return drained; 1122} 1123 1124template <class Impl> 1125void 1126FullO3CPU<Impl>::commitDrained(ThreadID tid) 1127{ 1128 fetch.drainStall(tid); 1129} 1130 1131template <class Impl> 1132void 1133FullO3CPU<Impl>::drainResume() 1134{ 1135 setDrainState(Drainable::Running); 1136 if (switchedOut()) 1137 return; 1138 1139 DPRINTF(Drain, "Resuming...\n"); 1140 verifyMemoryMode(); 1141 1142 fetch.drainResume(); 1143 commit.drainResume(); 1144 1145 _status = Idle; 1146 for (ThreadID i = 0; i < thread.size(); i++) { 1147 if (thread[i]->status() == ThreadContext::Active) { 1148 DPRINTF(Drain, "Activating thread: %i\n", i); 1149 activateThread(i); 1150 _status = Running; 1151 } 1152 } 1153 1154 assert(!tickEvent.scheduled()); 1155 if (_status == Running) 1156 schedule(tickEvent, nextCycle()); 1157} 1158 1159template <class Impl> 1160void 1161FullO3CPU<Impl>::switchOut() 1162{ 1163 DPRINTF(O3CPU, "Switching out\n"); 1164 BaseCPU::switchOut(); 1165 1166 activityRec.reset(); 1167 1168 _status = SwitchedOut; 1169 1170 if (checker) 1171 checker->switchOut(); 1172} 1173 1174template <class Impl> 1175void 1176FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 1177{ 1178 BaseCPU::takeOverFrom(oldCPU); 1179 1180 fetch.takeOverFrom(); 1181 decode.takeOverFrom(); 1182 rename.takeOverFrom(); 1183 iew.takeOverFrom(); 1184 commit.takeOverFrom(); 1185 1186 assert(!tickEvent.scheduled()); 1187 1188 FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU); 1189 if (oldO3CPU) 1190 globalSeqNum = oldO3CPU->globalSeqNum; 1191 1192 lastRunningCycle = curCycle(); 1193 _status = Idle; 1194} 1195 1196template <class Impl> 1197void 1198FullO3CPU<Impl>::verifyMemoryMode() const 1199{ 1200 if (!system->isTimingMode()) { 1201 fatal("The O3 CPU requires the memory system to be in " 1202 "'timing' mode.\n"); 1203 } 1204} 1205 1206template <class Impl> 1207TheISA::MiscReg 1208FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) 1209{ 1210 return this->isa[tid]->readMiscRegNoEffect(misc_reg); 1211} 1212 1213template <class Impl> 1214TheISA::MiscReg 1215FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 1216{ 1217 miscRegfileReads++; 1218 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); 1219} 1220 1221template <class Impl> 1222void 1223FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 1224 const TheISA::MiscReg &val, ThreadID tid) 1225{ 1226 this->isa[tid]->setMiscRegNoEffect(misc_reg, val); 1227} 1228 1229template <class Impl> 1230void 1231FullO3CPU<Impl>::setMiscReg(int misc_reg, 1232 const TheISA::MiscReg &val, ThreadID tid) 1233{ 1234 miscRegfileWrites++; 1235 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); 1236} 1237 1238template <class Impl> 1239uint64_t 1240FullO3CPU<Impl>::readIntReg(int reg_idx) 1241{ 1242 intRegfileReads++; 1243 return regFile.readIntReg(reg_idx); 1244} 1245 1246template <class Impl> 1247FloatReg 1248FullO3CPU<Impl>::readFloatReg(int reg_idx) 1249{ 1250 fpRegfileReads++; 1251 return regFile.readFloatReg(reg_idx); 1252} 1253 1254template <class Impl> 1255FloatRegBits 1256FullO3CPU<Impl>::readFloatRegBits(int reg_idx) 1257{ 1258 fpRegfileReads++; 1259 return regFile.readFloatRegBits(reg_idx); 1260} 1261 1262template <class Impl> 1263CCReg 1264FullO3CPU<Impl>::readCCReg(int reg_idx) 1265{ 1266 ccRegfileReads++; 1267 return regFile.readCCReg(reg_idx); 1268} 1269 1270template <class Impl> 1271void 1272FullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 1273{ 1274 intRegfileWrites++; 1275 regFile.setIntReg(reg_idx, val); 1276} 1277 1278template <class Impl> 1279void 1280FullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 1281{ 1282 fpRegfileWrites++; 1283 regFile.setFloatReg(reg_idx, val); 1284} 1285 1286template <class Impl> 1287void 1288FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 1289{ 1290 fpRegfileWrites++; 1291 regFile.setFloatRegBits(reg_idx, val); 1292} 1293 1294template <class Impl> 1295void 1296FullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val) 1297{ 1298 ccRegfileWrites++; 1299 regFile.setCCReg(reg_idx, val); 1300} 1301 1302template <class Impl> 1303uint64_t 1304FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 1305{ 1306 intRegfileReads++; 1307 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx); 1308 1309 return regFile.readIntReg(phys_reg); 1310} 1311 1312template <class Impl> 1313float 1314FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 1315{ 1316 fpRegfileReads++; 1317 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 1318 1319 return regFile.readFloatReg(phys_reg); 1320} 1321 1322template <class Impl> 1323uint64_t 1324FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 1325{ 1326 fpRegfileReads++; 1327 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 1328 1329 return regFile.readFloatRegBits(phys_reg); 1330} 1331 1332template <class Impl> 1333CCReg 1334FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid) 1335{ 1336 ccRegfileReads++; 1337 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx); 1338 1339 return regFile.readCCReg(phys_reg); 1340} 1341 1342template <class Impl> 1343void 1344FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 1345{ 1346 intRegfileWrites++; 1347 PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx); 1348 1349 regFile.setIntReg(phys_reg, val); 1350} 1351 1352template <class Impl> 1353void 1354FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 1355{ 1356 fpRegfileWrites++; 1357 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 1358 1359 regFile.setFloatReg(phys_reg, val); 1360} 1361 1362template <class Impl> 1363void 1364FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 1365{ 1366 fpRegfileWrites++; 1367 PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 1368 1369 regFile.setFloatRegBits(phys_reg, val); 1370} 1371 1372template <class Impl> 1373void 1374FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid) 1375{ 1376 ccRegfileWrites++; 1377 PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx); 1378 1379 regFile.setCCReg(phys_reg, val); 1380} 1381 1382template <class Impl> 1383TheISA::PCState 1384FullO3CPU<Impl>::pcState(ThreadID tid) 1385{ 1386 return commit.pcState(tid); 1387} 1388 1389template <class Impl> 1390void 1391FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 1392{ 1393 commit.pcState(val, tid); 1394} 1395 1396template <class Impl> 1397Addr 1398FullO3CPU<Impl>::instAddr(ThreadID tid) 1399{ 1400 return commit.instAddr(tid); 1401} 1402 1403template <class Impl> 1404Addr 1405FullO3CPU<Impl>::nextInstAddr(ThreadID tid) 1406{ 1407 return commit.nextInstAddr(tid); 1408} 1409 1410template <class Impl> 1411MicroPC 1412FullO3CPU<Impl>::microPC(ThreadID tid) 1413{ 1414 return commit.microPC(tid); 1415} 1416 1417template <class Impl> 1418void 1419FullO3CPU<Impl>::squashFromTC(ThreadID tid) 1420{ 1421 this->thread[tid]->noSquashFromTC = true; 1422 this->commit.generateTCEvent(tid); 1423} 1424 1425template <class Impl> 1426typename FullO3CPU<Impl>::ListIt 1427FullO3CPU<Impl>::addInst(DynInstPtr &inst) 1428{ 1429 instList.push_back(inst); 1430 1431 return --(instList.end()); 1432} 1433 1434template <class Impl> 1435void 1436FullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst) 1437{ 1438 // Keep an instruction count. 1439 if (!inst->isMicroop() || inst->isLastMicroop()) { 1440 thread[tid]->numInst++; 1441 thread[tid]->numInsts++; 1442 committedInsts[tid]++; 1443 } 1444 thread[tid]->numOp++; 1445 thread[tid]->numOps++; 1446 committedOps[tid]++; 1447 1448 system->totalNumInsts++; 1449 // Check for instruction-count-based events. 1450 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 1451 system->instEventQueue.serviceEvents(system->totalNumInsts); 1452} 1453 1454template <class Impl> 1455void 1456FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 1457{ 1458 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 1459 "[sn:%lli]\n", 1460 inst->threadNumber, inst->pcState(), inst->seqNum); 1461 1462 removeInstsThisCycle = true; 1463 1464 // Remove the front instruction. 1465 removeList.push(inst->getInstListIt()); 1466} 1467 1468template <class Impl> 1469void 1470FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 1471{ 1472 DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 1473 " list.\n", tid); 1474 1475 ListIt end_it; 1476 1477 bool rob_empty = false; 1478 1479 if (instList.empty()) { 1480 return; 1481 } else if (rob.isEmpty(tid)) { 1482 DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 1483 end_it = instList.begin(); 1484 rob_empty = true; 1485 } else { 1486 end_it = (rob.readTailInst(tid))->getInstListIt(); 1487 DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 1488 } 1489 1490 removeInstsThisCycle = true; 1491 1492 ListIt inst_it = instList.end(); 1493 1494 inst_it--; 1495 1496 // Walk through the instruction list, removing any instructions 1497 // that were inserted after the given instruction iterator, end_it. 1498 while (inst_it != end_it) { 1499 assert(!instList.empty()); 1500 1501 squashInstIt(inst_it, tid); 1502 1503 inst_it--; 1504 } 1505 1506 // If the ROB was empty, then we actually need to remove the first 1507 // instruction as well. 1508 if (rob_empty) { 1509 squashInstIt(inst_it, tid); 1510 } 1511} 1512 1513template <class Impl> 1514void 1515FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 1516{ 1517 assert(!instList.empty()); 1518 1519 removeInstsThisCycle = true; 1520 1521 ListIt inst_iter = instList.end(); 1522 1523 inst_iter--; 1524 1525 DPRINTF(O3CPU, "Deleting instructions from instruction " 1526 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 1527 tid, seq_num, (*inst_iter)->seqNum); 1528 1529 while ((*inst_iter)->seqNum > seq_num) { 1530 1531 bool break_loop = (inst_iter == instList.begin()); 1532 1533 squashInstIt(inst_iter, tid); 1534 1535 inst_iter--; 1536 1537 if (break_loop) 1538 break; 1539 } 1540} 1541 1542template <class Impl> 1543inline void 1544FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 1545{ 1546 if ((*instIt)->threadNumber == tid) { 1547 DPRINTF(O3CPU, "Squashing instruction, " 1548 "[tid:%i] [sn:%lli] PC %s\n", 1549 (*instIt)->threadNumber, 1550 (*instIt)->seqNum, 1551 (*instIt)->pcState()); 1552 1553 // Mark it as squashed. 1554 (*instIt)->setSquashed(); 1555 1556 // @todo: Formulate a consistent method for deleting 1557 // instructions from the instruction list 1558 // Remove the instruction from the list. 1559 removeList.push(instIt); 1560 } 1561} 1562 1563template <class Impl> 1564void 1565FullO3CPU<Impl>::cleanUpRemovedInsts() 1566{ 1567 while (!removeList.empty()) { 1568 DPRINTF(O3CPU, "Removing instruction, " 1569 "[tid:%i] [sn:%lli] PC %s\n", 1570 (*removeList.front())->threadNumber, 1571 (*removeList.front())->seqNum, 1572 (*removeList.front())->pcState()); 1573 1574 instList.erase(removeList.front()); 1575 1576 removeList.pop(); 1577 } 1578 1579 removeInstsThisCycle = false; 1580} 1581/* 1582template <class Impl> 1583void 1584FullO3CPU<Impl>::removeAllInsts() 1585{ 1586 instList.clear(); 1587} 1588*/ 1589template <class Impl> 1590void 1591FullO3CPU<Impl>::dumpInsts() 1592{ 1593 int num = 0; 1594 1595 ListIt inst_list_it = instList.begin(); 1596 1597 cprintf("Dumping Instruction List\n"); 1598 1599 while (inst_list_it != instList.end()) { 1600 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 1601 "Squashed:%i\n\n", 1602 num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 1603 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 1604 (*inst_list_it)->isSquashed()); 1605 inst_list_it++; 1606 ++num; 1607 } 1608} 1609/* 1610template <class Impl> 1611void 1612FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 1613{ 1614 iew.wakeDependents(inst); 1615} 1616*/ 1617template <class Impl> 1618void 1619FullO3CPU<Impl>::wakeCPU() 1620{ 1621 if (activityRec.active() || tickEvent.scheduled()) { 1622 DPRINTF(Activity, "CPU already running.\n"); 1623 return; 1624 } 1625 1626 DPRINTF(Activity, "Waking up CPU\n"); 1627 1628 Cycles cycles(curCycle() - lastRunningCycle); 1629 // @todo: This is an oddity that is only here to match the stats 1630 if (cycles != 0) 1631 --cycles; 1632 idleCycles += cycles; 1633 numCycles += cycles; 1634 1635 schedule(tickEvent, clockEdge()); 1636} 1637 1638template <class Impl> 1639void 1640FullO3CPU<Impl>::wakeup() 1641{ 1642 if (this->thread[0]->status() != ThreadContext::Suspended) 1643 return; 1644 1645 this->wakeCPU(); 1646 1647 DPRINTF(Quiesce, "Suspended Processor woken\n"); 1648 this->threadContexts[0]->activate(); 1649} 1650 1651template <class Impl> 1652ThreadID 1653FullO3CPU<Impl>::getFreeTid() 1654{ 1655 for (ThreadID tid = 0; tid < numThreads; tid++) { 1656 if (!tids[tid]) { 1657 tids[tid] = true; 1658 return tid; 1659 } 1660 } 1661 1662 return InvalidThreadID; 1663} 1664 1665template <class Impl> 1666void 1667FullO3CPU<Impl>::updateThreadPriority() 1668{ 1669 if (activeThreads.size() > 1) { 1670 //DEFAULT TO ROUND ROBIN SCHEME 1671 //e.g. Move highest priority to end of thread list 1672 list<ThreadID>::iterator list_begin = activeThreads.begin(); 1673 1674 unsigned high_thread = *list_begin; 1675 1676 activeThreads.erase(list_begin); 1677 1678 activeThreads.push_back(high_thread); 1679 } 1680} 1681 1682// Forward declaration of FullO3CPU. 1683template class FullO3CPU<O3CPUImpl>; 1684