cpu.cc revision 9915
11689SN/A/* 28948Sandreas.hansson@arm.com * Copyright (c) 2011-2012 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 142325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422756Sksewell@umich.edu * Korey Sewell 437897Shestness@cs.utexas.edu * Rick Strong 441689SN/A */ 451689SN/A 468779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 498887Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 508229Snate@binkert.org#include "cpu/o3/cpu.hh" 518229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 528229Snate@binkert.org#include "cpu/o3/thread_context.hh" 534762Snate@binkert.org#include "cpu/activity.hh" 548779Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 554762Snate@binkert.org#include "cpu/simple_thread.hh" 564762Snate@binkert.org#include "cpu/thread_context.hh" 578232Snate@binkert.org#include "debug/Activity.hh" 589152Satgutier@umich.edu#include "debug/Drain.hh" 598232Snate@binkert.org#include "debug/O3CPU.hh" 608232Snate@binkert.org#include "debug/Quiesce.hh" 614762Snate@binkert.org#include "enums/MemoryMode.hh" 624762Snate@binkert.org#include "sim/core.hh" 638793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 648779Sgblack@eecs.umich.edu#include "sim/process.hh" 654762Snate@binkert.org#include "sim/stat_control.hh" 668460SAli.Saidi@ARM.com#include "sim/system.hh" 674762Snate@binkert.org 685702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 695702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 708232Snate@binkert.org#include "debug/Activity.hh" 715702Ssaidi@eecs.umich.edu#endif 725702Ssaidi@eecs.umich.edu 738737Skoansin.tan@gmail.comstruct BaseCPUParams; 745529Snate@binkert.org 752669Sktlim@umich.eduusing namespace TheISA; 766221Snate@binkert.orgusing namespace std; 771060SN/A 785529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 795712Shsul@eecs.umich.edu : BaseCPU(params) 801060SN/A{ 811060SN/A} 821060SN/A 832292SN/Avoid 842733Sktlim@umich.eduBaseO3CPU::regStats() 852292SN/A{ 862292SN/A BaseCPU::regStats(); 872292SN/A} 882292SN/A 898707Sandreas.hansson@arm.comtemplate<class Impl> 908707Sandreas.hansson@arm.combool 918975Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt) 928707Sandreas.hansson@arm.com{ 938707Sandreas.hansson@arm.com DPRINTF(O3CPU, "Fetch unit received timing\n"); 948948Sandreas.hansson@arm.com // We shouldn't ever get a block in ownership state 958948Sandreas.hansson@arm.com assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); 968948Sandreas.hansson@arm.com fetch->processCacheCompletion(pkt); 978707Sandreas.hansson@arm.com 988707Sandreas.hansson@arm.com return true; 998707Sandreas.hansson@arm.com} 1008707Sandreas.hansson@arm.com 1018707Sandreas.hansson@arm.comtemplate<class Impl> 1028707Sandreas.hansson@arm.comvoid 1038707Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvRetry() 1048707Sandreas.hansson@arm.com{ 1058707Sandreas.hansson@arm.com fetch->recvRetry(); 1068707Sandreas.hansson@arm.com} 1078707Sandreas.hansson@arm.com 1088707Sandreas.hansson@arm.comtemplate <class Impl> 1098707Sandreas.hansson@arm.combool 1108975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt) 1118707Sandreas.hansson@arm.com{ 1128975Sandreas.hansson@arm.com return lsq->recvTimingResp(pkt); 1138707Sandreas.hansson@arm.com} 1148707Sandreas.hansson@arm.com 1158707Sandreas.hansson@arm.comtemplate <class Impl> 1168975Sandreas.hansson@arm.comvoid 1178975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 1188948Sandreas.hansson@arm.com{ 1198975Sandreas.hansson@arm.com lsq->recvTimingSnoopReq(pkt); 1208948Sandreas.hansson@arm.com} 1218948Sandreas.hansson@arm.com 1228948Sandreas.hansson@arm.comtemplate <class Impl> 1238707Sandreas.hansson@arm.comvoid 1248707Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvRetry() 1258707Sandreas.hansson@arm.com{ 1268707Sandreas.hansson@arm.com lsq->recvRetry(); 1278707Sandreas.hansson@arm.com} 1288707Sandreas.hansson@arm.com 1291060SN/Atemplate <class Impl> 1301755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 1315606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 1321060SN/A{ 1331060SN/A} 1341060SN/A 1351060SN/Atemplate <class Impl> 1361060SN/Avoid 1371755SN/AFullO3CPU<Impl>::TickEvent::process() 1381060SN/A{ 1391060SN/A cpu->tick(); 1401060SN/A} 1411060SN/A 1421060SN/Atemplate <class Impl> 1431060SN/Aconst char * 1445336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 1451060SN/A{ 1464873Sstever@eecs.umich.edu return "FullO3CPU tick"; 1471060SN/A} 1481060SN/A 1491060SN/Atemplate <class Impl> 1502829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 1515606Snate@binkert.org : Event(CPU_Switch_Pri) 1522829Sksewell@umich.edu{ 1532829Sksewell@umich.edu} 1542829Sksewell@umich.edu 1552829Sksewell@umich.edutemplate <class Impl> 1562829Sksewell@umich.eduvoid 1572829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 1582829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1592829Sksewell@umich.edu{ 1602829Sksewell@umich.edu tid = thread_num; 1612829Sksewell@umich.edu cpu = thread_cpu; 1622829Sksewell@umich.edu} 1632829Sksewell@umich.edu 1642829Sksewell@umich.edutemplate <class Impl> 1652829Sksewell@umich.eduvoid 1662829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1672829Sksewell@umich.edu{ 1682829Sksewell@umich.edu cpu->activateThread(tid); 1692829Sksewell@umich.edu} 1702829Sksewell@umich.edu 1712829Sksewell@umich.edutemplate <class Impl> 1722829Sksewell@umich.educonst char * 1735336Shines@cs.fsu.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1742829Sksewell@umich.edu{ 1754873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1762829Sksewell@umich.edu} 1772829Sksewell@umich.edu 1782829Sksewell@umich.edutemplate <class Impl> 1792875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1805606Snate@binkert.org : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1812875Sksewell@umich.edu{ 1822875Sksewell@umich.edu} 1832875Sksewell@umich.edu 1842875Sksewell@umich.edutemplate <class Impl> 1852875Sksewell@umich.eduvoid 1862875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1873859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1882875Sksewell@umich.edu{ 1892875Sksewell@umich.edu tid = thread_num; 1902875Sksewell@umich.edu cpu = thread_cpu; 1913859Sbinkertn@umich.edu remove = false; 1922875Sksewell@umich.edu} 1932875Sksewell@umich.edu 1942875Sksewell@umich.edutemplate <class Impl> 1952875Sksewell@umich.eduvoid 1962875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1972875Sksewell@umich.edu{ 1982875Sksewell@umich.edu cpu->deactivateThread(tid); 1993221Sktlim@umich.edu if (remove) 2003221Sktlim@umich.edu cpu->removeThread(tid); 2012875Sksewell@umich.edu} 2022875Sksewell@umich.edu 2032875Sksewell@umich.edutemplate <class Impl> 2042875Sksewell@umich.educonst char * 2055336Shines@cs.fsu.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 2062875Sksewell@umich.edu{ 2074873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 2082875Sksewell@umich.edu} 2092875Sksewell@umich.edu 2102875Sksewell@umich.edutemplate <class Impl> 2115595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 2122733Sktlim@umich.edu : BaseO3CPU(params), 2133781Sgblack@eecs.umich.edu itb(params->itb), 2143781Sgblack@eecs.umich.edu dtb(params->dtb), 2151060SN/A tickEvent(this), 2165737Scws3k@cs.virginia.edu#ifndef NDEBUG 2175737Scws3k@cs.virginia.edu instcount(0), 2185737Scws3k@cs.virginia.edu#endif 2192292SN/A removeInstsThisCycle(false), 2205595Sgblack@eecs.umich.edu fetch(this, params), 2215595Sgblack@eecs.umich.edu decode(this, params), 2225595Sgblack@eecs.umich.edu rename(this, params), 2235595Sgblack@eecs.umich.edu iew(this, params), 2245595Sgblack@eecs.umich.edu commit(this, params), 2251060SN/A 2269915Ssteve.reinhardt@amd.com regFile(params->numPhysIntRegs, 2274329Sktlim@umich.edu params->numPhysFloatRegs), 2281060SN/A 2295529Snate@binkert.org freeList(params->numThreads, 2302292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 2312292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 2321060SN/A 2335595Sgblack@eecs.umich.edu rob(this, 2344329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 2352292SN/A params->smtROBPolicy, params->smtROBThreshold, 2365529Snate@binkert.org params->numThreads), 2371060SN/A 2385529Snate@binkert.org scoreboard(params->numThreads, 2392292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 2402292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 2416221Snate@binkert.org TheISA::NumMiscRegs * numThreads, 2422292SN/A TheISA::ZeroReg), 2431060SN/A 2449384SAndreas.Sandberg@arm.com isa(numThreads, NULL), 2459384SAndreas.Sandberg@arm.com 2468707Sandreas.hansson@arm.com icachePort(&fetch, this), 2478707Sandreas.hansson@arm.com dcachePort(&iew.ldstQueue, this), 2488707Sandreas.hansson@arm.com 2492873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 2502873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 2512873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 2522873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 2532873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 2545804Snate@binkert.org activityRec(name(), NumStages, 2552873Sktlim@umich.edu params->backComSize + params->forwardComSize, 2562873Sktlim@umich.edu params->activity), 2571060SN/A 2581060SN/A globalSeqNum(1), 2592292SN/A system(params->system), 2609444SAndreas.Sandberg@ARM.com drainManager(NULL), 2619180Sandreas.hansson@arm.com lastRunningCycle(curCycle()) 2621060SN/A{ 2639433SAndreas.Sandberg@ARM.com if (!params->switched_out) { 2643221Sktlim@umich.edu _status = Running; 2653221Sktlim@umich.edu } else { 2669152Satgutier@umich.edu _status = SwitchedOut; 2673221Sktlim@umich.edu } 2681681SN/A 2692794Sktlim@umich.edu if (params->checker) { 2702316SN/A BaseCPU *temp_checker = params->checker; 2718733Sgeoffrey.blake@arm.com checker = dynamic_cast<Checker<Impl> *>(temp_checker); 2728707Sandreas.hansson@arm.com checker->setIcachePort(&icachePort); 2732316SN/A checker->setSystem(params->system); 2744598Sbinkertn@umich.edu } else { 2754598Sbinkertn@umich.edu checker = NULL; 2764598Sbinkertn@umich.edu } 2772316SN/A 2788793Sgblack@eecs.umich.edu if (!FullSystem) { 2798793Sgblack@eecs.umich.edu thread.resize(numThreads); 2808793Sgblack@eecs.umich.edu tids.resize(numThreads); 2818793Sgblack@eecs.umich.edu } 2821681SN/A 2832325SN/A // The stages also need their CPU pointer setup. However this 2842325SN/A // must be done at the upper level CPU because they have pointers 2852325SN/A // to the upper level CPU, and not this FullO3CPU. 2861060SN/A 2872292SN/A // Set up Pointers to the activeThreads list for each stage 2882292SN/A fetch.setActiveThreads(&activeThreads); 2892292SN/A decode.setActiveThreads(&activeThreads); 2902292SN/A rename.setActiveThreads(&activeThreads); 2912292SN/A iew.setActiveThreads(&activeThreads); 2922292SN/A commit.setActiveThreads(&activeThreads); 2931060SN/A 2941060SN/A // Give each of the stages the time buffer they will use. 2951060SN/A fetch.setTimeBuffer(&timeBuffer); 2961060SN/A decode.setTimeBuffer(&timeBuffer); 2971060SN/A rename.setTimeBuffer(&timeBuffer); 2981060SN/A iew.setTimeBuffer(&timeBuffer); 2991060SN/A commit.setTimeBuffer(&timeBuffer); 3001060SN/A 3011060SN/A // Also setup each of the stages' queues. 3021060SN/A fetch.setFetchQueue(&fetchQueue); 3031060SN/A decode.setFetchQueue(&fetchQueue); 3042292SN/A commit.setFetchQueue(&fetchQueue); 3051060SN/A decode.setDecodeQueue(&decodeQueue); 3061060SN/A rename.setDecodeQueue(&decodeQueue); 3071060SN/A rename.setRenameQueue(&renameQueue); 3081060SN/A iew.setRenameQueue(&renameQueue); 3091060SN/A iew.setIEWQueue(&iewQueue); 3101060SN/A commit.setIEWQueue(&iewQueue); 3111060SN/A commit.setRenameQueue(&renameQueue); 3121060SN/A 3132292SN/A commit.setIEWStage(&iew); 3142292SN/A rename.setIEWStage(&iew); 3152292SN/A rename.setCommitStage(&commit); 3162292SN/A 3178793Sgblack@eecs.umich.edu ThreadID active_threads; 3188793Sgblack@eecs.umich.edu if (FullSystem) { 3198793Sgblack@eecs.umich.edu active_threads = 1; 3208793Sgblack@eecs.umich.edu } else { 3218793Sgblack@eecs.umich.edu active_threads = params->workload.size(); 3222831Sksewell@umich.edu 3238793Sgblack@eecs.umich.edu if (active_threads > Impl::MaxThreads) { 3248793Sgblack@eecs.umich.edu panic("Workload Size too large. Increase the 'MaxThreads' " 3258793Sgblack@eecs.umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 3268793Sgblack@eecs.umich.edu "or edit your workload size."); 3278793Sgblack@eecs.umich.edu } 3282831Sksewell@umich.edu } 3292292SN/A 3302316SN/A //Make Sure That this a Valid Architeture 3312292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 3322292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 3332292SN/A 3342292SN/A rename.setScoreboard(&scoreboard); 3352292SN/A iew.setScoreboard(&scoreboard); 3362292SN/A 3371060SN/A // Setup the rename map for whichever stages need it. 3382292SN/A PhysRegIndex lreg_idx = 0; 3392292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 3401060SN/A 3416221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3422307SN/A bool bindRegs = (tid <= active_threads - 1); 3432292SN/A 3449384SAndreas.Sandberg@arm.com isa[tid] = params->isa[tid]; 3459384SAndreas.Sandberg@arm.com 3462292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 3472292SN/A params->numPhysIntRegs, 3482325SN/A lreg_idx, //Index for Logical. Regs 3492292SN/A 3502292SN/A TheISA::NumFloatRegs, 3512292SN/A params->numPhysFloatRegs, 3522325SN/A freg_idx, //Index for Float Regs 3532292SN/A 3542292SN/A TheISA::NumMiscRegs, 3552292SN/A 3562292SN/A TheISA::ZeroReg, 3572292SN/A TheISA::ZeroReg, 3582292SN/A 3592292SN/A tid, 3602292SN/A false); 3612292SN/A 3622292SN/A renameMap[tid].init(TheISA::NumIntRegs, 3632292SN/A params->numPhysIntRegs, 3642325SN/A lreg_idx, //Index for Logical. Regs 3652292SN/A 3662292SN/A TheISA::NumFloatRegs, 3672292SN/A params->numPhysFloatRegs, 3682325SN/A freg_idx, //Index for Float Regs 3692292SN/A 3702292SN/A TheISA::NumMiscRegs, 3712292SN/A 3722292SN/A TheISA::ZeroReg, 3732292SN/A TheISA::ZeroReg, 3742292SN/A 3752292SN/A tid, 3762292SN/A bindRegs); 3773221Sktlim@umich.edu 3783221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3793221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3802292SN/A } 3812292SN/A 3822292SN/A rename.setRenameMap(renameMap); 3832292SN/A commit.setRenameMap(commitRenameMap); 3842292SN/A 3852292SN/A // Give renameMap & rename stage access to the freeList; 3866221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3876221Snate@binkert.org renameMap[tid].setFreeList(&freeList); 3881060SN/A rename.setFreeList(&freeList); 3892292SN/A 3901060SN/A // Setup the ROB for whichever stages need it. 3911060SN/A commit.setROB(&rob); 3922292SN/A 3939158Sandreas.hansson@arm.com lastActivatedCycle = 0; 3946221Snate@binkert.org#if 0 3953093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3966221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3976221Snate@binkert.org globalSeqNum[tid] = 1; 3986221Snate@binkert.org#endif 3993093Sksewell@umich.edu 4002292SN/A contextSwitch = false; 4015595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 4025595Sgblack@eecs.umich.edu 4035595Sgblack@eecs.umich.edu // Setup any thread state. 4045595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 4055595Sgblack@eecs.umich.edu 4066221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 4078793Sgblack@eecs.umich.edu if (FullSystem) { 4088793Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 4098793Sgblack@eecs.umich.edu assert(this->numThreads == 1); 4108793Sgblack@eecs.umich.edu this->thread[tid] = new Thread(this, 0, NULL); 4118793Sgblack@eecs.umich.edu } else { 4128793Sgblack@eecs.umich.edu if (tid < params->workload.size()) { 4138793Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 4148793Sgblack@eecs.umich.edu tid, this->thread[tid]); 4158793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 4168793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 4178793Sgblack@eecs.umich.edu tid, params->workload[tid]); 4185595Sgblack@eecs.umich.edu 4198793Sgblack@eecs.umich.edu //usedTids[tid] = true; 4208793Sgblack@eecs.umich.edu //threadMap[tid] = tid; 4218793Sgblack@eecs.umich.edu } else { 4228793Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 4238793Sgblack@eecs.umich.edu //when scheduling threads to CPU 4248793Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 4255595Sgblack@eecs.umich.edu 4268793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 4278793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 4288793Sgblack@eecs.umich.edu tid, dummy_proc); 4298793Sgblack@eecs.umich.edu //usedTids[tid] = false; 4308793Sgblack@eecs.umich.edu } 4315595Sgblack@eecs.umich.edu } 4325595Sgblack@eecs.umich.edu 4335595Sgblack@eecs.umich.edu ThreadContext *tc; 4345595Sgblack@eecs.umich.edu 4355595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 4365595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 4375595Sgblack@eecs.umich.edu 4385595Sgblack@eecs.umich.edu tc = o3_tc; 4395595Sgblack@eecs.umich.edu 4405595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 4415595Sgblack@eecs.umich.edu // CheckerThreadContext. 4425595Sgblack@eecs.umich.edu if (params->checker) { 4435595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 4445595Sgblack@eecs.umich.edu o3_tc, this->checker); 4455595Sgblack@eecs.umich.edu } 4465595Sgblack@eecs.umich.edu 4475595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 4485595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 4496221Snate@binkert.org o3_tc->thread = this->thread[tid]; 4505595Sgblack@eecs.umich.edu 4518793Sgblack@eecs.umich.edu if (FullSystem) { 4528793Sgblack@eecs.umich.edu // Setup quiesce event. 4538793Sgblack@eecs.umich.edu this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 4548793Sgblack@eecs.umich.edu } 4555595Sgblack@eecs.umich.edu // Give the thread the TC. 4566221Snate@binkert.org this->thread[tid]->tc = tc; 4575595Sgblack@eecs.umich.edu 4585595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4595595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4605595Sgblack@eecs.umich.edu } 4615595Sgblack@eecs.umich.edu 4628876Sandreas.hansson@arm.com // FullO3CPU always requires an interrupt controller. 4639433SAndreas.Sandberg@ARM.com if (!params->switched_out && !interrupts) { 4648876Sandreas.hansson@arm.com fatal("FullO3CPU %s has no interrupt controller.\n" 4658876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 4668876Sandreas.hansson@arm.com } 4678876Sandreas.hansson@arm.com 4686221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4696221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4701060SN/A} 4711060SN/A 4721060SN/Atemplate <class Impl> 4731755SN/AFullO3CPU<Impl>::~FullO3CPU() 4741060SN/A{ 4751060SN/A} 4761060SN/A 4771060SN/Atemplate <class Impl> 4781060SN/Avoid 4795595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4801062SN/A{ 4812733Sktlim@umich.edu BaseO3CPU::regStats(); 4822292SN/A 4832733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4842292SN/A timesIdled 4852292SN/A .name(name() + ".timesIdled") 4862292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4872292SN/A " unscheduled itself") 4882292SN/A .prereq(timesIdled); 4892292SN/A 4902292SN/A idleCycles 4912292SN/A .name(name() + ".idleCycles") 4922292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4932292SN/A "to idling") 4942292SN/A .prereq(idleCycles); 4952292SN/A 4968627SAli.Saidi@ARM.com quiesceCycles 4978627SAli.Saidi@ARM.com .name(name() + ".quiesceCycles") 4988627SAli.Saidi@ARM.com .desc("Total number of cycles that CPU has spent quiesced or waiting " 4998627SAli.Saidi@ARM.com "for an interrupt") 5008627SAli.Saidi@ARM.com .prereq(quiesceCycles); 5018627SAli.Saidi@ARM.com 5022292SN/A // Number of Instructions simulated 5032292SN/A // -------------------------------- 5042292SN/A // Should probably be in Base CPU but need templated 5052292SN/A // MaxThreads so put in here instead 5062292SN/A committedInsts 5072292SN/A .init(numThreads) 5082292SN/A .name(name() + ".committedInsts") 5092292SN/A .desc("Number of Instructions Simulated"); 5102292SN/A 5118834Satgutier@umich.edu committedOps 5128834Satgutier@umich.edu .init(numThreads) 5138834Satgutier@umich.edu .name(name() + ".committedOps") 5148834Satgutier@umich.edu .desc("Number of Ops (including micro ops) Simulated"); 5158834Satgutier@umich.edu 5162292SN/A totalCommittedInsts 5172292SN/A .name(name() + ".committedInsts_total") 5182292SN/A .desc("Number of Instructions Simulated"); 5192292SN/A 5202292SN/A cpi 5212292SN/A .name(name() + ".cpi") 5222292SN/A .desc("CPI: Cycles Per Instruction") 5232292SN/A .precision(6); 5244392Sktlim@umich.edu cpi = numCycles / committedInsts; 5252292SN/A 5262292SN/A totalCpi 5272292SN/A .name(name() + ".cpi_total") 5282292SN/A .desc("CPI: Total CPI of All Threads") 5292292SN/A .precision(6); 5304392Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 5312292SN/A 5322292SN/A ipc 5332292SN/A .name(name() + ".ipc") 5342292SN/A .desc("IPC: Instructions Per Cycle") 5352292SN/A .precision(6); 5364392Sktlim@umich.edu ipc = committedInsts / numCycles; 5372292SN/A 5382292SN/A totalIpc 5392292SN/A .name(name() + ".ipc_total") 5402292SN/A .desc("IPC: Total IPC of All Threads") 5412292SN/A .precision(6); 5424392Sktlim@umich.edu totalIpc = totalCommittedInsts / numCycles; 5432292SN/A 5445595Sgblack@eecs.umich.edu this->fetch.regStats(); 5455595Sgblack@eecs.umich.edu this->decode.regStats(); 5465595Sgblack@eecs.umich.edu this->rename.regStats(); 5475595Sgblack@eecs.umich.edu this->iew.regStats(); 5485595Sgblack@eecs.umich.edu this->commit.regStats(); 5497897Shestness@cs.utexas.edu this->rob.regStats(); 5507897Shestness@cs.utexas.edu 5517897Shestness@cs.utexas.edu intRegfileReads 5527897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 5537897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 5547897Shestness@cs.utexas.edu .prereq(intRegfileReads); 5557897Shestness@cs.utexas.edu 5567897Shestness@cs.utexas.edu intRegfileWrites 5577897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 5587897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 5597897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 5607897Shestness@cs.utexas.edu 5617897Shestness@cs.utexas.edu fpRegfileReads 5627897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 5637897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 5647897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 5657897Shestness@cs.utexas.edu 5667897Shestness@cs.utexas.edu fpRegfileWrites 5677897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 5687897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 5697897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 5707897Shestness@cs.utexas.edu 5717897Shestness@cs.utexas.edu miscRegfileReads 5727897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5737897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5747897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5757897Shestness@cs.utexas.edu 5767897Shestness@cs.utexas.edu miscRegfileWrites 5777897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5787897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5797897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5801062SN/A} 5811062SN/A 5821062SN/Atemplate <class Impl> 5831062SN/Avoid 5841755SN/AFullO3CPU<Impl>::tick() 5851060SN/A{ 5862733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5879444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 5889444SAndreas.Sandberg@ARM.com assert(getDrainState() != Drainable::Drained); 5891060SN/A 5902292SN/A ++numCycles; 5912292SN/A 5922325SN/A// activity = false; 5932292SN/A 5942292SN/A //Tick each of the stages 5951060SN/A fetch.tick(); 5961060SN/A 5971060SN/A decode.tick(); 5981060SN/A 5991060SN/A rename.tick(); 6001060SN/A 6011060SN/A iew.tick(); 6021060SN/A 6031060SN/A commit.tick(); 6041060SN/A 6058793Sgblack@eecs.umich.edu if (!FullSystem) 6068793Sgblack@eecs.umich.edu doContextSwitch(); 6072292SN/A 6082292SN/A // Now advance the time buffers 6091060SN/A timeBuffer.advance(); 6101060SN/A 6111060SN/A fetchQueue.advance(); 6121060SN/A decodeQueue.advance(); 6131060SN/A renameQueue.advance(); 6141060SN/A iewQueue.advance(); 6151060SN/A 6162325SN/A activityRec.advance(); 6172292SN/A 6182292SN/A if (removeInstsThisCycle) { 6192292SN/A cleanUpRemovedInsts(); 6202292SN/A } 6212292SN/A 6222325SN/A if (!tickEvent.scheduled()) { 6239444SAndreas.Sandberg@ARM.com if (_status == SwitchedOut) { 6243226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 6252325SN/A // increment stat 6269179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 6273221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 6283226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 6299179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 6302325SN/A timesIdled++; 6312325SN/A } else { 6329180Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(Cycles(1))); 6333226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 6342325SN/A } 6352292SN/A } 6362292SN/A 6378793Sgblack@eecs.umich.edu if (!FullSystem) 6388793Sgblack@eecs.umich.edu updateThreadPriority(); 6399444SAndreas.Sandberg@ARM.com 6409444SAndreas.Sandberg@ARM.com tryDrain(); 6411060SN/A} 6421060SN/A 6431060SN/Atemplate <class Impl> 6441060SN/Avoid 6451755SN/AFullO3CPU<Impl>::init() 6461060SN/A{ 6475714Shsul@eecs.umich.edu BaseCPU::init(); 6481060SN/A 6498921Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 6509382SAli.Saidi@ARM.com // Set noSquashFromTC so that the CPU doesn't squash when initially 6518921Sandreas.hansson@arm.com // setting up registers. 6529382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = true; 6538921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 6548921Sandreas.hansson@arm.com thread[tid]->initMemProxies(thread[tid]->getTC()); 6558921Sandreas.hansson@arm.com } 6562292SN/A 6579433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 6588793Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 6598793Sgblack@eecs.umich.edu ThreadContext *src_tc = threadContexts[tid]; 6608793Sgblack@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 6618793Sgblack@eecs.umich.edu } 6626034Ssteve.reinhardt@amd.com } 6632292SN/A 6649382SAli.Saidi@ARM.com // Clear noSquashFromTC. 6656221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6669382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6672292SN/A 6689427SAndreas.Sandberg@ARM.com commit.setThreads(thread); 6699427SAndreas.Sandberg@ARM.com} 6702292SN/A 6719427SAndreas.Sandberg@ARM.comtemplate <class Impl> 6729427SAndreas.Sandberg@ARM.comvoid 6739427SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::startup() 6749427SAndreas.Sandberg@ARM.com{ 6759461Snilay@cs.wisc.edu for (int tid = 0; tid < numThreads; ++tid) 6769461Snilay@cs.wisc.edu isa[tid]->startup(threadContexts[tid]); 6779461Snilay@cs.wisc.edu 6789427SAndreas.Sandberg@ARM.com fetch.startupStage(); 6799444SAndreas.Sandberg@ARM.com decode.startupStage(); 6809427SAndreas.Sandberg@ARM.com iew.startupStage(); 6819427SAndreas.Sandberg@ARM.com rename.startupStage(); 6829427SAndreas.Sandberg@ARM.com commit.startupStage(); 6832292SN/A} 6842292SN/A 6852292SN/Atemplate <class Impl> 6862292SN/Avoid 6876221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 6882875Sksewell@umich.edu{ 6896221Snate@binkert.org list<ThreadID>::iterator isActive = 6905314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6912875Sksewell@umich.edu 6923226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6939444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 6943226Sktlim@umich.edu 6952875Sksewell@umich.edu if (isActive == activeThreads.end()) { 6962875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6972875Sksewell@umich.edu tid); 6982875Sksewell@umich.edu 6992875Sksewell@umich.edu activeThreads.push_back(tid); 7002875Sksewell@umich.edu } 7012875Sksewell@umich.edu} 7022875Sksewell@umich.edu 7032875Sksewell@umich.edutemplate <class Impl> 7042875Sksewell@umich.eduvoid 7056221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 7062875Sksewell@umich.edu{ 7072875Sksewell@umich.edu //Remove From Active List, if Active 7086221Snate@binkert.org list<ThreadID>::iterator thread_it = 7095314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 7102875Sksewell@umich.edu 7113226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 7129444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 7133226Sktlim@umich.edu 7142875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 7152875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 7162875Sksewell@umich.edu tid); 7172875Sksewell@umich.edu activeThreads.erase(thread_it); 7182875Sksewell@umich.edu } 7192875Sksewell@umich.edu} 7202875Sksewell@umich.edu 7212875Sksewell@umich.edutemplate <class Impl> 7226221Snate@binkert.orgCounter 7238834Satgutier@umich.eduFullO3CPU<Impl>::totalInsts() const 7246221Snate@binkert.org{ 7256221Snate@binkert.org Counter total(0); 7266221Snate@binkert.org 7276221Snate@binkert.org ThreadID size = thread.size(); 7286221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 7296221Snate@binkert.org total += thread[i]->numInst; 7306221Snate@binkert.org 7316221Snate@binkert.org return total; 7326221Snate@binkert.org} 7336221Snate@binkert.org 7346221Snate@binkert.orgtemplate <class Impl> 7358834Satgutier@umich.eduCounter 7368834Satgutier@umich.eduFullO3CPU<Impl>::totalOps() const 7378834Satgutier@umich.edu{ 7388834Satgutier@umich.edu Counter total(0); 7398834Satgutier@umich.edu 7408834Satgutier@umich.edu ThreadID size = thread.size(); 7418834Satgutier@umich.edu for (ThreadID i = 0; i < size; i++) 7428834Satgutier@umich.edu total += thread[i]->numOp; 7438834Satgutier@umich.edu 7448834Satgutier@umich.edu return total; 7458834Satgutier@umich.edu} 7468834Satgutier@umich.edu 7478834Satgutier@umich.edutemplate <class Impl> 7482875Sksewell@umich.eduvoid 7499180Sandreas.hansson@arm.comFullO3CPU<Impl>::activateContext(ThreadID tid, Cycles delay) 7502875Sksewell@umich.edu{ 7519444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 7529444SAndreas.Sandberg@ARM.com 7532875Sksewell@umich.edu // Needs to set each stage to running as well. 7542875Sksewell@umich.edu if (delay){ 7552875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 7569180Sandreas.hansson@arm.com "on cycle %d\n", tid, clockEdge(delay)); 7572875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 7582875Sksewell@umich.edu } else { 7592875Sksewell@umich.edu activateThread(tid); 7602875Sksewell@umich.edu } 7612875Sksewell@umich.edu 7629444SAndreas.Sandberg@ARM.com // We don't want to wake the CPU if it is drained. In that case, 7639444SAndreas.Sandberg@ARM.com // we just want to flag the thread as active and schedule the tick 7649444SAndreas.Sandberg@ARM.com // event from drainResume() instead. 7659444SAndreas.Sandberg@ARM.com if (getDrainState() == Drainable::Drained) 7669444SAndreas.Sandberg@ARM.com return; 7679444SAndreas.Sandberg@ARM.com 7689158Sandreas.hansson@arm.com // If we are time 0 or if the last activation time is in the past, 7699158Sandreas.hansson@arm.com // schedule the next tick and wake up the fetch unit 7709158Sandreas.hansson@arm.com if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) { 7712875Sksewell@umich.edu scheduleTickEvent(delay); 7722875Sksewell@umich.edu 7732875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 7742875Sksewell@umich.edu // deschedule itself. 7752875Sksewell@umich.edu activityRec.activity(); 7762875Sksewell@umich.edu fetch.wakeFromQuiesce(); 7772875Sksewell@umich.edu 7789180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 7799180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 7809179Sandreas.hansson@arm.com if (cycles != 0) 7819179Sandreas.hansson@arm.com --cycles; 7829179Sandreas.hansson@arm.com quiesceCycles += cycles; 7838627SAli.Saidi@ARM.com 7847823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 7852875Sksewell@umich.edu 7862875Sksewell@umich.edu _status = Running; 7872875Sksewell@umich.edu } 7882875Sksewell@umich.edu} 7892875Sksewell@umich.edu 7902875Sksewell@umich.edutemplate <class Impl> 7913221Sktlim@umich.edubool 7928737Skoansin.tan@gmail.comFullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove, 7939180Sandreas.hansson@arm.com Cycles delay) 7942875Sksewell@umich.edu{ 7952875Sksewell@umich.edu // Schedule removal of thread data from CPU 7962875Sksewell@umich.edu if (delay){ 7972875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 7989180Sandreas.hansson@arm.com "on tick %d\n", tid, clockEdge(delay)); 7993221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 8003221Sktlim@umich.edu return false; 8012875Sksewell@umich.edu } else { 8022875Sksewell@umich.edu deactivateThread(tid); 8033221Sktlim@umich.edu if (remove) 8043221Sktlim@umich.edu removeThread(tid); 8053221Sktlim@umich.edu return true; 8062875Sksewell@umich.edu } 8072875Sksewell@umich.edu} 8082875Sksewell@umich.edu 8092875Sksewell@umich.edutemplate <class Impl> 8102875Sksewell@umich.eduvoid 8116221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 8122875Sksewell@umich.edu{ 8132875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 8149444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 8159180Sandreas.hansson@arm.com bool deallocated = scheduleDeallocateContext(tid, false, Cycles(1)); 8163221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 8175570Snate@binkert.org if ((activeThreads.size() == 1 && !deallocated) || 8183859Sbinkertn@umich.edu activeThreads.size() == 0) 8192910Sksewell@umich.edu unscheduleTickEvent(); 8208627SAli.Saidi@ARM.com 8218627SAli.Saidi@ARM.com DPRINTF(Quiesce, "Suspending Context\n"); 8229179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 8232875Sksewell@umich.edu _status = Idle; 8242875Sksewell@umich.edu} 8252875Sksewell@umich.edu 8262875Sksewell@umich.edutemplate <class Impl> 8272875Sksewell@umich.eduvoid 8286221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 8292875Sksewell@umich.edu{ 8302910Sksewell@umich.edu //For now, this is the same as deallocate 8312910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 8329444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 8339180Sandreas.hansson@arm.com scheduleDeallocateContext(tid, true, Cycles(1)); 8342875Sksewell@umich.edu} 8352875Sksewell@umich.edu 8362875Sksewell@umich.edutemplate <class Impl> 8372875Sksewell@umich.eduvoid 8386221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 8392292SN/A{ 8402847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 8412292SN/A // Will change now that the PC and thread state is internal to the CPU 8422683Sktlim@umich.edu // and not in the ThreadContext. 8438793Sgblack@eecs.umich.edu ThreadContext *src_tc; 8448793Sgblack@eecs.umich.edu if (FullSystem) 8458793Sgblack@eecs.umich.edu src_tc = system->threadContexts[tid]; 8468793Sgblack@eecs.umich.edu else 8478793Sgblack@eecs.umich.edu src_tc = tcBase(tid); 8482292SN/A 8492292SN/A //Bind Int Regs to Rename Map 8502292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 8512292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 8522292SN/A 8532292SN/A renameMap[tid].setEntry(ireg,phys_reg); 8542292SN/A scoreboard.setReg(phys_reg); 8552292SN/A } 8562292SN/A 8572292SN/A //Bind Float Regs to Rename Map 8582292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 8592292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 8602292SN/A 8612292SN/A renameMap[tid].setEntry(freg,phys_reg); 8622292SN/A scoreboard.setReg(phys_reg); 8632292SN/A } 8642292SN/A 8652292SN/A //Copy Thread Data Into RegFile 8662847Sksewell@umich.edu //this->copyFromTC(tid); 8672292SN/A 8682847Sksewell@umich.edu //Set PC/NPC/NNPC 8697720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 8702292SN/A 8712680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 8722292SN/A 8739180Sandreas.hansson@arm.com activateContext(tid, Cycles(1)); 8742292SN/A 8752292SN/A //Reset ROB/IQ/LSQ Entries 8762292SN/A commit.rob->resetEntries(); 8772292SN/A iew.resetEntries(); 8782292SN/A} 8792292SN/A 8802292SN/Atemplate <class Impl> 8812292SN/Avoid 8826221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 8832292SN/A{ 8842877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 8852847Sksewell@umich.edu 8862847Sksewell@umich.edu // Copy Thread Data From RegFile 8872847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 8885364Sksewell@umich.edu // this->copyToTC(tid); 8895364Sksewell@umich.edu 8905364Sksewell@umich.edu 8915364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 8925364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 8935364Sksewell@umich.edu // in SMT workloads. 8942847Sksewell@umich.edu 8952847Sksewell@umich.edu // Unbind Int Regs from Rename Map 8962292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 8972292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 8982292SN/A 8992292SN/A scoreboard.unsetReg(phys_reg); 9002292SN/A freeList.addReg(phys_reg); 9012292SN/A } 9022292SN/A 9032847Sksewell@umich.edu // Unbind Float Regs from Rename Map 9045362Sksewell@umich.edu for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 9052292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 9062292SN/A 9072292SN/A scoreboard.unsetReg(phys_reg); 9082292SN/A freeList.addReg(phys_reg); 9092292SN/A } 9102292SN/A 9112847Sksewell@umich.edu // Squash Throughout Pipeline 9128138SAli.Saidi@ARM.com DynInstPtr inst = commit.rob->readHeadInst(tid); 9138138SAli.Saidi@ARM.com InstSeqNum squash_seq_num = inst->seqNum; 9148138SAli.Saidi@ARM.com fetch.squash(0, squash_seq_num, inst, tid); 9152292SN/A decode.squash(tid); 9162935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 9172875Sksewell@umich.edu iew.squash(tid); 9185363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 9192935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 9202292SN/A 9215362Sksewell@umich.edu 9225362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 9232292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 9242292SN/A 9252847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 9263229Sktlim@umich.edu 9273229Sktlim@umich.edu // Commented out for now. This should be possible to do by 9283229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 9293229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 9303229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 9313229Sktlim@umich.edu/* 9322292SN/A if (activeThreads.size() >= 1) { 9332292SN/A commit.rob->resetEntries(); 9342292SN/A iew.resetEntries(); 9352292SN/A } 9363229Sktlim@umich.edu*/ 9372292SN/A} 9382292SN/A 9392292SN/A 9402292SN/Atemplate <class Impl> 9412292SN/Avoid 9426221Snate@binkert.orgFullO3CPU<Impl>::activateWhenReady(ThreadID tid) 9432292SN/A{ 9442733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 9452292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 9462292SN/A tid); 9472292SN/A 9482292SN/A bool ready = true; 9492292SN/A 9502292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 9512733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9522292SN/A "Phys. Int. Regs.\n", 9532292SN/A tid); 9542292SN/A ready = false; 9552292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 9562733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9572292SN/A "Phys. Float. Regs.\n", 9582292SN/A tid); 9592292SN/A ready = false; 9602292SN/A } else if (commit.rob->numFreeEntries() >= 9612292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 9622733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9632292SN/A "ROB entries.\n", 9642292SN/A tid); 9652292SN/A ready = false; 9662292SN/A } else if (iew.instQueue.numFreeEntries() >= 9672292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 9682733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9692292SN/A "IQ entries.\n", 9702292SN/A tid); 9712292SN/A ready = false; 9722292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 9732292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 9742733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9752292SN/A "LSQ entries.\n", 9762292SN/A tid); 9772292SN/A ready = false; 9782292SN/A } 9792292SN/A 9802292SN/A if (ready) { 9812292SN/A insertThread(tid); 9822292SN/A 9832292SN/A contextSwitch = false; 9842292SN/A 9852292SN/A cpuWaitList.remove(tid); 9862292SN/A } else { 9872292SN/A suspendContext(tid); 9882292SN/A 9892292SN/A //blocks fetch 9902292SN/A contextSwitch = true; 9912292SN/A 9922875Sksewell@umich.edu //@todo: dont always add to waitlist 9932292SN/A //do waitlist 9942292SN/A cpuWaitList.push_back(tid); 9951060SN/A } 9961060SN/A} 9971060SN/A 9984192Sktlim@umich.edutemplate <class Impl> 9995595Sgblack@eecs.umich.eduFault 10006221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 10015702Ssaidi@eecs.umich.edu{ 10025702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 10035702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 10045702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 10055702Ssaidi@eecs.umich.edu 10065702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 10075702Ssaidi@eecs.umich.edu 10085702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 10095702Ssaidi@eecs.umich.edu#endif 10105702Ssaidi@eecs.umich.edu return NoFault; 10115702Ssaidi@eecs.umich.edu} 10125702Ssaidi@eecs.umich.edu 10135702Ssaidi@eecs.umich.edutemplate <class Impl> 10145702Ssaidi@eecs.umich.edubool 10156221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 10165702Ssaidi@eecs.umich.edu{ 10175702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 10185702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 10195702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 10205702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 10215702Ssaidi@eecs.umich.edu 10225702Ssaidi@eecs.umich.edu switch (palFunc) { 10235702Ssaidi@eecs.umich.edu case PAL::halt: 10245702Ssaidi@eecs.umich.edu halt(); 10255702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 10265702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 10275702Ssaidi@eecs.umich.edu break; 10285702Ssaidi@eecs.umich.edu 10295702Ssaidi@eecs.umich.edu case PAL::bpt: 10305702Ssaidi@eecs.umich.edu case PAL::bugchk: 10315702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 10325702Ssaidi@eecs.umich.edu return false; 10335702Ssaidi@eecs.umich.edu break; 10345702Ssaidi@eecs.umich.edu } 10355702Ssaidi@eecs.umich.edu#endif 10365702Ssaidi@eecs.umich.edu return true; 10375702Ssaidi@eecs.umich.edu} 10385702Ssaidi@eecs.umich.edu 10395702Ssaidi@eecs.umich.edutemplate <class Impl> 10405702Ssaidi@eecs.umich.eduFault 10415595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 10425595Sgblack@eecs.umich.edu{ 10435595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 10445647Sgblack@eecs.umich.edu return this->interrupts->getInterrupt(this->threadContexts[0]); 10455595Sgblack@eecs.umich.edu} 10465595Sgblack@eecs.umich.edu 10475595Sgblack@eecs.umich.edutemplate <class Impl> 10485595Sgblack@eecs.umich.eduvoid 10495595Sgblack@eecs.umich.eduFullO3CPU<Impl>::processInterrupts(Fault interrupt) 10505595Sgblack@eecs.umich.edu{ 10515595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 10525595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 10535595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 10545595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 10555595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 10565595Sgblack@eecs.umich.edu 10575595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 10585647Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 10595595Sgblack@eecs.umich.edu 10605595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 10617684Sgblack@eecs.umich.edu this->trap(interrupt, 0, NULL); 10625595Sgblack@eecs.umich.edu} 10635595Sgblack@eecs.umich.edu 10641060SN/Atemplate <class Impl> 10652852Sktlim@umich.eduvoid 10667684Sgblack@eecs.umich.eduFullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst) 10675595Sgblack@eecs.umich.edu{ 10685595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 10697684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 10705595Sgblack@eecs.umich.edu} 10715595Sgblack@eecs.umich.edu 10725595Sgblack@eecs.umich.edutemplate <class Impl> 10735595Sgblack@eecs.umich.eduvoid 10746221Snate@binkert.orgFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 10755595Sgblack@eecs.umich.edu{ 10765595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 10775595Sgblack@eecs.umich.edu 10785595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 10795595Sgblack@eecs.umich.edu 10805595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 10815595Sgblack@eecs.umich.edu // instruction. 10825595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 10835595Sgblack@eecs.umich.edu 10845595Sgblack@eecs.umich.edu // Execute the actual syscall. 10855595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 10865595Sgblack@eecs.umich.edu 10875595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 10885595Sgblack@eecs.umich.edu // incrementing it. 10895595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 10905595Sgblack@eecs.umich.edu} 10915595Sgblack@eecs.umich.edu 10925595Sgblack@eecs.umich.edutemplate <class Impl> 10935595Sgblack@eecs.umich.eduvoid 10949448SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::serializeThread(std::ostream &os, ThreadID tid) 10952864Sktlim@umich.edu{ 10969448SAndreas.Sandberg@ARM.com thread[tid]->serialize(os); 10972864Sktlim@umich.edu} 10982864Sktlim@umich.edu 10992864Sktlim@umich.edutemplate <class Impl> 11002864Sktlim@umich.eduvoid 11019448SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::unserializeThread(Checkpoint *cp, const std::string §ion, 11029448SAndreas.Sandberg@ARM.com ThreadID tid) 11032864Sktlim@umich.edu{ 11049448SAndreas.Sandberg@ARM.com thread[tid]->unserialize(cp, section); 11052864Sktlim@umich.edu} 11062864Sktlim@umich.edu 11072864Sktlim@umich.edutemplate <class Impl> 11082905Sktlim@umich.eduunsigned int 11099342SAndreas.Sandberg@arm.comFullO3CPU<Impl>::drain(DrainManager *drain_manager) 11101060SN/A{ 11119444SAndreas.Sandberg@ARM.com // If the CPU isn't doing anything, then return immediately. 11129444SAndreas.Sandberg@ARM.com if (switchedOut()) { 11139444SAndreas.Sandberg@ARM.com setDrainState(Drainable::Drained); 11149444SAndreas.Sandberg@ARM.com return 0; 11159444SAndreas.Sandberg@ARM.com } 11163512Sktlim@umich.edu 11179444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Draining...\n"); 11189444SAndreas.Sandberg@ARM.com setDrainState(Drainable::Draining); 11193512Sktlim@umich.edu 11209444SAndreas.Sandberg@ARM.com // We only need to signal a drain to the commit stage as this 11219444SAndreas.Sandberg@ARM.com // initiates squashing controls the draining. Once the commit 11229444SAndreas.Sandberg@ARM.com // stage commits an instruction where it is safe to stop, it'll 11239444SAndreas.Sandberg@ARM.com // squash the rest of the instructions in the pipeline and force 11249444SAndreas.Sandberg@ARM.com // the fetch stage to stall. The pipeline will be drained once all 11259444SAndreas.Sandberg@ARM.com // in-flight instructions have retired. 11262843Sktlim@umich.edu commit.drain(); 11272325SN/A 11282325SN/A // Wake the CPU and record activity so everything can drain out if 11292863Sktlim@umich.edu // the CPU was not able to immediately drain. 11309444SAndreas.Sandberg@ARM.com if (!isDrained()) { 11319342SAndreas.Sandberg@arm.com drainManager = drain_manager; 11322843Sktlim@umich.edu 11332863Sktlim@umich.edu wakeCPU(); 11342863Sktlim@umich.edu activityRec.activity(); 11352852Sktlim@umich.edu 11369152Satgutier@umich.edu DPRINTF(Drain, "CPU not drained\n"); 11379152Satgutier@umich.edu 11382905Sktlim@umich.edu return 1; 11392863Sktlim@umich.edu } else { 11409444SAndreas.Sandberg@ARM.com setDrainState(Drainable::Drained); 11419444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU is already drained\n"); 11429444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 11439444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 11449444SAndreas.Sandberg@ARM.com 11459444SAndreas.Sandberg@ARM.com // Flush out any old data from the time buffers. In 11469444SAndreas.Sandberg@ARM.com // particular, there might be some data in flight from the 11479444SAndreas.Sandberg@ARM.com // fetch stage that isn't visible in any of the CPU buffers we 11489444SAndreas.Sandberg@ARM.com // test in isDrained(). 11499444SAndreas.Sandberg@ARM.com for (int i = 0; i < timeBuffer.getSize(); ++i) { 11509444SAndreas.Sandberg@ARM.com timeBuffer.advance(); 11519444SAndreas.Sandberg@ARM.com fetchQueue.advance(); 11529444SAndreas.Sandberg@ARM.com decodeQueue.advance(); 11539444SAndreas.Sandberg@ARM.com renameQueue.advance(); 11549444SAndreas.Sandberg@ARM.com iewQueue.advance(); 11559444SAndreas.Sandberg@ARM.com } 11569444SAndreas.Sandberg@ARM.com 11579444SAndreas.Sandberg@ARM.com drainSanityCheck(); 11582905Sktlim@umich.edu return 0; 11592863Sktlim@umich.edu } 11602316SN/A} 11612310SN/A 11622316SN/Atemplate <class Impl> 11639444SAndreas.Sandberg@ARM.combool 11649444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::tryDrain() 11659444SAndreas.Sandberg@ARM.com{ 11669444SAndreas.Sandberg@ARM.com if (!drainManager || !isDrained()) 11679444SAndreas.Sandberg@ARM.com return false; 11689444SAndreas.Sandberg@ARM.com 11699444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 11709444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 11719444SAndreas.Sandberg@ARM.com 11729444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 11739444SAndreas.Sandberg@ARM.com drainManager->signalDrainDone(); 11749444SAndreas.Sandberg@ARM.com drainManager = NULL; 11759444SAndreas.Sandberg@ARM.com 11769444SAndreas.Sandberg@ARM.com return true; 11779444SAndreas.Sandberg@ARM.com} 11789444SAndreas.Sandberg@ARM.com 11799444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11809444SAndreas.Sandberg@ARM.comvoid 11819444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::drainSanityCheck() const 11829444SAndreas.Sandberg@ARM.com{ 11839444SAndreas.Sandberg@ARM.com assert(isDrained()); 11849444SAndreas.Sandberg@ARM.com fetch.drainSanityCheck(); 11859444SAndreas.Sandberg@ARM.com decode.drainSanityCheck(); 11869444SAndreas.Sandberg@ARM.com rename.drainSanityCheck(); 11879444SAndreas.Sandberg@ARM.com iew.drainSanityCheck(); 11889444SAndreas.Sandberg@ARM.com commit.drainSanityCheck(); 11899444SAndreas.Sandberg@ARM.com} 11909444SAndreas.Sandberg@ARM.com 11919444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11929444SAndreas.Sandberg@ARM.combool 11939444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::isDrained() const 11949444SAndreas.Sandberg@ARM.com{ 11959444SAndreas.Sandberg@ARM.com bool drained(true); 11969444SAndreas.Sandberg@ARM.com 11979444SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < thread.size(); ++i) { 11989444SAndreas.Sandberg@ARM.com if (activateThreadEvent[i].scheduled()) { 11999444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU not drained, tread %i has a " 12009444SAndreas.Sandberg@ARM.com "pending activate event\n", i); 12019444SAndreas.Sandberg@ARM.com drained = false; 12029444SAndreas.Sandberg@ARM.com } 12039444SAndreas.Sandberg@ARM.com if (deallocateContextEvent[i].scheduled()) { 12049444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU not drained, tread %i has a " 12059444SAndreas.Sandberg@ARM.com "pending deallocate context event\n", i); 12069444SAndreas.Sandberg@ARM.com drained = false; 12079444SAndreas.Sandberg@ARM.com } 12089444SAndreas.Sandberg@ARM.com } 12099444SAndreas.Sandberg@ARM.com 12109444SAndreas.Sandberg@ARM.com if (!instList.empty() || !removeList.empty()) { 12119444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Main CPU structures not drained.\n"); 12129444SAndreas.Sandberg@ARM.com drained = false; 12139444SAndreas.Sandberg@ARM.com } 12149444SAndreas.Sandberg@ARM.com 12159444SAndreas.Sandberg@ARM.com if (!fetch.isDrained()) { 12169444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Fetch not drained.\n"); 12179444SAndreas.Sandberg@ARM.com drained = false; 12189444SAndreas.Sandberg@ARM.com } 12199444SAndreas.Sandberg@ARM.com 12209444SAndreas.Sandberg@ARM.com if (!decode.isDrained()) { 12219444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Decode not drained.\n"); 12229444SAndreas.Sandberg@ARM.com drained = false; 12239444SAndreas.Sandberg@ARM.com } 12249444SAndreas.Sandberg@ARM.com 12259444SAndreas.Sandberg@ARM.com if (!rename.isDrained()) { 12269444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Rename not drained.\n"); 12279444SAndreas.Sandberg@ARM.com drained = false; 12289444SAndreas.Sandberg@ARM.com } 12299444SAndreas.Sandberg@ARM.com 12309444SAndreas.Sandberg@ARM.com if (!iew.isDrained()) { 12319444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "IEW not drained.\n"); 12329444SAndreas.Sandberg@ARM.com drained = false; 12339444SAndreas.Sandberg@ARM.com } 12349444SAndreas.Sandberg@ARM.com 12359444SAndreas.Sandberg@ARM.com if (!commit.isDrained()) { 12369444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Commit not drained.\n"); 12379444SAndreas.Sandberg@ARM.com drained = false; 12389444SAndreas.Sandberg@ARM.com } 12399444SAndreas.Sandberg@ARM.com 12409444SAndreas.Sandberg@ARM.com return drained; 12419444SAndreas.Sandberg@ARM.com} 12429444SAndreas.Sandberg@ARM.com 12439444SAndreas.Sandberg@ARM.comtemplate <class Impl> 12449444SAndreas.Sandberg@ARM.comvoid 12459444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::commitDrained(ThreadID tid) 12469444SAndreas.Sandberg@ARM.com{ 12479444SAndreas.Sandberg@ARM.com fetch.drainStall(tid); 12489444SAndreas.Sandberg@ARM.com} 12499444SAndreas.Sandberg@ARM.com 12509444SAndreas.Sandberg@ARM.comtemplate <class Impl> 12512316SN/Avoid 12529342SAndreas.Sandberg@arm.comFullO3CPU<Impl>::drainResume() 12532316SN/A{ 12549444SAndreas.Sandberg@ARM.com setDrainState(Drainable::Running); 12559444SAndreas.Sandberg@ARM.com if (switchedOut()) 12569444SAndreas.Sandberg@ARM.com return; 12572316SN/A 12589444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Resuming...\n"); 12599523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 12603319Shsul@eecs.umich.edu 12619444SAndreas.Sandberg@ARM.com fetch.drainResume(); 12629444SAndreas.Sandberg@ARM.com commit.drainResume(); 12632316SN/A 12649444SAndreas.Sandberg@ARM.com _status = Idle; 12659444SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < thread.size(); i++) { 12669444SAndreas.Sandberg@ARM.com if (thread[i]->status() == ThreadContext::Active) { 12679444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Activating thread: %i\n", i); 12689444SAndreas.Sandberg@ARM.com activateThread(i); 12699444SAndreas.Sandberg@ARM.com _status = Running; 12702863Sktlim@umich.edu } 12712310SN/A } 12729444SAndreas.Sandberg@ARM.com 12739444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 12749444SAndreas.Sandberg@ARM.com if (_status == Running) 12759444SAndreas.Sandberg@ARM.com schedule(tickEvent, nextCycle()); 12762843Sktlim@umich.edu} 12772843Sktlim@umich.edu 12782843Sktlim@umich.edutemplate <class Impl> 12792843Sktlim@umich.eduvoid 12802843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 12812843Sktlim@umich.edu{ 12829444SAndreas.Sandberg@ARM.com DPRINTF(O3CPU, "Switching out\n"); 12839429SAndreas.Sandberg@ARM.com BaseCPU::switchOut(); 12849429SAndreas.Sandberg@ARM.com 12859444SAndreas.Sandberg@ARM.com activityRec.reset(); 12862843Sktlim@umich.edu 12872843Sktlim@umich.edu _status = SwitchedOut; 12888887Sgeoffrey.blake@arm.com 12892843Sktlim@umich.edu if (checker) 12902843Sktlim@umich.edu checker->switchOut(); 12911060SN/A} 12921060SN/A 12931060SN/Atemplate <class Impl> 12941060SN/Avoid 12951755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 12961060SN/A{ 12978737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 12981060SN/A 12992307SN/A fetch.takeOverFrom(); 13002307SN/A decode.takeOverFrom(); 13012307SN/A rename.takeOverFrom(); 13022307SN/A iew.takeOverFrom(); 13032307SN/A commit.takeOverFrom(); 13042307SN/A 13059444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 13061060SN/A 13079152Satgutier@umich.edu FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU); 13089152Satgutier@umich.edu if (oldO3CPU) 13099152Satgutier@umich.edu globalSeqNum = oldO3CPU->globalSeqNum; 13109152Satgutier@umich.edu 13119179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 13129444SAndreas.Sandberg@ARM.com _status = Idle; 13131060SN/A} 13141060SN/A 13151060SN/Atemplate <class Impl> 13169523SAndreas.Sandberg@ARM.comvoid 13179523SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::verifyMemoryMode() const 13189523SAndreas.Sandberg@ARM.com{ 13199524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 13209523SAndreas.Sandberg@ARM.com fatal("The O3 CPU requires the memory system to be in " 13219523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 13229523SAndreas.Sandberg@ARM.com } 13239523SAndreas.Sandberg@ARM.com} 13249523SAndreas.Sandberg@ARM.com 13259523SAndreas.Sandberg@ARM.comtemplate <class Impl> 13265595Sgblack@eecs.umich.eduTheISA::MiscReg 13276221Snate@binkert.orgFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) 13285595Sgblack@eecs.umich.edu{ 13299384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscRegNoEffect(misc_reg); 13305595Sgblack@eecs.umich.edu} 13315595Sgblack@eecs.umich.edu 13325595Sgblack@eecs.umich.edutemplate <class Impl> 13335595Sgblack@eecs.umich.eduTheISA::MiscReg 13346221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 13355595Sgblack@eecs.umich.edu{ 13367897Shestness@cs.utexas.edu miscRegfileReads++; 13379384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); 13385595Sgblack@eecs.umich.edu} 13395595Sgblack@eecs.umich.edu 13405595Sgblack@eecs.umich.edutemplate <class Impl> 13415595Sgblack@eecs.umich.eduvoid 13425595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 13436221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 13445595Sgblack@eecs.umich.edu{ 13459384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscRegNoEffect(misc_reg, val); 13465595Sgblack@eecs.umich.edu} 13475595Sgblack@eecs.umich.edu 13485595Sgblack@eecs.umich.edutemplate <class Impl> 13495595Sgblack@eecs.umich.eduvoid 13505595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 13516221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 13525595Sgblack@eecs.umich.edu{ 13537897Shestness@cs.utexas.edu miscRegfileWrites++; 13549384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); 13555595Sgblack@eecs.umich.edu} 13565595Sgblack@eecs.umich.edu 13575595Sgblack@eecs.umich.edutemplate <class Impl> 13581060SN/Auint64_t 13591755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 13601060SN/A{ 13617897Shestness@cs.utexas.edu intRegfileReads++; 13621060SN/A return regFile.readIntReg(reg_idx); 13631060SN/A} 13641060SN/A 13651060SN/Atemplate <class Impl> 13662455SN/AFloatReg 13672455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 13681060SN/A{ 13697897Shestness@cs.utexas.edu fpRegfileReads++; 13702455SN/A return regFile.readFloatReg(reg_idx); 13711060SN/A} 13721060SN/A 13731060SN/Atemplate <class Impl> 13742455SN/AFloatRegBits 13752455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 13762455SN/A{ 13777897Shestness@cs.utexas.edu fpRegfileReads++; 13782455SN/A return regFile.readFloatRegBits(reg_idx); 13791060SN/A} 13801060SN/A 13811060SN/Atemplate <class Impl> 13821060SN/Avoid 13831755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 13841060SN/A{ 13857897Shestness@cs.utexas.edu intRegfileWrites++; 13861060SN/A regFile.setIntReg(reg_idx, val); 13871060SN/A} 13881060SN/A 13891060SN/Atemplate <class Impl> 13901060SN/Avoid 13912455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 13921060SN/A{ 13937897Shestness@cs.utexas.edu fpRegfileWrites++; 13942455SN/A regFile.setFloatReg(reg_idx, val); 13951060SN/A} 13961060SN/A 13971060SN/Atemplate <class Impl> 13981060SN/Avoid 13992455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 14002455SN/A{ 14017897Shestness@cs.utexas.edu fpRegfileWrites++; 14022455SN/A regFile.setFloatRegBits(reg_idx, val); 14031060SN/A} 14041060SN/A 14051060SN/Atemplate <class Impl> 14061060SN/Auint64_t 14076221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 14081060SN/A{ 14097897Shestness@cs.utexas.edu intRegfileReads++; 14102292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 14112292SN/A 14122292SN/A return regFile.readIntReg(phys_reg); 14132292SN/A} 14142292SN/A 14152292SN/Atemplate <class Impl> 14162292SN/Afloat 14176314Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 14182292SN/A{ 14197897Shestness@cs.utexas.edu fpRegfileReads++; 14206032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 14212307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 14222292SN/A 14232669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 14242292SN/A} 14252292SN/A 14262292SN/Atemplate <class Impl> 14272292SN/Auint64_t 14286221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 14292292SN/A{ 14307897Shestness@cs.utexas.edu fpRegfileReads++; 14316032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 14322307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 14332292SN/A 14342669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 14351060SN/A} 14361060SN/A 14371060SN/Atemplate <class Impl> 14381060SN/Avoid 14396221Snate@binkert.orgFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 14401060SN/A{ 14417897Shestness@cs.utexas.edu intRegfileWrites++; 14422292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 14432292SN/A 14442292SN/A regFile.setIntReg(phys_reg, val); 14451060SN/A} 14461060SN/A 14471060SN/Atemplate <class Impl> 14481060SN/Avoid 14496314Sgblack@eecs.umich.eduFullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 14501060SN/A{ 14517897Shestness@cs.utexas.edu fpRegfileWrites++; 14526032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 14532918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 14542292SN/A 14552669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 14561060SN/A} 14571060SN/A 14581060SN/Atemplate <class Impl> 14591060SN/Avoid 14606221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 14611060SN/A{ 14627897Shestness@cs.utexas.edu fpRegfileWrites++; 14636032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 14642918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 14651060SN/A 14662669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 14672292SN/A} 14682292SN/A 14692292SN/Atemplate <class Impl> 14707720Sgblack@eecs.umich.eduTheISA::PCState 14717720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 14722292SN/A{ 14737720Sgblack@eecs.umich.edu return commit.pcState(tid); 14741060SN/A} 14751060SN/A 14761060SN/Atemplate <class Impl> 14771060SN/Avoid 14787720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 14791060SN/A{ 14807720Sgblack@eecs.umich.edu commit.pcState(val, tid); 14812292SN/A} 14821060SN/A 14832292SN/Atemplate <class Impl> 14847720Sgblack@eecs.umich.eduAddr 14857720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 14864636Sgblack@eecs.umich.edu{ 14877720Sgblack@eecs.umich.edu return commit.instAddr(tid); 14884636Sgblack@eecs.umich.edu} 14894636Sgblack@eecs.umich.edu 14904636Sgblack@eecs.umich.edutemplate <class Impl> 14917720Sgblack@eecs.umich.eduAddr 14927720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 14934636Sgblack@eecs.umich.edu{ 14947720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 14954636Sgblack@eecs.umich.edu} 14964636Sgblack@eecs.umich.edu 14974636Sgblack@eecs.umich.edutemplate <class Impl> 14987720Sgblack@eecs.umich.eduMicroPC 14997720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 15002292SN/A{ 15017720Sgblack@eecs.umich.edu return commit.microPC(tid); 15024636Sgblack@eecs.umich.edu} 15034636Sgblack@eecs.umich.edu 15044636Sgblack@eecs.umich.edutemplate <class Impl> 15055595Sgblack@eecs.umich.eduvoid 15066221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 15075595Sgblack@eecs.umich.edu{ 15089382SAli.Saidi@ARM.com this->thread[tid]->noSquashFromTC = true; 15095595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 15105595Sgblack@eecs.umich.edu} 15115595Sgblack@eecs.umich.edu 15125595Sgblack@eecs.umich.edutemplate <class Impl> 15132292SN/Atypename FullO3CPU<Impl>::ListIt 15142292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 15152292SN/A{ 15162292SN/A instList.push_back(inst); 15171060SN/A 15182292SN/A return --(instList.end()); 15192292SN/A} 15201060SN/A 15212292SN/Atemplate <class Impl> 15222292SN/Avoid 15238834Satgutier@umich.eduFullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst) 15242292SN/A{ 15252292SN/A // Keep an instruction count. 15268834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) { 15278834Satgutier@umich.edu thread[tid]->numInst++; 15288834Satgutier@umich.edu thread[tid]->numInsts++; 15298834Satgutier@umich.edu committedInsts[tid]++; 15308834Satgutier@umich.edu totalCommittedInsts++; 15318834Satgutier@umich.edu } 15328834Satgutier@umich.edu thread[tid]->numOp++; 15338834Satgutier@umich.edu thread[tid]->numOps++; 15348834Satgutier@umich.edu committedOps[tid]++; 15358834Satgutier@umich.edu 15367897Shestness@cs.utexas.edu system->totalNumInsts++; 15372292SN/A // Check for instruction-count-based events. 15382292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 15397897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 15402292SN/A} 15412292SN/A 15422292SN/Atemplate <class Impl> 15432292SN/Avoid 15441755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 15451060SN/A{ 15467720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 15472292SN/A "[sn:%lli]\n", 15487720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 15491060SN/A 15502292SN/A removeInstsThisCycle = true; 15511060SN/A 15521060SN/A // Remove the front instruction. 15532292SN/A removeList.push(inst->getInstListIt()); 15541060SN/A} 15551060SN/A 15561060SN/Atemplate <class Impl> 15571060SN/Avoid 15586221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 15591060SN/A{ 15602733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 15612292SN/A " list.\n", tid); 15621060SN/A 15632292SN/A ListIt end_it; 15641060SN/A 15652292SN/A bool rob_empty = false; 15662292SN/A 15672292SN/A if (instList.empty()) { 15682292SN/A return; 15692292SN/A } else if (rob.isEmpty(/*tid*/)) { 15702733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 15712292SN/A end_it = instList.begin(); 15722292SN/A rob_empty = true; 15732292SN/A } else { 15742292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 15752733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 15762292SN/A } 15772292SN/A 15782292SN/A removeInstsThisCycle = true; 15792292SN/A 15802292SN/A ListIt inst_it = instList.end(); 15812292SN/A 15822292SN/A inst_it--; 15832292SN/A 15842292SN/A // Walk through the instruction list, removing any instructions 15852292SN/A // that were inserted after the given instruction iterator, end_it. 15862292SN/A while (inst_it != end_it) { 15872292SN/A assert(!instList.empty()); 15882292SN/A 15892292SN/A squashInstIt(inst_it, tid); 15902292SN/A 15912292SN/A inst_it--; 15922292SN/A } 15932292SN/A 15942292SN/A // If the ROB was empty, then we actually need to remove the first 15952292SN/A // instruction as well. 15962292SN/A if (rob_empty) { 15972292SN/A squashInstIt(inst_it, tid); 15982292SN/A } 15991060SN/A} 16001060SN/A 16011060SN/Atemplate <class Impl> 16021060SN/Avoid 16036221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 16041062SN/A{ 16052292SN/A assert(!instList.empty()); 16062292SN/A 16072292SN/A removeInstsThisCycle = true; 16082292SN/A 16092292SN/A ListIt inst_iter = instList.end(); 16102292SN/A 16112292SN/A inst_iter--; 16122292SN/A 16132733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 16142292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 16152292SN/A tid, seq_num, (*inst_iter)->seqNum); 16161062SN/A 16172292SN/A while ((*inst_iter)->seqNum > seq_num) { 16181062SN/A 16192292SN/A bool break_loop = (inst_iter == instList.begin()); 16201062SN/A 16212292SN/A squashInstIt(inst_iter, tid); 16221062SN/A 16232292SN/A inst_iter--; 16241062SN/A 16252292SN/A if (break_loop) 16262292SN/A break; 16272292SN/A } 16282292SN/A} 16292292SN/A 16302292SN/Atemplate <class Impl> 16312292SN/Ainline void 16326221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 16332292SN/A{ 16342292SN/A if ((*instIt)->threadNumber == tid) { 16352733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 16367720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 16372292SN/A (*instIt)->threadNumber, 16382292SN/A (*instIt)->seqNum, 16397720Sgblack@eecs.umich.edu (*instIt)->pcState()); 16401062SN/A 16411062SN/A // Mark it as squashed. 16422292SN/A (*instIt)->setSquashed(); 16432292SN/A 16442325SN/A // @todo: Formulate a consistent method for deleting 16452325SN/A // instructions from the instruction list 16462292SN/A // Remove the instruction from the list. 16472292SN/A removeList.push(instIt); 16482292SN/A } 16492292SN/A} 16502292SN/A 16512292SN/Atemplate <class Impl> 16522292SN/Avoid 16532292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 16542292SN/A{ 16552292SN/A while (!removeList.empty()) { 16562733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 16577720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 16582292SN/A (*removeList.front())->threadNumber, 16592292SN/A (*removeList.front())->seqNum, 16607720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 16612292SN/A 16622292SN/A instList.erase(removeList.front()); 16632292SN/A 16642292SN/A removeList.pop(); 16651062SN/A } 16661062SN/A 16672292SN/A removeInstsThisCycle = false; 16681062SN/A} 16692325SN/A/* 16701062SN/Atemplate <class Impl> 16711062SN/Avoid 16721755SN/AFullO3CPU<Impl>::removeAllInsts() 16731060SN/A{ 16741060SN/A instList.clear(); 16751060SN/A} 16762325SN/A*/ 16771060SN/Atemplate <class Impl> 16781060SN/Avoid 16791755SN/AFullO3CPU<Impl>::dumpInsts() 16801060SN/A{ 16811060SN/A int num = 0; 16821060SN/A 16832292SN/A ListIt inst_list_it = instList.begin(); 16842292SN/A 16852292SN/A cprintf("Dumping Instruction List\n"); 16862292SN/A 16872292SN/A while (inst_list_it != instList.end()) { 16882292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 16892292SN/A "Squashed:%i\n\n", 16907720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 16912292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 16922292SN/A (*inst_list_it)->isSquashed()); 16931060SN/A inst_list_it++; 16941060SN/A ++num; 16951060SN/A } 16961060SN/A} 16972325SN/A/* 16981060SN/Atemplate <class Impl> 16991060SN/Avoid 17001755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 17011060SN/A{ 17021060SN/A iew.wakeDependents(inst); 17031060SN/A} 17042325SN/A*/ 17052292SN/Atemplate <class Impl> 17062292SN/Avoid 17072292SN/AFullO3CPU<Impl>::wakeCPU() 17082292SN/A{ 17092325SN/A if (activityRec.active() || tickEvent.scheduled()) { 17102325SN/A DPRINTF(Activity, "CPU already running.\n"); 17112292SN/A return; 17122292SN/A } 17132292SN/A 17142325SN/A DPRINTF(Activity, "Waking up CPU\n"); 17152325SN/A 17169180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 17179180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 17189179Sandreas.hansson@arm.com if (cycles != 0) 17199179Sandreas.hansson@arm.com --cycles; 17209179Sandreas.hansson@arm.com idleCycles += cycles; 17219179Sandreas.hansson@arm.com numCycles += cycles; 17222292SN/A 17239648Sdam.sunwoo@arm.com schedule(tickEvent, clockEdge()); 17242292SN/A} 17252292SN/A 17265807Snate@binkert.orgtemplate <class Impl> 17275807Snate@binkert.orgvoid 17285807Snate@binkert.orgFullO3CPU<Impl>::wakeup() 17295807Snate@binkert.org{ 17305807Snate@binkert.org if (this->thread[0]->status() != ThreadContext::Suspended) 17315807Snate@binkert.org return; 17325807Snate@binkert.org 17335807Snate@binkert.org this->wakeCPU(); 17345807Snate@binkert.org 17355807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 17365807Snate@binkert.org this->threadContexts[0]->activate(); 17375807Snate@binkert.org} 17385807Snate@binkert.org 17392292SN/Atemplate <class Impl> 17406221Snate@binkert.orgThreadID 17412292SN/AFullO3CPU<Impl>::getFreeTid() 17422292SN/A{ 17436221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 17446221Snate@binkert.org if (!tids[tid]) { 17456221Snate@binkert.org tids[tid] = true; 17466221Snate@binkert.org return tid; 17472292SN/A } 17482292SN/A } 17492292SN/A 17506221Snate@binkert.org return InvalidThreadID; 17512292SN/A} 17522292SN/A 17532292SN/Atemplate <class Impl> 17542292SN/Avoid 17552292SN/AFullO3CPU<Impl>::doContextSwitch() 17562292SN/A{ 17572292SN/A if (contextSwitch) { 17582292SN/A 17592292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 17602292SN/A 17616221Snate@binkert.org ThreadID size = cpuWaitList.size(); 17626221Snate@binkert.org for (ThreadID tid = 0; tid < size; tid++) { 17632292SN/A activateWhenReady(tid); 17642292SN/A } 17652292SN/A 17662292SN/A if (cpuWaitList.size() == 0) 17672292SN/A contextSwitch = true; 17682292SN/A } 17692292SN/A} 17702292SN/A 17712292SN/Atemplate <class Impl> 17722292SN/Avoid 17732292SN/AFullO3CPU<Impl>::updateThreadPriority() 17742292SN/A{ 17756221Snate@binkert.org if (activeThreads.size() > 1) { 17762292SN/A //DEFAULT TO ROUND ROBIN SCHEME 17772292SN/A //e.g. Move highest priority to end of thread list 17786221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 17792292SN/A 17802292SN/A unsigned high_thread = *list_begin; 17812292SN/A 17822292SN/A activeThreads.erase(list_begin); 17832292SN/A 17842292SN/A activeThreads.push_back(high_thread); 17852292SN/A } 17862292SN/A} 17871060SN/A 17881755SN/A// Forward declaration of FullO3CPU. 17892818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1790