cpu.cc revision 9428
11689SN/A/* 28948Sandreas.hansson@arm.com * Copyright (c) 2011-2012 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 142325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422756Sksewell@umich.edu * Korey Sewell 437897Shestness@cs.utexas.edu * Rick Strong 441689SN/A */ 451689SN/A 468779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 498887Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 508229Snate@binkert.org#include "cpu/o3/cpu.hh" 518229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 528229Snate@binkert.org#include "cpu/o3/thread_context.hh" 534762Snate@binkert.org#include "cpu/activity.hh" 548779Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 554762Snate@binkert.org#include "cpu/simple_thread.hh" 564762Snate@binkert.org#include "cpu/thread_context.hh" 578232Snate@binkert.org#include "debug/Activity.hh" 589152Satgutier@umich.edu#include "debug/Drain.hh" 598232Snate@binkert.org#include "debug/O3CPU.hh" 608232Snate@binkert.org#include "debug/Quiesce.hh" 614762Snate@binkert.org#include "enums/MemoryMode.hh" 624762Snate@binkert.org#include "sim/core.hh" 638793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 648779Sgblack@eecs.umich.edu#include "sim/process.hh" 654762Snate@binkert.org#include "sim/stat_control.hh" 668460SAli.Saidi@ARM.com#include "sim/system.hh" 674762Snate@binkert.org 685702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 695702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 708232Snate@binkert.org#include "debug/Activity.hh" 715702Ssaidi@eecs.umich.edu#endif 725702Ssaidi@eecs.umich.edu 738737Skoansin.tan@gmail.comstruct BaseCPUParams; 745529Snate@binkert.org 752669Sktlim@umich.eduusing namespace TheISA; 766221Snate@binkert.orgusing namespace std; 771060SN/A 785529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 795712Shsul@eecs.umich.edu : BaseCPU(params) 801060SN/A{ 811060SN/A} 821060SN/A 832292SN/Avoid 842733Sktlim@umich.eduBaseO3CPU::regStats() 852292SN/A{ 862292SN/A BaseCPU::regStats(); 872292SN/A} 882292SN/A 898707Sandreas.hansson@arm.comtemplate<class Impl> 908707Sandreas.hansson@arm.combool 918975Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt) 928707Sandreas.hansson@arm.com{ 938707Sandreas.hansson@arm.com DPRINTF(O3CPU, "Fetch unit received timing\n"); 948948Sandreas.hansson@arm.com // We shouldn't ever get a block in ownership state 958948Sandreas.hansson@arm.com assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); 968948Sandreas.hansson@arm.com fetch->processCacheCompletion(pkt); 978707Sandreas.hansson@arm.com 988707Sandreas.hansson@arm.com return true; 998707Sandreas.hansson@arm.com} 1008707Sandreas.hansson@arm.com 1018707Sandreas.hansson@arm.comtemplate<class Impl> 1028707Sandreas.hansson@arm.comvoid 1038707Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvRetry() 1048707Sandreas.hansson@arm.com{ 1058707Sandreas.hansson@arm.com fetch->recvRetry(); 1068707Sandreas.hansson@arm.com} 1078707Sandreas.hansson@arm.com 1088707Sandreas.hansson@arm.comtemplate <class Impl> 1098707Sandreas.hansson@arm.combool 1108975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt) 1118707Sandreas.hansson@arm.com{ 1128975Sandreas.hansson@arm.com return lsq->recvTimingResp(pkt); 1138707Sandreas.hansson@arm.com} 1148707Sandreas.hansson@arm.com 1158707Sandreas.hansson@arm.comtemplate <class Impl> 1168975Sandreas.hansson@arm.comvoid 1178975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 1188948Sandreas.hansson@arm.com{ 1198975Sandreas.hansson@arm.com lsq->recvTimingSnoopReq(pkt); 1208948Sandreas.hansson@arm.com} 1218948Sandreas.hansson@arm.com 1228948Sandreas.hansson@arm.comtemplate <class Impl> 1238707Sandreas.hansson@arm.comvoid 1248707Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvRetry() 1258707Sandreas.hansson@arm.com{ 1268707Sandreas.hansson@arm.com lsq->recvRetry(); 1278707Sandreas.hansson@arm.com} 1288707Sandreas.hansson@arm.com 1291060SN/Atemplate <class Impl> 1301755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 1315606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 1321060SN/A{ 1331060SN/A} 1341060SN/A 1351060SN/Atemplate <class Impl> 1361060SN/Avoid 1371755SN/AFullO3CPU<Impl>::TickEvent::process() 1381060SN/A{ 1391060SN/A cpu->tick(); 1401060SN/A} 1411060SN/A 1421060SN/Atemplate <class Impl> 1431060SN/Aconst char * 1445336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 1451060SN/A{ 1464873Sstever@eecs.umich.edu return "FullO3CPU tick"; 1471060SN/A} 1481060SN/A 1491060SN/Atemplate <class Impl> 1502829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 1515606Snate@binkert.org : Event(CPU_Switch_Pri) 1522829Sksewell@umich.edu{ 1532829Sksewell@umich.edu} 1542829Sksewell@umich.edu 1552829Sksewell@umich.edutemplate <class Impl> 1562829Sksewell@umich.eduvoid 1572829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 1582829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1592829Sksewell@umich.edu{ 1602829Sksewell@umich.edu tid = thread_num; 1612829Sksewell@umich.edu cpu = thread_cpu; 1622829Sksewell@umich.edu} 1632829Sksewell@umich.edu 1642829Sksewell@umich.edutemplate <class Impl> 1652829Sksewell@umich.eduvoid 1662829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1672829Sksewell@umich.edu{ 1682829Sksewell@umich.edu cpu->activateThread(tid); 1692829Sksewell@umich.edu} 1702829Sksewell@umich.edu 1712829Sksewell@umich.edutemplate <class Impl> 1722829Sksewell@umich.educonst char * 1735336Shines@cs.fsu.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1742829Sksewell@umich.edu{ 1754873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1762829Sksewell@umich.edu} 1772829Sksewell@umich.edu 1782829Sksewell@umich.edutemplate <class Impl> 1792875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1805606Snate@binkert.org : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1812875Sksewell@umich.edu{ 1822875Sksewell@umich.edu} 1832875Sksewell@umich.edu 1842875Sksewell@umich.edutemplate <class Impl> 1852875Sksewell@umich.eduvoid 1862875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1873859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1882875Sksewell@umich.edu{ 1892875Sksewell@umich.edu tid = thread_num; 1902875Sksewell@umich.edu cpu = thread_cpu; 1913859Sbinkertn@umich.edu remove = false; 1922875Sksewell@umich.edu} 1932875Sksewell@umich.edu 1942875Sksewell@umich.edutemplate <class Impl> 1952875Sksewell@umich.eduvoid 1962875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1972875Sksewell@umich.edu{ 1982875Sksewell@umich.edu cpu->deactivateThread(tid); 1993221Sktlim@umich.edu if (remove) 2003221Sktlim@umich.edu cpu->removeThread(tid); 2012875Sksewell@umich.edu} 2022875Sksewell@umich.edu 2032875Sksewell@umich.edutemplate <class Impl> 2042875Sksewell@umich.educonst char * 2055336Shines@cs.fsu.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 2062875Sksewell@umich.edu{ 2074873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 2082875Sksewell@umich.edu} 2092875Sksewell@umich.edu 2102875Sksewell@umich.edutemplate <class Impl> 2115595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 2122733Sktlim@umich.edu : BaseO3CPU(params), 2133781Sgblack@eecs.umich.edu itb(params->itb), 2143781Sgblack@eecs.umich.edu dtb(params->dtb), 2151060SN/A tickEvent(this), 2165737Scws3k@cs.virginia.edu#ifndef NDEBUG 2175737Scws3k@cs.virginia.edu instcount(0), 2185737Scws3k@cs.virginia.edu#endif 2192292SN/A removeInstsThisCycle(false), 2205595Sgblack@eecs.umich.edu fetch(this, params), 2215595Sgblack@eecs.umich.edu decode(this, params), 2225595Sgblack@eecs.umich.edu rename(this, params), 2235595Sgblack@eecs.umich.edu iew(this, params), 2245595Sgblack@eecs.umich.edu commit(this, params), 2251060SN/A 2265595Sgblack@eecs.umich.edu regFile(this, params->numPhysIntRegs, 2274329Sktlim@umich.edu params->numPhysFloatRegs), 2281060SN/A 2295529Snate@binkert.org freeList(params->numThreads, 2302292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 2312292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 2321060SN/A 2335595Sgblack@eecs.umich.edu rob(this, 2344329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 2352292SN/A params->smtROBPolicy, params->smtROBThreshold, 2365529Snate@binkert.org params->numThreads), 2371060SN/A 2385529Snate@binkert.org scoreboard(params->numThreads, 2392292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 2402292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 2416221Snate@binkert.org TheISA::NumMiscRegs * numThreads, 2422292SN/A TheISA::ZeroReg), 2431060SN/A 2449384SAndreas.Sandberg@arm.com isa(numThreads, NULL), 2459384SAndreas.Sandberg@arm.com 2468707Sandreas.hansson@arm.com icachePort(&fetch, this), 2478707Sandreas.hansson@arm.com dcachePort(&iew.ldstQueue, this), 2488707Sandreas.hansson@arm.com 2492873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 2502873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 2512873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 2522873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 2532873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 2545804Snate@binkert.org activityRec(name(), NumStages, 2552873Sktlim@umich.edu params->backComSize + params->forwardComSize, 2562873Sktlim@umich.edu params->activity), 2571060SN/A 2581060SN/A globalSeqNum(1), 2592292SN/A system(params->system), 2602843Sktlim@umich.edu drainCount(0), 2619180Sandreas.hansson@arm.com deferRegistration(params->defer_registration), 2629180Sandreas.hansson@arm.com lastRunningCycle(curCycle()) 2631060SN/A{ 2643221Sktlim@umich.edu if (!deferRegistration) { 2653221Sktlim@umich.edu _status = Running; 2663221Sktlim@umich.edu } else { 2679152Satgutier@umich.edu _status = SwitchedOut; 2683221Sktlim@umich.edu } 2691681SN/A 2702794Sktlim@umich.edu if (params->checker) { 2712316SN/A BaseCPU *temp_checker = params->checker; 2728733Sgeoffrey.blake@arm.com checker = dynamic_cast<Checker<Impl> *>(temp_checker); 2738707Sandreas.hansson@arm.com checker->setIcachePort(&icachePort); 2742316SN/A checker->setSystem(params->system); 2754598Sbinkertn@umich.edu } else { 2764598Sbinkertn@umich.edu checker = NULL; 2774598Sbinkertn@umich.edu } 2782316SN/A 2798793Sgblack@eecs.umich.edu if (!FullSystem) { 2808793Sgblack@eecs.umich.edu thread.resize(numThreads); 2818793Sgblack@eecs.umich.edu tids.resize(numThreads); 2828793Sgblack@eecs.umich.edu } 2831681SN/A 2842325SN/A // The stages also need their CPU pointer setup. However this 2852325SN/A // must be done at the upper level CPU because they have pointers 2862325SN/A // to the upper level CPU, and not this FullO3CPU. 2871060SN/A 2882292SN/A // Set up Pointers to the activeThreads list for each stage 2892292SN/A fetch.setActiveThreads(&activeThreads); 2902292SN/A decode.setActiveThreads(&activeThreads); 2912292SN/A rename.setActiveThreads(&activeThreads); 2922292SN/A iew.setActiveThreads(&activeThreads); 2932292SN/A commit.setActiveThreads(&activeThreads); 2941060SN/A 2951060SN/A // Give each of the stages the time buffer they will use. 2961060SN/A fetch.setTimeBuffer(&timeBuffer); 2971060SN/A decode.setTimeBuffer(&timeBuffer); 2981060SN/A rename.setTimeBuffer(&timeBuffer); 2991060SN/A iew.setTimeBuffer(&timeBuffer); 3001060SN/A commit.setTimeBuffer(&timeBuffer); 3011060SN/A 3021060SN/A // Also setup each of the stages' queues. 3031060SN/A fetch.setFetchQueue(&fetchQueue); 3041060SN/A decode.setFetchQueue(&fetchQueue); 3052292SN/A commit.setFetchQueue(&fetchQueue); 3061060SN/A decode.setDecodeQueue(&decodeQueue); 3071060SN/A rename.setDecodeQueue(&decodeQueue); 3081060SN/A rename.setRenameQueue(&renameQueue); 3091060SN/A iew.setRenameQueue(&renameQueue); 3101060SN/A iew.setIEWQueue(&iewQueue); 3111060SN/A commit.setIEWQueue(&iewQueue); 3121060SN/A commit.setRenameQueue(&renameQueue); 3131060SN/A 3142292SN/A commit.setIEWStage(&iew); 3152292SN/A rename.setIEWStage(&iew); 3162292SN/A rename.setCommitStage(&commit); 3172292SN/A 3188793Sgblack@eecs.umich.edu ThreadID active_threads; 3198793Sgblack@eecs.umich.edu if (FullSystem) { 3208793Sgblack@eecs.umich.edu active_threads = 1; 3218793Sgblack@eecs.umich.edu } else { 3228793Sgblack@eecs.umich.edu active_threads = params->workload.size(); 3232831Sksewell@umich.edu 3248793Sgblack@eecs.umich.edu if (active_threads > Impl::MaxThreads) { 3258793Sgblack@eecs.umich.edu panic("Workload Size too large. Increase the 'MaxThreads' " 3268793Sgblack@eecs.umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 3278793Sgblack@eecs.umich.edu "or edit your workload size."); 3288793Sgblack@eecs.umich.edu } 3292831Sksewell@umich.edu } 3302292SN/A 3312316SN/A //Make Sure That this a Valid Architeture 3322292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 3332292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 3342292SN/A 3352292SN/A rename.setScoreboard(&scoreboard); 3362292SN/A iew.setScoreboard(&scoreboard); 3372292SN/A 3381060SN/A // Setup the rename map for whichever stages need it. 3392292SN/A PhysRegIndex lreg_idx = 0; 3402292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 3411060SN/A 3426221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3432307SN/A bool bindRegs = (tid <= active_threads - 1); 3442292SN/A 3459384SAndreas.Sandberg@arm.com isa[tid] = params->isa[tid]; 3469384SAndreas.Sandberg@arm.com 3472292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 3482292SN/A params->numPhysIntRegs, 3492325SN/A lreg_idx, //Index for Logical. Regs 3502292SN/A 3512292SN/A TheISA::NumFloatRegs, 3522292SN/A params->numPhysFloatRegs, 3532325SN/A freg_idx, //Index for Float Regs 3542292SN/A 3552292SN/A TheISA::NumMiscRegs, 3562292SN/A 3572292SN/A TheISA::ZeroReg, 3582292SN/A TheISA::ZeroReg, 3592292SN/A 3602292SN/A tid, 3612292SN/A false); 3622292SN/A 3632292SN/A renameMap[tid].init(TheISA::NumIntRegs, 3642292SN/A params->numPhysIntRegs, 3652325SN/A lreg_idx, //Index for Logical. Regs 3662292SN/A 3672292SN/A TheISA::NumFloatRegs, 3682292SN/A params->numPhysFloatRegs, 3692325SN/A freg_idx, //Index for Float Regs 3702292SN/A 3712292SN/A TheISA::NumMiscRegs, 3722292SN/A 3732292SN/A TheISA::ZeroReg, 3742292SN/A TheISA::ZeroReg, 3752292SN/A 3762292SN/A tid, 3772292SN/A bindRegs); 3783221Sktlim@umich.edu 3793221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3803221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3812292SN/A } 3822292SN/A 3832292SN/A rename.setRenameMap(renameMap); 3842292SN/A commit.setRenameMap(commitRenameMap); 3852292SN/A 3862292SN/A // Give renameMap & rename stage access to the freeList; 3876221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3886221Snate@binkert.org renameMap[tid].setFreeList(&freeList); 3891060SN/A rename.setFreeList(&freeList); 3902292SN/A 3911060SN/A // Setup the ROB for whichever stages need it. 3921060SN/A commit.setROB(&rob); 3932292SN/A 3949158Sandreas.hansson@arm.com lastActivatedCycle = 0; 3956221Snate@binkert.org#if 0 3963093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3976221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3986221Snate@binkert.org globalSeqNum[tid] = 1; 3996221Snate@binkert.org#endif 4003093Sksewell@umich.edu 4012292SN/A contextSwitch = false; 4025595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 4035595Sgblack@eecs.umich.edu 4045595Sgblack@eecs.umich.edu // Setup any thread state. 4055595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 4065595Sgblack@eecs.umich.edu 4076221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 4088793Sgblack@eecs.umich.edu if (FullSystem) { 4098793Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 4108793Sgblack@eecs.umich.edu assert(this->numThreads == 1); 4118793Sgblack@eecs.umich.edu this->thread[tid] = new Thread(this, 0, NULL); 4128793Sgblack@eecs.umich.edu } else { 4138793Sgblack@eecs.umich.edu if (tid < params->workload.size()) { 4148793Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 4158793Sgblack@eecs.umich.edu tid, this->thread[tid]); 4168793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 4178793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 4188793Sgblack@eecs.umich.edu tid, params->workload[tid]); 4195595Sgblack@eecs.umich.edu 4208793Sgblack@eecs.umich.edu //usedTids[tid] = true; 4218793Sgblack@eecs.umich.edu //threadMap[tid] = tid; 4228793Sgblack@eecs.umich.edu } else { 4238793Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 4248793Sgblack@eecs.umich.edu //when scheduling threads to CPU 4258793Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 4265595Sgblack@eecs.umich.edu 4278793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 4288793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 4298793Sgblack@eecs.umich.edu tid, dummy_proc); 4308793Sgblack@eecs.umich.edu //usedTids[tid] = false; 4318793Sgblack@eecs.umich.edu } 4325595Sgblack@eecs.umich.edu } 4335595Sgblack@eecs.umich.edu 4345595Sgblack@eecs.umich.edu ThreadContext *tc; 4355595Sgblack@eecs.umich.edu 4365595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 4375595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 4385595Sgblack@eecs.umich.edu 4395595Sgblack@eecs.umich.edu tc = o3_tc; 4405595Sgblack@eecs.umich.edu 4415595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 4425595Sgblack@eecs.umich.edu // CheckerThreadContext. 4435595Sgblack@eecs.umich.edu if (params->checker) { 4445595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 4455595Sgblack@eecs.umich.edu o3_tc, this->checker); 4465595Sgblack@eecs.umich.edu } 4475595Sgblack@eecs.umich.edu 4485595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 4495595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 4506221Snate@binkert.org o3_tc->thread = this->thread[tid]; 4515595Sgblack@eecs.umich.edu 4528793Sgblack@eecs.umich.edu if (FullSystem) { 4538793Sgblack@eecs.umich.edu // Setup quiesce event. 4548793Sgblack@eecs.umich.edu this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 4558793Sgblack@eecs.umich.edu } 4565595Sgblack@eecs.umich.edu // Give the thread the TC. 4576221Snate@binkert.org this->thread[tid]->tc = tc; 4585595Sgblack@eecs.umich.edu 4595595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4605595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4615595Sgblack@eecs.umich.edu } 4625595Sgblack@eecs.umich.edu 4638876Sandreas.hansson@arm.com // FullO3CPU always requires an interrupt controller. 4648876Sandreas.hansson@arm.com if (!params->defer_registration && !interrupts) { 4658876Sandreas.hansson@arm.com fatal("FullO3CPU %s has no interrupt controller.\n" 4668876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 4678876Sandreas.hansson@arm.com } 4688876Sandreas.hansson@arm.com 4696221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4706221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4715595Sgblack@eecs.umich.edu 4725595Sgblack@eecs.umich.edu lockAddr = 0; 4735595Sgblack@eecs.umich.edu lockFlag = false; 4741060SN/A} 4751060SN/A 4761060SN/Atemplate <class Impl> 4771755SN/AFullO3CPU<Impl>::~FullO3CPU() 4781060SN/A{ 4791060SN/A} 4801060SN/A 4811060SN/Atemplate <class Impl> 4821060SN/Avoid 4835595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4841062SN/A{ 4852733Sktlim@umich.edu BaseO3CPU::regStats(); 4862292SN/A 4872733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4882292SN/A timesIdled 4892292SN/A .name(name() + ".timesIdled") 4902292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4912292SN/A " unscheduled itself") 4922292SN/A .prereq(timesIdled); 4932292SN/A 4942292SN/A idleCycles 4952292SN/A .name(name() + ".idleCycles") 4962292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4972292SN/A "to idling") 4982292SN/A .prereq(idleCycles); 4992292SN/A 5008627SAli.Saidi@ARM.com quiesceCycles 5018627SAli.Saidi@ARM.com .name(name() + ".quiesceCycles") 5028627SAli.Saidi@ARM.com .desc("Total number of cycles that CPU has spent quiesced or waiting " 5038627SAli.Saidi@ARM.com "for an interrupt") 5048627SAli.Saidi@ARM.com .prereq(quiesceCycles); 5058627SAli.Saidi@ARM.com 5062292SN/A // Number of Instructions simulated 5072292SN/A // -------------------------------- 5082292SN/A // Should probably be in Base CPU but need templated 5092292SN/A // MaxThreads so put in here instead 5102292SN/A committedInsts 5112292SN/A .init(numThreads) 5122292SN/A .name(name() + ".committedInsts") 5132292SN/A .desc("Number of Instructions Simulated"); 5142292SN/A 5158834Satgutier@umich.edu committedOps 5168834Satgutier@umich.edu .init(numThreads) 5178834Satgutier@umich.edu .name(name() + ".committedOps") 5188834Satgutier@umich.edu .desc("Number of Ops (including micro ops) Simulated"); 5198834Satgutier@umich.edu 5202292SN/A totalCommittedInsts 5212292SN/A .name(name() + ".committedInsts_total") 5222292SN/A .desc("Number of Instructions Simulated"); 5232292SN/A 5242292SN/A cpi 5252292SN/A .name(name() + ".cpi") 5262292SN/A .desc("CPI: Cycles Per Instruction") 5272292SN/A .precision(6); 5284392Sktlim@umich.edu cpi = numCycles / committedInsts; 5292292SN/A 5302292SN/A totalCpi 5312292SN/A .name(name() + ".cpi_total") 5322292SN/A .desc("CPI: Total CPI of All Threads") 5332292SN/A .precision(6); 5344392Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 5352292SN/A 5362292SN/A ipc 5372292SN/A .name(name() + ".ipc") 5382292SN/A .desc("IPC: Instructions Per Cycle") 5392292SN/A .precision(6); 5404392Sktlim@umich.edu ipc = committedInsts / numCycles; 5412292SN/A 5422292SN/A totalIpc 5432292SN/A .name(name() + ".ipc_total") 5442292SN/A .desc("IPC: Total IPC of All Threads") 5452292SN/A .precision(6); 5464392Sktlim@umich.edu totalIpc = totalCommittedInsts / numCycles; 5472292SN/A 5485595Sgblack@eecs.umich.edu this->fetch.regStats(); 5495595Sgblack@eecs.umich.edu this->decode.regStats(); 5505595Sgblack@eecs.umich.edu this->rename.regStats(); 5515595Sgblack@eecs.umich.edu this->iew.regStats(); 5525595Sgblack@eecs.umich.edu this->commit.regStats(); 5537897Shestness@cs.utexas.edu this->rob.regStats(); 5547897Shestness@cs.utexas.edu 5557897Shestness@cs.utexas.edu intRegfileReads 5567897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 5577897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 5587897Shestness@cs.utexas.edu .prereq(intRegfileReads); 5597897Shestness@cs.utexas.edu 5607897Shestness@cs.utexas.edu intRegfileWrites 5617897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 5627897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 5637897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 5647897Shestness@cs.utexas.edu 5657897Shestness@cs.utexas.edu fpRegfileReads 5667897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 5677897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 5687897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 5697897Shestness@cs.utexas.edu 5707897Shestness@cs.utexas.edu fpRegfileWrites 5717897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 5727897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 5737897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 5747897Shestness@cs.utexas.edu 5757897Shestness@cs.utexas.edu miscRegfileReads 5767897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5777897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5787897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5797897Shestness@cs.utexas.edu 5807897Shestness@cs.utexas.edu miscRegfileWrites 5817897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5827897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5837897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5841062SN/A} 5851062SN/A 5861062SN/Atemplate <class Impl> 5871062SN/Avoid 5881755SN/AFullO3CPU<Impl>::tick() 5891060SN/A{ 5902733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5911060SN/A 5922292SN/A ++numCycles; 5932292SN/A 5942325SN/A// activity = false; 5952292SN/A 5962292SN/A //Tick each of the stages 5971060SN/A fetch.tick(); 5981060SN/A 5991060SN/A decode.tick(); 6001060SN/A 6011060SN/A rename.tick(); 6021060SN/A 6031060SN/A iew.tick(); 6041060SN/A 6051060SN/A commit.tick(); 6061060SN/A 6078793Sgblack@eecs.umich.edu if (!FullSystem) 6088793Sgblack@eecs.umich.edu doContextSwitch(); 6092292SN/A 6102292SN/A // Now advance the time buffers 6111060SN/A timeBuffer.advance(); 6121060SN/A 6131060SN/A fetchQueue.advance(); 6141060SN/A decodeQueue.advance(); 6151060SN/A renameQueue.advance(); 6161060SN/A iewQueue.advance(); 6171060SN/A 6182325SN/A activityRec.advance(); 6192292SN/A 6202292SN/A if (removeInstsThisCycle) { 6212292SN/A cleanUpRemovedInsts(); 6222292SN/A } 6232292SN/A 6242325SN/A if (!tickEvent.scheduled()) { 6252867Sktlim@umich.edu if (_status == SwitchedOut || 6269342SAndreas.Sandberg@arm.com getDrainState() == Drainable::Drained) { 6273226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 6282325SN/A // increment stat 6299179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 6303221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 6313226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 6329179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 6332325SN/A timesIdled++; 6342325SN/A } else { 6359180Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(Cycles(1))); 6363226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 6372325SN/A } 6382292SN/A } 6392292SN/A 6408793Sgblack@eecs.umich.edu if (!FullSystem) 6418793Sgblack@eecs.umich.edu updateThreadPriority(); 6421060SN/A} 6431060SN/A 6441060SN/Atemplate <class Impl> 6451060SN/Avoid 6461755SN/AFullO3CPU<Impl>::init() 6471060SN/A{ 6485714Shsul@eecs.umich.edu BaseCPU::init(); 6491060SN/A 6509424SAndreas.Sandberg@ARM.com if (!params()->defer_registration && 6519424SAndreas.Sandberg@ARM.com system->getMemoryMode() != Enums::timing) { 6529424SAndreas.Sandberg@ARM.com fatal("The O3 CPU requires the memory system to be in " 6539424SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 6549424SAndreas.Sandberg@ARM.com } 6559424SAndreas.Sandberg@ARM.com 6568921Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 6579382SAli.Saidi@ARM.com // Set noSquashFromTC so that the CPU doesn't squash when initially 6588921Sandreas.hansson@arm.com // setting up registers. 6599382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = true; 6608921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 6618921Sandreas.hansson@arm.com thread[tid]->initMemProxies(thread[tid]->getTC()); 6628921Sandreas.hansson@arm.com } 6632292SN/A 6648707Sandreas.hansson@arm.com // this CPU could still be unconnected if we are restoring from a 6658707Sandreas.hansson@arm.com // checkpoint and this CPU is to be switched in, thus we can only 6668707Sandreas.hansson@arm.com // do this here if the instruction port is actually connected, if 6678707Sandreas.hansson@arm.com // not we have to do it as part of takeOverFrom 6688707Sandreas.hansson@arm.com if (icachePort.isConnected()) 6698707Sandreas.hansson@arm.com fetch.setIcache(); 6708707Sandreas.hansson@arm.com 6718863Snilay@cs.wisc.edu if (FullSystem && !params()->defer_registration) { 6728793Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 6738793Sgblack@eecs.umich.edu ThreadContext *src_tc = threadContexts[tid]; 6748793Sgblack@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 6758793Sgblack@eecs.umich.edu } 6766034Ssteve.reinhardt@amd.com } 6772292SN/A 6789382SAli.Saidi@ARM.com // Clear noSquashFromTC. 6796221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6809382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6812292SN/A 6829427SAndreas.Sandberg@ARM.com commit.setThreads(thread); 6839427SAndreas.Sandberg@ARM.com} 6842292SN/A 6859427SAndreas.Sandberg@ARM.comtemplate <class Impl> 6869427SAndreas.Sandberg@ARM.comvoid 6879427SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::startup() 6889427SAndreas.Sandberg@ARM.com{ 6899427SAndreas.Sandberg@ARM.com fetch.startupStage(); 6909427SAndreas.Sandberg@ARM.com iew.startupStage(); 6919427SAndreas.Sandberg@ARM.com rename.startupStage(); 6929427SAndreas.Sandberg@ARM.com commit.startupStage(); 6932292SN/A} 6942292SN/A 6952292SN/Atemplate <class Impl> 6962292SN/Avoid 6976221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 6982875Sksewell@umich.edu{ 6996221Snate@binkert.org list<ThreadID>::iterator isActive = 7005314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 7012875Sksewell@umich.edu 7023226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 7033226Sktlim@umich.edu 7042875Sksewell@umich.edu if (isActive == activeThreads.end()) { 7052875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 7062875Sksewell@umich.edu tid); 7072875Sksewell@umich.edu 7082875Sksewell@umich.edu activeThreads.push_back(tid); 7092875Sksewell@umich.edu } 7102875Sksewell@umich.edu} 7112875Sksewell@umich.edu 7122875Sksewell@umich.edutemplate <class Impl> 7132875Sksewell@umich.eduvoid 7146221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 7152875Sksewell@umich.edu{ 7162875Sksewell@umich.edu //Remove From Active List, if Active 7176221Snate@binkert.org list<ThreadID>::iterator thread_it = 7185314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 7192875Sksewell@umich.edu 7203226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 7213226Sktlim@umich.edu 7222875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 7232875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 7242875Sksewell@umich.edu tid); 7252875Sksewell@umich.edu activeThreads.erase(thread_it); 7262875Sksewell@umich.edu } 7272875Sksewell@umich.edu} 7282875Sksewell@umich.edu 7292875Sksewell@umich.edutemplate <class Impl> 7306221Snate@binkert.orgCounter 7318834Satgutier@umich.eduFullO3CPU<Impl>::totalInsts() const 7326221Snate@binkert.org{ 7336221Snate@binkert.org Counter total(0); 7346221Snate@binkert.org 7356221Snate@binkert.org ThreadID size = thread.size(); 7366221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 7376221Snate@binkert.org total += thread[i]->numInst; 7386221Snate@binkert.org 7396221Snate@binkert.org return total; 7406221Snate@binkert.org} 7416221Snate@binkert.org 7426221Snate@binkert.orgtemplate <class Impl> 7438834Satgutier@umich.eduCounter 7448834Satgutier@umich.eduFullO3CPU<Impl>::totalOps() const 7458834Satgutier@umich.edu{ 7468834Satgutier@umich.edu Counter total(0); 7478834Satgutier@umich.edu 7488834Satgutier@umich.edu ThreadID size = thread.size(); 7498834Satgutier@umich.edu for (ThreadID i = 0; i < size; i++) 7508834Satgutier@umich.edu total += thread[i]->numOp; 7518834Satgutier@umich.edu 7528834Satgutier@umich.edu return total; 7538834Satgutier@umich.edu} 7548834Satgutier@umich.edu 7558834Satgutier@umich.edutemplate <class Impl> 7562875Sksewell@umich.eduvoid 7579180Sandreas.hansson@arm.comFullO3CPU<Impl>::activateContext(ThreadID tid, Cycles delay) 7582875Sksewell@umich.edu{ 7592875Sksewell@umich.edu // Needs to set each stage to running as well. 7602875Sksewell@umich.edu if (delay){ 7612875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 7629180Sandreas.hansson@arm.com "on cycle %d\n", tid, clockEdge(delay)); 7632875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 7642875Sksewell@umich.edu } else { 7652875Sksewell@umich.edu activateThread(tid); 7662875Sksewell@umich.edu } 7672875Sksewell@umich.edu 7689158Sandreas.hansson@arm.com // If we are time 0 or if the last activation time is in the past, 7699158Sandreas.hansson@arm.com // schedule the next tick and wake up the fetch unit 7709158Sandreas.hansson@arm.com if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) { 7712875Sksewell@umich.edu scheduleTickEvent(delay); 7722875Sksewell@umich.edu 7732875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 7742875Sksewell@umich.edu // deschedule itself. 7752875Sksewell@umich.edu activityRec.activity(); 7762875Sksewell@umich.edu fetch.wakeFromQuiesce(); 7772875Sksewell@umich.edu 7789180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 7799180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 7809179Sandreas.hansson@arm.com if (cycles != 0) 7819179Sandreas.hansson@arm.com --cycles; 7829179Sandreas.hansson@arm.com quiesceCycles += cycles; 7838627SAli.Saidi@ARM.com 7847823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 7852875Sksewell@umich.edu 7862875Sksewell@umich.edu _status = Running; 7872875Sksewell@umich.edu } 7882875Sksewell@umich.edu} 7892875Sksewell@umich.edu 7902875Sksewell@umich.edutemplate <class Impl> 7913221Sktlim@umich.edubool 7928737Skoansin.tan@gmail.comFullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove, 7939180Sandreas.hansson@arm.com Cycles delay) 7942875Sksewell@umich.edu{ 7952875Sksewell@umich.edu // Schedule removal of thread data from CPU 7962875Sksewell@umich.edu if (delay){ 7972875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 7989180Sandreas.hansson@arm.com "on tick %d\n", tid, clockEdge(delay)); 7993221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 8003221Sktlim@umich.edu return false; 8012875Sksewell@umich.edu } else { 8022875Sksewell@umich.edu deactivateThread(tid); 8033221Sktlim@umich.edu if (remove) 8043221Sktlim@umich.edu removeThread(tid); 8053221Sktlim@umich.edu return true; 8062875Sksewell@umich.edu } 8072875Sksewell@umich.edu} 8082875Sksewell@umich.edu 8092875Sksewell@umich.edutemplate <class Impl> 8102875Sksewell@umich.eduvoid 8116221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 8122875Sksewell@umich.edu{ 8132875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 8149180Sandreas.hansson@arm.com bool deallocated = scheduleDeallocateContext(tid, false, Cycles(1)); 8153221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 8165570Snate@binkert.org if ((activeThreads.size() == 1 && !deallocated) || 8173859Sbinkertn@umich.edu activeThreads.size() == 0) 8182910Sksewell@umich.edu unscheduleTickEvent(); 8198627SAli.Saidi@ARM.com 8208627SAli.Saidi@ARM.com DPRINTF(Quiesce, "Suspending Context\n"); 8219179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 8222875Sksewell@umich.edu _status = Idle; 8232875Sksewell@umich.edu} 8242875Sksewell@umich.edu 8252875Sksewell@umich.edutemplate <class Impl> 8262875Sksewell@umich.eduvoid 8276221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 8282875Sksewell@umich.edu{ 8292910Sksewell@umich.edu //For now, this is the same as deallocate 8302910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 8319180Sandreas.hansson@arm.com scheduleDeallocateContext(tid, true, Cycles(1)); 8322875Sksewell@umich.edu} 8332875Sksewell@umich.edu 8342875Sksewell@umich.edutemplate <class Impl> 8352875Sksewell@umich.eduvoid 8366221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 8372292SN/A{ 8382847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 8392292SN/A // Will change now that the PC and thread state is internal to the CPU 8402683Sktlim@umich.edu // and not in the ThreadContext. 8418793Sgblack@eecs.umich.edu ThreadContext *src_tc; 8428793Sgblack@eecs.umich.edu if (FullSystem) 8438793Sgblack@eecs.umich.edu src_tc = system->threadContexts[tid]; 8448793Sgblack@eecs.umich.edu else 8458793Sgblack@eecs.umich.edu src_tc = tcBase(tid); 8462292SN/A 8472292SN/A //Bind Int Regs to Rename Map 8482292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 8492292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 8502292SN/A 8512292SN/A renameMap[tid].setEntry(ireg,phys_reg); 8522292SN/A scoreboard.setReg(phys_reg); 8532292SN/A } 8542292SN/A 8552292SN/A //Bind Float Regs to Rename Map 8562292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 8572292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 8582292SN/A 8592292SN/A renameMap[tid].setEntry(freg,phys_reg); 8602292SN/A scoreboard.setReg(phys_reg); 8612292SN/A } 8622292SN/A 8632292SN/A //Copy Thread Data Into RegFile 8642847Sksewell@umich.edu //this->copyFromTC(tid); 8652292SN/A 8662847Sksewell@umich.edu //Set PC/NPC/NNPC 8677720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 8682292SN/A 8692680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 8702292SN/A 8719180Sandreas.hansson@arm.com activateContext(tid, Cycles(1)); 8722292SN/A 8732292SN/A //Reset ROB/IQ/LSQ Entries 8742292SN/A commit.rob->resetEntries(); 8752292SN/A iew.resetEntries(); 8762292SN/A} 8772292SN/A 8782292SN/Atemplate <class Impl> 8792292SN/Avoid 8806221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 8812292SN/A{ 8822877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 8832847Sksewell@umich.edu 8842847Sksewell@umich.edu // Copy Thread Data From RegFile 8852847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 8865364Sksewell@umich.edu // this->copyToTC(tid); 8875364Sksewell@umich.edu 8885364Sksewell@umich.edu 8895364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 8905364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 8915364Sksewell@umich.edu // in SMT workloads. 8922847Sksewell@umich.edu 8932847Sksewell@umich.edu // Unbind Int Regs from Rename Map 8942292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 8952292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 8962292SN/A 8972292SN/A scoreboard.unsetReg(phys_reg); 8982292SN/A freeList.addReg(phys_reg); 8992292SN/A } 9002292SN/A 9012847Sksewell@umich.edu // Unbind Float Regs from Rename Map 9025362Sksewell@umich.edu for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 9032292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 9042292SN/A 9052292SN/A scoreboard.unsetReg(phys_reg); 9062292SN/A freeList.addReg(phys_reg); 9072292SN/A } 9082292SN/A 9092847Sksewell@umich.edu // Squash Throughout Pipeline 9108138SAli.Saidi@ARM.com DynInstPtr inst = commit.rob->readHeadInst(tid); 9118138SAli.Saidi@ARM.com InstSeqNum squash_seq_num = inst->seqNum; 9128138SAli.Saidi@ARM.com fetch.squash(0, squash_seq_num, inst, tid); 9132292SN/A decode.squash(tid); 9142935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 9152875Sksewell@umich.edu iew.squash(tid); 9165363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 9172935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 9182292SN/A 9195362Sksewell@umich.edu 9205362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 9212292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 9222292SN/A 9232847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 9243229Sktlim@umich.edu 9253229Sktlim@umich.edu // Commented out for now. This should be possible to do by 9263229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 9273229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 9283229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 9293229Sktlim@umich.edu/* 9302292SN/A if (activeThreads.size() >= 1) { 9312292SN/A commit.rob->resetEntries(); 9322292SN/A iew.resetEntries(); 9332292SN/A } 9343229Sktlim@umich.edu*/ 9352292SN/A} 9362292SN/A 9372292SN/A 9382292SN/Atemplate <class Impl> 9392292SN/Avoid 9406221Snate@binkert.orgFullO3CPU<Impl>::activateWhenReady(ThreadID tid) 9412292SN/A{ 9422733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 9432292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 9442292SN/A tid); 9452292SN/A 9462292SN/A bool ready = true; 9472292SN/A 9482292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 9492733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9502292SN/A "Phys. Int. Regs.\n", 9512292SN/A tid); 9522292SN/A ready = false; 9532292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 9542733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9552292SN/A "Phys. Float. Regs.\n", 9562292SN/A tid); 9572292SN/A ready = false; 9582292SN/A } else if (commit.rob->numFreeEntries() >= 9592292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 9602733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9612292SN/A "ROB entries.\n", 9622292SN/A tid); 9632292SN/A ready = false; 9642292SN/A } else if (iew.instQueue.numFreeEntries() >= 9652292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 9662733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9672292SN/A "IQ entries.\n", 9682292SN/A tid); 9692292SN/A ready = false; 9702292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 9712292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 9722733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9732292SN/A "LSQ entries.\n", 9742292SN/A tid); 9752292SN/A ready = false; 9762292SN/A } 9772292SN/A 9782292SN/A if (ready) { 9792292SN/A insertThread(tid); 9802292SN/A 9812292SN/A contextSwitch = false; 9822292SN/A 9832292SN/A cpuWaitList.remove(tid); 9842292SN/A } else { 9852292SN/A suspendContext(tid); 9862292SN/A 9872292SN/A //blocks fetch 9882292SN/A contextSwitch = true; 9892292SN/A 9902875Sksewell@umich.edu //@todo: dont always add to waitlist 9912292SN/A //do waitlist 9922292SN/A cpuWaitList.push_back(tid); 9931060SN/A } 9941060SN/A} 9951060SN/A 9964192Sktlim@umich.edutemplate <class Impl> 9975595Sgblack@eecs.umich.eduFault 9986221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 9995702Ssaidi@eecs.umich.edu{ 10005702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 10015702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 10025702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 10035702Ssaidi@eecs.umich.edu 10045702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 10055702Ssaidi@eecs.umich.edu 10065702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 10075702Ssaidi@eecs.umich.edu#endif 10085702Ssaidi@eecs.umich.edu return NoFault; 10095702Ssaidi@eecs.umich.edu} 10105702Ssaidi@eecs.umich.edu 10115702Ssaidi@eecs.umich.edutemplate <class Impl> 10125702Ssaidi@eecs.umich.edubool 10136221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 10145702Ssaidi@eecs.umich.edu{ 10155702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 10165702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 10175702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 10185702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 10195702Ssaidi@eecs.umich.edu 10205702Ssaidi@eecs.umich.edu switch (palFunc) { 10215702Ssaidi@eecs.umich.edu case PAL::halt: 10225702Ssaidi@eecs.umich.edu halt(); 10235702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 10245702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 10255702Ssaidi@eecs.umich.edu break; 10265702Ssaidi@eecs.umich.edu 10275702Ssaidi@eecs.umich.edu case PAL::bpt: 10285702Ssaidi@eecs.umich.edu case PAL::bugchk: 10295702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 10305702Ssaidi@eecs.umich.edu return false; 10315702Ssaidi@eecs.umich.edu break; 10325702Ssaidi@eecs.umich.edu } 10335702Ssaidi@eecs.umich.edu#endif 10345702Ssaidi@eecs.umich.edu return true; 10355702Ssaidi@eecs.umich.edu} 10365702Ssaidi@eecs.umich.edu 10375702Ssaidi@eecs.umich.edutemplate <class Impl> 10385702Ssaidi@eecs.umich.eduFault 10395595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 10405595Sgblack@eecs.umich.edu{ 10415595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 10425647Sgblack@eecs.umich.edu return this->interrupts->getInterrupt(this->threadContexts[0]); 10435595Sgblack@eecs.umich.edu} 10445595Sgblack@eecs.umich.edu 10455595Sgblack@eecs.umich.edutemplate <class Impl> 10465595Sgblack@eecs.umich.eduvoid 10475595Sgblack@eecs.umich.eduFullO3CPU<Impl>::processInterrupts(Fault interrupt) 10485595Sgblack@eecs.umich.edu{ 10495595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 10505595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 10515595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 10525595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 10535595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 10545595Sgblack@eecs.umich.edu 10555595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 10565647Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 10575595Sgblack@eecs.umich.edu 10585595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 10597684Sgblack@eecs.umich.edu this->trap(interrupt, 0, NULL); 10605595Sgblack@eecs.umich.edu} 10615595Sgblack@eecs.umich.edu 10621060SN/Atemplate <class Impl> 10632852Sktlim@umich.eduvoid 10647684Sgblack@eecs.umich.eduFullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst) 10655595Sgblack@eecs.umich.edu{ 10665595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 10677684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 10685595Sgblack@eecs.umich.edu} 10695595Sgblack@eecs.umich.edu 10705595Sgblack@eecs.umich.edutemplate <class Impl> 10715595Sgblack@eecs.umich.eduvoid 10726221Snate@binkert.orgFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 10735595Sgblack@eecs.umich.edu{ 10745595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 10755595Sgblack@eecs.umich.edu 10765595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 10775595Sgblack@eecs.umich.edu 10785595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 10795595Sgblack@eecs.umich.edu // instruction. 10805595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 10815595Sgblack@eecs.umich.edu 10825595Sgblack@eecs.umich.edu // Execute the actual syscall. 10835595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 10845595Sgblack@eecs.umich.edu 10855595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 10865595Sgblack@eecs.umich.edu // incrementing it. 10875595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 10885595Sgblack@eecs.umich.edu} 10895595Sgblack@eecs.umich.edu 10905595Sgblack@eecs.umich.edutemplate <class Impl> 10915595Sgblack@eecs.umich.eduvoid 10922864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 10932864Sktlim@umich.edu{ 10949342SAndreas.Sandberg@arm.com Drainable::State so_state(getDrainState()); 10952918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 10962864Sktlim@umich.edu BaseCPU::serialize(os); 10972864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 10982864Sktlim@umich.edu tickEvent.serialize(os); 10992864Sktlim@umich.edu 11009428SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < thread.size(); i++) { 11012864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 11029428SAndreas.Sandberg@ARM.com thread[i]->serialize(os); 11032864Sktlim@umich.edu } 11042864Sktlim@umich.edu} 11052864Sktlim@umich.edu 11062864Sktlim@umich.edutemplate <class Impl> 11072864Sktlim@umich.eduvoid 11082864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 11092864Sktlim@umich.edu{ 11109342SAndreas.Sandberg@arm.com Drainable::State so_state; 11112918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 11122864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 11132864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 11142864Sktlim@umich.edu 11159428SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < thread.size(); i++) { 11169428SAndreas.Sandberg@ARM.com thread[i]->unserialize(cp, 11179428SAndreas.Sandberg@ARM.com csprintf("%s.xc.%i", section, i)); 11189428SAndreas.Sandberg@ARM.com if (thread[i]->status() == ThreadContext::Active) 11199428SAndreas.Sandberg@ARM.com activateThread(i); 11202864Sktlim@umich.edu } 11212864Sktlim@umich.edu} 11222864Sktlim@umich.edu 11232864Sktlim@umich.edutemplate <class Impl> 11242905Sktlim@umich.eduunsigned int 11259342SAndreas.Sandberg@arm.comFullO3CPU<Impl>::drain(DrainManager *drain_manager) 11261060SN/A{ 11273125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 11283512Sktlim@umich.edu 11293512Sktlim@umich.edu // If the CPU isn't doing anything, then return immediately. 11309152Satgutier@umich.edu if (_status == SwitchedOut) 11313512Sktlim@umich.edu return 0; 11323512Sktlim@umich.edu 11332843Sktlim@umich.edu drainCount = 0; 11342843Sktlim@umich.edu fetch.drain(); 11352843Sktlim@umich.edu decode.drain(); 11362843Sktlim@umich.edu rename.drain(); 11372843Sktlim@umich.edu iew.drain(); 11382843Sktlim@umich.edu commit.drain(); 11392325SN/A 11402325SN/A // Wake the CPU and record activity so everything can drain out if 11412863Sktlim@umich.edu // the CPU was not able to immediately drain. 11429342SAndreas.Sandberg@arm.com if (getDrainState() != Drainable::Drained) { 11439342SAndreas.Sandberg@arm.com // A bit of a hack...set the drainManager after all the drain() 11442864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 11452864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 11462864Sktlim@umich.edu // process on the drain event. 11479342SAndreas.Sandberg@arm.com drainManager = drain_manager; 11482843Sktlim@umich.edu 11492863Sktlim@umich.edu wakeCPU(); 11502863Sktlim@umich.edu activityRec.activity(); 11512852Sktlim@umich.edu 11529152Satgutier@umich.edu DPRINTF(Drain, "CPU not drained\n"); 11539152Satgutier@umich.edu 11542905Sktlim@umich.edu return 1; 11552863Sktlim@umich.edu } else { 11562905Sktlim@umich.edu return 0; 11572863Sktlim@umich.edu } 11582316SN/A} 11592310SN/A 11602316SN/Atemplate <class Impl> 11612316SN/Avoid 11629342SAndreas.Sandberg@arm.comFullO3CPU<Impl>::drainResume() 11632316SN/A{ 11642843Sktlim@umich.edu fetch.resume(); 11652843Sktlim@umich.edu decode.resume(); 11662843Sktlim@umich.edu rename.resume(); 11672843Sktlim@umich.edu iew.resume(); 11682843Sktlim@umich.edu commit.resume(); 11692316SN/A 11709342SAndreas.Sandberg@arm.com setDrainState(Drainable::Running); 11712905Sktlim@umich.edu 11729152Satgutier@umich.edu if (_status == SwitchedOut) 11732864Sktlim@umich.edu return; 11742864Sktlim@umich.edu 11759424SAndreas.Sandberg@ARM.com if (system->getMemoryMode() != Enums::timing) { 11769424SAndreas.Sandberg@ARM.com fatal("The O3 CPU requires the memory system to be in " 11779424SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 11789424SAndreas.Sandberg@ARM.com } 11793319Shsul@eecs.umich.edu 11802843Sktlim@umich.edu if (!tickEvent.scheduled()) 11815606Snate@binkert.org schedule(tickEvent, nextCycle()); 11822843Sktlim@umich.edu _status = Running; 11832843Sktlim@umich.edu} 11842316SN/A 11852843Sktlim@umich.edutemplate <class Impl> 11862843Sktlim@umich.eduvoid 11872843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 11882843Sktlim@umich.edu{ 11892843Sktlim@umich.edu if (++drainCount == NumStages) { 11902316SN/A if (tickEvent.scheduled()) 11912316SN/A tickEvent.squash(); 11922863Sktlim@umich.edu 11939342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 11942863Sktlim@umich.edu 11953126Sktlim@umich.edu BaseCPU::switchOut(); 11963126Sktlim@umich.edu 11979342SAndreas.Sandberg@arm.com if (drainManager) { 11989152Satgutier@umich.edu DPRINTF(Drain, "CPU done draining, processing drain event\n"); 11999342SAndreas.Sandberg@arm.com drainManager->signalDrainDone(); 12009342SAndreas.Sandberg@arm.com drainManager = NULL; 12012863Sktlim@umich.edu } 12022310SN/A } 12032843Sktlim@umich.edu assert(drainCount <= 5); 12042843Sktlim@umich.edu} 12052843Sktlim@umich.edu 12062843Sktlim@umich.edutemplate <class Impl> 12072843Sktlim@umich.eduvoid 12082843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 12092843Sktlim@umich.edu{ 12102843Sktlim@umich.edu fetch.switchOut(); 12112843Sktlim@umich.edu rename.switchOut(); 12122325SN/A iew.switchOut(); 12132843Sktlim@umich.edu commit.switchOut(); 12142843Sktlim@umich.edu instList.clear(); 12152843Sktlim@umich.edu while (!removeList.empty()) { 12162843Sktlim@umich.edu removeList.pop(); 12172843Sktlim@umich.edu } 12182843Sktlim@umich.edu 12192843Sktlim@umich.edu _status = SwitchedOut; 12208887Sgeoffrey.blake@arm.com 12212843Sktlim@umich.edu if (checker) 12222843Sktlim@umich.edu checker->switchOut(); 12238887Sgeoffrey.blake@arm.com 12243126Sktlim@umich.edu if (tickEvent.scheduled()) 12253126Sktlim@umich.edu tickEvent.squash(); 12261060SN/A} 12271060SN/A 12281060SN/Atemplate <class Impl> 12291060SN/Avoid 12301755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 12311060SN/A{ 12322325SN/A // Flush out any old data from the time buffers. 12332873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 12342307SN/A timeBuffer.advance(); 12352307SN/A fetchQueue.advance(); 12362307SN/A decodeQueue.advance(); 12372307SN/A renameQueue.advance(); 12382307SN/A iewQueue.advance(); 12392307SN/A } 12402307SN/A 12412325SN/A activityRec.reset(); 12422307SN/A 12438737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 12441060SN/A 12452307SN/A fetch.takeOverFrom(); 12462307SN/A decode.takeOverFrom(); 12472307SN/A rename.takeOverFrom(); 12482307SN/A iew.takeOverFrom(); 12492307SN/A commit.takeOverFrom(); 12502307SN/A 12517507Stjones1@inf.ed.ac.uk assert(!tickEvent.scheduled() || tickEvent.squashed()); 12521060SN/A 12539152Satgutier@umich.edu FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU); 12549152Satgutier@umich.edu if (oldO3CPU) 12559152Satgutier@umich.edu globalSeqNum = oldO3CPU->globalSeqNum; 12569152Satgutier@umich.edu 12572325SN/A // @todo: Figure out how to properly select the tid to put onto 12582325SN/A // the active threads list. 12596221Snate@binkert.org ThreadID tid = 0; 12602307SN/A 12616221Snate@binkert.org list<ThreadID>::iterator isActive = 12625314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 12632307SN/A 12642307SN/A if (isActive == activeThreads.end()) { 12652325SN/A //May Need to Re-code this if the delay variable is the delay 12662325SN/A //needed for thread to activate 12672733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 12682307SN/A tid); 12692307SN/A 12702307SN/A activeThreads.push_back(tid); 12712307SN/A } 12722307SN/A 12732325SN/A // Set all statuses to active, schedule the CPU's tick event. 12742307SN/A // @todo: Fix up statuses so this is handled properly 12756221Snate@binkert.org ThreadID size = threadContexts.size(); 12766221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 12772680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 12782680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 12791681SN/A _status = Running; 12807507Stjones1@inf.ed.ac.uk reschedule(tickEvent, nextCycle(), true); 12811681SN/A } 12821060SN/A } 12832307SN/A if (!tickEvent.scheduled()) 12845606Snate@binkert.org schedule(tickEvent, nextCycle()); 12858627SAli.Saidi@ARM.com 12869179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 12871060SN/A} 12881060SN/A 12891060SN/Atemplate <class Impl> 12905595Sgblack@eecs.umich.eduTheISA::MiscReg 12916221Snate@binkert.orgFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) 12925595Sgblack@eecs.umich.edu{ 12939384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscRegNoEffect(misc_reg); 12945595Sgblack@eecs.umich.edu} 12955595Sgblack@eecs.umich.edu 12965595Sgblack@eecs.umich.edutemplate <class Impl> 12975595Sgblack@eecs.umich.eduTheISA::MiscReg 12986221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 12995595Sgblack@eecs.umich.edu{ 13007897Shestness@cs.utexas.edu miscRegfileReads++; 13019384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); 13025595Sgblack@eecs.umich.edu} 13035595Sgblack@eecs.umich.edu 13045595Sgblack@eecs.umich.edutemplate <class Impl> 13055595Sgblack@eecs.umich.eduvoid 13065595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 13076221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 13085595Sgblack@eecs.umich.edu{ 13099384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscRegNoEffect(misc_reg, val); 13105595Sgblack@eecs.umich.edu} 13115595Sgblack@eecs.umich.edu 13125595Sgblack@eecs.umich.edutemplate <class Impl> 13135595Sgblack@eecs.umich.eduvoid 13145595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 13156221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 13165595Sgblack@eecs.umich.edu{ 13177897Shestness@cs.utexas.edu miscRegfileWrites++; 13189384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); 13195595Sgblack@eecs.umich.edu} 13205595Sgblack@eecs.umich.edu 13215595Sgblack@eecs.umich.edutemplate <class Impl> 13221060SN/Auint64_t 13231755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 13241060SN/A{ 13257897Shestness@cs.utexas.edu intRegfileReads++; 13261060SN/A return regFile.readIntReg(reg_idx); 13271060SN/A} 13281060SN/A 13291060SN/Atemplate <class Impl> 13302455SN/AFloatReg 13312455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 13321060SN/A{ 13337897Shestness@cs.utexas.edu fpRegfileReads++; 13342455SN/A return regFile.readFloatReg(reg_idx); 13351060SN/A} 13361060SN/A 13371060SN/Atemplate <class Impl> 13382455SN/AFloatRegBits 13392455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 13402455SN/A{ 13417897Shestness@cs.utexas.edu fpRegfileReads++; 13422455SN/A return regFile.readFloatRegBits(reg_idx); 13431060SN/A} 13441060SN/A 13451060SN/Atemplate <class Impl> 13461060SN/Avoid 13471755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 13481060SN/A{ 13497897Shestness@cs.utexas.edu intRegfileWrites++; 13501060SN/A regFile.setIntReg(reg_idx, val); 13511060SN/A} 13521060SN/A 13531060SN/Atemplate <class Impl> 13541060SN/Avoid 13552455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 13561060SN/A{ 13577897Shestness@cs.utexas.edu fpRegfileWrites++; 13582455SN/A regFile.setFloatReg(reg_idx, val); 13591060SN/A} 13601060SN/A 13611060SN/Atemplate <class Impl> 13621060SN/Avoid 13632455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 13642455SN/A{ 13657897Shestness@cs.utexas.edu fpRegfileWrites++; 13662455SN/A regFile.setFloatRegBits(reg_idx, val); 13671060SN/A} 13681060SN/A 13691060SN/Atemplate <class Impl> 13701060SN/Auint64_t 13716221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 13721060SN/A{ 13737897Shestness@cs.utexas.edu intRegfileReads++; 13742292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13752292SN/A 13762292SN/A return regFile.readIntReg(phys_reg); 13772292SN/A} 13782292SN/A 13792292SN/Atemplate <class Impl> 13802292SN/Afloat 13816314Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 13822292SN/A{ 13837897Shestness@cs.utexas.edu fpRegfileReads++; 13846032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13852307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13862292SN/A 13872669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 13882292SN/A} 13892292SN/A 13902292SN/Atemplate <class Impl> 13912292SN/Auint64_t 13926221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 13932292SN/A{ 13947897Shestness@cs.utexas.edu fpRegfileReads++; 13956032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13962307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13972292SN/A 13982669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 13991060SN/A} 14001060SN/A 14011060SN/Atemplate <class Impl> 14021060SN/Avoid 14036221Snate@binkert.orgFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 14041060SN/A{ 14057897Shestness@cs.utexas.edu intRegfileWrites++; 14062292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 14072292SN/A 14082292SN/A regFile.setIntReg(phys_reg, val); 14091060SN/A} 14101060SN/A 14111060SN/Atemplate <class Impl> 14121060SN/Avoid 14136314Sgblack@eecs.umich.eduFullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 14141060SN/A{ 14157897Shestness@cs.utexas.edu fpRegfileWrites++; 14166032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 14172918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 14182292SN/A 14192669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 14201060SN/A} 14211060SN/A 14221060SN/Atemplate <class Impl> 14231060SN/Avoid 14246221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 14251060SN/A{ 14267897Shestness@cs.utexas.edu fpRegfileWrites++; 14276032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 14282918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 14291060SN/A 14302669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 14312292SN/A} 14322292SN/A 14332292SN/Atemplate <class Impl> 14347720Sgblack@eecs.umich.eduTheISA::PCState 14357720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 14362292SN/A{ 14377720Sgblack@eecs.umich.edu return commit.pcState(tid); 14381060SN/A} 14391060SN/A 14401060SN/Atemplate <class Impl> 14411060SN/Avoid 14427720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 14431060SN/A{ 14447720Sgblack@eecs.umich.edu commit.pcState(val, tid); 14452292SN/A} 14461060SN/A 14472292SN/Atemplate <class Impl> 14487720Sgblack@eecs.umich.eduAddr 14497720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 14504636Sgblack@eecs.umich.edu{ 14517720Sgblack@eecs.umich.edu return commit.instAddr(tid); 14524636Sgblack@eecs.umich.edu} 14534636Sgblack@eecs.umich.edu 14544636Sgblack@eecs.umich.edutemplate <class Impl> 14557720Sgblack@eecs.umich.eduAddr 14567720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 14574636Sgblack@eecs.umich.edu{ 14587720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 14594636Sgblack@eecs.umich.edu} 14604636Sgblack@eecs.umich.edu 14614636Sgblack@eecs.umich.edutemplate <class Impl> 14627720Sgblack@eecs.umich.eduMicroPC 14637720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 14642292SN/A{ 14657720Sgblack@eecs.umich.edu return commit.microPC(tid); 14664636Sgblack@eecs.umich.edu} 14674636Sgblack@eecs.umich.edu 14684636Sgblack@eecs.umich.edutemplate <class Impl> 14695595Sgblack@eecs.umich.eduvoid 14706221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 14715595Sgblack@eecs.umich.edu{ 14729382SAli.Saidi@ARM.com this->thread[tid]->noSquashFromTC = true; 14735595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 14745595Sgblack@eecs.umich.edu} 14755595Sgblack@eecs.umich.edu 14765595Sgblack@eecs.umich.edutemplate <class Impl> 14772292SN/Atypename FullO3CPU<Impl>::ListIt 14782292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 14792292SN/A{ 14802292SN/A instList.push_back(inst); 14811060SN/A 14822292SN/A return --(instList.end()); 14832292SN/A} 14841060SN/A 14852292SN/Atemplate <class Impl> 14862292SN/Avoid 14878834Satgutier@umich.eduFullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst) 14882292SN/A{ 14892292SN/A // Keep an instruction count. 14908834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) { 14918834Satgutier@umich.edu thread[tid]->numInst++; 14928834Satgutier@umich.edu thread[tid]->numInsts++; 14938834Satgutier@umich.edu committedInsts[tid]++; 14948834Satgutier@umich.edu totalCommittedInsts++; 14958834Satgutier@umich.edu } 14968834Satgutier@umich.edu thread[tid]->numOp++; 14978834Satgutier@umich.edu thread[tid]->numOps++; 14988834Satgutier@umich.edu committedOps[tid]++; 14998834Satgutier@umich.edu 15007897Shestness@cs.utexas.edu system->totalNumInsts++; 15012292SN/A // Check for instruction-count-based events. 15022292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 15037897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 15042292SN/A} 15052292SN/A 15062292SN/Atemplate <class Impl> 15072292SN/Avoid 15081755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 15091060SN/A{ 15107720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 15112292SN/A "[sn:%lli]\n", 15127720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 15131060SN/A 15142292SN/A removeInstsThisCycle = true; 15151060SN/A 15161060SN/A // Remove the front instruction. 15172292SN/A removeList.push(inst->getInstListIt()); 15181060SN/A} 15191060SN/A 15201060SN/Atemplate <class Impl> 15211060SN/Avoid 15226221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 15231060SN/A{ 15242733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 15252292SN/A " list.\n", tid); 15261060SN/A 15272292SN/A ListIt end_it; 15281060SN/A 15292292SN/A bool rob_empty = false; 15302292SN/A 15312292SN/A if (instList.empty()) { 15322292SN/A return; 15332292SN/A } else if (rob.isEmpty(/*tid*/)) { 15342733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 15352292SN/A end_it = instList.begin(); 15362292SN/A rob_empty = true; 15372292SN/A } else { 15382292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 15392733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 15402292SN/A } 15412292SN/A 15422292SN/A removeInstsThisCycle = true; 15432292SN/A 15442292SN/A ListIt inst_it = instList.end(); 15452292SN/A 15462292SN/A inst_it--; 15472292SN/A 15482292SN/A // Walk through the instruction list, removing any instructions 15492292SN/A // that were inserted after the given instruction iterator, end_it. 15502292SN/A while (inst_it != end_it) { 15512292SN/A assert(!instList.empty()); 15522292SN/A 15532292SN/A squashInstIt(inst_it, tid); 15542292SN/A 15552292SN/A inst_it--; 15562292SN/A } 15572292SN/A 15582292SN/A // If the ROB was empty, then we actually need to remove the first 15592292SN/A // instruction as well. 15602292SN/A if (rob_empty) { 15612292SN/A squashInstIt(inst_it, tid); 15622292SN/A } 15631060SN/A} 15641060SN/A 15651060SN/Atemplate <class Impl> 15661060SN/Avoid 15676221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 15681062SN/A{ 15692292SN/A assert(!instList.empty()); 15702292SN/A 15712292SN/A removeInstsThisCycle = true; 15722292SN/A 15732292SN/A ListIt inst_iter = instList.end(); 15742292SN/A 15752292SN/A inst_iter--; 15762292SN/A 15772733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 15782292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 15792292SN/A tid, seq_num, (*inst_iter)->seqNum); 15801062SN/A 15812292SN/A while ((*inst_iter)->seqNum > seq_num) { 15821062SN/A 15832292SN/A bool break_loop = (inst_iter == instList.begin()); 15841062SN/A 15852292SN/A squashInstIt(inst_iter, tid); 15861062SN/A 15872292SN/A inst_iter--; 15881062SN/A 15892292SN/A if (break_loop) 15902292SN/A break; 15912292SN/A } 15922292SN/A} 15932292SN/A 15942292SN/Atemplate <class Impl> 15952292SN/Ainline void 15966221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 15972292SN/A{ 15982292SN/A if ((*instIt)->threadNumber == tid) { 15992733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 16007720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 16012292SN/A (*instIt)->threadNumber, 16022292SN/A (*instIt)->seqNum, 16037720Sgblack@eecs.umich.edu (*instIt)->pcState()); 16041062SN/A 16051062SN/A // Mark it as squashed. 16062292SN/A (*instIt)->setSquashed(); 16072292SN/A 16082325SN/A // @todo: Formulate a consistent method for deleting 16092325SN/A // instructions from the instruction list 16102292SN/A // Remove the instruction from the list. 16112292SN/A removeList.push(instIt); 16122292SN/A } 16132292SN/A} 16142292SN/A 16152292SN/Atemplate <class Impl> 16162292SN/Avoid 16172292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 16182292SN/A{ 16192292SN/A while (!removeList.empty()) { 16202733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 16217720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 16222292SN/A (*removeList.front())->threadNumber, 16232292SN/A (*removeList.front())->seqNum, 16247720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 16252292SN/A 16262292SN/A instList.erase(removeList.front()); 16272292SN/A 16282292SN/A removeList.pop(); 16291062SN/A } 16301062SN/A 16312292SN/A removeInstsThisCycle = false; 16321062SN/A} 16332325SN/A/* 16341062SN/Atemplate <class Impl> 16351062SN/Avoid 16361755SN/AFullO3CPU<Impl>::removeAllInsts() 16371060SN/A{ 16381060SN/A instList.clear(); 16391060SN/A} 16402325SN/A*/ 16411060SN/Atemplate <class Impl> 16421060SN/Avoid 16431755SN/AFullO3CPU<Impl>::dumpInsts() 16441060SN/A{ 16451060SN/A int num = 0; 16461060SN/A 16472292SN/A ListIt inst_list_it = instList.begin(); 16482292SN/A 16492292SN/A cprintf("Dumping Instruction List\n"); 16502292SN/A 16512292SN/A while (inst_list_it != instList.end()) { 16522292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 16532292SN/A "Squashed:%i\n\n", 16547720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 16552292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 16562292SN/A (*inst_list_it)->isSquashed()); 16571060SN/A inst_list_it++; 16581060SN/A ++num; 16591060SN/A } 16601060SN/A} 16612325SN/A/* 16621060SN/Atemplate <class Impl> 16631060SN/Avoid 16641755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 16651060SN/A{ 16661060SN/A iew.wakeDependents(inst); 16671060SN/A} 16682325SN/A*/ 16692292SN/Atemplate <class Impl> 16702292SN/Avoid 16712292SN/AFullO3CPU<Impl>::wakeCPU() 16722292SN/A{ 16732325SN/A if (activityRec.active() || tickEvent.scheduled()) { 16742325SN/A DPRINTF(Activity, "CPU already running.\n"); 16752292SN/A return; 16762292SN/A } 16772292SN/A 16782325SN/A DPRINTF(Activity, "Waking up CPU\n"); 16792325SN/A 16809180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 16819180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 16829179Sandreas.hansson@arm.com if (cycles != 0) 16839179Sandreas.hansson@arm.com --cycles; 16849179Sandreas.hansson@arm.com idleCycles += cycles; 16859179Sandreas.hansson@arm.com numCycles += cycles; 16862292SN/A 16875606Snate@binkert.org schedule(tickEvent, nextCycle()); 16882292SN/A} 16892292SN/A 16905807Snate@binkert.orgtemplate <class Impl> 16915807Snate@binkert.orgvoid 16925807Snate@binkert.orgFullO3CPU<Impl>::wakeup() 16935807Snate@binkert.org{ 16945807Snate@binkert.org if (this->thread[0]->status() != ThreadContext::Suspended) 16955807Snate@binkert.org return; 16965807Snate@binkert.org 16975807Snate@binkert.org this->wakeCPU(); 16985807Snate@binkert.org 16995807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 17005807Snate@binkert.org this->threadContexts[0]->activate(); 17015807Snate@binkert.org} 17025807Snate@binkert.org 17032292SN/Atemplate <class Impl> 17046221Snate@binkert.orgThreadID 17052292SN/AFullO3CPU<Impl>::getFreeTid() 17062292SN/A{ 17076221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 17086221Snate@binkert.org if (!tids[tid]) { 17096221Snate@binkert.org tids[tid] = true; 17106221Snate@binkert.org return tid; 17112292SN/A } 17122292SN/A } 17132292SN/A 17146221Snate@binkert.org return InvalidThreadID; 17152292SN/A} 17162292SN/A 17172292SN/Atemplate <class Impl> 17182292SN/Avoid 17192292SN/AFullO3CPU<Impl>::doContextSwitch() 17202292SN/A{ 17212292SN/A if (contextSwitch) { 17222292SN/A 17232292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 17242292SN/A 17256221Snate@binkert.org ThreadID size = cpuWaitList.size(); 17266221Snate@binkert.org for (ThreadID tid = 0; tid < size; tid++) { 17272292SN/A activateWhenReady(tid); 17282292SN/A } 17292292SN/A 17302292SN/A if (cpuWaitList.size() == 0) 17312292SN/A contextSwitch = true; 17322292SN/A } 17332292SN/A} 17342292SN/A 17352292SN/Atemplate <class Impl> 17362292SN/Avoid 17372292SN/AFullO3CPU<Impl>::updateThreadPriority() 17382292SN/A{ 17396221Snate@binkert.org if (activeThreads.size() > 1) { 17402292SN/A //DEFAULT TO ROUND ROBIN SCHEME 17412292SN/A //e.g. Move highest priority to end of thread list 17426221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 17432292SN/A 17442292SN/A unsigned high_thread = *list_begin; 17452292SN/A 17462292SN/A activeThreads.erase(list_begin); 17472292SN/A 17482292SN/A activeThreads.push_back(high_thread); 17492292SN/A } 17502292SN/A} 17511060SN/A 17521755SN/A// Forward declaration of FullO3CPU. 17532818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1754