cpu.cc revision 8921
11689SN/A/* 28707Sandreas.hansson@arm.com * Copyright (c) 2011 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 142325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422756Sksewell@umich.edu * Korey Sewell 437897Shestness@cs.utexas.edu * Rick Strong 441689SN/A */ 451689SN/A 468779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 488887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 498887Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 508229Snate@binkert.org#include "cpu/o3/cpu.hh" 518229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 528229Snate@binkert.org#include "cpu/o3/thread_context.hh" 534762Snate@binkert.org#include "cpu/activity.hh" 548779Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 554762Snate@binkert.org#include "cpu/simple_thread.hh" 564762Snate@binkert.org#include "cpu/thread_context.hh" 578232Snate@binkert.org#include "debug/Activity.hh" 588232Snate@binkert.org#include "debug/O3CPU.hh" 598232Snate@binkert.org#include "debug/Quiesce.hh" 604762Snate@binkert.org#include "enums/MemoryMode.hh" 614762Snate@binkert.org#include "sim/core.hh" 628793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 638779Sgblack@eecs.umich.edu#include "sim/process.hh" 644762Snate@binkert.org#include "sim/stat_control.hh" 658460SAli.Saidi@ARM.com#include "sim/system.hh" 664762Snate@binkert.org 675702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 685702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 698232Snate@binkert.org#include "debug/Activity.hh" 705702Ssaidi@eecs.umich.edu#endif 715702Ssaidi@eecs.umich.edu 728737Skoansin.tan@gmail.comstruct BaseCPUParams; 735529Snate@binkert.org 742669Sktlim@umich.eduusing namespace TheISA; 756221Snate@binkert.orgusing namespace std; 761060SN/A 775529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 785712Shsul@eecs.umich.edu : BaseCPU(params) 791060SN/A{ 801060SN/A} 811060SN/A 822292SN/Avoid 832733Sktlim@umich.eduBaseO3CPU::regStats() 842292SN/A{ 852292SN/A BaseCPU::regStats(); 862292SN/A} 872292SN/A 888707Sandreas.hansson@arm.comtemplate<class Impl> 898707Sandreas.hansson@arm.combool 908707Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvTiming(PacketPtr pkt) 918707Sandreas.hansson@arm.com{ 928707Sandreas.hansson@arm.com DPRINTF(O3CPU, "Fetch unit received timing\n"); 938707Sandreas.hansson@arm.com if (pkt->isResponse()) { 948707Sandreas.hansson@arm.com // We shouldn't ever get a block in ownership state 958707Sandreas.hansson@arm.com assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); 968707Sandreas.hansson@arm.com 978707Sandreas.hansson@arm.com fetch->processCacheCompletion(pkt); 988707Sandreas.hansson@arm.com } 998707Sandreas.hansson@arm.com //else Snooped a coherence request, just return 1008707Sandreas.hansson@arm.com return true; 1018707Sandreas.hansson@arm.com} 1028707Sandreas.hansson@arm.com 1038707Sandreas.hansson@arm.comtemplate<class Impl> 1048707Sandreas.hansson@arm.comvoid 1058707Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvRetry() 1068707Sandreas.hansson@arm.com{ 1078707Sandreas.hansson@arm.com fetch->recvRetry(); 1088707Sandreas.hansson@arm.com} 1098707Sandreas.hansson@arm.com 1108707Sandreas.hansson@arm.comtemplate <class Impl> 1118707Sandreas.hansson@arm.combool 1128707Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTiming(PacketPtr pkt) 1138707Sandreas.hansson@arm.com{ 1148707Sandreas.hansson@arm.com return lsq->recvTiming(pkt); 1158707Sandreas.hansson@arm.com} 1168707Sandreas.hansson@arm.com 1178707Sandreas.hansson@arm.comtemplate <class Impl> 1188707Sandreas.hansson@arm.comvoid 1198707Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvRetry() 1208707Sandreas.hansson@arm.com{ 1218707Sandreas.hansson@arm.com lsq->recvRetry(); 1228707Sandreas.hansson@arm.com} 1238707Sandreas.hansson@arm.com 1241060SN/Atemplate <class Impl> 1251755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 1265606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 1271060SN/A{ 1281060SN/A} 1291060SN/A 1301060SN/Atemplate <class Impl> 1311060SN/Avoid 1321755SN/AFullO3CPU<Impl>::TickEvent::process() 1331060SN/A{ 1341060SN/A cpu->tick(); 1351060SN/A} 1361060SN/A 1371060SN/Atemplate <class Impl> 1381060SN/Aconst char * 1395336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 1401060SN/A{ 1414873Sstever@eecs.umich.edu return "FullO3CPU tick"; 1421060SN/A} 1431060SN/A 1441060SN/Atemplate <class Impl> 1452829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 1465606Snate@binkert.org : Event(CPU_Switch_Pri) 1472829Sksewell@umich.edu{ 1482829Sksewell@umich.edu} 1492829Sksewell@umich.edu 1502829Sksewell@umich.edutemplate <class Impl> 1512829Sksewell@umich.eduvoid 1522829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 1532829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1542829Sksewell@umich.edu{ 1552829Sksewell@umich.edu tid = thread_num; 1562829Sksewell@umich.edu cpu = thread_cpu; 1572829Sksewell@umich.edu} 1582829Sksewell@umich.edu 1592829Sksewell@umich.edutemplate <class Impl> 1602829Sksewell@umich.eduvoid 1612829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1622829Sksewell@umich.edu{ 1632829Sksewell@umich.edu cpu->activateThread(tid); 1642829Sksewell@umich.edu} 1652829Sksewell@umich.edu 1662829Sksewell@umich.edutemplate <class Impl> 1672829Sksewell@umich.educonst char * 1685336Shines@cs.fsu.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1692829Sksewell@umich.edu{ 1704873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1712829Sksewell@umich.edu} 1722829Sksewell@umich.edu 1732829Sksewell@umich.edutemplate <class Impl> 1742875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1755606Snate@binkert.org : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1762875Sksewell@umich.edu{ 1772875Sksewell@umich.edu} 1782875Sksewell@umich.edu 1792875Sksewell@umich.edutemplate <class Impl> 1802875Sksewell@umich.eduvoid 1812875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1823859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1832875Sksewell@umich.edu{ 1842875Sksewell@umich.edu tid = thread_num; 1852875Sksewell@umich.edu cpu = thread_cpu; 1863859Sbinkertn@umich.edu remove = false; 1872875Sksewell@umich.edu} 1882875Sksewell@umich.edu 1892875Sksewell@umich.edutemplate <class Impl> 1902875Sksewell@umich.eduvoid 1912875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1922875Sksewell@umich.edu{ 1932875Sksewell@umich.edu cpu->deactivateThread(tid); 1943221Sktlim@umich.edu if (remove) 1953221Sktlim@umich.edu cpu->removeThread(tid); 1962875Sksewell@umich.edu} 1972875Sksewell@umich.edu 1982875Sksewell@umich.edutemplate <class Impl> 1992875Sksewell@umich.educonst char * 2005336Shines@cs.fsu.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 2012875Sksewell@umich.edu{ 2024873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 2032875Sksewell@umich.edu} 2042875Sksewell@umich.edu 2052875Sksewell@umich.edutemplate <class Impl> 2065595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 2072733Sktlim@umich.edu : BaseO3CPU(params), 2083781Sgblack@eecs.umich.edu itb(params->itb), 2093781Sgblack@eecs.umich.edu dtb(params->dtb), 2101060SN/A tickEvent(this), 2115737Scws3k@cs.virginia.edu#ifndef NDEBUG 2125737Scws3k@cs.virginia.edu instcount(0), 2135737Scws3k@cs.virginia.edu#endif 2142292SN/A removeInstsThisCycle(false), 2155595Sgblack@eecs.umich.edu fetch(this, params), 2165595Sgblack@eecs.umich.edu decode(this, params), 2175595Sgblack@eecs.umich.edu rename(this, params), 2185595Sgblack@eecs.umich.edu iew(this, params), 2195595Sgblack@eecs.umich.edu commit(this, params), 2201060SN/A 2215595Sgblack@eecs.umich.edu regFile(this, params->numPhysIntRegs, 2224329Sktlim@umich.edu params->numPhysFloatRegs), 2231060SN/A 2245529Snate@binkert.org freeList(params->numThreads, 2252292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 2262292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 2271060SN/A 2285595Sgblack@eecs.umich.edu rob(this, 2294329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 2302292SN/A params->smtROBPolicy, params->smtROBThreshold, 2315529Snate@binkert.org params->numThreads), 2321060SN/A 2335529Snate@binkert.org scoreboard(params->numThreads, 2342292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 2352292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 2366221Snate@binkert.org TheISA::NumMiscRegs * numThreads, 2372292SN/A TheISA::ZeroReg), 2381060SN/A 2398707Sandreas.hansson@arm.com icachePort(&fetch, this), 2408707Sandreas.hansson@arm.com dcachePort(&iew.ldstQueue, this), 2418707Sandreas.hansson@arm.com 2422873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 2432873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 2442873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 2452873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 2462873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 2475804Snate@binkert.org activityRec(name(), NumStages, 2482873Sktlim@umich.edu params->backComSize + params->forwardComSize, 2492873Sktlim@umich.edu params->activity), 2501060SN/A 2511060SN/A globalSeqNum(1), 2522292SN/A system(params->system), 2532843Sktlim@umich.edu drainCount(0), 2546221Snate@binkert.org deferRegistration(params->defer_registration) 2551060SN/A{ 2563221Sktlim@umich.edu if (!deferRegistration) { 2573221Sktlim@umich.edu _status = Running; 2583221Sktlim@umich.edu } else { 2593221Sktlim@umich.edu _status = Idle; 2603221Sktlim@umich.edu } 2611681SN/A 2622794Sktlim@umich.edu if (params->checker) { 2632316SN/A BaseCPU *temp_checker = params->checker; 2648733Sgeoffrey.blake@arm.com checker = dynamic_cast<Checker<Impl> *>(temp_checker); 2658707Sandreas.hansson@arm.com checker->setIcachePort(&icachePort); 2662316SN/A checker->setSystem(params->system); 2674598Sbinkertn@umich.edu } else { 2684598Sbinkertn@umich.edu checker = NULL; 2694598Sbinkertn@umich.edu } 2702316SN/A 2718793Sgblack@eecs.umich.edu if (!FullSystem) { 2728793Sgblack@eecs.umich.edu thread.resize(numThreads); 2738793Sgblack@eecs.umich.edu tids.resize(numThreads); 2748793Sgblack@eecs.umich.edu } 2751681SN/A 2762325SN/A // The stages also need their CPU pointer setup. However this 2772325SN/A // must be done at the upper level CPU because they have pointers 2782325SN/A // to the upper level CPU, and not this FullO3CPU. 2791060SN/A 2802292SN/A // Set up Pointers to the activeThreads list for each stage 2812292SN/A fetch.setActiveThreads(&activeThreads); 2822292SN/A decode.setActiveThreads(&activeThreads); 2832292SN/A rename.setActiveThreads(&activeThreads); 2842292SN/A iew.setActiveThreads(&activeThreads); 2852292SN/A commit.setActiveThreads(&activeThreads); 2861060SN/A 2871060SN/A // Give each of the stages the time buffer they will use. 2881060SN/A fetch.setTimeBuffer(&timeBuffer); 2891060SN/A decode.setTimeBuffer(&timeBuffer); 2901060SN/A rename.setTimeBuffer(&timeBuffer); 2911060SN/A iew.setTimeBuffer(&timeBuffer); 2921060SN/A commit.setTimeBuffer(&timeBuffer); 2931060SN/A 2941060SN/A // Also setup each of the stages' queues. 2951060SN/A fetch.setFetchQueue(&fetchQueue); 2961060SN/A decode.setFetchQueue(&fetchQueue); 2972292SN/A commit.setFetchQueue(&fetchQueue); 2981060SN/A decode.setDecodeQueue(&decodeQueue); 2991060SN/A rename.setDecodeQueue(&decodeQueue); 3001060SN/A rename.setRenameQueue(&renameQueue); 3011060SN/A iew.setRenameQueue(&renameQueue); 3021060SN/A iew.setIEWQueue(&iewQueue); 3031060SN/A commit.setIEWQueue(&iewQueue); 3041060SN/A commit.setRenameQueue(&renameQueue); 3051060SN/A 3062292SN/A commit.setIEWStage(&iew); 3072292SN/A rename.setIEWStage(&iew); 3082292SN/A rename.setCommitStage(&commit); 3092292SN/A 3108793Sgblack@eecs.umich.edu ThreadID active_threads; 3118793Sgblack@eecs.umich.edu if (FullSystem) { 3128793Sgblack@eecs.umich.edu active_threads = 1; 3138793Sgblack@eecs.umich.edu } else { 3148793Sgblack@eecs.umich.edu active_threads = params->workload.size(); 3152831Sksewell@umich.edu 3168793Sgblack@eecs.umich.edu if (active_threads > Impl::MaxThreads) { 3178793Sgblack@eecs.umich.edu panic("Workload Size too large. Increase the 'MaxThreads' " 3188793Sgblack@eecs.umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 3198793Sgblack@eecs.umich.edu "or edit your workload size."); 3208793Sgblack@eecs.umich.edu } 3212831Sksewell@umich.edu } 3222292SN/A 3232316SN/A //Make Sure That this a Valid Architeture 3242292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 3252292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 3262292SN/A 3272292SN/A rename.setScoreboard(&scoreboard); 3282292SN/A iew.setScoreboard(&scoreboard); 3292292SN/A 3301060SN/A // Setup the rename map for whichever stages need it. 3312292SN/A PhysRegIndex lreg_idx = 0; 3322292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 3331060SN/A 3346221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3352307SN/A bool bindRegs = (tid <= active_threads - 1); 3362292SN/A 3372292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 3382292SN/A params->numPhysIntRegs, 3392325SN/A lreg_idx, //Index for Logical. Regs 3402292SN/A 3412292SN/A TheISA::NumFloatRegs, 3422292SN/A params->numPhysFloatRegs, 3432325SN/A freg_idx, //Index for Float Regs 3442292SN/A 3452292SN/A TheISA::NumMiscRegs, 3462292SN/A 3472292SN/A TheISA::ZeroReg, 3482292SN/A TheISA::ZeroReg, 3492292SN/A 3502292SN/A tid, 3512292SN/A false); 3522292SN/A 3532292SN/A renameMap[tid].init(TheISA::NumIntRegs, 3542292SN/A params->numPhysIntRegs, 3552325SN/A lreg_idx, //Index for Logical. Regs 3562292SN/A 3572292SN/A TheISA::NumFloatRegs, 3582292SN/A params->numPhysFloatRegs, 3592325SN/A freg_idx, //Index for Float Regs 3602292SN/A 3612292SN/A TheISA::NumMiscRegs, 3622292SN/A 3632292SN/A TheISA::ZeroReg, 3642292SN/A TheISA::ZeroReg, 3652292SN/A 3662292SN/A tid, 3672292SN/A bindRegs); 3683221Sktlim@umich.edu 3693221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3703221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3712292SN/A } 3722292SN/A 3732292SN/A rename.setRenameMap(renameMap); 3742292SN/A commit.setRenameMap(commitRenameMap); 3752292SN/A 3762292SN/A // Give renameMap & rename stage access to the freeList; 3776221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3786221Snate@binkert.org renameMap[tid].setFreeList(&freeList); 3791060SN/A rename.setFreeList(&freeList); 3802292SN/A 3811060SN/A // Setup the ROB for whichever stages need it. 3821060SN/A commit.setROB(&rob); 3832292SN/A 3847823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 3852292SN/A 3862829Sksewell@umich.edu lastActivatedCycle = -1; 3876221Snate@binkert.org#if 0 3883093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3896221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3906221Snate@binkert.org globalSeqNum[tid] = 1; 3916221Snate@binkert.org#endif 3923093Sksewell@umich.edu 3932292SN/A contextSwitch = false; 3945595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3955595Sgblack@eecs.umich.edu 3965595Sgblack@eecs.umich.edu // Setup any thread state. 3975595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 3985595Sgblack@eecs.umich.edu 3996221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 4008793Sgblack@eecs.umich.edu if (FullSystem) { 4018793Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 4028793Sgblack@eecs.umich.edu assert(this->numThreads == 1); 4038793Sgblack@eecs.umich.edu this->thread[tid] = new Thread(this, 0, NULL); 4048793Sgblack@eecs.umich.edu } else { 4058793Sgblack@eecs.umich.edu if (tid < params->workload.size()) { 4068793Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 4078793Sgblack@eecs.umich.edu tid, this->thread[tid]); 4088793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 4098793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 4108793Sgblack@eecs.umich.edu tid, params->workload[tid]); 4115595Sgblack@eecs.umich.edu 4128793Sgblack@eecs.umich.edu //usedTids[tid] = true; 4138793Sgblack@eecs.umich.edu //threadMap[tid] = tid; 4148793Sgblack@eecs.umich.edu } else { 4158793Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 4168793Sgblack@eecs.umich.edu //when scheduling threads to CPU 4178793Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 4185595Sgblack@eecs.umich.edu 4198793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 4208793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 4218793Sgblack@eecs.umich.edu tid, dummy_proc); 4228793Sgblack@eecs.umich.edu //usedTids[tid] = false; 4238793Sgblack@eecs.umich.edu } 4245595Sgblack@eecs.umich.edu } 4255595Sgblack@eecs.umich.edu 4265595Sgblack@eecs.umich.edu ThreadContext *tc; 4275595Sgblack@eecs.umich.edu 4285595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 4295595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 4305595Sgblack@eecs.umich.edu 4315595Sgblack@eecs.umich.edu tc = o3_tc; 4325595Sgblack@eecs.umich.edu 4335595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 4345595Sgblack@eecs.umich.edu // CheckerThreadContext. 4355595Sgblack@eecs.umich.edu if (params->checker) { 4365595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 4375595Sgblack@eecs.umich.edu o3_tc, this->checker); 4385595Sgblack@eecs.umich.edu } 4395595Sgblack@eecs.umich.edu 4405595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 4415595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 4426221Snate@binkert.org o3_tc->thread = this->thread[tid]; 4435595Sgblack@eecs.umich.edu 4448793Sgblack@eecs.umich.edu if (FullSystem) { 4458793Sgblack@eecs.umich.edu // Setup quiesce event. 4468793Sgblack@eecs.umich.edu this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 4478793Sgblack@eecs.umich.edu } 4485595Sgblack@eecs.umich.edu // Give the thread the TC. 4496221Snate@binkert.org this->thread[tid]->tc = tc; 4505595Sgblack@eecs.umich.edu 4515595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4525595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4535595Sgblack@eecs.umich.edu } 4545595Sgblack@eecs.umich.edu 4558876Sandreas.hansson@arm.com // FullO3CPU always requires an interrupt controller. 4568876Sandreas.hansson@arm.com if (!params->defer_registration && !interrupts) { 4578876Sandreas.hansson@arm.com fatal("FullO3CPU %s has no interrupt controller.\n" 4588876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 4598876Sandreas.hansson@arm.com } 4608876Sandreas.hansson@arm.com 4616221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4626221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4635595Sgblack@eecs.umich.edu 4645595Sgblack@eecs.umich.edu lockAddr = 0; 4655595Sgblack@eecs.umich.edu lockFlag = false; 4661060SN/A} 4671060SN/A 4681060SN/Atemplate <class Impl> 4691755SN/AFullO3CPU<Impl>::~FullO3CPU() 4701060SN/A{ 4711060SN/A} 4721060SN/A 4731060SN/Atemplate <class Impl> 4741060SN/Avoid 4755595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4761062SN/A{ 4772733Sktlim@umich.edu BaseO3CPU::regStats(); 4782292SN/A 4792733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4802292SN/A timesIdled 4812292SN/A .name(name() + ".timesIdled") 4822292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4832292SN/A " unscheduled itself") 4842292SN/A .prereq(timesIdled); 4852292SN/A 4862292SN/A idleCycles 4872292SN/A .name(name() + ".idleCycles") 4882292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4892292SN/A "to idling") 4902292SN/A .prereq(idleCycles); 4912292SN/A 4928627SAli.Saidi@ARM.com quiesceCycles 4938627SAli.Saidi@ARM.com .name(name() + ".quiesceCycles") 4948627SAli.Saidi@ARM.com .desc("Total number of cycles that CPU has spent quiesced or waiting " 4958627SAli.Saidi@ARM.com "for an interrupt") 4968627SAli.Saidi@ARM.com .prereq(quiesceCycles); 4978627SAli.Saidi@ARM.com 4982292SN/A // Number of Instructions simulated 4992292SN/A // -------------------------------- 5002292SN/A // Should probably be in Base CPU but need templated 5012292SN/A // MaxThreads so put in here instead 5022292SN/A committedInsts 5032292SN/A .init(numThreads) 5042292SN/A .name(name() + ".committedInsts") 5052292SN/A .desc("Number of Instructions Simulated"); 5062292SN/A 5078834Satgutier@umich.edu committedOps 5088834Satgutier@umich.edu .init(numThreads) 5098834Satgutier@umich.edu .name(name() + ".committedOps") 5108834Satgutier@umich.edu .desc("Number of Ops (including micro ops) Simulated"); 5118834Satgutier@umich.edu 5122292SN/A totalCommittedInsts 5132292SN/A .name(name() + ".committedInsts_total") 5142292SN/A .desc("Number of Instructions Simulated"); 5152292SN/A 5162292SN/A cpi 5172292SN/A .name(name() + ".cpi") 5182292SN/A .desc("CPI: Cycles Per Instruction") 5192292SN/A .precision(6); 5204392Sktlim@umich.edu cpi = numCycles / committedInsts; 5212292SN/A 5222292SN/A totalCpi 5232292SN/A .name(name() + ".cpi_total") 5242292SN/A .desc("CPI: Total CPI of All Threads") 5252292SN/A .precision(6); 5264392Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 5272292SN/A 5282292SN/A ipc 5292292SN/A .name(name() + ".ipc") 5302292SN/A .desc("IPC: Instructions Per Cycle") 5312292SN/A .precision(6); 5324392Sktlim@umich.edu ipc = committedInsts / numCycles; 5332292SN/A 5342292SN/A totalIpc 5352292SN/A .name(name() + ".ipc_total") 5362292SN/A .desc("IPC: Total IPC of All Threads") 5372292SN/A .precision(6); 5384392Sktlim@umich.edu totalIpc = totalCommittedInsts / numCycles; 5392292SN/A 5405595Sgblack@eecs.umich.edu this->fetch.regStats(); 5415595Sgblack@eecs.umich.edu this->decode.regStats(); 5425595Sgblack@eecs.umich.edu this->rename.regStats(); 5435595Sgblack@eecs.umich.edu this->iew.regStats(); 5445595Sgblack@eecs.umich.edu this->commit.regStats(); 5457897Shestness@cs.utexas.edu this->rob.regStats(); 5467897Shestness@cs.utexas.edu 5477897Shestness@cs.utexas.edu intRegfileReads 5487897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 5497897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 5507897Shestness@cs.utexas.edu .prereq(intRegfileReads); 5517897Shestness@cs.utexas.edu 5527897Shestness@cs.utexas.edu intRegfileWrites 5537897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 5547897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 5557897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 5567897Shestness@cs.utexas.edu 5577897Shestness@cs.utexas.edu fpRegfileReads 5587897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 5597897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 5607897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 5617897Shestness@cs.utexas.edu 5627897Shestness@cs.utexas.edu fpRegfileWrites 5637897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 5647897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 5657897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 5667897Shestness@cs.utexas.edu 5677897Shestness@cs.utexas.edu miscRegfileReads 5687897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5697897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5707897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5717897Shestness@cs.utexas.edu 5727897Shestness@cs.utexas.edu miscRegfileWrites 5737897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5747897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5757897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5761062SN/A} 5771062SN/A 5781062SN/Atemplate <class Impl> 5791062SN/Avoid 5801755SN/AFullO3CPU<Impl>::tick() 5811060SN/A{ 5822733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5831060SN/A 5842292SN/A ++numCycles; 5852292SN/A 5862325SN/A// activity = false; 5872292SN/A 5882292SN/A //Tick each of the stages 5891060SN/A fetch.tick(); 5901060SN/A 5911060SN/A decode.tick(); 5921060SN/A 5931060SN/A rename.tick(); 5941060SN/A 5951060SN/A iew.tick(); 5961060SN/A 5971060SN/A commit.tick(); 5981060SN/A 5998793Sgblack@eecs.umich.edu if (!FullSystem) 6008793Sgblack@eecs.umich.edu doContextSwitch(); 6012292SN/A 6022292SN/A // Now advance the time buffers 6031060SN/A timeBuffer.advance(); 6041060SN/A 6051060SN/A fetchQueue.advance(); 6061060SN/A decodeQueue.advance(); 6071060SN/A renameQueue.advance(); 6081060SN/A iewQueue.advance(); 6091060SN/A 6102325SN/A activityRec.advance(); 6112292SN/A 6122292SN/A if (removeInstsThisCycle) { 6132292SN/A cleanUpRemovedInsts(); 6142292SN/A } 6152292SN/A 6162325SN/A if (!tickEvent.scheduled()) { 6172867Sktlim@umich.edu if (_status == SwitchedOut || 6182905Sktlim@umich.edu getState() == SimObject::Drained) { 6193226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 6202325SN/A // increment stat 6217823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 6223221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 6233226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 6247823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 6252325SN/A timesIdled++; 6262325SN/A } else { 6277823Ssteve.reinhardt@amd.com schedule(tickEvent, nextCycle(curTick() + ticks(1))); 6283226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 6292325SN/A } 6302292SN/A } 6312292SN/A 6328793Sgblack@eecs.umich.edu if (!FullSystem) 6338793Sgblack@eecs.umich.edu updateThreadPriority(); 6341060SN/A} 6351060SN/A 6361060SN/Atemplate <class Impl> 6371060SN/Avoid 6381755SN/AFullO3CPU<Impl>::init() 6391060SN/A{ 6405714Shsul@eecs.umich.edu BaseCPU::init(); 6411060SN/A 6428921Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 6438921Sandreas.hansson@arm.com // Set inSyscall so that the CPU doesn't squash when initially 6448921Sandreas.hansson@arm.com // setting up registers. 6456221Snate@binkert.org thread[tid]->inSyscall = true; 6468921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 6478921Sandreas.hansson@arm.com thread[tid]->initMemProxies(thread[tid]->getTC()); 6488921Sandreas.hansson@arm.com } 6492292SN/A 6508707Sandreas.hansson@arm.com // this CPU could still be unconnected if we are restoring from a 6518707Sandreas.hansson@arm.com // checkpoint and this CPU is to be switched in, thus we can only 6528707Sandreas.hansson@arm.com // do this here if the instruction port is actually connected, if 6538707Sandreas.hansson@arm.com // not we have to do it as part of takeOverFrom 6548707Sandreas.hansson@arm.com if (icachePort.isConnected()) 6558707Sandreas.hansson@arm.com fetch.setIcache(); 6568707Sandreas.hansson@arm.com 6578863Snilay@cs.wisc.edu if (FullSystem && !params()->defer_registration) { 6588793Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 6598793Sgblack@eecs.umich.edu ThreadContext *src_tc = threadContexts[tid]; 6608793Sgblack@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 6618793Sgblack@eecs.umich.edu } 6626034Ssteve.reinhardt@amd.com } 6632292SN/A 6642292SN/A // Clear inSyscall. 6656221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6666221Snate@binkert.org thread[tid]->inSyscall = false; 6672292SN/A 6682316SN/A // Initialize stages. 6692292SN/A fetch.initStage(); 6702292SN/A iew.initStage(); 6712292SN/A rename.initStage(); 6722292SN/A commit.initStage(); 6732292SN/A 6742292SN/A commit.setThreads(thread); 6752292SN/A} 6762292SN/A 6772292SN/Atemplate <class Impl> 6782292SN/Avoid 6796221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 6802875Sksewell@umich.edu{ 6816221Snate@binkert.org list<ThreadID>::iterator isActive = 6825314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6832875Sksewell@umich.edu 6843226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6853226Sktlim@umich.edu 6862875Sksewell@umich.edu if (isActive == activeThreads.end()) { 6872875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6882875Sksewell@umich.edu tid); 6892875Sksewell@umich.edu 6902875Sksewell@umich.edu activeThreads.push_back(tid); 6912875Sksewell@umich.edu } 6922875Sksewell@umich.edu} 6932875Sksewell@umich.edu 6942875Sksewell@umich.edutemplate <class Impl> 6952875Sksewell@umich.eduvoid 6966221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 6972875Sksewell@umich.edu{ 6982875Sksewell@umich.edu //Remove From Active List, if Active 6996221Snate@binkert.org list<ThreadID>::iterator thread_it = 7005314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 7012875Sksewell@umich.edu 7023226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 7033226Sktlim@umich.edu 7042875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 7052875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 7062875Sksewell@umich.edu tid); 7072875Sksewell@umich.edu activeThreads.erase(thread_it); 7082875Sksewell@umich.edu } 7092875Sksewell@umich.edu} 7102875Sksewell@umich.edu 7112875Sksewell@umich.edutemplate <class Impl> 7126221Snate@binkert.orgCounter 7138834Satgutier@umich.eduFullO3CPU<Impl>::totalInsts() const 7146221Snate@binkert.org{ 7156221Snate@binkert.org Counter total(0); 7166221Snate@binkert.org 7176221Snate@binkert.org ThreadID size = thread.size(); 7186221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 7196221Snate@binkert.org total += thread[i]->numInst; 7206221Snate@binkert.org 7216221Snate@binkert.org return total; 7226221Snate@binkert.org} 7236221Snate@binkert.org 7246221Snate@binkert.orgtemplate <class Impl> 7258834Satgutier@umich.eduCounter 7268834Satgutier@umich.eduFullO3CPU<Impl>::totalOps() const 7278834Satgutier@umich.edu{ 7288834Satgutier@umich.edu Counter total(0); 7298834Satgutier@umich.edu 7308834Satgutier@umich.edu ThreadID size = thread.size(); 7318834Satgutier@umich.edu for (ThreadID i = 0; i < size; i++) 7328834Satgutier@umich.edu total += thread[i]->numOp; 7338834Satgutier@umich.edu 7348834Satgutier@umich.edu return total; 7358834Satgutier@umich.edu} 7368834Satgutier@umich.edu 7378834Satgutier@umich.edutemplate <class Impl> 7382875Sksewell@umich.eduvoid 7396221Snate@binkert.orgFullO3CPU<Impl>::activateContext(ThreadID tid, int delay) 7402875Sksewell@umich.edu{ 7412875Sksewell@umich.edu // Needs to set each stage to running as well. 7422875Sksewell@umich.edu if (delay){ 7432875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 7447823Ssteve.reinhardt@amd.com "on cycle %d\n", tid, curTick() + ticks(delay)); 7452875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 7462875Sksewell@umich.edu } else { 7472875Sksewell@umich.edu activateThread(tid); 7482875Sksewell@umich.edu } 7492875Sksewell@umich.edu 7507823Ssteve.reinhardt@amd.com if (lastActivatedCycle < curTick()) { 7512875Sksewell@umich.edu scheduleTickEvent(delay); 7522875Sksewell@umich.edu 7532875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 7542875Sksewell@umich.edu // deschedule itself. 7552875Sksewell@umich.edu activityRec.activity(); 7562875Sksewell@umich.edu fetch.wakeFromQuiesce(); 7572875Sksewell@umich.edu 7588627SAli.Saidi@ARM.com quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle); 7598627SAli.Saidi@ARM.com 7607823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 7612875Sksewell@umich.edu 7622875Sksewell@umich.edu _status = Running; 7632875Sksewell@umich.edu } 7642875Sksewell@umich.edu} 7652875Sksewell@umich.edu 7662875Sksewell@umich.edutemplate <class Impl> 7673221Sktlim@umich.edubool 7688737Skoansin.tan@gmail.comFullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove, 7698737Skoansin.tan@gmail.com int delay) 7702875Sksewell@umich.edu{ 7712875Sksewell@umich.edu // Schedule removal of thread data from CPU 7722875Sksewell@umich.edu if (delay){ 7732875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 7747823Ssteve.reinhardt@amd.com "on cycle %d\n", tid, curTick() + ticks(delay)); 7753221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 7763221Sktlim@umich.edu return false; 7772875Sksewell@umich.edu } else { 7782875Sksewell@umich.edu deactivateThread(tid); 7793221Sktlim@umich.edu if (remove) 7803221Sktlim@umich.edu removeThread(tid); 7813221Sktlim@umich.edu return true; 7822875Sksewell@umich.edu } 7832875Sksewell@umich.edu} 7842875Sksewell@umich.edu 7852875Sksewell@umich.edutemplate <class Impl> 7862875Sksewell@umich.eduvoid 7876221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 7882875Sksewell@umich.edu{ 7892875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 7908737Skoansin.tan@gmail.com bool deallocated = scheduleDeallocateContext(tid, false, 1); 7913221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 7925570Snate@binkert.org if ((activeThreads.size() == 1 && !deallocated) || 7933859Sbinkertn@umich.edu activeThreads.size() == 0) 7942910Sksewell@umich.edu unscheduleTickEvent(); 7958627SAli.Saidi@ARM.com 7968627SAli.Saidi@ARM.com DPRINTF(Quiesce, "Suspending Context\n"); 7978627SAli.Saidi@ARM.com lastRunningCycle = curTick(); 7982875Sksewell@umich.edu _status = Idle; 7992875Sksewell@umich.edu} 8002875Sksewell@umich.edu 8012875Sksewell@umich.edutemplate <class Impl> 8022875Sksewell@umich.eduvoid 8036221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 8042875Sksewell@umich.edu{ 8052910Sksewell@umich.edu //For now, this is the same as deallocate 8062910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 8078737Skoansin.tan@gmail.com scheduleDeallocateContext(tid, true, 1); 8082875Sksewell@umich.edu} 8092875Sksewell@umich.edu 8102875Sksewell@umich.edutemplate <class Impl> 8112875Sksewell@umich.eduvoid 8126221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 8132292SN/A{ 8142847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 8152292SN/A // Will change now that the PC and thread state is internal to the CPU 8162683Sktlim@umich.edu // and not in the ThreadContext. 8178793Sgblack@eecs.umich.edu ThreadContext *src_tc; 8188793Sgblack@eecs.umich.edu if (FullSystem) 8198793Sgblack@eecs.umich.edu src_tc = system->threadContexts[tid]; 8208793Sgblack@eecs.umich.edu else 8218793Sgblack@eecs.umich.edu src_tc = tcBase(tid); 8222292SN/A 8232292SN/A //Bind Int Regs to Rename Map 8242292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 8252292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 8262292SN/A 8272292SN/A renameMap[tid].setEntry(ireg,phys_reg); 8282292SN/A scoreboard.setReg(phys_reg); 8292292SN/A } 8302292SN/A 8312292SN/A //Bind Float Regs to Rename Map 8322292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 8332292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 8342292SN/A 8352292SN/A renameMap[tid].setEntry(freg,phys_reg); 8362292SN/A scoreboard.setReg(phys_reg); 8372292SN/A } 8382292SN/A 8392292SN/A //Copy Thread Data Into RegFile 8402847Sksewell@umich.edu //this->copyFromTC(tid); 8412292SN/A 8422847Sksewell@umich.edu //Set PC/NPC/NNPC 8437720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 8442292SN/A 8452680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 8462292SN/A 8472292SN/A activateContext(tid,1); 8482292SN/A 8492292SN/A //Reset ROB/IQ/LSQ Entries 8502292SN/A commit.rob->resetEntries(); 8512292SN/A iew.resetEntries(); 8522292SN/A} 8532292SN/A 8542292SN/Atemplate <class Impl> 8552292SN/Avoid 8566221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 8572292SN/A{ 8582877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 8592847Sksewell@umich.edu 8602847Sksewell@umich.edu // Copy Thread Data From RegFile 8612847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 8625364Sksewell@umich.edu // this->copyToTC(tid); 8635364Sksewell@umich.edu 8645364Sksewell@umich.edu 8655364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 8665364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 8675364Sksewell@umich.edu // in SMT workloads. 8682847Sksewell@umich.edu 8692847Sksewell@umich.edu // Unbind Int Regs from Rename Map 8702292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 8712292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 8722292SN/A 8732292SN/A scoreboard.unsetReg(phys_reg); 8742292SN/A freeList.addReg(phys_reg); 8752292SN/A } 8762292SN/A 8772847Sksewell@umich.edu // Unbind Float Regs from Rename Map 8785362Sksewell@umich.edu for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 8792292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 8802292SN/A 8812292SN/A scoreboard.unsetReg(phys_reg); 8822292SN/A freeList.addReg(phys_reg); 8832292SN/A } 8842292SN/A 8852847Sksewell@umich.edu // Squash Throughout Pipeline 8868138SAli.Saidi@ARM.com DynInstPtr inst = commit.rob->readHeadInst(tid); 8878138SAli.Saidi@ARM.com InstSeqNum squash_seq_num = inst->seqNum; 8888138SAli.Saidi@ARM.com fetch.squash(0, squash_seq_num, inst, tid); 8892292SN/A decode.squash(tid); 8902935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 8912875Sksewell@umich.edu iew.squash(tid); 8925363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 8932935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 8942292SN/A 8955362Sksewell@umich.edu 8965362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 8972292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 8982292SN/A 8992847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 9003229Sktlim@umich.edu 9013229Sktlim@umich.edu // Commented out for now. This should be possible to do by 9023229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 9033229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 9043229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 9053229Sktlim@umich.edu/* 9062292SN/A if (activeThreads.size() >= 1) { 9072292SN/A commit.rob->resetEntries(); 9082292SN/A iew.resetEntries(); 9092292SN/A } 9103229Sktlim@umich.edu*/ 9112292SN/A} 9122292SN/A 9132292SN/A 9142292SN/Atemplate <class Impl> 9152292SN/Avoid 9166221Snate@binkert.orgFullO3CPU<Impl>::activateWhenReady(ThreadID tid) 9172292SN/A{ 9182733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 9192292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 9202292SN/A tid); 9212292SN/A 9222292SN/A bool ready = true; 9232292SN/A 9242292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 9252733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9262292SN/A "Phys. Int. Regs.\n", 9272292SN/A tid); 9282292SN/A ready = false; 9292292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 9302733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9312292SN/A "Phys. Float. Regs.\n", 9322292SN/A tid); 9332292SN/A ready = false; 9342292SN/A } else if (commit.rob->numFreeEntries() >= 9352292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 9362733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9372292SN/A "ROB entries.\n", 9382292SN/A tid); 9392292SN/A ready = false; 9402292SN/A } else if (iew.instQueue.numFreeEntries() >= 9412292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 9422733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9432292SN/A "IQ entries.\n", 9442292SN/A tid); 9452292SN/A ready = false; 9462292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 9472292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 9482733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9492292SN/A "LSQ entries.\n", 9502292SN/A tid); 9512292SN/A ready = false; 9522292SN/A } 9532292SN/A 9542292SN/A if (ready) { 9552292SN/A insertThread(tid); 9562292SN/A 9572292SN/A contextSwitch = false; 9582292SN/A 9592292SN/A cpuWaitList.remove(tid); 9602292SN/A } else { 9612292SN/A suspendContext(tid); 9622292SN/A 9632292SN/A //blocks fetch 9642292SN/A contextSwitch = true; 9652292SN/A 9662875Sksewell@umich.edu //@todo: dont always add to waitlist 9672292SN/A //do waitlist 9682292SN/A cpuWaitList.push_back(tid); 9691060SN/A } 9701060SN/A} 9711060SN/A 9724192Sktlim@umich.edutemplate <class Impl> 9735595Sgblack@eecs.umich.eduFault 9746221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 9755702Ssaidi@eecs.umich.edu{ 9765702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9775702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 9785702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 9795702Ssaidi@eecs.umich.edu 9805702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 9815702Ssaidi@eecs.umich.edu 9825702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 9835702Ssaidi@eecs.umich.edu#endif 9845702Ssaidi@eecs.umich.edu return NoFault; 9855702Ssaidi@eecs.umich.edu} 9865702Ssaidi@eecs.umich.edu 9875702Ssaidi@eecs.umich.edutemplate <class Impl> 9885702Ssaidi@eecs.umich.edubool 9896221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 9905702Ssaidi@eecs.umich.edu{ 9915702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9925702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 9935702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 9945702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 9955702Ssaidi@eecs.umich.edu 9965702Ssaidi@eecs.umich.edu switch (palFunc) { 9975702Ssaidi@eecs.umich.edu case PAL::halt: 9985702Ssaidi@eecs.umich.edu halt(); 9995702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 10005702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 10015702Ssaidi@eecs.umich.edu break; 10025702Ssaidi@eecs.umich.edu 10035702Ssaidi@eecs.umich.edu case PAL::bpt: 10045702Ssaidi@eecs.umich.edu case PAL::bugchk: 10055702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 10065702Ssaidi@eecs.umich.edu return false; 10075702Ssaidi@eecs.umich.edu break; 10085702Ssaidi@eecs.umich.edu } 10095702Ssaidi@eecs.umich.edu#endif 10105702Ssaidi@eecs.umich.edu return true; 10115702Ssaidi@eecs.umich.edu} 10125702Ssaidi@eecs.umich.edu 10135702Ssaidi@eecs.umich.edutemplate <class Impl> 10145702Ssaidi@eecs.umich.eduFault 10155595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 10165595Sgblack@eecs.umich.edu{ 10175595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 10185647Sgblack@eecs.umich.edu return this->interrupts->getInterrupt(this->threadContexts[0]); 10195595Sgblack@eecs.umich.edu} 10205595Sgblack@eecs.umich.edu 10215595Sgblack@eecs.umich.edutemplate <class Impl> 10225595Sgblack@eecs.umich.eduvoid 10235595Sgblack@eecs.umich.eduFullO3CPU<Impl>::processInterrupts(Fault interrupt) 10245595Sgblack@eecs.umich.edu{ 10255595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 10265595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 10275595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 10285595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 10295595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 10305595Sgblack@eecs.umich.edu 10315595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 10325647Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 10335595Sgblack@eecs.umich.edu 10345595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 10357684Sgblack@eecs.umich.edu this->trap(interrupt, 0, NULL); 10365595Sgblack@eecs.umich.edu} 10375595Sgblack@eecs.umich.edu 10381060SN/Atemplate <class Impl> 10392852Sktlim@umich.eduvoid 10407684Sgblack@eecs.umich.eduFullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst) 10415595Sgblack@eecs.umich.edu{ 10425595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 10437684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 10445595Sgblack@eecs.umich.edu} 10455595Sgblack@eecs.umich.edu 10465595Sgblack@eecs.umich.edutemplate <class Impl> 10475595Sgblack@eecs.umich.eduvoid 10486221Snate@binkert.orgFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 10495595Sgblack@eecs.umich.edu{ 10505595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 10515595Sgblack@eecs.umich.edu 10525595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 10535595Sgblack@eecs.umich.edu 10545595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 10555595Sgblack@eecs.umich.edu // instruction. 10565595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 10575595Sgblack@eecs.umich.edu 10585595Sgblack@eecs.umich.edu // Execute the actual syscall. 10595595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 10605595Sgblack@eecs.umich.edu 10615595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 10625595Sgblack@eecs.umich.edu // incrementing it. 10635595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 10645595Sgblack@eecs.umich.edu} 10655595Sgblack@eecs.umich.edu 10665595Sgblack@eecs.umich.edutemplate <class Impl> 10675595Sgblack@eecs.umich.eduvoid 10682864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 10692864Sktlim@umich.edu{ 10702918Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 10712918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 10722864Sktlim@umich.edu BaseCPU::serialize(os); 10732864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 10742864Sktlim@umich.edu tickEvent.serialize(os); 10752864Sktlim@umich.edu 10762864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10772864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 10782864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 10792864Sktlim@umich.edu static SimpleThread temp; 10802864Sktlim@umich.edu 10816221Snate@binkert.org ThreadID size = thread.size(); 10826221Snate@binkert.org for (ThreadID i = 0; i < size; i++) { 10832864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 10842864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10852864Sktlim@umich.edu temp.serialize(os); 10862864Sktlim@umich.edu } 10872864Sktlim@umich.edu} 10882864Sktlim@umich.edu 10892864Sktlim@umich.edutemplate <class Impl> 10902864Sktlim@umich.eduvoid 10912864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 10922864Sktlim@umich.edu{ 10932918Sktlim@umich.edu SimObject::State so_state; 10942918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 10952864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 10962864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 10972864Sktlim@umich.edu 10982864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10992864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 11002864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 11012864Sktlim@umich.edu static SimpleThread temp; 11022864Sktlim@umich.edu 11036221Snate@binkert.org ThreadID size = thread.size(); 11046221Snate@binkert.org for (ThreadID i = 0; i < size; i++) { 11052864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 11062864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 11072864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 11082864Sktlim@umich.edu } 11092864Sktlim@umich.edu} 11102864Sktlim@umich.edu 11112864Sktlim@umich.edutemplate <class Impl> 11122905Sktlim@umich.eduunsigned int 11132843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 11141060SN/A{ 11153125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 11163512Sktlim@umich.edu 11173512Sktlim@umich.edu // If the CPU isn't doing anything, then return immediately. 11183512Sktlim@umich.edu if (_status == Idle || _status == SwitchedOut) { 11193512Sktlim@umich.edu return 0; 11203512Sktlim@umich.edu } 11213512Sktlim@umich.edu 11222843Sktlim@umich.edu drainCount = 0; 11232843Sktlim@umich.edu fetch.drain(); 11242843Sktlim@umich.edu decode.drain(); 11252843Sktlim@umich.edu rename.drain(); 11262843Sktlim@umich.edu iew.drain(); 11272843Sktlim@umich.edu commit.drain(); 11282325SN/A 11292325SN/A // Wake the CPU and record activity so everything can drain out if 11302863Sktlim@umich.edu // the CPU was not able to immediately drain. 11312905Sktlim@umich.edu if (getState() != SimObject::Drained) { 11322864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 11332864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 11342864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 11352864Sktlim@umich.edu // process on the drain event. 11362864Sktlim@umich.edu drainEvent = drain_event; 11372843Sktlim@umich.edu 11382863Sktlim@umich.edu wakeCPU(); 11392863Sktlim@umich.edu activityRec.activity(); 11402852Sktlim@umich.edu 11412905Sktlim@umich.edu return 1; 11422863Sktlim@umich.edu } else { 11432905Sktlim@umich.edu return 0; 11442863Sktlim@umich.edu } 11452316SN/A} 11462310SN/A 11472316SN/Atemplate <class Impl> 11482316SN/Avoid 11492843Sktlim@umich.eduFullO3CPU<Impl>::resume() 11502316SN/A{ 11512843Sktlim@umich.edu fetch.resume(); 11522843Sktlim@umich.edu decode.resume(); 11532843Sktlim@umich.edu rename.resume(); 11542843Sktlim@umich.edu iew.resume(); 11552843Sktlim@umich.edu commit.resume(); 11562316SN/A 11572905Sktlim@umich.edu changeState(SimObject::Running); 11582905Sktlim@umich.edu 11592864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 11602864Sktlim@umich.edu return; 11612864Sktlim@umich.edu 11624762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 11633319Shsul@eecs.umich.edu 11642843Sktlim@umich.edu if (!tickEvent.scheduled()) 11655606Snate@binkert.org schedule(tickEvent, nextCycle()); 11662843Sktlim@umich.edu _status = Running; 11672843Sktlim@umich.edu} 11682316SN/A 11692843Sktlim@umich.edutemplate <class Impl> 11702843Sktlim@umich.eduvoid 11712843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 11722843Sktlim@umich.edu{ 11732843Sktlim@umich.edu if (++drainCount == NumStages) { 11742316SN/A if (tickEvent.scheduled()) 11752316SN/A tickEvent.squash(); 11762863Sktlim@umich.edu 11772905Sktlim@umich.edu changeState(SimObject::Drained); 11782863Sktlim@umich.edu 11793126Sktlim@umich.edu BaseCPU::switchOut(); 11803126Sktlim@umich.edu 11812863Sktlim@umich.edu if (drainEvent) { 11822863Sktlim@umich.edu drainEvent->process(); 11832863Sktlim@umich.edu drainEvent = NULL; 11842863Sktlim@umich.edu } 11852310SN/A } 11862843Sktlim@umich.edu assert(drainCount <= 5); 11872843Sktlim@umich.edu} 11882843Sktlim@umich.edu 11892843Sktlim@umich.edutemplate <class Impl> 11902843Sktlim@umich.eduvoid 11912843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 11922843Sktlim@umich.edu{ 11932843Sktlim@umich.edu fetch.switchOut(); 11942843Sktlim@umich.edu rename.switchOut(); 11952325SN/A iew.switchOut(); 11962843Sktlim@umich.edu commit.switchOut(); 11972843Sktlim@umich.edu instList.clear(); 11982843Sktlim@umich.edu while (!removeList.empty()) { 11992843Sktlim@umich.edu removeList.pop(); 12002843Sktlim@umich.edu } 12012843Sktlim@umich.edu 12022843Sktlim@umich.edu _status = SwitchedOut; 12038887Sgeoffrey.blake@arm.com 12042843Sktlim@umich.edu if (checker) 12052843Sktlim@umich.edu checker->switchOut(); 12068887Sgeoffrey.blake@arm.com 12073126Sktlim@umich.edu if (tickEvent.scheduled()) 12083126Sktlim@umich.edu tickEvent.squash(); 12091060SN/A} 12101060SN/A 12111060SN/Atemplate <class Impl> 12121060SN/Avoid 12131755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 12141060SN/A{ 12152325SN/A // Flush out any old data from the time buffers. 12162873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 12172307SN/A timeBuffer.advance(); 12182307SN/A fetchQueue.advance(); 12192307SN/A decodeQueue.advance(); 12202307SN/A renameQueue.advance(); 12212307SN/A iewQueue.advance(); 12222307SN/A } 12232307SN/A 12242325SN/A activityRec.reset(); 12252307SN/A 12268737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 12271060SN/A 12282307SN/A fetch.takeOverFrom(); 12292307SN/A decode.takeOverFrom(); 12302307SN/A rename.takeOverFrom(); 12312307SN/A iew.takeOverFrom(); 12322307SN/A commit.takeOverFrom(); 12332307SN/A 12347507Stjones1@inf.ed.ac.uk assert(!tickEvent.scheduled() || tickEvent.squashed()); 12351060SN/A 12362325SN/A // @todo: Figure out how to properly select the tid to put onto 12372325SN/A // the active threads list. 12386221Snate@binkert.org ThreadID tid = 0; 12392307SN/A 12406221Snate@binkert.org list<ThreadID>::iterator isActive = 12415314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 12422307SN/A 12432307SN/A if (isActive == activeThreads.end()) { 12442325SN/A //May Need to Re-code this if the delay variable is the delay 12452325SN/A //needed for thread to activate 12462733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 12472307SN/A tid); 12482307SN/A 12492307SN/A activeThreads.push_back(tid); 12502307SN/A } 12512307SN/A 12522325SN/A // Set all statuses to active, schedule the CPU's tick event. 12532307SN/A // @todo: Fix up statuses so this is handled properly 12546221Snate@binkert.org ThreadID size = threadContexts.size(); 12556221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 12562680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 12572680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 12581681SN/A _status = Running; 12597507Stjones1@inf.ed.ac.uk reschedule(tickEvent, nextCycle(), true); 12601681SN/A } 12611060SN/A } 12622307SN/A if (!tickEvent.scheduled()) 12635606Snate@binkert.org schedule(tickEvent, nextCycle()); 12648627SAli.Saidi@ARM.com 12658627SAli.Saidi@ARM.com lastRunningCycle = curTick(); 12661060SN/A} 12671060SN/A 12681060SN/Atemplate <class Impl> 12695595Sgblack@eecs.umich.eduTheISA::MiscReg 12706221Snate@binkert.orgFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) 12715595Sgblack@eecs.umich.edu{ 12726313Sgblack@eecs.umich.edu return this->isa[tid].readMiscRegNoEffect(misc_reg); 12735595Sgblack@eecs.umich.edu} 12745595Sgblack@eecs.umich.edu 12755595Sgblack@eecs.umich.edutemplate <class Impl> 12765595Sgblack@eecs.umich.eduTheISA::MiscReg 12776221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 12785595Sgblack@eecs.umich.edu{ 12797897Shestness@cs.utexas.edu miscRegfileReads++; 12806313Sgblack@eecs.umich.edu return this->isa[tid].readMiscReg(misc_reg, tcBase(tid)); 12815595Sgblack@eecs.umich.edu} 12825595Sgblack@eecs.umich.edu 12835595Sgblack@eecs.umich.edutemplate <class Impl> 12845595Sgblack@eecs.umich.eduvoid 12855595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 12866221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12875595Sgblack@eecs.umich.edu{ 12886313Sgblack@eecs.umich.edu this->isa[tid].setMiscRegNoEffect(misc_reg, val); 12895595Sgblack@eecs.umich.edu} 12905595Sgblack@eecs.umich.edu 12915595Sgblack@eecs.umich.edutemplate <class Impl> 12925595Sgblack@eecs.umich.eduvoid 12935595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 12946221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12955595Sgblack@eecs.umich.edu{ 12967897Shestness@cs.utexas.edu miscRegfileWrites++; 12976313Sgblack@eecs.umich.edu this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid)); 12985595Sgblack@eecs.umich.edu} 12995595Sgblack@eecs.umich.edu 13005595Sgblack@eecs.umich.edutemplate <class Impl> 13011060SN/Auint64_t 13021755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 13031060SN/A{ 13047897Shestness@cs.utexas.edu intRegfileReads++; 13051060SN/A return regFile.readIntReg(reg_idx); 13061060SN/A} 13071060SN/A 13081060SN/Atemplate <class Impl> 13092455SN/AFloatReg 13102455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 13111060SN/A{ 13127897Shestness@cs.utexas.edu fpRegfileReads++; 13132455SN/A return regFile.readFloatReg(reg_idx); 13141060SN/A} 13151060SN/A 13161060SN/Atemplate <class Impl> 13172455SN/AFloatRegBits 13182455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 13192455SN/A{ 13207897Shestness@cs.utexas.edu fpRegfileReads++; 13212455SN/A return regFile.readFloatRegBits(reg_idx); 13221060SN/A} 13231060SN/A 13241060SN/Atemplate <class Impl> 13251060SN/Avoid 13261755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 13271060SN/A{ 13287897Shestness@cs.utexas.edu intRegfileWrites++; 13291060SN/A regFile.setIntReg(reg_idx, val); 13301060SN/A} 13311060SN/A 13321060SN/Atemplate <class Impl> 13331060SN/Avoid 13342455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 13351060SN/A{ 13367897Shestness@cs.utexas.edu fpRegfileWrites++; 13372455SN/A regFile.setFloatReg(reg_idx, val); 13381060SN/A} 13391060SN/A 13401060SN/Atemplate <class Impl> 13411060SN/Avoid 13422455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 13432455SN/A{ 13447897Shestness@cs.utexas.edu fpRegfileWrites++; 13452455SN/A regFile.setFloatRegBits(reg_idx, val); 13461060SN/A} 13471060SN/A 13481060SN/Atemplate <class Impl> 13491060SN/Auint64_t 13506221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 13511060SN/A{ 13527897Shestness@cs.utexas.edu intRegfileReads++; 13532292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13542292SN/A 13552292SN/A return regFile.readIntReg(phys_reg); 13562292SN/A} 13572292SN/A 13582292SN/Atemplate <class Impl> 13592292SN/Afloat 13606314Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 13612292SN/A{ 13627897Shestness@cs.utexas.edu fpRegfileReads++; 13636032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13642307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13652292SN/A 13662669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 13672292SN/A} 13682292SN/A 13692292SN/Atemplate <class Impl> 13702292SN/Auint64_t 13716221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 13722292SN/A{ 13737897Shestness@cs.utexas.edu fpRegfileReads++; 13746032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13752307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13762292SN/A 13772669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 13781060SN/A} 13791060SN/A 13801060SN/Atemplate <class Impl> 13811060SN/Avoid 13826221Snate@binkert.orgFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 13831060SN/A{ 13847897Shestness@cs.utexas.edu intRegfileWrites++; 13852292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13862292SN/A 13872292SN/A regFile.setIntReg(phys_reg, val); 13881060SN/A} 13891060SN/A 13901060SN/Atemplate <class Impl> 13911060SN/Avoid 13926314Sgblack@eecs.umich.eduFullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 13931060SN/A{ 13947897Shestness@cs.utexas.edu fpRegfileWrites++; 13956032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13962918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13972292SN/A 13982669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 13991060SN/A} 14001060SN/A 14011060SN/Atemplate <class Impl> 14021060SN/Avoid 14036221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 14041060SN/A{ 14057897Shestness@cs.utexas.edu fpRegfileWrites++; 14066032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 14072918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 14081060SN/A 14092669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 14102292SN/A} 14112292SN/A 14122292SN/Atemplate <class Impl> 14137720Sgblack@eecs.umich.eduTheISA::PCState 14147720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 14152292SN/A{ 14167720Sgblack@eecs.umich.edu return commit.pcState(tid); 14171060SN/A} 14181060SN/A 14191060SN/Atemplate <class Impl> 14201060SN/Avoid 14217720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 14221060SN/A{ 14237720Sgblack@eecs.umich.edu commit.pcState(val, tid); 14242292SN/A} 14251060SN/A 14262292SN/Atemplate <class Impl> 14277720Sgblack@eecs.umich.eduAddr 14287720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 14294636Sgblack@eecs.umich.edu{ 14307720Sgblack@eecs.umich.edu return commit.instAddr(tid); 14314636Sgblack@eecs.umich.edu} 14324636Sgblack@eecs.umich.edu 14334636Sgblack@eecs.umich.edutemplate <class Impl> 14347720Sgblack@eecs.umich.eduAddr 14357720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 14364636Sgblack@eecs.umich.edu{ 14377720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 14384636Sgblack@eecs.umich.edu} 14394636Sgblack@eecs.umich.edu 14404636Sgblack@eecs.umich.edutemplate <class Impl> 14417720Sgblack@eecs.umich.eduMicroPC 14427720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 14432292SN/A{ 14447720Sgblack@eecs.umich.edu return commit.microPC(tid); 14454636Sgblack@eecs.umich.edu} 14464636Sgblack@eecs.umich.edu 14474636Sgblack@eecs.umich.edutemplate <class Impl> 14485595Sgblack@eecs.umich.eduvoid 14496221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 14505595Sgblack@eecs.umich.edu{ 14515595Sgblack@eecs.umich.edu this->thread[tid]->inSyscall = true; 14525595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 14535595Sgblack@eecs.umich.edu} 14545595Sgblack@eecs.umich.edu 14555595Sgblack@eecs.umich.edutemplate <class Impl> 14562292SN/Atypename FullO3CPU<Impl>::ListIt 14572292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 14582292SN/A{ 14592292SN/A instList.push_back(inst); 14601060SN/A 14612292SN/A return --(instList.end()); 14622292SN/A} 14631060SN/A 14642292SN/Atemplate <class Impl> 14652292SN/Avoid 14668834Satgutier@umich.eduFullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst) 14672292SN/A{ 14682292SN/A // Keep an instruction count. 14698834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) { 14708834Satgutier@umich.edu thread[tid]->numInst++; 14718834Satgutier@umich.edu thread[tid]->numInsts++; 14728834Satgutier@umich.edu committedInsts[tid]++; 14738834Satgutier@umich.edu totalCommittedInsts++; 14748834Satgutier@umich.edu } 14758834Satgutier@umich.edu thread[tid]->numOp++; 14768834Satgutier@umich.edu thread[tid]->numOps++; 14778834Satgutier@umich.edu committedOps[tid]++; 14788834Satgutier@umich.edu 14797897Shestness@cs.utexas.edu system->totalNumInsts++; 14802292SN/A // Check for instruction-count-based events. 14812292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 14827897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 14832292SN/A} 14842292SN/A 14852292SN/Atemplate <class Impl> 14862292SN/Avoid 14871755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 14881060SN/A{ 14897720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 14902292SN/A "[sn:%lli]\n", 14917720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 14921060SN/A 14932292SN/A removeInstsThisCycle = true; 14941060SN/A 14951060SN/A // Remove the front instruction. 14962292SN/A removeList.push(inst->getInstListIt()); 14971060SN/A} 14981060SN/A 14991060SN/Atemplate <class Impl> 15001060SN/Avoid 15016221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 15021060SN/A{ 15032733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 15042292SN/A " list.\n", tid); 15051060SN/A 15062292SN/A ListIt end_it; 15071060SN/A 15082292SN/A bool rob_empty = false; 15092292SN/A 15102292SN/A if (instList.empty()) { 15112292SN/A return; 15122292SN/A } else if (rob.isEmpty(/*tid*/)) { 15132733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 15142292SN/A end_it = instList.begin(); 15152292SN/A rob_empty = true; 15162292SN/A } else { 15172292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 15182733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 15192292SN/A } 15202292SN/A 15212292SN/A removeInstsThisCycle = true; 15222292SN/A 15232292SN/A ListIt inst_it = instList.end(); 15242292SN/A 15252292SN/A inst_it--; 15262292SN/A 15272292SN/A // Walk through the instruction list, removing any instructions 15282292SN/A // that were inserted after the given instruction iterator, end_it. 15292292SN/A while (inst_it != end_it) { 15302292SN/A assert(!instList.empty()); 15312292SN/A 15322292SN/A squashInstIt(inst_it, tid); 15332292SN/A 15342292SN/A inst_it--; 15352292SN/A } 15362292SN/A 15372292SN/A // If the ROB was empty, then we actually need to remove the first 15382292SN/A // instruction as well. 15392292SN/A if (rob_empty) { 15402292SN/A squashInstIt(inst_it, tid); 15412292SN/A } 15421060SN/A} 15431060SN/A 15441060SN/Atemplate <class Impl> 15451060SN/Avoid 15466221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 15471062SN/A{ 15482292SN/A assert(!instList.empty()); 15492292SN/A 15502292SN/A removeInstsThisCycle = true; 15512292SN/A 15522292SN/A ListIt inst_iter = instList.end(); 15532292SN/A 15542292SN/A inst_iter--; 15552292SN/A 15562733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 15572292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 15582292SN/A tid, seq_num, (*inst_iter)->seqNum); 15591062SN/A 15602292SN/A while ((*inst_iter)->seqNum > seq_num) { 15611062SN/A 15622292SN/A bool break_loop = (inst_iter == instList.begin()); 15631062SN/A 15642292SN/A squashInstIt(inst_iter, tid); 15651062SN/A 15662292SN/A inst_iter--; 15671062SN/A 15682292SN/A if (break_loop) 15692292SN/A break; 15702292SN/A } 15712292SN/A} 15722292SN/A 15732292SN/Atemplate <class Impl> 15742292SN/Ainline void 15756221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 15762292SN/A{ 15772292SN/A if ((*instIt)->threadNumber == tid) { 15782733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 15797720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 15802292SN/A (*instIt)->threadNumber, 15812292SN/A (*instIt)->seqNum, 15827720Sgblack@eecs.umich.edu (*instIt)->pcState()); 15831062SN/A 15841062SN/A // Mark it as squashed. 15852292SN/A (*instIt)->setSquashed(); 15862292SN/A 15872325SN/A // @todo: Formulate a consistent method for deleting 15882325SN/A // instructions from the instruction list 15892292SN/A // Remove the instruction from the list. 15902292SN/A removeList.push(instIt); 15912292SN/A } 15922292SN/A} 15932292SN/A 15942292SN/Atemplate <class Impl> 15952292SN/Avoid 15962292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 15972292SN/A{ 15982292SN/A while (!removeList.empty()) { 15992733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 16007720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 16012292SN/A (*removeList.front())->threadNumber, 16022292SN/A (*removeList.front())->seqNum, 16037720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 16042292SN/A 16052292SN/A instList.erase(removeList.front()); 16062292SN/A 16072292SN/A removeList.pop(); 16081062SN/A } 16091062SN/A 16102292SN/A removeInstsThisCycle = false; 16111062SN/A} 16122325SN/A/* 16131062SN/Atemplate <class Impl> 16141062SN/Avoid 16151755SN/AFullO3CPU<Impl>::removeAllInsts() 16161060SN/A{ 16171060SN/A instList.clear(); 16181060SN/A} 16192325SN/A*/ 16201060SN/Atemplate <class Impl> 16211060SN/Avoid 16221755SN/AFullO3CPU<Impl>::dumpInsts() 16231060SN/A{ 16241060SN/A int num = 0; 16251060SN/A 16262292SN/A ListIt inst_list_it = instList.begin(); 16272292SN/A 16282292SN/A cprintf("Dumping Instruction List\n"); 16292292SN/A 16302292SN/A while (inst_list_it != instList.end()) { 16312292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 16322292SN/A "Squashed:%i\n\n", 16337720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 16342292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 16352292SN/A (*inst_list_it)->isSquashed()); 16361060SN/A inst_list_it++; 16371060SN/A ++num; 16381060SN/A } 16391060SN/A} 16402325SN/A/* 16411060SN/Atemplate <class Impl> 16421060SN/Avoid 16431755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 16441060SN/A{ 16451060SN/A iew.wakeDependents(inst); 16461060SN/A} 16472325SN/A*/ 16482292SN/Atemplate <class Impl> 16492292SN/Avoid 16502292SN/AFullO3CPU<Impl>::wakeCPU() 16512292SN/A{ 16522325SN/A if (activityRec.active() || tickEvent.scheduled()) { 16532325SN/A DPRINTF(Activity, "CPU already running.\n"); 16542292SN/A return; 16552292SN/A } 16562292SN/A 16572325SN/A DPRINTF(Activity, "Waking up CPU\n"); 16582325SN/A 16597823Ssteve.reinhardt@amd.com idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle); 16607823Ssteve.reinhardt@amd.com numCycles += tickToCycles((curTick() - 1) - lastRunningCycle); 16612292SN/A 16625606Snate@binkert.org schedule(tickEvent, nextCycle()); 16632292SN/A} 16642292SN/A 16655807Snate@binkert.orgtemplate <class Impl> 16665807Snate@binkert.orgvoid 16675807Snate@binkert.orgFullO3CPU<Impl>::wakeup() 16685807Snate@binkert.org{ 16695807Snate@binkert.org if (this->thread[0]->status() != ThreadContext::Suspended) 16705807Snate@binkert.org return; 16715807Snate@binkert.org 16725807Snate@binkert.org this->wakeCPU(); 16735807Snate@binkert.org 16745807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 16755807Snate@binkert.org this->threadContexts[0]->activate(); 16765807Snate@binkert.org} 16775807Snate@binkert.org 16782292SN/Atemplate <class Impl> 16796221Snate@binkert.orgThreadID 16802292SN/AFullO3CPU<Impl>::getFreeTid() 16812292SN/A{ 16826221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 16836221Snate@binkert.org if (!tids[tid]) { 16846221Snate@binkert.org tids[tid] = true; 16856221Snate@binkert.org return tid; 16862292SN/A } 16872292SN/A } 16882292SN/A 16896221Snate@binkert.org return InvalidThreadID; 16902292SN/A} 16912292SN/A 16922292SN/Atemplate <class Impl> 16932292SN/Avoid 16942292SN/AFullO3CPU<Impl>::doContextSwitch() 16952292SN/A{ 16962292SN/A if (contextSwitch) { 16972292SN/A 16982292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 16992292SN/A 17006221Snate@binkert.org ThreadID size = cpuWaitList.size(); 17016221Snate@binkert.org for (ThreadID tid = 0; tid < size; tid++) { 17022292SN/A activateWhenReady(tid); 17032292SN/A } 17042292SN/A 17052292SN/A if (cpuWaitList.size() == 0) 17062292SN/A contextSwitch = true; 17072292SN/A } 17082292SN/A} 17092292SN/A 17102292SN/Atemplate <class Impl> 17112292SN/Avoid 17122292SN/AFullO3CPU<Impl>::updateThreadPriority() 17132292SN/A{ 17146221Snate@binkert.org if (activeThreads.size() > 1) { 17152292SN/A //DEFAULT TO ROUND ROBIN SCHEME 17162292SN/A //e.g. Move highest priority to end of thread list 17176221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 17182292SN/A 17192292SN/A unsigned high_thread = *list_begin; 17202292SN/A 17212292SN/A activeThreads.erase(list_begin); 17222292SN/A 17232292SN/A activeThreads.push_back(high_thread); 17242292SN/A } 17252292SN/A} 17261060SN/A 17271755SN/A// Forward declaration of FullO3CPU. 17282818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1729