cpu.cc revision 8876
11689SN/A/* 28707Sandreas.hansson@arm.com * Copyright (c) 2011 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 142325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422756Sksewell@umich.edu * Korey Sewell 437897Shestness@cs.utexas.edu * Rick Strong 441689SN/A */ 451689SN/A 468779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 482733Sktlim@umich.edu#include "config/use_checker.hh" 498229Snate@binkert.org#include "cpu/o3/cpu.hh" 508229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 518229Snate@binkert.org#include "cpu/o3/thread_context.hh" 524762Snate@binkert.org#include "cpu/activity.hh" 538779Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 544762Snate@binkert.org#include "cpu/simple_thread.hh" 554762Snate@binkert.org#include "cpu/thread_context.hh" 568232Snate@binkert.org#include "debug/Activity.hh" 578232Snate@binkert.org#include "debug/O3CPU.hh" 588232Snate@binkert.org#include "debug/Quiesce.hh" 594762Snate@binkert.org#include "enums/MemoryMode.hh" 604762Snate@binkert.org#include "sim/core.hh" 618793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 628779Sgblack@eecs.umich.edu#include "sim/process.hh" 634762Snate@binkert.org#include "sim/stat_control.hh" 648460SAli.Saidi@ARM.com#include "sim/system.hh" 654762Snate@binkert.org 662794Sktlim@umich.edu#if USE_CHECKER 672794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 688733Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 692794Sktlim@umich.edu#endif 702794Sktlim@umich.edu 715702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 725702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 738232Snate@binkert.org#include "debug/Activity.hh" 745702Ssaidi@eecs.umich.edu#endif 755702Ssaidi@eecs.umich.edu 768737Skoansin.tan@gmail.comstruct BaseCPUParams; 775529Snate@binkert.org 782669Sktlim@umich.eduusing namespace TheISA; 796221Snate@binkert.orgusing namespace std; 801060SN/A 815529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 825712Shsul@eecs.umich.edu : BaseCPU(params) 831060SN/A{ 841060SN/A} 851060SN/A 862292SN/Avoid 872733Sktlim@umich.eduBaseO3CPU::regStats() 882292SN/A{ 892292SN/A BaseCPU::regStats(); 902292SN/A} 912292SN/A 928707Sandreas.hansson@arm.comtemplate<class Impl> 938707Sandreas.hansson@arm.combool 948707Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvTiming(PacketPtr pkt) 958707Sandreas.hansson@arm.com{ 968707Sandreas.hansson@arm.com DPRINTF(O3CPU, "Fetch unit received timing\n"); 978707Sandreas.hansson@arm.com if (pkt->isResponse()) { 988707Sandreas.hansson@arm.com // We shouldn't ever get a block in ownership state 998707Sandreas.hansson@arm.com assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); 1008707Sandreas.hansson@arm.com 1018707Sandreas.hansson@arm.com fetch->processCacheCompletion(pkt); 1028707Sandreas.hansson@arm.com } 1038707Sandreas.hansson@arm.com //else Snooped a coherence request, just return 1048707Sandreas.hansson@arm.com return true; 1058707Sandreas.hansson@arm.com} 1068707Sandreas.hansson@arm.com 1078707Sandreas.hansson@arm.comtemplate<class Impl> 1088707Sandreas.hansson@arm.comvoid 1098707Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvRetry() 1108707Sandreas.hansson@arm.com{ 1118707Sandreas.hansson@arm.com fetch->recvRetry(); 1128707Sandreas.hansson@arm.com} 1138707Sandreas.hansson@arm.com 1148707Sandreas.hansson@arm.comtemplate <class Impl> 1158707Sandreas.hansson@arm.combool 1168707Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTiming(PacketPtr pkt) 1178707Sandreas.hansson@arm.com{ 1188707Sandreas.hansson@arm.com return lsq->recvTiming(pkt); 1198707Sandreas.hansson@arm.com} 1208707Sandreas.hansson@arm.com 1218707Sandreas.hansson@arm.comtemplate <class Impl> 1228707Sandreas.hansson@arm.comvoid 1238707Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvRetry() 1248707Sandreas.hansson@arm.com{ 1258707Sandreas.hansson@arm.com lsq->recvRetry(); 1268707Sandreas.hansson@arm.com} 1278707Sandreas.hansson@arm.com 1281060SN/Atemplate <class Impl> 1291755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 1305606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 1311060SN/A{ 1321060SN/A} 1331060SN/A 1341060SN/Atemplate <class Impl> 1351060SN/Avoid 1361755SN/AFullO3CPU<Impl>::TickEvent::process() 1371060SN/A{ 1381060SN/A cpu->tick(); 1391060SN/A} 1401060SN/A 1411060SN/Atemplate <class Impl> 1421060SN/Aconst char * 1435336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 1441060SN/A{ 1454873Sstever@eecs.umich.edu return "FullO3CPU tick"; 1461060SN/A} 1471060SN/A 1481060SN/Atemplate <class Impl> 1492829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 1505606Snate@binkert.org : Event(CPU_Switch_Pri) 1512829Sksewell@umich.edu{ 1522829Sksewell@umich.edu} 1532829Sksewell@umich.edu 1542829Sksewell@umich.edutemplate <class Impl> 1552829Sksewell@umich.eduvoid 1562829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 1572829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1582829Sksewell@umich.edu{ 1592829Sksewell@umich.edu tid = thread_num; 1602829Sksewell@umich.edu cpu = thread_cpu; 1612829Sksewell@umich.edu} 1622829Sksewell@umich.edu 1632829Sksewell@umich.edutemplate <class Impl> 1642829Sksewell@umich.eduvoid 1652829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1662829Sksewell@umich.edu{ 1672829Sksewell@umich.edu cpu->activateThread(tid); 1682829Sksewell@umich.edu} 1692829Sksewell@umich.edu 1702829Sksewell@umich.edutemplate <class Impl> 1712829Sksewell@umich.educonst char * 1725336Shines@cs.fsu.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1732829Sksewell@umich.edu{ 1744873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1752829Sksewell@umich.edu} 1762829Sksewell@umich.edu 1772829Sksewell@umich.edutemplate <class Impl> 1782875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1795606Snate@binkert.org : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1802875Sksewell@umich.edu{ 1812875Sksewell@umich.edu} 1822875Sksewell@umich.edu 1832875Sksewell@umich.edutemplate <class Impl> 1842875Sksewell@umich.eduvoid 1852875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1863859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1872875Sksewell@umich.edu{ 1882875Sksewell@umich.edu tid = thread_num; 1892875Sksewell@umich.edu cpu = thread_cpu; 1903859Sbinkertn@umich.edu remove = false; 1912875Sksewell@umich.edu} 1922875Sksewell@umich.edu 1932875Sksewell@umich.edutemplate <class Impl> 1942875Sksewell@umich.eduvoid 1952875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1962875Sksewell@umich.edu{ 1972875Sksewell@umich.edu cpu->deactivateThread(tid); 1983221Sktlim@umich.edu if (remove) 1993221Sktlim@umich.edu cpu->removeThread(tid); 2002875Sksewell@umich.edu} 2012875Sksewell@umich.edu 2022875Sksewell@umich.edutemplate <class Impl> 2032875Sksewell@umich.educonst char * 2045336Shines@cs.fsu.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 2052875Sksewell@umich.edu{ 2064873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 2072875Sksewell@umich.edu} 2082875Sksewell@umich.edu 2092875Sksewell@umich.edutemplate <class Impl> 2105595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 2112733Sktlim@umich.edu : BaseO3CPU(params), 2123781Sgblack@eecs.umich.edu itb(params->itb), 2133781Sgblack@eecs.umich.edu dtb(params->dtb), 2141060SN/A tickEvent(this), 2155737Scws3k@cs.virginia.edu#ifndef NDEBUG 2165737Scws3k@cs.virginia.edu instcount(0), 2175737Scws3k@cs.virginia.edu#endif 2182292SN/A removeInstsThisCycle(false), 2195595Sgblack@eecs.umich.edu fetch(this, params), 2205595Sgblack@eecs.umich.edu decode(this, params), 2215595Sgblack@eecs.umich.edu rename(this, params), 2225595Sgblack@eecs.umich.edu iew(this, params), 2235595Sgblack@eecs.umich.edu commit(this, params), 2241060SN/A 2255595Sgblack@eecs.umich.edu regFile(this, params->numPhysIntRegs, 2264329Sktlim@umich.edu params->numPhysFloatRegs), 2271060SN/A 2285529Snate@binkert.org freeList(params->numThreads, 2292292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 2302292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 2311060SN/A 2325595Sgblack@eecs.umich.edu rob(this, 2334329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 2342292SN/A params->smtROBPolicy, params->smtROBThreshold, 2355529Snate@binkert.org params->numThreads), 2361060SN/A 2375529Snate@binkert.org scoreboard(params->numThreads, 2382292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 2392292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 2406221Snate@binkert.org TheISA::NumMiscRegs * numThreads, 2412292SN/A TheISA::ZeroReg), 2421060SN/A 2438707Sandreas.hansson@arm.com icachePort(&fetch, this), 2448707Sandreas.hansson@arm.com dcachePort(&iew.ldstQueue, this), 2458707Sandreas.hansson@arm.com 2462873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 2472873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 2482873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 2492873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 2502873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 2515804Snate@binkert.org activityRec(name(), NumStages, 2522873Sktlim@umich.edu params->backComSize + params->forwardComSize, 2532873Sktlim@umich.edu params->activity), 2541060SN/A 2551060SN/A globalSeqNum(1), 2562292SN/A system(params->system), 2572843Sktlim@umich.edu drainCount(0), 2586221Snate@binkert.org deferRegistration(params->defer_registration) 2591060SN/A{ 2603221Sktlim@umich.edu if (!deferRegistration) { 2613221Sktlim@umich.edu _status = Running; 2623221Sktlim@umich.edu } else { 2633221Sktlim@umich.edu _status = Idle; 2643221Sktlim@umich.edu } 2651681SN/A 2664598Sbinkertn@umich.edu#if USE_CHECKER 2672794Sktlim@umich.edu if (params->checker) { 2682316SN/A BaseCPU *temp_checker = params->checker; 2698733Sgeoffrey.blake@arm.com checker = dynamic_cast<Checker<Impl> *>(temp_checker); 2708707Sandreas.hansson@arm.com checker->setIcachePort(&icachePort); 2712316SN/A checker->setSystem(params->system); 2724598Sbinkertn@umich.edu } else { 2734598Sbinkertn@umich.edu checker = NULL; 2744598Sbinkertn@umich.edu } 2752794Sktlim@umich.edu#endif // USE_CHECKER 2762316SN/A 2778793Sgblack@eecs.umich.edu if (!FullSystem) { 2788793Sgblack@eecs.umich.edu thread.resize(numThreads); 2798793Sgblack@eecs.umich.edu tids.resize(numThreads); 2808793Sgblack@eecs.umich.edu } 2811681SN/A 2822325SN/A // The stages also need their CPU pointer setup. However this 2832325SN/A // must be done at the upper level CPU because they have pointers 2842325SN/A // to the upper level CPU, and not this FullO3CPU. 2851060SN/A 2862292SN/A // Set up Pointers to the activeThreads list for each stage 2872292SN/A fetch.setActiveThreads(&activeThreads); 2882292SN/A decode.setActiveThreads(&activeThreads); 2892292SN/A rename.setActiveThreads(&activeThreads); 2902292SN/A iew.setActiveThreads(&activeThreads); 2912292SN/A commit.setActiveThreads(&activeThreads); 2921060SN/A 2931060SN/A // Give each of the stages the time buffer they will use. 2941060SN/A fetch.setTimeBuffer(&timeBuffer); 2951060SN/A decode.setTimeBuffer(&timeBuffer); 2961060SN/A rename.setTimeBuffer(&timeBuffer); 2971060SN/A iew.setTimeBuffer(&timeBuffer); 2981060SN/A commit.setTimeBuffer(&timeBuffer); 2991060SN/A 3001060SN/A // Also setup each of the stages' queues. 3011060SN/A fetch.setFetchQueue(&fetchQueue); 3021060SN/A decode.setFetchQueue(&fetchQueue); 3032292SN/A commit.setFetchQueue(&fetchQueue); 3041060SN/A decode.setDecodeQueue(&decodeQueue); 3051060SN/A rename.setDecodeQueue(&decodeQueue); 3061060SN/A rename.setRenameQueue(&renameQueue); 3071060SN/A iew.setRenameQueue(&renameQueue); 3081060SN/A iew.setIEWQueue(&iewQueue); 3091060SN/A commit.setIEWQueue(&iewQueue); 3101060SN/A commit.setRenameQueue(&renameQueue); 3111060SN/A 3122292SN/A commit.setIEWStage(&iew); 3132292SN/A rename.setIEWStage(&iew); 3142292SN/A rename.setCommitStage(&commit); 3152292SN/A 3168793Sgblack@eecs.umich.edu ThreadID active_threads; 3178793Sgblack@eecs.umich.edu if (FullSystem) { 3188793Sgblack@eecs.umich.edu active_threads = 1; 3198793Sgblack@eecs.umich.edu } else { 3208793Sgblack@eecs.umich.edu active_threads = params->workload.size(); 3212831Sksewell@umich.edu 3228793Sgblack@eecs.umich.edu if (active_threads > Impl::MaxThreads) { 3238793Sgblack@eecs.umich.edu panic("Workload Size too large. Increase the 'MaxThreads' " 3248793Sgblack@eecs.umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 3258793Sgblack@eecs.umich.edu "or edit your workload size."); 3268793Sgblack@eecs.umich.edu } 3272831Sksewell@umich.edu } 3282292SN/A 3292316SN/A //Make Sure That this a Valid Architeture 3302292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 3312292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 3322292SN/A 3332292SN/A rename.setScoreboard(&scoreboard); 3342292SN/A iew.setScoreboard(&scoreboard); 3352292SN/A 3361060SN/A // Setup the rename map for whichever stages need it. 3372292SN/A PhysRegIndex lreg_idx = 0; 3382292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 3391060SN/A 3406221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3412307SN/A bool bindRegs = (tid <= active_threads - 1); 3422292SN/A 3432292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 3442292SN/A params->numPhysIntRegs, 3452325SN/A lreg_idx, //Index for Logical. Regs 3462292SN/A 3472292SN/A TheISA::NumFloatRegs, 3482292SN/A params->numPhysFloatRegs, 3492325SN/A freg_idx, //Index for Float Regs 3502292SN/A 3512292SN/A TheISA::NumMiscRegs, 3522292SN/A 3532292SN/A TheISA::ZeroReg, 3542292SN/A TheISA::ZeroReg, 3552292SN/A 3562292SN/A tid, 3572292SN/A false); 3582292SN/A 3592292SN/A renameMap[tid].init(TheISA::NumIntRegs, 3602292SN/A params->numPhysIntRegs, 3612325SN/A lreg_idx, //Index for Logical. Regs 3622292SN/A 3632292SN/A TheISA::NumFloatRegs, 3642292SN/A params->numPhysFloatRegs, 3652325SN/A freg_idx, //Index for Float Regs 3662292SN/A 3672292SN/A TheISA::NumMiscRegs, 3682292SN/A 3692292SN/A TheISA::ZeroReg, 3702292SN/A TheISA::ZeroReg, 3712292SN/A 3722292SN/A tid, 3732292SN/A bindRegs); 3743221Sktlim@umich.edu 3753221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3763221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3772292SN/A } 3782292SN/A 3792292SN/A rename.setRenameMap(renameMap); 3802292SN/A commit.setRenameMap(commitRenameMap); 3812292SN/A 3822292SN/A // Give renameMap & rename stage access to the freeList; 3836221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3846221Snate@binkert.org renameMap[tid].setFreeList(&freeList); 3851060SN/A rename.setFreeList(&freeList); 3862292SN/A 3871060SN/A // Setup the ROB for whichever stages need it. 3881060SN/A commit.setROB(&rob); 3892292SN/A 3907823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 3912292SN/A 3922829Sksewell@umich.edu lastActivatedCycle = -1; 3936221Snate@binkert.org#if 0 3943093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3956221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3966221Snate@binkert.org globalSeqNum[tid] = 1; 3976221Snate@binkert.org#endif 3983093Sksewell@umich.edu 3992292SN/A contextSwitch = false; 4005595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 4015595Sgblack@eecs.umich.edu 4025595Sgblack@eecs.umich.edu // Setup any thread state. 4035595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 4045595Sgblack@eecs.umich.edu 4056221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 4068793Sgblack@eecs.umich.edu if (FullSystem) { 4078793Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 4088793Sgblack@eecs.umich.edu assert(this->numThreads == 1); 4098793Sgblack@eecs.umich.edu this->thread[tid] = new Thread(this, 0, NULL); 4108793Sgblack@eecs.umich.edu } else { 4118793Sgblack@eecs.umich.edu if (tid < params->workload.size()) { 4128793Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 4138793Sgblack@eecs.umich.edu tid, this->thread[tid]); 4148793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 4158793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 4168793Sgblack@eecs.umich.edu tid, params->workload[tid]); 4175595Sgblack@eecs.umich.edu 4188793Sgblack@eecs.umich.edu //usedTids[tid] = true; 4198793Sgblack@eecs.umich.edu //threadMap[tid] = tid; 4208793Sgblack@eecs.umich.edu } else { 4218793Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 4228793Sgblack@eecs.umich.edu //when scheduling threads to CPU 4238793Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 4245595Sgblack@eecs.umich.edu 4258793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 4268793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 4278793Sgblack@eecs.umich.edu tid, dummy_proc); 4288793Sgblack@eecs.umich.edu //usedTids[tid] = false; 4298793Sgblack@eecs.umich.edu } 4305595Sgblack@eecs.umich.edu } 4315595Sgblack@eecs.umich.edu 4325595Sgblack@eecs.umich.edu ThreadContext *tc; 4335595Sgblack@eecs.umich.edu 4345595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 4355595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 4365595Sgblack@eecs.umich.edu 4375595Sgblack@eecs.umich.edu tc = o3_tc; 4385595Sgblack@eecs.umich.edu 4395595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 4405595Sgblack@eecs.umich.edu // CheckerThreadContext. 4415595Sgblack@eecs.umich.edu#if USE_CHECKER 4425595Sgblack@eecs.umich.edu if (params->checker) { 4435595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 4445595Sgblack@eecs.umich.edu o3_tc, this->checker); 4455595Sgblack@eecs.umich.edu } 4465595Sgblack@eecs.umich.edu#endif 4475595Sgblack@eecs.umich.edu 4485595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 4495595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 4506221Snate@binkert.org o3_tc->thread = this->thread[tid]; 4515595Sgblack@eecs.umich.edu 4528793Sgblack@eecs.umich.edu if (FullSystem) { 4538793Sgblack@eecs.umich.edu // Setup quiesce event. 4548793Sgblack@eecs.umich.edu this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 4558793Sgblack@eecs.umich.edu } 4565595Sgblack@eecs.umich.edu // Give the thread the TC. 4576221Snate@binkert.org this->thread[tid]->tc = tc; 4585595Sgblack@eecs.umich.edu 4595595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4605595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4615595Sgblack@eecs.umich.edu } 4625595Sgblack@eecs.umich.edu 4638876Sandreas.hansson@arm.com // FullO3CPU always requires an interrupt controller. 4648876Sandreas.hansson@arm.com if (!params->defer_registration && !interrupts) { 4658876Sandreas.hansson@arm.com fatal("FullO3CPU %s has no interrupt controller.\n" 4668876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 4678876Sandreas.hansson@arm.com } 4688876Sandreas.hansson@arm.com 4696221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4706221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4715595Sgblack@eecs.umich.edu 4725595Sgblack@eecs.umich.edu lockAddr = 0; 4735595Sgblack@eecs.umich.edu lockFlag = false; 4741060SN/A} 4751060SN/A 4761060SN/Atemplate <class Impl> 4771755SN/AFullO3CPU<Impl>::~FullO3CPU() 4781060SN/A{ 4791060SN/A} 4801060SN/A 4811060SN/Atemplate <class Impl> 4821060SN/Avoid 4835595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4841062SN/A{ 4852733Sktlim@umich.edu BaseO3CPU::regStats(); 4862292SN/A 4872733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4882292SN/A timesIdled 4892292SN/A .name(name() + ".timesIdled") 4902292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4912292SN/A " unscheduled itself") 4922292SN/A .prereq(timesIdled); 4932292SN/A 4942292SN/A idleCycles 4952292SN/A .name(name() + ".idleCycles") 4962292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4972292SN/A "to idling") 4982292SN/A .prereq(idleCycles); 4992292SN/A 5008627SAli.Saidi@ARM.com quiesceCycles 5018627SAli.Saidi@ARM.com .name(name() + ".quiesceCycles") 5028627SAli.Saidi@ARM.com .desc("Total number of cycles that CPU has spent quiesced or waiting " 5038627SAli.Saidi@ARM.com "for an interrupt") 5048627SAli.Saidi@ARM.com .prereq(quiesceCycles); 5058627SAli.Saidi@ARM.com 5062292SN/A // Number of Instructions simulated 5072292SN/A // -------------------------------- 5082292SN/A // Should probably be in Base CPU but need templated 5092292SN/A // MaxThreads so put in here instead 5102292SN/A committedInsts 5112292SN/A .init(numThreads) 5122292SN/A .name(name() + ".committedInsts") 5132292SN/A .desc("Number of Instructions Simulated"); 5142292SN/A 5158834Satgutier@umich.edu committedOps 5168834Satgutier@umich.edu .init(numThreads) 5178834Satgutier@umich.edu .name(name() + ".committedOps") 5188834Satgutier@umich.edu .desc("Number of Ops (including micro ops) Simulated"); 5198834Satgutier@umich.edu 5202292SN/A totalCommittedInsts 5212292SN/A .name(name() + ".committedInsts_total") 5222292SN/A .desc("Number of Instructions Simulated"); 5232292SN/A 5242292SN/A cpi 5252292SN/A .name(name() + ".cpi") 5262292SN/A .desc("CPI: Cycles Per Instruction") 5272292SN/A .precision(6); 5284392Sktlim@umich.edu cpi = numCycles / committedInsts; 5292292SN/A 5302292SN/A totalCpi 5312292SN/A .name(name() + ".cpi_total") 5322292SN/A .desc("CPI: Total CPI of All Threads") 5332292SN/A .precision(6); 5344392Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 5352292SN/A 5362292SN/A ipc 5372292SN/A .name(name() + ".ipc") 5382292SN/A .desc("IPC: Instructions Per Cycle") 5392292SN/A .precision(6); 5404392Sktlim@umich.edu ipc = committedInsts / numCycles; 5412292SN/A 5422292SN/A totalIpc 5432292SN/A .name(name() + ".ipc_total") 5442292SN/A .desc("IPC: Total IPC of All Threads") 5452292SN/A .precision(6); 5464392Sktlim@umich.edu totalIpc = totalCommittedInsts / numCycles; 5472292SN/A 5485595Sgblack@eecs.umich.edu this->fetch.regStats(); 5495595Sgblack@eecs.umich.edu this->decode.regStats(); 5505595Sgblack@eecs.umich.edu this->rename.regStats(); 5515595Sgblack@eecs.umich.edu this->iew.regStats(); 5525595Sgblack@eecs.umich.edu this->commit.regStats(); 5537897Shestness@cs.utexas.edu this->rob.regStats(); 5547897Shestness@cs.utexas.edu 5557897Shestness@cs.utexas.edu intRegfileReads 5567897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 5577897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 5587897Shestness@cs.utexas.edu .prereq(intRegfileReads); 5597897Shestness@cs.utexas.edu 5607897Shestness@cs.utexas.edu intRegfileWrites 5617897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 5627897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 5637897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 5647897Shestness@cs.utexas.edu 5657897Shestness@cs.utexas.edu fpRegfileReads 5667897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 5677897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 5687897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 5697897Shestness@cs.utexas.edu 5707897Shestness@cs.utexas.edu fpRegfileWrites 5717897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 5727897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 5737897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 5747897Shestness@cs.utexas.edu 5757897Shestness@cs.utexas.edu miscRegfileReads 5767897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5777897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5787897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5797897Shestness@cs.utexas.edu 5807897Shestness@cs.utexas.edu miscRegfileWrites 5817897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5827897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5837897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5841062SN/A} 5851062SN/A 5861062SN/Atemplate <class Impl> 5871062SN/Avoid 5881755SN/AFullO3CPU<Impl>::tick() 5891060SN/A{ 5902733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5911060SN/A 5922292SN/A ++numCycles; 5932292SN/A 5942325SN/A// activity = false; 5952292SN/A 5962292SN/A //Tick each of the stages 5971060SN/A fetch.tick(); 5981060SN/A 5991060SN/A decode.tick(); 6001060SN/A 6011060SN/A rename.tick(); 6021060SN/A 6031060SN/A iew.tick(); 6041060SN/A 6051060SN/A commit.tick(); 6061060SN/A 6078793Sgblack@eecs.umich.edu if (!FullSystem) 6088793Sgblack@eecs.umich.edu doContextSwitch(); 6092292SN/A 6102292SN/A // Now advance the time buffers 6111060SN/A timeBuffer.advance(); 6121060SN/A 6131060SN/A fetchQueue.advance(); 6141060SN/A decodeQueue.advance(); 6151060SN/A renameQueue.advance(); 6161060SN/A iewQueue.advance(); 6171060SN/A 6182325SN/A activityRec.advance(); 6192292SN/A 6202292SN/A if (removeInstsThisCycle) { 6212292SN/A cleanUpRemovedInsts(); 6222292SN/A } 6232292SN/A 6242325SN/A if (!tickEvent.scheduled()) { 6252867Sktlim@umich.edu if (_status == SwitchedOut || 6262905Sktlim@umich.edu getState() == SimObject::Drained) { 6273226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 6282325SN/A // increment stat 6297823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 6303221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 6313226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 6327823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 6332325SN/A timesIdled++; 6342325SN/A } else { 6357823Ssteve.reinhardt@amd.com schedule(tickEvent, nextCycle(curTick() + ticks(1))); 6363226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 6372325SN/A } 6382292SN/A } 6392292SN/A 6408793Sgblack@eecs.umich.edu if (!FullSystem) 6418793Sgblack@eecs.umich.edu updateThreadPriority(); 6421060SN/A} 6431060SN/A 6441060SN/Atemplate <class Impl> 6451060SN/Avoid 6461755SN/AFullO3CPU<Impl>::init() 6471060SN/A{ 6485714Shsul@eecs.umich.edu BaseCPU::init(); 6491060SN/A 6502292SN/A // Set inSyscall so that the CPU doesn't squash when initially 6512292SN/A // setting up registers. 6526221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 6536221Snate@binkert.org thread[tid]->inSyscall = true; 6542292SN/A 6558707Sandreas.hansson@arm.com // this CPU could still be unconnected if we are restoring from a 6568707Sandreas.hansson@arm.com // checkpoint and this CPU is to be switched in, thus we can only 6578707Sandreas.hansson@arm.com // do this here if the instruction port is actually connected, if 6588707Sandreas.hansson@arm.com // not we have to do it as part of takeOverFrom 6598707Sandreas.hansson@arm.com if (icachePort.isConnected()) 6608707Sandreas.hansson@arm.com fetch.setIcache(); 6618707Sandreas.hansson@arm.com 6628863Snilay@cs.wisc.edu if (FullSystem && !params()->defer_registration) { 6638793Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 6648793Sgblack@eecs.umich.edu ThreadContext *src_tc = threadContexts[tid]; 6658793Sgblack@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 6668799Sgblack@eecs.umich.edu // Initialise the ThreadContext's memory proxies 6678799Sgblack@eecs.umich.edu thread[tid]->initMemProxies(thread[tid]->getTC()); 6688793Sgblack@eecs.umich.edu } 6696034Ssteve.reinhardt@amd.com } 6702292SN/A 6712292SN/A // Clear inSyscall. 6726221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6736221Snate@binkert.org thread[tid]->inSyscall = false; 6742292SN/A 6752316SN/A // Initialize stages. 6762292SN/A fetch.initStage(); 6772292SN/A iew.initStage(); 6782292SN/A rename.initStage(); 6792292SN/A commit.initStage(); 6802292SN/A 6812292SN/A commit.setThreads(thread); 6822292SN/A} 6832292SN/A 6842292SN/Atemplate <class Impl> 6852292SN/Avoid 6866221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 6872875Sksewell@umich.edu{ 6886221Snate@binkert.org list<ThreadID>::iterator isActive = 6895314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6902875Sksewell@umich.edu 6913226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6923226Sktlim@umich.edu 6932875Sksewell@umich.edu if (isActive == activeThreads.end()) { 6942875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6952875Sksewell@umich.edu tid); 6962875Sksewell@umich.edu 6972875Sksewell@umich.edu activeThreads.push_back(tid); 6982875Sksewell@umich.edu } 6992875Sksewell@umich.edu} 7002875Sksewell@umich.edu 7012875Sksewell@umich.edutemplate <class Impl> 7022875Sksewell@umich.eduvoid 7036221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 7042875Sksewell@umich.edu{ 7052875Sksewell@umich.edu //Remove From Active List, if Active 7066221Snate@binkert.org list<ThreadID>::iterator thread_it = 7075314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 7082875Sksewell@umich.edu 7093226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 7103226Sktlim@umich.edu 7112875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 7122875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 7132875Sksewell@umich.edu tid); 7142875Sksewell@umich.edu activeThreads.erase(thread_it); 7152875Sksewell@umich.edu } 7162875Sksewell@umich.edu} 7172875Sksewell@umich.edu 7182875Sksewell@umich.edutemplate <class Impl> 7196221Snate@binkert.orgCounter 7208834Satgutier@umich.eduFullO3CPU<Impl>::totalInsts() const 7216221Snate@binkert.org{ 7226221Snate@binkert.org Counter total(0); 7236221Snate@binkert.org 7246221Snate@binkert.org ThreadID size = thread.size(); 7256221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 7266221Snate@binkert.org total += thread[i]->numInst; 7276221Snate@binkert.org 7286221Snate@binkert.org return total; 7296221Snate@binkert.org} 7306221Snate@binkert.org 7316221Snate@binkert.orgtemplate <class Impl> 7328834Satgutier@umich.eduCounter 7338834Satgutier@umich.eduFullO3CPU<Impl>::totalOps() const 7348834Satgutier@umich.edu{ 7358834Satgutier@umich.edu Counter total(0); 7368834Satgutier@umich.edu 7378834Satgutier@umich.edu ThreadID size = thread.size(); 7388834Satgutier@umich.edu for (ThreadID i = 0; i < size; i++) 7398834Satgutier@umich.edu total += thread[i]->numOp; 7408834Satgutier@umich.edu 7418834Satgutier@umich.edu return total; 7428834Satgutier@umich.edu} 7438834Satgutier@umich.edu 7448834Satgutier@umich.edutemplate <class Impl> 7452875Sksewell@umich.eduvoid 7466221Snate@binkert.orgFullO3CPU<Impl>::activateContext(ThreadID tid, int delay) 7472875Sksewell@umich.edu{ 7482875Sksewell@umich.edu // Needs to set each stage to running as well. 7492875Sksewell@umich.edu if (delay){ 7502875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 7517823Ssteve.reinhardt@amd.com "on cycle %d\n", tid, curTick() + ticks(delay)); 7522875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 7532875Sksewell@umich.edu } else { 7542875Sksewell@umich.edu activateThread(tid); 7552875Sksewell@umich.edu } 7562875Sksewell@umich.edu 7577823Ssteve.reinhardt@amd.com if (lastActivatedCycle < curTick()) { 7582875Sksewell@umich.edu scheduleTickEvent(delay); 7592875Sksewell@umich.edu 7602875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 7612875Sksewell@umich.edu // deschedule itself. 7622875Sksewell@umich.edu activityRec.activity(); 7632875Sksewell@umich.edu fetch.wakeFromQuiesce(); 7642875Sksewell@umich.edu 7658627SAli.Saidi@ARM.com quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle); 7668627SAli.Saidi@ARM.com 7677823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 7682875Sksewell@umich.edu 7692875Sksewell@umich.edu _status = Running; 7702875Sksewell@umich.edu } 7712875Sksewell@umich.edu} 7722875Sksewell@umich.edu 7732875Sksewell@umich.edutemplate <class Impl> 7743221Sktlim@umich.edubool 7758737Skoansin.tan@gmail.comFullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove, 7768737Skoansin.tan@gmail.com int delay) 7772875Sksewell@umich.edu{ 7782875Sksewell@umich.edu // Schedule removal of thread data from CPU 7792875Sksewell@umich.edu if (delay){ 7802875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 7817823Ssteve.reinhardt@amd.com "on cycle %d\n", tid, curTick() + ticks(delay)); 7823221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 7833221Sktlim@umich.edu return false; 7842875Sksewell@umich.edu } else { 7852875Sksewell@umich.edu deactivateThread(tid); 7863221Sktlim@umich.edu if (remove) 7873221Sktlim@umich.edu removeThread(tid); 7883221Sktlim@umich.edu return true; 7892875Sksewell@umich.edu } 7902875Sksewell@umich.edu} 7912875Sksewell@umich.edu 7922875Sksewell@umich.edutemplate <class Impl> 7932875Sksewell@umich.eduvoid 7946221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 7952875Sksewell@umich.edu{ 7962875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 7978737Skoansin.tan@gmail.com bool deallocated = scheduleDeallocateContext(tid, false, 1); 7983221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 7995570Snate@binkert.org if ((activeThreads.size() == 1 && !deallocated) || 8003859Sbinkertn@umich.edu activeThreads.size() == 0) 8012910Sksewell@umich.edu unscheduleTickEvent(); 8028627SAli.Saidi@ARM.com 8038627SAli.Saidi@ARM.com DPRINTF(Quiesce, "Suspending Context\n"); 8048627SAli.Saidi@ARM.com lastRunningCycle = curTick(); 8052875Sksewell@umich.edu _status = Idle; 8062875Sksewell@umich.edu} 8072875Sksewell@umich.edu 8082875Sksewell@umich.edutemplate <class Impl> 8092875Sksewell@umich.eduvoid 8106221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 8112875Sksewell@umich.edu{ 8122910Sksewell@umich.edu //For now, this is the same as deallocate 8132910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 8148737Skoansin.tan@gmail.com scheduleDeallocateContext(tid, true, 1); 8152875Sksewell@umich.edu} 8162875Sksewell@umich.edu 8172875Sksewell@umich.edutemplate <class Impl> 8182875Sksewell@umich.eduvoid 8196221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 8202292SN/A{ 8212847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 8222292SN/A // Will change now that the PC and thread state is internal to the CPU 8232683Sktlim@umich.edu // and not in the ThreadContext. 8248793Sgblack@eecs.umich.edu ThreadContext *src_tc; 8258793Sgblack@eecs.umich.edu if (FullSystem) 8268793Sgblack@eecs.umich.edu src_tc = system->threadContexts[tid]; 8278793Sgblack@eecs.umich.edu else 8288793Sgblack@eecs.umich.edu src_tc = tcBase(tid); 8292292SN/A 8302292SN/A //Bind Int Regs to Rename Map 8312292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 8322292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 8332292SN/A 8342292SN/A renameMap[tid].setEntry(ireg,phys_reg); 8352292SN/A scoreboard.setReg(phys_reg); 8362292SN/A } 8372292SN/A 8382292SN/A //Bind Float Regs to Rename Map 8392292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 8402292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 8412292SN/A 8422292SN/A renameMap[tid].setEntry(freg,phys_reg); 8432292SN/A scoreboard.setReg(phys_reg); 8442292SN/A } 8452292SN/A 8462292SN/A //Copy Thread Data Into RegFile 8472847Sksewell@umich.edu //this->copyFromTC(tid); 8482292SN/A 8492847Sksewell@umich.edu //Set PC/NPC/NNPC 8507720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 8512292SN/A 8522680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 8532292SN/A 8542292SN/A activateContext(tid,1); 8552292SN/A 8562292SN/A //Reset ROB/IQ/LSQ Entries 8572292SN/A commit.rob->resetEntries(); 8582292SN/A iew.resetEntries(); 8592292SN/A} 8602292SN/A 8612292SN/Atemplate <class Impl> 8622292SN/Avoid 8636221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 8642292SN/A{ 8652877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 8662847Sksewell@umich.edu 8672847Sksewell@umich.edu // Copy Thread Data From RegFile 8682847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 8695364Sksewell@umich.edu // this->copyToTC(tid); 8705364Sksewell@umich.edu 8715364Sksewell@umich.edu 8725364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 8735364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 8745364Sksewell@umich.edu // in SMT workloads. 8752847Sksewell@umich.edu 8762847Sksewell@umich.edu // Unbind Int Regs from Rename Map 8772292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 8782292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 8792292SN/A 8802292SN/A scoreboard.unsetReg(phys_reg); 8812292SN/A freeList.addReg(phys_reg); 8822292SN/A } 8832292SN/A 8842847Sksewell@umich.edu // Unbind Float Regs from Rename Map 8855362Sksewell@umich.edu for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 8862292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 8872292SN/A 8882292SN/A scoreboard.unsetReg(phys_reg); 8892292SN/A freeList.addReg(phys_reg); 8902292SN/A } 8912292SN/A 8922847Sksewell@umich.edu // Squash Throughout Pipeline 8938138SAli.Saidi@ARM.com DynInstPtr inst = commit.rob->readHeadInst(tid); 8948138SAli.Saidi@ARM.com InstSeqNum squash_seq_num = inst->seqNum; 8958138SAli.Saidi@ARM.com fetch.squash(0, squash_seq_num, inst, tid); 8962292SN/A decode.squash(tid); 8972935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 8982875Sksewell@umich.edu iew.squash(tid); 8995363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 9002935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 9012292SN/A 9025362Sksewell@umich.edu 9035362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 9042292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 9052292SN/A 9062847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 9073229Sktlim@umich.edu 9083229Sktlim@umich.edu // Commented out for now. This should be possible to do by 9093229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 9103229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 9113229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 9123229Sktlim@umich.edu/* 9132292SN/A if (activeThreads.size() >= 1) { 9142292SN/A commit.rob->resetEntries(); 9152292SN/A iew.resetEntries(); 9162292SN/A } 9173229Sktlim@umich.edu*/ 9182292SN/A} 9192292SN/A 9202292SN/A 9212292SN/Atemplate <class Impl> 9222292SN/Avoid 9236221Snate@binkert.orgFullO3CPU<Impl>::activateWhenReady(ThreadID tid) 9242292SN/A{ 9252733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 9262292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 9272292SN/A tid); 9282292SN/A 9292292SN/A bool ready = true; 9302292SN/A 9312292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 9322733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9332292SN/A "Phys. Int. Regs.\n", 9342292SN/A tid); 9352292SN/A ready = false; 9362292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 9372733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9382292SN/A "Phys. Float. Regs.\n", 9392292SN/A tid); 9402292SN/A ready = false; 9412292SN/A } else if (commit.rob->numFreeEntries() >= 9422292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 9432733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9442292SN/A "ROB entries.\n", 9452292SN/A tid); 9462292SN/A ready = false; 9472292SN/A } else if (iew.instQueue.numFreeEntries() >= 9482292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 9492733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9502292SN/A "IQ entries.\n", 9512292SN/A tid); 9522292SN/A ready = false; 9532292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 9542292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 9552733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9562292SN/A "LSQ entries.\n", 9572292SN/A tid); 9582292SN/A ready = false; 9592292SN/A } 9602292SN/A 9612292SN/A if (ready) { 9622292SN/A insertThread(tid); 9632292SN/A 9642292SN/A contextSwitch = false; 9652292SN/A 9662292SN/A cpuWaitList.remove(tid); 9672292SN/A } else { 9682292SN/A suspendContext(tid); 9692292SN/A 9702292SN/A //blocks fetch 9712292SN/A contextSwitch = true; 9722292SN/A 9732875Sksewell@umich.edu //@todo: dont always add to waitlist 9742292SN/A //do waitlist 9752292SN/A cpuWaitList.push_back(tid); 9761060SN/A } 9771060SN/A} 9781060SN/A 9794192Sktlim@umich.edutemplate <class Impl> 9805595Sgblack@eecs.umich.eduFault 9816221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 9825702Ssaidi@eecs.umich.edu{ 9835702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9845702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 9855702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 9865702Ssaidi@eecs.umich.edu 9875702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 9885702Ssaidi@eecs.umich.edu 9895702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 9905702Ssaidi@eecs.umich.edu#endif 9915702Ssaidi@eecs.umich.edu return NoFault; 9925702Ssaidi@eecs.umich.edu} 9935702Ssaidi@eecs.umich.edu 9945702Ssaidi@eecs.umich.edutemplate <class Impl> 9955702Ssaidi@eecs.umich.edubool 9966221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 9975702Ssaidi@eecs.umich.edu{ 9985702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9995702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 10005702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 10015702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 10025702Ssaidi@eecs.umich.edu 10035702Ssaidi@eecs.umich.edu switch (palFunc) { 10045702Ssaidi@eecs.umich.edu case PAL::halt: 10055702Ssaidi@eecs.umich.edu halt(); 10065702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 10075702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 10085702Ssaidi@eecs.umich.edu break; 10095702Ssaidi@eecs.umich.edu 10105702Ssaidi@eecs.umich.edu case PAL::bpt: 10115702Ssaidi@eecs.umich.edu case PAL::bugchk: 10125702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 10135702Ssaidi@eecs.umich.edu return false; 10145702Ssaidi@eecs.umich.edu break; 10155702Ssaidi@eecs.umich.edu } 10165702Ssaidi@eecs.umich.edu#endif 10175702Ssaidi@eecs.umich.edu return true; 10185702Ssaidi@eecs.umich.edu} 10195702Ssaidi@eecs.umich.edu 10205702Ssaidi@eecs.umich.edutemplate <class Impl> 10215702Ssaidi@eecs.umich.eduFault 10225595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 10235595Sgblack@eecs.umich.edu{ 10245595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 10255647Sgblack@eecs.umich.edu return this->interrupts->getInterrupt(this->threadContexts[0]); 10265595Sgblack@eecs.umich.edu} 10275595Sgblack@eecs.umich.edu 10285595Sgblack@eecs.umich.edutemplate <class Impl> 10295595Sgblack@eecs.umich.eduvoid 10305595Sgblack@eecs.umich.eduFullO3CPU<Impl>::processInterrupts(Fault interrupt) 10315595Sgblack@eecs.umich.edu{ 10325595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 10335595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 10345595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 10355595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 10365595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 10375595Sgblack@eecs.umich.edu 10385595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 10395647Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 10405595Sgblack@eecs.umich.edu 10415595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 10427684Sgblack@eecs.umich.edu this->trap(interrupt, 0, NULL); 10435595Sgblack@eecs.umich.edu} 10445595Sgblack@eecs.umich.edu 10451060SN/Atemplate <class Impl> 10462852Sktlim@umich.eduvoid 10477684Sgblack@eecs.umich.eduFullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst) 10485595Sgblack@eecs.umich.edu{ 10495595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 10507684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 10515595Sgblack@eecs.umich.edu} 10525595Sgblack@eecs.umich.edu 10535595Sgblack@eecs.umich.edutemplate <class Impl> 10545595Sgblack@eecs.umich.eduvoid 10556221Snate@binkert.orgFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 10565595Sgblack@eecs.umich.edu{ 10575595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 10585595Sgblack@eecs.umich.edu 10595595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 10605595Sgblack@eecs.umich.edu 10615595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 10625595Sgblack@eecs.umich.edu // instruction. 10635595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 10645595Sgblack@eecs.umich.edu 10655595Sgblack@eecs.umich.edu // Execute the actual syscall. 10665595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 10675595Sgblack@eecs.umich.edu 10685595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 10695595Sgblack@eecs.umich.edu // incrementing it. 10705595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 10715595Sgblack@eecs.umich.edu} 10725595Sgblack@eecs.umich.edu 10735595Sgblack@eecs.umich.edutemplate <class Impl> 10745595Sgblack@eecs.umich.eduvoid 10752864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 10762864Sktlim@umich.edu{ 10772918Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 10782918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 10792864Sktlim@umich.edu BaseCPU::serialize(os); 10802864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 10812864Sktlim@umich.edu tickEvent.serialize(os); 10822864Sktlim@umich.edu 10832864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10842864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 10852864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 10862864Sktlim@umich.edu static SimpleThread temp; 10872864Sktlim@umich.edu 10886221Snate@binkert.org ThreadID size = thread.size(); 10896221Snate@binkert.org for (ThreadID i = 0; i < size; i++) { 10902864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 10912864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10922864Sktlim@umich.edu temp.serialize(os); 10932864Sktlim@umich.edu } 10942864Sktlim@umich.edu} 10952864Sktlim@umich.edu 10962864Sktlim@umich.edutemplate <class Impl> 10972864Sktlim@umich.eduvoid 10982864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 10992864Sktlim@umich.edu{ 11002918Sktlim@umich.edu SimObject::State so_state; 11012918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 11022864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 11032864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 11042864Sktlim@umich.edu 11052864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 11062864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 11072864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 11082864Sktlim@umich.edu static SimpleThread temp; 11092864Sktlim@umich.edu 11106221Snate@binkert.org ThreadID size = thread.size(); 11116221Snate@binkert.org for (ThreadID i = 0; i < size; i++) { 11122864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 11132864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 11142864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 11152864Sktlim@umich.edu } 11162864Sktlim@umich.edu} 11172864Sktlim@umich.edu 11182864Sktlim@umich.edutemplate <class Impl> 11192905Sktlim@umich.eduunsigned int 11202843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 11211060SN/A{ 11223125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 11233512Sktlim@umich.edu 11243512Sktlim@umich.edu // If the CPU isn't doing anything, then return immediately. 11253512Sktlim@umich.edu if (_status == Idle || _status == SwitchedOut) { 11263512Sktlim@umich.edu return 0; 11273512Sktlim@umich.edu } 11283512Sktlim@umich.edu 11292843Sktlim@umich.edu drainCount = 0; 11302843Sktlim@umich.edu fetch.drain(); 11312843Sktlim@umich.edu decode.drain(); 11322843Sktlim@umich.edu rename.drain(); 11332843Sktlim@umich.edu iew.drain(); 11342843Sktlim@umich.edu commit.drain(); 11352325SN/A 11362325SN/A // Wake the CPU and record activity so everything can drain out if 11372863Sktlim@umich.edu // the CPU was not able to immediately drain. 11382905Sktlim@umich.edu if (getState() != SimObject::Drained) { 11392864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 11402864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 11412864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 11422864Sktlim@umich.edu // process on the drain event. 11432864Sktlim@umich.edu drainEvent = drain_event; 11442843Sktlim@umich.edu 11452863Sktlim@umich.edu wakeCPU(); 11462863Sktlim@umich.edu activityRec.activity(); 11472852Sktlim@umich.edu 11482905Sktlim@umich.edu return 1; 11492863Sktlim@umich.edu } else { 11502905Sktlim@umich.edu return 0; 11512863Sktlim@umich.edu } 11522316SN/A} 11532310SN/A 11542316SN/Atemplate <class Impl> 11552316SN/Avoid 11562843Sktlim@umich.eduFullO3CPU<Impl>::resume() 11572316SN/A{ 11582843Sktlim@umich.edu fetch.resume(); 11592843Sktlim@umich.edu decode.resume(); 11602843Sktlim@umich.edu rename.resume(); 11612843Sktlim@umich.edu iew.resume(); 11622843Sktlim@umich.edu commit.resume(); 11632316SN/A 11642905Sktlim@umich.edu changeState(SimObject::Running); 11652905Sktlim@umich.edu 11662864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 11672864Sktlim@umich.edu return; 11682864Sktlim@umich.edu 11694762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 11703319Shsul@eecs.umich.edu 11712843Sktlim@umich.edu if (!tickEvent.scheduled()) 11725606Snate@binkert.org schedule(tickEvent, nextCycle()); 11732843Sktlim@umich.edu _status = Running; 11742843Sktlim@umich.edu} 11752316SN/A 11762843Sktlim@umich.edutemplate <class Impl> 11772843Sktlim@umich.eduvoid 11782843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 11792843Sktlim@umich.edu{ 11802843Sktlim@umich.edu if (++drainCount == NumStages) { 11812316SN/A if (tickEvent.scheduled()) 11822316SN/A tickEvent.squash(); 11832863Sktlim@umich.edu 11842905Sktlim@umich.edu changeState(SimObject::Drained); 11852863Sktlim@umich.edu 11863126Sktlim@umich.edu BaseCPU::switchOut(); 11873126Sktlim@umich.edu 11882863Sktlim@umich.edu if (drainEvent) { 11892863Sktlim@umich.edu drainEvent->process(); 11902863Sktlim@umich.edu drainEvent = NULL; 11912863Sktlim@umich.edu } 11922310SN/A } 11932843Sktlim@umich.edu assert(drainCount <= 5); 11942843Sktlim@umich.edu} 11952843Sktlim@umich.edu 11962843Sktlim@umich.edutemplate <class Impl> 11972843Sktlim@umich.eduvoid 11982843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 11992843Sktlim@umich.edu{ 12002843Sktlim@umich.edu fetch.switchOut(); 12012843Sktlim@umich.edu rename.switchOut(); 12022325SN/A iew.switchOut(); 12032843Sktlim@umich.edu commit.switchOut(); 12042843Sktlim@umich.edu instList.clear(); 12052843Sktlim@umich.edu while (!removeList.empty()) { 12062843Sktlim@umich.edu removeList.pop(); 12072843Sktlim@umich.edu } 12082843Sktlim@umich.edu 12092843Sktlim@umich.edu _status = SwitchedOut; 12102843Sktlim@umich.edu#if USE_CHECKER 12112843Sktlim@umich.edu if (checker) 12122843Sktlim@umich.edu checker->switchOut(); 12132843Sktlim@umich.edu#endif 12143126Sktlim@umich.edu if (tickEvent.scheduled()) 12153126Sktlim@umich.edu tickEvent.squash(); 12161060SN/A} 12171060SN/A 12181060SN/Atemplate <class Impl> 12191060SN/Avoid 12201755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 12211060SN/A{ 12222325SN/A // Flush out any old data from the time buffers. 12232873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 12242307SN/A timeBuffer.advance(); 12252307SN/A fetchQueue.advance(); 12262307SN/A decodeQueue.advance(); 12272307SN/A renameQueue.advance(); 12282307SN/A iewQueue.advance(); 12292307SN/A } 12302307SN/A 12312325SN/A activityRec.reset(); 12322307SN/A 12338737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 12341060SN/A 12352307SN/A fetch.takeOverFrom(); 12362307SN/A decode.takeOverFrom(); 12372307SN/A rename.takeOverFrom(); 12382307SN/A iew.takeOverFrom(); 12392307SN/A commit.takeOverFrom(); 12402307SN/A 12417507Stjones1@inf.ed.ac.uk assert(!tickEvent.scheduled() || tickEvent.squashed()); 12421060SN/A 12432325SN/A // @todo: Figure out how to properly select the tid to put onto 12442325SN/A // the active threads list. 12456221Snate@binkert.org ThreadID tid = 0; 12462307SN/A 12476221Snate@binkert.org list<ThreadID>::iterator isActive = 12485314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 12492307SN/A 12502307SN/A if (isActive == activeThreads.end()) { 12512325SN/A //May Need to Re-code this if the delay variable is the delay 12522325SN/A //needed for thread to activate 12532733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 12542307SN/A tid); 12552307SN/A 12562307SN/A activeThreads.push_back(tid); 12572307SN/A } 12582307SN/A 12592325SN/A // Set all statuses to active, schedule the CPU's tick event. 12602307SN/A // @todo: Fix up statuses so this is handled properly 12616221Snate@binkert.org ThreadID size = threadContexts.size(); 12626221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 12632680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 12642680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 12651681SN/A _status = Running; 12667507Stjones1@inf.ed.ac.uk reschedule(tickEvent, nextCycle(), true); 12671681SN/A } 12681060SN/A } 12692307SN/A if (!tickEvent.scheduled()) 12705606Snate@binkert.org schedule(tickEvent, nextCycle()); 12718627SAli.Saidi@ARM.com 12728627SAli.Saidi@ARM.com lastRunningCycle = curTick(); 12731060SN/A} 12741060SN/A 12751060SN/Atemplate <class Impl> 12765595Sgblack@eecs.umich.eduTheISA::MiscReg 12776221Snate@binkert.orgFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) 12785595Sgblack@eecs.umich.edu{ 12796313Sgblack@eecs.umich.edu return this->isa[tid].readMiscRegNoEffect(misc_reg); 12805595Sgblack@eecs.umich.edu} 12815595Sgblack@eecs.umich.edu 12825595Sgblack@eecs.umich.edutemplate <class Impl> 12835595Sgblack@eecs.umich.eduTheISA::MiscReg 12846221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 12855595Sgblack@eecs.umich.edu{ 12867897Shestness@cs.utexas.edu miscRegfileReads++; 12876313Sgblack@eecs.umich.edu return this->isa[tid].readMiscReg(misc_reg, tcBase(tid)); 12885595Sgblack@eecs.umich.edu} 12895595Sgblack@eecs.umich.edu 12905595Sgblack@eecs.umich.edutemplate <class Impl> 12915595Sgblack@eecs.umich.eduvoid 12925595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 12936221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12945595Sgblack@eecs.umich.edu{ 12956313Sgblack@eecs.umich.edu this->isa[tid].setMiscRegNoEffect(misc_reg, val); 12965595Sgblack@eecs.umich.edu} 12975595Sgblack@eecs.umich.edu 12985595Sgblack@eecs.umich.edutemplate <class Impl> 12995595Sgblack@eecs.umich.eduvoid 13005595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 13016221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 13025595Sgblack@eecs.umich.edu{ 13037897Shestness@cs.utexas.edu miscRegfileWrites++; 13046313Sgblack@eecs.umich.edu this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid)); 13055595Sgblack@eecs.umich.edu} 13065595Sgblack@eecs.umich.edu 13075595Sgblack@eecs.umich.edutemplate <class Impl> 13081060SN/Auint64_t 13091755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 13101060SN/A{ 13117897Shestness@cs.utexas.edu intRegfileReads++; 13121060SN/A return regFile.readIntReg(reg_idx); 13131060SN/A} 13141060SN/A 13151060SN/Atemplate <class Impl> 13162455SN/AFloatReg 13172455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 13181060SN/A{ 13197897Shestness@cs.utexas.edu fpRegfileReads++; 13202455SN/A return regFile.readFloatReg(reg_idx); 13211060SN/A} 13221060SN/A 13231060SN/Atemplate <class Impl> 13242455SN/AFloatRegBits 13252455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 13262455SN/A{ 13277897Shestness@cs.utexas.edu fpRegfileReads++; 13282455SN/A return regFile.readFloatRegBits(reg_idx); 13291060SN/A} 13301060SN/A 13311060SN/Atemplate <class Impl> 13321060SN/Avoid 13331755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 13341060SN/A{ 13357897Shestness@cs.utexas.edu intRegfileWrites++; 13361060SN/A regFile.setIntReg(reg_idx, val); 13371060SN/A} 13381060SN/A 13391060SN/Atemplate <class Impl> 13401060SN/Avoid 13412455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 13421060SN/A{ 13437897Shestness@cs.utexas.edu fpRegfileWrites++; 13442455SN/A regFile.setFloatReg(reg_idx, val); 13451060SN/A} 13461060SN/A 13471060SN/Atemplate <class Impl> 13481060SN/Avoid 13492455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 13502455SN/A{ 13517897Shestness@cs.utexas.edu fpRegfileWrites++; 13522455SN/A regFile.setFloatRegBits(reg_idx, val); 13531060SN/A} 13541060SN/A 13551060SN/Atemplate <class Impl> 13561060SN/Auint64_t 13576221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 13581060SN/A{ 13597897Shestness@cs.utexas.edu intRegfileReads++; 13602292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13612292SN/A 13622292SN/A return regFile.readIntReg(phys_reg); 13632292SN/A} 13642292SN/A 13652292SN/Atemplate <class Impl> 13662292SN/Afloat 13676314Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 13682292SN/A{ 13697897Shestness@cs.utexas.edu fpRegfileReads++; 13706032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13712307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13722292SN/A 13732669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 13742292SN/A} 13752292SN/A 13762292SN/Atemplate <class Impl> 13772292SN/Auint64_t 13786221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 13792292SN/A{ 13807897Shestness@cs.utexas.edu fpRegfileReads++; 13816032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13822307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13832292SN/A 13842669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 13851060SN/A} 13861060SN/A 13871060SN/Atemplate <class Impl> 13881060SN/Avoid 13896221Snate@binkert.orgFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 13901060SN/A{ 13917897Shestness@cs.utexas.edu intRegfileWrites++; 13922292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13932292SN/A 13942292SN/A regFile.setIntReg(phys_reg, val); 13951060SN/A} 13961060SN/A 13971060SN/Atemplate <class Impl> 13981060SN/Avoid 13996314Sgblack@eecs.umich.eduFullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 14001060SN/A{ 14017897Shestness@cs.utexas.edu fpRegfileWrites++; 14026032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 14032918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 14042292SN/A 14052669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 14061060SN/A} 14071060SN/A 14081060SN/Atemplate <class Impl> 14091060SN/Avoid 14106221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 14111060SN/A{ 14127897Shestness@cs.utexas.edu fpRegfileWrites++; 14136032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 14142918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 14151060SN/A 14162669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 14172292SN/A} 14182292SN/A 14192292SN/Atemplate <class Impl> 14207720Sgblack@eecs.umich.eduTheISA::PCState 14217720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 14222292SN/A{ 14237720Sgblack@eecs.umich.edu return commit.pcState(tid); 14241060SN/A} 14251060SN/A 14261060SN/Atemplate <class Impl> 14271060SN/Avoid 14287720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 14291060SN/A{ 14307720Sgblack@eecs.umich.edu commit.pcState(val, tid); 14312292SN/A} 14321060SN/A 14332292SN/Atemplate <class Impl> 14347720Sgblack@eecs.umich.eduAddr 14357720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 14364636Sgblack@eecs.umich.edu{ 14377720Sgblack@eecs.umich.edu return commit.instAddr(tid); 14384636Sgblack@eecs.umich.edu} 14394636Sgblack@eecs.umich.edu 14404636Sgblack@eecs.umich.edutemplate <class Impl> 14417720Sgblack@eecs.umich.eduAddr 14427720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 14434636Sgblack@eecs.umich.edu{ 14447720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 14454636Sgblack@eecs.umich.edu} 14464636Sgblack@eecs.umich.edu 14474636Sgblack@eecs.umich.edutemplate <class Impl> 14487720Sgblack@eecs.umich.eduMicroPC 14497720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 14502292SN/A{ 14517720Sgblack@eecs.umich.edu return commit.microPC(tid); 14524636Sgblack@eecs.umich.edu} 14534636Sgblack@eecs.umich.edu 14544636Sgblack@eecs.umich.edutemplate <class Impl> 14555595Sgblack@eecs.umich.eduvoid 14566221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 14575595Sgblack@eecs.umich.edu{ 14585595Sgblack@eecs.umich.edu this->thread[tid]->inSyscall = true; 14595595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 14605595Sgblack@eecs.umich.edu} 14615595Sgblack@eecs.umich.edu 14625595Sgblack@eecs.umich.edutemplate <class Impl> 14632292SN/Atypename FullO3CPU<Impl>::ListIt 14642292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 14652292SN/A{ 14662292SN/A instList.push_back(inst); 14671060SN/A 14682292SN/A return --(instList.end()); 14692292SN/A} 14701060SN/A 14712292SN/Atemplate <class Impl> 14722292SN/Avoid 14738834Satgutier@umich.eduFullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst) 14742292SN/A{ 14752292SN/A // Keep an instruction count. 14768834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) { 14778834Satgutier@umich.edu thread[tid]->numInst++; 14788834Satgutier@umich.edu thread[tid]->numInsts++; 14798834Satgutier@umich.edu committedInsts[tid]++; 14808834Satgutier@umich.edu totalCommittedInsts++; 14818834Satgutier@umich.edu } 14828834Satgutier@umich.edu thread[tid]->numOp++; 14838834Satgutier@umich.edu thread[tid]->numOps++; 14848834Satgutier@umich.edu committedOps[tid]++; 14858834Satgutier@umich.edu 14867897Shestness@cs.utexas.edu system->totalNumInsts++; 14872292SN/A // Check for instruction-count-based events. 14882292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 14897897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 14902292SN/A} 14912292SN/A 14922292SN/Atemplate <class Impl> 14932292SN/Avoid 14941755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 14951060SN/A{ 14967720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 14972292SN/A "[sn:%lli]\n", 14987720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 14991060SN/A 15002292SN/A removeInstsThisCycle = true; 15011060SN/A 15021060SN/A // Remove the front instruction. 15032292SN/A removeList.push(inst->getInstListIt()); 15041060SN/A} 15051060SN/A 15061060SN/Atemplate <class Impl> 15071060SN/Avoid 15086221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 15091060SN/A{ 15102733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 15112292SN/A " list.\n", tid); 15121060SN/A 15132292SN/A ListIt end_it; 15141060SN/A 15152292SN/A bool rob_empty = false; 15162292SN/A 15172292SN/A if (instList.empty()) { 15182292SN/A return; 15192292SN/A } else if (rob.isEmpty(/*tid*/)) { 15202733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 15212292SN/A end_it = instList.begin(); 15222292SN/A rob_empty = true; 15232292SN/A } else { 15242292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 15252733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 15262292SN/A } 15272292SN/A 15282292SN/A removeInstsThisCycle = true; 15292292SN/A 15302292SN/A ListIt inst_it = instList.end(); 15312292SN/A 15322292SN/A inst_it--; 15332292SN/A 15342292SN/A // Walk through the instruction list, removing any instructions 15352292SN/A // that were inserted after the given instruction iterator, end_it. 15362292SN/A while (inst_it != end_it) { 15372292SN/A assert(!instList.empty()); 15382292SN/A 15392292SN/A squashInstIt(inst_it, tid); 15402292SN/A 15412292SN/A inst_it--; 15422292SN/A } 15432292SN/A 15442292SN/A // If the ROB was empty, then we actually need to remove the first 15452292SN/A // instruction as well. 15462292SN/A if (rob_empty) { 15472292SN/A squashInstIt(inst_it, tid); 15482292SN/A } 15491060SN/A} 15501060SN/A 15511060SN/Atemplate <class Impl> 15521060SN/Avoid 15536221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 15541062SN/A{ 15552292SN/A assert(!instList.empty()); 15562292SN/A 15572292SN/A removeInstsThisCycle = true; 15582292SN/A 15592292SN/A ListIt inst_iter = instList.end(); 15602292SN/A 15612292SN/A inst_iter--; 15622292SN/A 15632733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 15642292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 15652292SN/A tid, seq_num, (*inst_iter)->seqNum); 15661062SN/A 15672292SN/A while ((*inst_iter)->seqNum > seq_num) { 15681062SN/A 15692292SN/A bool break_loop = (inst_iter == instList.begin()); 15701062SN/A 15712292SN/A squashInstIt(inst_iter, tid); 15721062SN/A 15732292SN/A inst_iter--; 15741062SN/A 15752292SN/A if (break_loop) 15762292SN/A break; 15772292SN/A } 15782292SN/A} 15792292SN/A 15802292SN/Atemplate <class Impl> 15812292SN/Ainline void 15826221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 15832292SN/A{ 15842292SN/A if ((*instIt)->threadNumber == tid) { 15852733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 15867720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 15872292SN/A (*instIt)->threadNumber, 15882292SN/A (*instIt)->seqNum, 15897720Sgblack@eecs.umich.edu (*instIt)->pcState()); 15901062SN/A 15911062SN/A // Mark it as squashed. 15922292SN/A (*instIt)->setSquashed(); 15932292SN/A 15942325SN/A // @todo: Formulate a consistent method for deleting 15952325SN/A // instructions from the instruction list 15962292SN/A // Remove the instruction from the list. 15972292SN/A removeList.push(instIt); 15982292SN/A } 15992292SN/A} 16002292SN/A 16012292SN/Atemplate <class Impl> 16022292SN/Avoid 16032292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 16042292SN/A{ 16052292SN/A while (!removeList.empty()) { 16062733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 16077720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 16082292SN/A (*removeList.front())->threadNumber, 16092292SN/A (*removeList.front())->seqNum, 16107720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 16112292SN/A 16122292SN/A instList.erase(removeList.front()); 16132292SN/A 16142292SN/A removeList.pop(); 16151062SN/A } 16161062SN/A 16172292SN/A removeInstsThisCycle = false; 16181062SN/A} 16192325SN/A/* 16201062SN/Atemplate <class Impl> 16211062SN/Avoid 16221755SN/AFullO3CPU<Impl>::removeAllInsts() 16231060SN/A{ 16241060SN/A instList.clear(); 16251060SN/A} 16262325SN/A*/ 16271060SN/Atemplate <class Impl> 16281060SN/Avoid 16291755SN/AFullO3CPU<Impl>::dumpInsts() 16301060SN/A{ 16311060SN/A int num = 0; 16321060SN/A 16332292SN/A ListIt inst_list_it = instList.begin(); 16342292SN/A 16352292SN/A cprintf("Dumping Instruction List\n"); 16362292SN/A 16372292SN/A while (inst_list_it != instList.end()) { 16382292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 16392292SN/A "Squashed:%i\n\n", 16407720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 16412292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 16422292SN/A (*inst_list_it)->isSquashed()); 16431060SN/A inst_list_it++; 16441060SN/A ++num; 16451060SN/A } 16461060SN/A} 16472325SN/A/* 16481060SN/Atemplate <class Impl> 16491060SN/Avoid 16501755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 16511060SN/A{ 16521060SN/A iew.wakeDependents(inst); 16531060SN/A} 16542325SN/A*/ 16552292SN/Atemplate <class Impl> 16562292SN/Avoid 16572292SN/AFullO3CPU<Impl>::wakeCPU() 16582292SN/A{ 16592325SN/A if (activityRec.active() || tickEvent.scheduled()) { 16602325SN/A DPRINTF(Activity, "CPU already running.\n"); 16612292SN/A return; 16622292SN/A } 16632292SN/A 16642325SN/A DPRINTF(Activity, "Waking up CPU\n"); 16652325SN/A 16667823Ssteve.reinhardt@amd.com idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle); 16677823Ssteve.reinhardt@amd.com numCycles += tickToCycles((curTick() - 1) - lastRunningCycle); 16682292SN/A 16695606Snate@binkert.org schedule(tickEvent, nextCycle()); 16702292SN/A} 16712292SN/A 16725807Snate@binkert.orgtemplate <class Impl> 16735807Snate@binkert.orgvoid 16745807Snate@binkert.orgFullO3CPU<Impl>::wakeup() 16755807Snate@binkert.org{ 16765807Snate@binkert.org if (this->thread[0]->status() != ThreadContext::Suspended) 16775807Snate@binkert.org return; 16785807Snate@binkert.org 16795807Snate@binkert.org this->wakeCPU(); 16805807Snate@binkert.org 16815807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 16825807Snate@binkert.org this->threadContexts[0]->activate(); 16835807Snate@binkert.org} 16845807Snate@binkert.org 16852292SN/Atemplate <class Impl> 16866221Snate@binkert.orgThreadID 16872292SN/AFullO3CPU<Impl>::getFreeTid() 16882292SN/A{ 16896221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 16906221Snate@binkert.org if (!tids[tid]) { 16916221Snate@binkert.org tids[tid] = true; 16926221Snate@binkert.org return tid; 16932292SN/A } 16942292SN/A } 16952292SN/A 16966221Snate@binkert.org return InvalidThreadID; 16972292SN/A} 16982292SN/A 16992292SN/Atemplate <class Impl> 17002292SN/Avoid 17012292SN/AFullO3CPU<Impl>::doContextSwitch() 17022292SN/A{ 17032292SN/A if (contextSwitch) { 17042292SN/A 17052292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 17062292SN/A 17076221Snate@binkert.org ThreadID size = cpuWaitList.size(); 17086221Snate@binkert.org for (ThreadID tid = 0; tid < size; tid++) { 17092292SN/A activateWhenReady(tid); 17102292SN/A } 17112292SN/A 17122292SN/A if (cpuWaitList.size() == 0) 17132292SN/A contextSwitch = true; 17142292SN/A } 17152292SN/A} 17162292SN/A 17172292SN/Atemplate <class Impl> 17182292SN/Avoid 17192292SN/AFullO3CPU<Impl>::updateThreadPriority() 17202292SN/A{ 17216221Snate@binkert.org if (activeThreads.size() > 1) { 17222292SN/A //DEFAULT TO ROUND ROBIN SCHEME 17232292SN/A //e.g. Move highest priority to end of thread list 17246221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 17252292SN/A 17262292SN/A unsigned high_thread = *list_begin; 17272292SN/A 17282292SN/A activeThreads.erase(list_begin); 17292292SN/A 17302292SN/A activeThreads.push_back(high_thread); 17312292SN/A } 17322292SN/A} 17331060SN/A 17341755SN/A// Forward declaration of FullO3CPU. 17352818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1736