cpu.cc revision 8799
11689SN/A/* 28707Sandreas.hansson@arm.com * Copyright (c) 2011 ARM Limited 38707Sandreas.hansson@arm.com * All rights reserved 48707Sandreas.hansson@arm.com * 58707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138707Sandreas.hansson@arm.com * 142325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422756Sksewell@umich.edu * Korey Sewell 437897Shestness@cs.utexas.edu * Rick Strong 441689SN/A */ 451689SN/A 468779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 476658Snate@binkert.org#include "config/the_isa.hh" 482733Sktlim@umich.edu#include "config/use_checker.hh" 498229Snate@binkert.org#include "cpu/o3/cpu.hh" 508229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 518229Snate@binkert.org#include "cpu/o3/thread_context.hh" 524762Snate@binkert.org#include "cpu/activity.hh" 538779Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 544762Snate@binkert.org#include "cpu/simple_thread.hh" 554762Snate@binkert.org#include "cpu/thread_context.hh" 568232Snate@binkert.org#include "debug/Activity.hh" 578232Snate@binkert.org#include "debug/O3CPU.hh" 588232Snate@binkert.org#include "debug/Quiesce.hh" 594762Snate@binkert.org#include "enums/MemoryMode.hh" 604762Snate@binkert.org#include "sim/core.hh" 618793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 628779Sgblack@eecs.umich.edu#include "sim/process.hh" 634762Snate@binkert.org#include "sim/stat_control.hh" 648460SAli.Saidi@ARM.com#include "sim/system.hh" 654762Snate@binkert.org 662794Sktlim@umich.edu#if USE_CHECKER 672794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 682794Sktlim@umich.edu#endif 692794Sktlim@umich.edu 705702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 715702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 728232Snate@binkert.org#include "debug/Activity.hh" 735702Ssaidi@eecs.umich.edu#endif 745702Ssaidi@eecs.umich.edu 755529Snate@binkert.orgclass BaseCPUParams; 765529Snate@binkert.org 772669Sktlim@umich.eduusing namespace TheISA; 786221Snate@binkert.orgusing namespace std; 791060SN/A 805529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 815712Shsul@eecs.umich.edu : BaseCPU(params) 821060SN/A{ 831060SN/A} 841060SN/A 852292SN/Avoid 862733Sktlim@umich.eduBaseO3CPU::regStats() 872292SN/A{ 882292SN/A BaseCPU::regStats(); 892292SN/A} 902292SN/A 918707Sandreas.hansson@arm.comtemplate<class Impl> 928707Sandreas.hansson@arm.combool 938707Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvTiming(PacketPtr pkt) 948707Sandreas.hansson@arm.com{ 958707Sandreas.hansson@arm.com DPRINTF(O3CPU, "Fetch unit received timing\n"); 968707Sandreas.hansson@arm.com if (pkt->isResponse()) { 978707Sandreas.hansson@arm.com // We shouldn't ever get a block in ownership state 988707Sandreas.hansson@arm.com assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); 998707Sandreas.hansson@arm.com 1008707Sandreas.hansson@arm.com fetch->processCacheCompletion(pkt); 1018707Sandreas.hansson@arm.com } 1028707Sandreas.hansson@arm.com //else Snooped a coherence request, just return 1038707Sandreas.hansson@arm.com return true; 1048707Sandreas.hansson@arm.com} 1058707Sandreas.hansson@arm.com 1068707Sandreas.hansson@arm.comtemplate<class Impl> 1078707Sandreas.hansson@arm.comvoid 1088707Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvRetry() 1098707Sandreas.hansson@arm.com{ 1108707Sandreas.hansson@arm.com fetch->recvRetry(); 1118707Sandreas.hansson@arm.com} 1128707Sandreas.hansson@arm.com 1138707Sandreas.hansson@arm.comtemplate <class Impl> 1148707Sandreas.hansson@arm.combool 1158707Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTiming(PacketPtr pkt) 1168707Sandreas.hansson@arm.com{ 1178707Sandreas.hansson@arm.com return lsq->recvTiming(pkt); 1188707Sandreas.hansson@arm.com} 1198707Sandreas.hansson@arm.com 1208707Sandreas.hansson@arm.comtemplate <class Impl> 1218707Sandreas.hansson@arm.comvoid 1228707Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvRetry() 1238707Sandreas.hansson@arm.com{ 1248707Sandreas.hansson@arm.com lsq->recvRetry(); 1258707Sandreas.hansson@arm.com} 1268707Sandreas.hansson@arm.com 1271060SN/Atemplate <class Impl> 1281755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 1295606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 1301060SN/A{ 1311060SN/A} 1321060SN/A 1331060SN/Atemplate <class Impl> 1341060SN/Avoid 1351755SN/AFullO3CPU<Impl>::TickEvent::process() 1361060SN/A{ 1371060SN/A cpu->tick(); 1381060SN/A} 1391060SN/A 1401060SN/Atemplate <class Impl> 1411060SN/Aconst char * 1425336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 1431060SN/A{ 1444873Sstever@eecs.umich.edu return "FullO3CPU tick"; 1451060SN/A} 1461060SN/A 1471060SN/Atemplate <class Impl> 1482829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 1495606Snate@binkert.org : Event(CPU_Switch_Pri) 1502829Sksewell@umich.edu{ 1512829Sksewell@umich.edu} 1522829Sksewell@umich.edu 1532829Sksewell@umich.edutemplate <class Impl> 1542829Sksewell@umich.eduvoid 1552829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 1562829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1572829Sksewell@umich.edu{ 1582829Sksewell@umich.edu tid = thread_num; 1592829Sksewell@umich.edu cpu = thread_cpu; 1602829Sksewell@umich.edu} 1612829Sksewell@umich.edu 1622829Sksewell@umich.edutemplate <class Impl> 1632829Sksewell@umich.eduvoid 1642829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1652829Sksewell@umich.edu{ 1662829Sksewell@umich.edu cpu->activateThread(tid); 1672829Sksewell@umich.edu} 1682829Sksewell@umich.edu 1692829Sksewell@umich.edutemplate <class Impl> 1702829Sksewell@umich.educonst char * 1715336Shines@cs.fsu.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1722829Sksewell@umich.edu{ 1734873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1742829Sksewell@umich.edu} 1752829Sksewell@umich.edu 1762829Sksewell@umich.edutemplate <class Impl> 1772875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1785606Snate@binkert.org : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1792875Sksewell@umich.edu{ 1802875Sksewell@umich.edu} 1812875Sksewell@umich.edu 1822875Sksewell@umich.edutemplate <class Impl> 1832875Sksewell@umich.eduvoid 1842875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1853859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1862875Sksewell@umich.edu{ 1872875Sksewell@umich.edu tid = thread_num; 1882875Sksewell@umich.edu cpu = thread_cpu; 1893859Sbinkertn@umich.edu remove = false; 1902875Sksewell@umich.edu} 1912875Sksewell@umich.edu 1922875Sksewell@umich.edutemplate <class Impl> 1932875Sksewell@umich.eduvoid 1942875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1952875Sksewell@umich.edu{ 1962875Sksewell@umich.edu cpu->deactivateThread(tid); 1973221Sktlim@umich.edu if (remove) 1983221Sktlim@umich.edu cpu->removeThread(tid); 1992875Sksewell@umich.edu} 2002875Sksewell@umich.edu 2012875Sksewell@umich.edutemplate <class Impl> 2022875Sksewell@umich.educonst char * 2035336Shines@cs.fsu.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 2042875Sksewell@umich.edu{ 2054873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 2062875Sksewell@umich.edu} 2072875Sksewell@umich.edu 2082875Sksewell@umich.edutemplate <class Impl> 2095595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 2102733Sktlim@umich.edu : BaseO3CPU(params), 2113781Sgblack@eecs.umich.edu itb(params->itb), 2123781Sgblack@eecs.umich.edu dtb(params->dtb), 2131060SN/A tickEvent(this), 2145737Scws3k@cs.virginia.edu#ifndef NDEBUG 2155737Scws3k@cs.virginia.edu instcount(0), 2165737Scws3k@cs.virginia.edu#endif 2172292SN/A removeInstsThisCycle(false), 2185595Sgblack@eecs.umich.edu fetch(this, params), 2195595Sgblack@eecs.umich.edu decode(this, params), 2205595Sgblack@eecs.umich.edu rename(this, params), 2215595Sgblack@eecs.umich.edu iew(this, params), 2225595Sgblack@eecs.umich.edu commit(this, params), 2231060SN/A 2245595Sgblack@eecs.umich.edu regFile(this, params->numPhysIntRegs, 2254329Sktlim@umich.edu params->numPhysFloatRegs), 2261060SN/A 2275529Snate@binkert.org freeList(params->numThreads, 2282292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 2292292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 2301060SN/A 2315595Sgblack@eecs.umich.edu rob(this, 2324329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 2332292SN/A params->smtROBPolicy, params->smtROBThreshold, 2345529Snate@binkert.org params->numThreads), 2351060SN/A 2365529Snate@binkert.org scoreboard(params->numThreads, 2372292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 2382292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 2396221Snate@binkert.org TheISA::NumMiscRegs * numThreads, 2402292SN/A TheISA::ZeroReg), 2411060SN/A 2428707Sandreas.hansson@arm.com icachePort(&fetch, this), 2438707Sandreas.hansson@arm.com dcachePort(&iew.ldstQueue, this), 2448707Sandreas.hansson@arm.com 2452873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 2462873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 2472873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 2482873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 2492873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 2505804Snate@binkert.org activityRec(name(), NumStages, 2512873Sktlim@umich.edu params->backComSize + params->forwardComSize, 2522873Sktlim@umich.edu params->activity), 2531060SN/A 2541060SN/A globalSeqNum(1), 2552292SN/A system(params->system), 2562843Sktlim@umich.edu drainCount(0), 2576221Snate@binkert.org deferRegistration(params->defer_registration) 2581060SN/A{ 2593221Sktlim@umich.edu if (!deferRegistration) { 2603221Sktlim@umich.edu _status = Running; 2613221Sktlim@umich.edu } else { 2623221Sktlim@umich.edu _status = Idle; 2633221Sktlim@umich.edu } 2641681SN/A 2654598Sbinkertn@umich.edu#if USE_CHECKER 2662794Sktlim@umich.edu if (params->checker) { 2672316SN/A BaseCPU *temp_checker = params->checker; 2682316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2698707Sandreas.hansson@arm.com checker->setIcachePort(&icachePort); 2702316SN/A checker->setSystem(params->system); 2714598Sbinkertn@umich.edu } else { 2724598Sbinkertn@umich.edu checker = NULL; 2734598Sbinkertn@umich.edu } 2742794Sktlim@umich.edu#endif // USE_CHECKER 2752316SN/A 2768793Sgblack@eecs.umich.edu if (!FullSystem) { 2778793Sgblack@eecs.umich.edu thread.resize(numThreads); 2788793Sgblack@eecs.umich.edu tids.resize(numThreads); 2798793Sgblack@eecs.umich.edu } 2801681SN/A 2812325SN/A // The stages also need their CPU pointer setup. However this 2822325SN/A // must be done at the upper level CPU because they have pointers 2832325SN/A // to the upper level CPU, and not this FullO3CPU. 2841060SN/A 2852292SN/A // Set up Pointers to the activeThreads list for each stage 2862292SN/A fetch.setActiveThreads(&activeThreads); 2872292SN/A decode.setActiveThreads(&activeThreads); 2882292SN/A rename.setActiveThreads(&activeThreads); 2892292SN/A iew.setActiveThreads(&activeThreads); 2902292SN/A commit.setActiveThreads(&activeThreads); 2911060SN/A 2921060SN/A // Give each of the stages the time buffer they will use. 2931060SN/A fetch.setTimeBuffer(&timeBuffer); 2941060SN/A decode.setTimeBuffer(&timeBuffer); 2951060SN/A rename.setTimeBuffer(&timeBuffer); 2961060SN/A iew.setTimeBuffer(&timeBuffer); 2971060SN/A commit.setTimeBuffer(&timeBuffer); 2981060SN/A 2991060SN/A // Also setup each of the stages' queues. 3001060SN/A fetch.setFetchQueue(&fetchQueue); 3011060SN/A decode.setFetchQueue(&fetchQueue); 3022292SN/A commit.setFetchQueue(&fetchQueue); 3031060SN/A decode.setDecodeQueue(&decodeQueue); 3041060SN/A rename.setDecodeQueue(&decodeQueue); 3051060SN/A rename.setRenameQueue(&renameQueue); 3061060SN/A iew.setRenameQueue(&renameQueue); 3071060SN/A iew.setIEWQueue(&iewQueue); 3081060SN/A commit.setIEWQueue(&iewQueue); 3091060SN/A commit.setRenameQueue(&renameQueue); 3101060SN/A 3112292SN/A commit.setIEWStage(&iew); 3122292SN/A rename.setIEWStage(&iew); 3132292SN/A rename.setCommitStage(&commit); 3142292SN/A 3158793Sgblack@eecs.umich.edu ThreadID active_threads; 3168793Sgblack@eecs.umich.edu if (FullSystem) { 3178793Sgblack@eecs.umich.edu active_threads = 1; 3188793Sgblack@eecs.umich.edu } else { 3198793Sgblack@eecs.umich.edu active_threads = params->workload.size(); 3202831Sksewell@umich.edu 3218793Sgblack@eecs.umich.edu if (active_threads > Impl::MaxThreads) { 3228793Sgblack@eecs.umich.edu panic("Workload Size too large. Increase the 'MaxThreads' " 3238793Sgblack@eecs.umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 3248793Sgblack@eecs.umich.edu "or edit your workload size."); 3258793Sgblack@eecs.umich.edu } 3262831Sksewell@umich.edu } 3272292SN/A 3282316SN/A //Make Sure That this a Valid Architeture 3292292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 3302292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 3312292SN/A 3322292SN/A rename.setScoreboard(&scoreboard); 3332292SN/A iew.setScoreboard(&scoreboard); 3342292SN/A 3351060SN/A // Setup the rename map for whichever stages need it. 3362292SN/A PhysRegIndex lreg_idx = 0; 3372292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 3381060SN/A 3396221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3402307SN/A bool bindRegs = (tid <= active_threads - 1); 3412292SN/A 3422292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 3432292SN/A params->numPhysIntRegs, 3442325SN/A lreg_idx, //Index for Logical. Regs 3452292SN/A 3462292SN/A TheISA::NumFloatRegs, 3472292SN/A params->numPhysFloatRegs, 3482325SN/A freg_idx, //Index for Float Regs 3492292SN/A 3502292SN/A TheISA::NumMiscRegs, 3512292SN/A 3522292SN/A TheISA::ZeroReg, 3532292SN/A TheISA::ZeroReg, 3542292SN/A 3552292SN/A tid, 3562292SN/A false); 3572292SN/A 3582292SN/A renameMap[tid].init(TheISA::NumIntRegs, 3592292SN/A params->numPhysIntRegs, 3602325SN/A lreg_idx, //Index for Logical. Regs 3612292SN/A 3622292SN/A TheISA::NumFloatRegs, 3632292SN/A params->numPhysFloatRegs, 3642325SN/A freg_idx, //Index for Float Regs 3652292SN/A 3662292SN/A TheISA::NumMiscRegs, 3672292SN/A 3682292SN/A TheISA::ZeroReg, 3692292SN/A TheISA::ZeroReg, 3702292SN/A 3712292SN/A tid, 3722292SN/A bindRegs); 3733221Sktlim@umich.edu 3743221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3753221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3762292SN/A } 3772292SN/A 3782292SN/A rename.setRenameMap(renameMap); 3792292SN/A commit.setRenameMap(commitRenameMap); 3802292SN/A 3812292SN/A // Give renameMap & rename stage access to the freeList; 3826221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3836221Snate@binkert.org renameMap[tid].setFreeList(&freeList); 3841060SN/A rename.setFreeList(&freeList); 3852292SN/A 3861060SN/A // Setup the ROB for whichever stages need it. 3871060SN/A commit.setROB(&rob); 3882292SN/A 3897823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 3902292SN/A 3912829Sksewell@umich.edu lastActivatedCycle = -1; 3926221Snate@binkert.org#if 0 3933093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3946221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3956221Snate@binkert.org globalSeqNum[tid] = 1; 3966221Snate@binkert.org#endif 3973093Sksewell@umich.edu 3982292SN/A contextSwitch = false; 3995595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 4005595Sgblack@eecs.umich.edu 4015595Sgblack@eecs.umich.edu // Setup any thread state. 4025595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 4035595Sgblack@eecs.umich.edu 4046221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 4058793Sgblack@eecs.umich.edu if (FullSystem) { 4068793Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 4078793Sgblack@eecs.umich.edu assert(this->numThreads == 1); 4088793Sgblack@eecs.umich.edu this->thread[tid] = new Thread(this, 0, NULL); 4098793Sgblack@eecs.umich.edu } else { 4108793Sgblack@eecs.umich.edu if (tid < params->workload.size()) { 4118793Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 4128793Sgblack@eecs.umich.edu tid, this->thread[tid]); 4138793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 4148793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 4158793Sgblack@eecs.umich.edu tid, params->workload[tid]); 4165595Sgblack@eecs.umich.edu 4178793Sgblack@eecs.umich.edu //usedTids[tid] = true; 4188793Sgblack@eecs.umich.edu //threadMap[tid] = tid; 4198793Sgblack@eecs.umich.edu } else { 4208793Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 4218793Sgblack@eecs.umich.edu //when scheduling threads to CPU 4228793Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 4235595Sgblack@eecs.umich.edu 4248793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 4258793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 4268793Sgblack@eecs.umich.edu tid, dummy_proc); 4278793Sgblack@eecs.umich.edu //usedTids[tid] = false; 4288793Sgblack@eecs.umich.edu } 4295595Sgblack@eecs.umich.edu } 4305595Sgblack@eecs.umich.edu 4315595Sgblack@eecs.umich.edu ThreadContext *tc; 4325595Sgblack@eecs.umich.edu 4335595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 4345595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 4355595Sgblack@eecs.umich.edu 4365595Sgblack@eecs.umich.edu tc = o3_tc; 4375595Sgblack@eecs.umich.edu 4385595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 4395595Sgblack@eecs.umich.edu // CheckerThreadContext. 4405595Sgblack@eecs.umich.edu#if USE_CHECKER 4415595Sgblack@eecs.umich.edu if (params->checker) { 4425595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 4435595Sgblack@eecs.umich.edu o3_tc, this->checker); 4445595Sgblack@eecs.umich.edu } 4455595Sgblack@eecs.umich.edu#endif 4465595Sgblack@eecs.umich.edu 4475595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 4485595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 4496221Snate@binkert.org o3_tc->thread = this->thread[tid]; 4505595Sgblack@eecs.umich.edu 4518793Sgblack@eecs.umich.edu if (FullSystem) { 4528793Sgblack@eecs.umich.edu // Setup quiesce event. 4538793Sgblack@eecs.umich.edu this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 4548793Sgblack@eecs.umich.edu } 4555595Sgblack@eecs.umich.edu // Give the thread the TC. 4566221Snate@binkert.org this->thread[tid]->tc = tc; 4575595Sgblack@eecs.umich.edu 4585595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4595595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4605595Sgblack@eecs.umich.edu } 4615595Sgblack@eecs.umich.edu 4626221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4636221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4645595Sgblack@eecs.umich.edu 4655595Sgblack@eecs.umich.edu lockAddr = 0; 4665595Sgblack@eecs.umich.edu lockFlag = false; 4671060SN/A} 4681060SN/A 4691060SN/Atemplate <class Impl> 4701755SN/AFullO3CPU<Impl>::~FullO3CPU() 4711060SN/A{ 4721060SN/A} 4731060SN/A 4741060SN/Atemplate <class Impl> 4751060SN/Avoid 4765595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4771062SN/A{ 4782733Sktlim@umich.edu BaseO3CPU::regStats(); 4792292SN/A 4802733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4812292SN/A timesIdled 4822292SN/A .name(name() + ".timesIdled") 4832292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4842292SN/A " unscheduled itself") 4852292SN/A .prereq(timesIdled); 4862292SN/A 4872292SN/A idleCycles 4882292SN/A .name(name() + ".idleCycles") 4892292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4902292SN/A "to idling") 4912292SN/A .prereq(idleCycles); 4922292SN/A 4938627SAli.Saidi@ARM.com quiesceCycles 4948627SAli.Saidi@ARM.com .name(name() + ".quiesceCycles") 4958627SAli.Saidi@ARM.com .desc("Total number of cycles that CPU has spent quiesced or waiting " 4968627SAli.Saidi@ARM.com "for an interrupt") 4978627SAli.Saidi@ARM.com .prereq(quiesceCycles); 4988627SAli.Saidi@ARM.com 4992292SN/A // Number of Instructions simulated 5002292SN/A // -------------------------------- 5012292SN/A // Should probably be in Base CPU but need templated 5022292SN/A // MaxThreads so put in here instead 5032292SN/A committedInsts 5042292SN/A .init(numThreads) 5052292SN/A .name(name() + ".committedInsts") 5062292SN/A .desc("Number of Instructions Simulated"); 5072292SN/A 5082292SN/A totalCommittedInsts 5092292SN/A .name(name() + ".committedInsts_total") 5102292SN/A .desc("Number of Instructions Simulated"); 5112292SN/A 5122292SN/A cpi 5132292SN/A .name(name() + ".cpi") 5142292SN/A .desc("CPI: Cycles Per Instruction") 5152292SN/A .precision(6); 5164392Sktlim@umich.edu cpi = numCycles / committedInsts; 5172292SN/A 5182292SN/A totalCpi 5192292SN/A .name(name() + ".cpi_total") 5202292SN/A .desc("CPI: Total CPI of All Threads") 5212292SN/A .precision(6); 5224392Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 5232292SN/A 5242292SN/A ipc 5252292SN/A .name(name() + ".ipc") 5262292SN/A .desc("IPC: Instructions Per Cycle") 5272292SN/A .precision(6); 5284392Sktlim@umich.edu ipc = committedInsts / numCycles; 5292292SN/A 5302292SN/A totalIpc 5312292SN/A .name(name() + ".ipc_total") 5322292SN/A .desc("IPC: Total IPC of All Threads") 5332292SN/A .precision(6); 5344392Sktlim@umich.edu totalIpc = totalCommittedInsts / numCycles; 5352292SN/A 5365595Sgblack@eecs.umich.edu this->fetch.regStats(); 5375595Sgblack@eecs.umich.edu this->decode.regStats(); 5385595Sgblack@eecs.umich.edu this->rename.regStats(); 5395595Sgblack@eecs.umich.edu this->iew.regStats(); 5405595Sgblack@eecs.umich.edu this->commit.regStats(); 5417897Shestness@cs.utexas.edu this->rob.regStats(); 5427897Shestness@cs.utexas.edu 5437897Shestness@cs.utexas.edu intRegfileReads 5447897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 5457897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 5467897Shestness@cs.utexas.edu .prereq(intRegfileReads); 5477897Shestness@cs.utexas.edu 5487897Shestness@cs.utexas.edu intRegfileWrites 5497897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 5507897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 5517897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 5527897Shestness@cs.utexas.edu 5537897Shestness@cs.utexas.edu fpRegfileReads 5547897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 5557897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 5567897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 5577897Shestness@cs.utexas.edu 5587897Shestness@cs.utexas.edu fpRegfileWrites 5597897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 5607897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 5617897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 5627897Shestness@cs.utexas.edu 5637897Shestness@cs.utexas.edu miscRegfileReads 5647897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5657897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5667897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5677897Shestness@cs.utexas.edu 5687897Shestness@cs.utexas.edu miscRegfileWrites 5697897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5707897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5717897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5721062SN/A} 5731062SN/A 5741062SN/Atemplate <class Impl> 5752871Sktlim@umich.eduPort * 5762871Sktlim@umich.eduFullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 5772871Sktlim@umich.edu{ 5782871Sktlim@umich.edu if (if_name == "dcache_port") 5798707Sandreas.hansson@arm.com return &dcachePort; 5802871Sktlim@umich.edu else if (if_name == "icache_port") 5818707Sandreas.hansson@arm.com return &icachePort; 5822871Sktlim@umich.edu else 5832871Sktlim@umich.edu panic("No Such Port\n"); 5842871Sktlim@umich.edu} 5852871Sktlim@umich.edu 5862871Sktlim@umich.edutemplate <class Impl> 5871062SN/Avoid 5881755SN/AFullO3CPU<Impl>::tick() 5891060SN/A{ 5902733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5911060SN/A 5922292SN/A ++numCycles; 5932292SN/A 5942325SN/A// activity = false; 5952292SN/A 5962292SN/A //Tick each of the stages 5971060SN/A fetch.tick(); 5981060SN/A 5991060SN/A decode.tick(); 6001060SN/A 6011060SN/A rename.tick(); 6021060SN/A 6031060SN/A iew.tick(); 6041060SN/A 6051060SN/A commit.tick(); 6061060SN/A 6078793Sgblack@eecs.umich.edu if (!FullSystem) 6088793Sgblack@eecs.umich.edu doContextSwitch(); 6092292SN/A 6102292SN/A // Now advance the time buffers 6111060SN/A timeBuffer.advance(); 6121060SN/A 6131060SN/A fetchQueue.advance(); 6141060SN/A decodeQueue.advance(); 6151060SN/A renameQueue.advance(); 6161060SN/A iewQueue.advance(); 6171060SN/A 6182325SN/A activityRec.advance(); 6192292SN/A 6202292SN/A if (removeInstsThisCycle) { 6212292SN/A cleanUpRemovedInsts(); 6222292SN/A } 6232292SN/A 6242325SN/A if (!tickEvent.scheduled()) { 6252867Sktlim@umich.edu if (_status == SwitchedOut || 6262905Sktlim@umich.edu getState() == SimObject::Drained) { 6273226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 6282325SN/A // increment stat 6297823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 6303221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 6313226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 6327823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 6332325SN/A timesIdled++; 6342325SN/A } else { 6357823Ssteve.reinhardt@amd.com schedule(tickEvent, nextCycle(curTick() + ticks(1))); 6363226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 6372325SN/A } 6382292SN/A } 6392292SN/A 6408793Sgblack@eecs.umich.edu if (!FullSystem) 6418793Sgblack@eecs.umich.edu updateThreadPriority(); 6421060SN/A} 6431060SN/A 6441060SN/Atemplate <class Impl> 6451060SN/Avoid 6461755SN/AFullO3CPU<Impl>::init() 6471060SN/A{ 6485714Shsul@eecs.umich.edu BaseCPU::init(); 6491060SN/A 6502292SN/A // Set inSyscall so that the CPU doesn't squash when initially 6512292SN/A // setting up registers. 6526221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 6536221Snate@binkert.org thread[tid]->inSyscall = true; 6542292SN/A 6558707Sandreas.hansson@arm.com // this CPU could still be unconnected if we are restoring from a 6568707Sandreas.hansson@arm.com // checkpoint and this CPU is to be switched in, thus we can only 6578707Sandreas.hansson@arm.com // do this here if the instruction port is actually connected, if 6588707Sandreas.hansson@arm.com // not we have to do it as part of takeOverFrom 6598707Sandreas.hansson@arm.com if (icachePort.isConnected()) 6608707Sandreas.hansson@arm.com fetch.setIcache(); 6618707Sandreas.hansson@arm.com 6628793Sgblack@eecs.umich.edu if (FullSystem) { 6638793Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 6648793Sgblack@eecs.umich.edu ThreadContext *src_tc = threadContexts[tid]; 6658793Sgblack@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 6668799Sgblack@eecs.umich.edu // Initialise the ThreadContext's memory proxies 6678799Sgblack@eecs.umich.edu thread[tid]->initMemProxies(thread[tid]->getTC()); 6688793Sgblack@eecs.umich.edu } 6696034Ssteve.reinhardt@amd.com } 6702292SN/A 6712292SN/A // Clear inSyscall. 6726221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6736221Snate@binkert.org thread[tid]->inSyscall = false; 6742292SN/A 6752316SN/A // Initialize stages. 6762292SN/A fetch.initStage(); 6772292SN/A iew.initStage(); 6782292SN/A rename.initStage(); 6792292SN/A commit.initStage(); 6802292SN/A 6812292SN/A commit.setThreads(thread); 6822292SN/A} 6832292SN/A 6842292SN/Atemplate <class Impl> 6852292SN/Avoid 6866221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 6872875Sksewell@umich.edu{ 6886221Snate@binkert.org list<ThreadID>::iterator isActive = 6895314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6902875Sksewell@umich.edu 6913226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6923226Sktlim@umich.edu 6932875Sksewell@umich.edu if (isActive == activeThreads.end()) { 6942875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6952875Sksewell@umich.edu tid); 6962875Sksewell@umich.edu 6972875Sksewell@umich.edu activeThreads.push_back(tid); 6982875Sksewell@umich.edu } 6992875Sksewell@umich.edu} 7002875Sksewell@umich.edu 7012875Sksewell@umich.edutemplate <class Impl> 7022875Sksewell@umich.eduvoid 7036221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 7042875Sksewell@umich.edu{ 7052875Sksewell@umich.edu //Remove From Active List, if Active 7066221Snate@binkert.org list<ThreadID>::iterator thread_it = 7075314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 7082875Sksewell@umich.edu 7093226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 7103226Sktlim@umich.edu 7112875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 7122875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 7132875Sksewell@umich.edu tid); 7142875Sksewell@umich.edu activeThreads.erase(thread_it); 7152875Sksewell@umich.edu } 7162875Sksewell@umich.edu} 7172875Sksewell@umich.edu 7182875Sksewell@umich.edutemplate <class Impl> 7196221Snate@binkert.orgCounter 7206221Snate@binkert.orgFullO3CPU<Impl>::totalInstructions() const 7216221Snate@binkert.org{ 7226221Snate@binkert.org Counter total(0); 7236221Snate@binkert.org 7246221Snate@binkert.org ThreadID size = thread.size(); 7256221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 7266221Snate@binkert.org total += thread[i]->numInst; 7276221Snate@binkert.org 7286221Snate@binkert.org return total; 7296221Snate@binkert.org} 7306221Snate@binkert.org 7316221Snate@binkert.orgtemplate <class Impl> 7322875Sksewell@umich.eduvoid 7336221Snate@binkert.orgFullO3CPU<Impl>::activateContext(ThreadID tid, int delay) 7342875Sksewell@umich.edu{ 7352875Sksewell@umich.edu // Needs to set each stage to running as well. 7362875Sksewell@umich.edu if (delay){ 7372875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 7387823Ssteve.reinhardt@amd.com "on cycle %d\n", tid, curTick() + ticks(delay)); 7392875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 7402875Sksewell@umich.edu } else { 7412875Sksewell@umich.edu activateThread(tid); 7422875Sksewell@umich.edu } 7432875Sksewell@umich.edu 7447823Ssteve.reinhardt@amd.com if (lastActivatedCycle < curTick()) { 7452875Sksewell@umich.edu scheduleTickEvent(delay); 7462875Sksewell@umich.edu 7472875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 7482875Sksewell@umich.edu // deschedule itself. 7492875Sksewell@umich.edu activityRec.activity(); 7502875Sksewell@umich.edu fetch.wakeFromQuiesce(); 7512875Sksewell@umich.edu 7528627SAli.Saidi@ARM.com quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle); 7538627SAli.Saidi@ARM.com 7547823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 7552875Sksewell@umich.edu 7562875Sksewell@umich.edu _status = Running; 7572875Sksewell@umich.edu } 7582875Sksewell@umich.edu} 7592875Sksewell@umich.edu 7602875Sksewell@umich.edutemplate <class Impl> 7613221Sktlim@umich.edubool 7626221Snate@binkert.orgFullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay) 7632875Sksewell@umich.edu{ 7642875Sksewell@umich.edu // Schedule removal of thread data from CPU 7652875Sksewell@umich.edu if (delay){ 7662875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 7677823Ssteve.reinhardt@amd.com "on cycle %d\n", tid, curTick() + ticks(delay)); 7683221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 7693221Sktlim@umich.edu return false; 7702875Sksewell@umich.edu } else { 7712875Sksewell@umich.edu deactivateThread(tid); 7723221Sktlim@umich.edu if (remove) 7733221Sktlim@umich.edu removeThread(tid); 7743221Sktlim@umich.edu return true; 7752875Sksewell@umich.edu } 7762875Sksewell@umich.edu} 7772875Sksewell@umich.edu 7782875Sksewell@umich.edutemplate <class Impl> 7792875Sksewell@umich.eduvoid 7806221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 7812875Sksewell@umich.edu{ 7822875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 7833221Sktlim@umich.edu bool deallocated = deallocateContext(tid, false, 1); 7843221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 7855570Snate@binkert.org if ((activeThreads.size() == 1 && !deallocated) || 7863859Sbinkertn@umich.edu activeThreads.size() == 0) 7872910Sksewell@umich.edu unscheduleTickEvent(); 7888627SAli.Saidi@ARM.com 7898627SAli.Saidi@ARM.com DPRINTF(Quiesce, "Suspending Context\n"); 7908627SAli.Saidi@ARM.com lastRunningCycle = curTick(); 7912875Sksewell@umich.edu _status = Idle; 7922875Sksewell@umich.edu} 7932875Sksewell@umich.edu 7942875Sksewell@umich.edutemplate <class Impl> 7952875Sksewell@umich.eduvoid 7966221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 7972875Sksewell@umich.edu{ 7982910Sksewell@umich.edu //For now, this is the same as deallocate 7992910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 8003221Sktlim@umich.edu deallocateContext(tid, true, 1); 8012875Sksewell@umich.edu} 8022875Sksewell@umich.edu 8032875Sksewell@umich.edutemplate <class Impl> 8042875Sksewell@umich.eduvoid 8056221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 8062292SN/A{ 8072847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 8082292SN/A // Will change now that the PC and thread state is internal to the CPU 8092683Sktlim@umich.edu // and not in the ThreadContext. 8108793Sgblack@eecs.umich.edu ThreadContext *src_tc; 8118793Sgblack@eecs.umich.edu if (FullSystem) 8128793Sgblack@eecs.umich.edu src_tc = system->threadContexts[tid]; 8138793Sgblack@eecs.umich.edu else 8148793Sgblack@eecs.umich.edu src_tc = tcBase(tid); 8152292SN/A 8162292SN/A //Bind Int Regs to Rename Map 8172292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 8182292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 8192292SN/A 8202292SN/A renameMap[tid].setEntry(ireg,phys_reg); 8212292SN/A scoreboard.setReg(phys_reg); 8222292SN/A } 8232292SN/A 8242292SN/A //Bind Float Regs to Rename Map 8252292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 8262292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 8272292SN/A 8282292SN/A renameMap[tid].setEntry(freg,phys_reg); 8292292SN/A scoreboard.setReg(phys_reg); 8302292SN/A } 8312292SN/A 8322292SN/A //Copy Thread Data Into RegFile 8332847Sksewell@umich.edu //this->copyFromTC(tid); 8342292SN/A 8352847Sksewell@umich.edu //Set PC/NPC/NNPC 8367720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 8372292SN/A 8382680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 8392292SN/A 8402292SN/A activateContext(tid,1); 8412292SN/A 8422292SN/A //Reset ROB/IQ/LSQ Entries 8432292SN/A commit.rob->resetEntries(); 8442292SN/A iew.resetEntries(); 8452292SN/A} 8462292SN/A 8472292SN/Atemplate <class Impl> 8482292SN/Avoid 8496221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 8502292SN/A{ 8512877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 8522847Sksewell@umich.edu 8532847Sksewell@umich.edu // Copy Thread Data From RegFile 8542847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 8555364Sksewell@umich.edu // this->copyToTC(tid); 8565364Sksewell@umich.edu 8575364Sksewell@umich.edu 8585364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 8595364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 8605364Sksewell@umich.edu // in SMT workloads. 8612847Sksewell@umich.edu 8622847Sksewell@umich.edu // Unbind Int Regs from Rename Map 8632292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 8642292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 8652292SN/A 8662292SN/A scoreboard.unsetReg(phys_reg); 8672292SN/A freeList.addReg(phys_reg); 8682292SN/A } 8692292SN/A 8702847Sksewell@umich.edu // Unbind Float Regs from Rename Map 8715362Sksewell@umich.edu for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 8722292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 8732292SN/A 8742292SN/A scoreboard.unsetReg(phys_reg); 8752292SN/A freeList.addReg(phys_reg); 8762292SN/A } 8772292SN/A 8782847Sksewell@umich.edu // Squash Throughout Pipeline 8798138SAli.Saidi@ARM.com DynInstPtr inst = commit.rob->readHeadInst(tid); 8808138SAli.Saidi@ARM.com InstSeqNum squash_seq_num = inst->seqNum; 8818138SAli.Saidi@ARM.com fetch.squash(0, squash_seq_num, inst, tid); 8822292SN/A decode.squash(tid); 8832935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 8842875Sksewell@umich.edu iew.squash(tid); 8855363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 8862935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 8872292SN/A 8885362Sksewell@umich.edu 8895362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 8902292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 8912292SN/A 8922847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 8933229Sktlim@umich.edu 8943229Sktlim@umich.edu // Commented out for now. This should be possible to do by 8953229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 8963229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 8973229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 8983229Sktlim@umich.edu/* 8992292SN/A if (activeThreads.size() >= 1) { 9002292SN/A commit.rob->resetEntries(); 9012292SN/A iew.resetEntries(); 9022292SN/A } 9033229Sktlim@umich.edu*/ 9042292SN/A} 9052292SN/A 9062292SN/A 9072292SN/Atemplate <class Impl> 9082292SN/Avoid 9096221Snate@binkert.orgFullO3CPU<Impl>::activateWhenReady(ThreadID tid) 9102292SN/A{ 9112733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 9122292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 9132292SN/A tid); 9142292SN/A 9152292SN/A bool ready = true; 9162292SN/A 9172292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 9182733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9192292SN/A "Phys. Int. Regs.\n", 9202292SN/A tid); 9212292SN/A ready = false; 9222292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 9232733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9242292SN/A "Phys. Float. Regs.\n", 9252292SN/A tid); 9262292SN/A ready = false; 9272292SN/A } else if (commit.rob->numFreeEntries() >= 9282292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 9292733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9302292SN/A "ROB entries.\n", 9312292SN/A tid); 9322292SN/A ready = false; 9332292SN/A } else if (iew.instQueue.numFreeEntries() >= 9342292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 9352733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9362292SN/A "IQ entries.\n", 9372292SN/A tid); 9382292SN/A ready = false; 9392292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 9402292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 9412733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9422292SN/A "LSQ entries.\n", 9432292SN/A tid); 9442292SN/A ready = false; 9452292SN/A } 9462292SN/A 9472292SN/A if (ready) { 9482292SN/A insertThread(tid); 9492292SN/A 9502292SN/A contextSwitch = false; 9512292SN/A 9522292SN/A cpuWaitList.remove(tid); 9532292SN/A } else { 9542292SN/A suspendContext(tid); 9552292SN/A 9562292SN/A //blocks fetch 9572292SN/A contextSwitch = true; 9582292SN/A 9592875Sksewell@umich.edu //@todo: dont always add to waitlist 9602292SN/A //do waitlist 9612292SN/A cpuWaitList.push_back(tid); 9621060SN/A } 9631060SN/A} 9641060SN/A 9654192Sktlim@umich.edutemplate <class Impl> 9665595Sgblack@eecs.umich.eduFault 9676221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 9685702Ssaidi@eecs.umich.edu{ 9695702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9705702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 9715702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 9725702Ssaidi@eecs.umich.edu 9735702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 9745702Ssaidi@eecs.umich.edu 9755702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 9765702Ssaidi@eecs.umich.edu#endif 9775702Ssaidi@eecs.umich.edu return NoFault; 9785702Ssaidi@eecs.umich.edu} 9795702Ssaidi@eecs.umich.edu 9805702Ssaidi@eecs.umich.edutemplate <class Impl> 9815702Ssaidi@eecs.umich.edubool 9826221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 9835702Ssaidi@eecs.umich.edu{ 9845702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9855702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 9865702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 9875702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 9885702Ssaidi@eecs.umich.edu 9895702Ssaidi@eecs.umich.edu switch (palFunc) { 9905702Ssaidi@eecs.umich.edu case PAL::halt: 9915702Ssaidi@eecs.umich.edu halt(); 9925702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 9935702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 9945702Ssaidi@eecs.umich.edu break; 9955702Ssaidi@eecs.umich.edu 9965702Ssaidi@eecs.umich.edu case PAL::bpt: 9975702Ssaidi@eecs.umich.edu case PAL::bugchk: 9985702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 9995702Ssaidi@eecs.umich.edu return false; 10005702Ssaidi@eecs.umich.edu break; 10015702Ssaidi@eecs.umich.edu } 10025702Ssaidi@eecs.umich.edu#endif 10035702Ssaidi@eecs.umich.edu return true; 10045702Ssaidi@eecs.umich.edu} 10055702Ssaidi@eecs.umich.edu 10065702Ssaidi@eecs.umich.edutemplate <class Impl> 10075702Ssaidi@eecs.umich.eduFault 10085595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 10095595Sgblack@eecs.umich.edu{ 10105595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 10115647Sgblack@eecs.umich.edu return this->interrupts->getInterrupt(this->threadContexts[0]); 10125595Sgblack@eecs.umich.edu} 10135595Sgblack@eecs.umich.edu 10145595Sgblack@eecs.umich.edutemplate <class Impl> 10155595Sgblack@eecs.umich.eduvoid 10165595Sgblack@eecs.umich.eduFullO3CPU<Impl>::processInterrupts(Fault interrupt) 10175595Sgblack@eecs.umich.edu{ 10185595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 10195595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 10205595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 10215595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 10225595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 10235595Sgblack@eecs.umich.edu 10245595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 10255647Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 10265595Sgblack@eecs.umich.edu 10275595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 10287684Sgblack@eecs.umich.edu this->trap(interrupt, 0, NULL); 10295595Sgblack@eecs.umich.edu} 10305595Sgblack@eecs.umich.edu 10311060SN/Atemplate <class Impl> 10322852Sktlim@umich.eduvoid 10337684Sgblack@eecs.umich.eduFullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst) 10345595Sgblack@eecs.umich.edu{ 10355595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 10367684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 10375595Sgblack@eecs.umich.edu} 10385595Sgblack@eecs.umich.edu 10395595Sgblack@eecs.umich.edutemplate <class Impl> 10405595Sgblack@eecs.umich.eduvoid 10416221Snate@binkert.orgFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 10425595Sgblack@eecs.umich.edu{ 10435595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 10445595Sgblack@eecs.umich.edu 10455595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 10465595Sgblack@eecs.umich.edu 10475595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 10485595Sgblack@eecs.umich.edu // instruction. 10495595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 10505595Sgblack@eecs.umich.edu 10515595Sgblack@eecs.umich.edu // Execute the actual syscall. 10525595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 10535595Sgblack@eecs.umich.edu 10545595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 10555595Sgblack@eecs.umich.edu // incrementing it. 10565595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 10575595Sgblack@eecs.umich.edu} 10585595Sgblack@eecs.umich.edu 10595595Sgblack@eecs.umich.edutemplate <class Impl> 10605595Sgblack@eecs.umich.eduvoid 10612864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 10622864Sktlim@umich.edu{ 10632918Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 10642918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 10652864Sktlim@umich.edu BaseCPU::serialize(os); 10662864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 10672864Sktlim@umich.edu tickEvent.serialize(os); 10682864Sktlim@umich.edu 10692864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10702864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 10712864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 10722864Sktlim@umich.edu static SimpleThread temp; 10732864Sktlim@umich.edu 10746221Snate@binkert.org ThreadID size = thread.size(); 10756221Snate@binkert.org for (ThreadID i = 0; i < size; i++) { 10762864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 10772864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10782864Sktlim@umich.edu temp.serialize(os); 10792864Sktlim@umich.edu } 10802864Sktlim@umich.edu} 10812864Sktlim@umich.edu 10822864Sktlim@umich.edutemplate <class Impl> 10832864Sktlim@umich.eduvoid 10842864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 10852864Sktlim@umich.edu{ 10862918Sktlim@umich.edu SimObject::State so_state; 10872918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 10882864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 10892864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 10902864Sktlim@umich.edu 10912864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10922864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 10932864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 10942864Sktlim@umich.edu static SimpleThread temp; 10952864Sktlim@umich.edu 10966221Snate@binkert.org ThreadID size = thread.size(); 10976221Snate@binkert.org for (ThreadID i = 0; i < size; i++) { 10982864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10992864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 11002864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 11012864Sktlim@umich.edu } 11022864Sktlim@umich.edu} 11032864Sktlim@umich.edu 11042864Sktlim@umich.edutemplate <class Impl> 11052905Sktlim@umich.eduunsigned int 11062843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 11071060SN/A{ 11083125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 11093512Sktlim@umich.edu 11103512Sktlim@umich.edu // If the CPU isn't doing anything, then return immediately. 11113512Sktlim@umich.edu if (_status == Idle || _status == SwitchedOut) { 11123512Sktlim@umich.edu return 0; 11133512Sktlim@umich.edu } 11143512Sktlim@umich.edu 11152843Sktlim@umich.edu drainCount = 0; 11162843Sktlim@umich.edu fetch.drain(); 11172843Sktlim@umich.edu decode.drain(); 11182843Sktlim@umich.edu rename.drain(); 11192843Sktlim@umich.edu iew.drain(); 11202843Sktlim@umich.edu commit.drain(); 11212325SN/A 11222325SN/A // Wake the CPU and record activity so everything can drain out if 11232863Sktlim@umich.edu // the CPU was not able to immediately drain. 11242905Sktlim@umich.edu if (getState() != SimObject::Drained) { 11252864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 11262864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 11272864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 11282864Sktlim@umich.edu // process on the drain event. 11292864Sktlim@umich.edu drainEvent = drain_event; 11302843Sktlim@umich.edu 11312863Sktlim@umich.edu wakeCPU(); 11322863Sktlim@umich.edu activityRec.activity(); 11332852Sktlim@umich.edu 11342905Sktlim@umich.edu return 1; 11352863Sktlim@umich.edu } else { 11362905Sktlim@umich.edu return 0; 11372863Sktlim@umich.edu } 11382316SN/A} 11392310SN/A 11402316SN/Atemplate <class Impl> 11412316SN/Avoid 11422843Sktlim@umich.eduFullO3CPU<Impl>::resume() 11432316SN/A{ 11442843Sktlim@umich.edu fetch.resume(); 11452843Sktlim@umich.edu decode.resume(); 11462843Sktlim@umich.edu rename.resume(); 11472843Sktlim@umich.edu iew.resume(); 11482843Sktlim@umich.edu commit.resume(); 11492316SN/A 11502905Sktlim@umich.edu changeState(SimObject::Running); 11512905Sktlim@umich.edu 11522864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 11532864Sktlim@umich.edu return; 11542864Sktlim@umich.edu 11554762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 11563319Shsul@eecs.umich.edu 11572843Sktlim@umich.edu if (!tickEvent.scheduled()) 11585606Snate@binkert.org schedule(tickEvent, nextCycle()); 11592843Sktlim@umich.edu _status = Running; 11602843Sktlim@umich.edu} 11612316SN/A 11622843Sktlim@umich.edutemplate <class Impl> 11632843Sktlim@umich.eduvoid 11642843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 11652843Sktlim@umich.edu{ 11662843Sktlim@umich.edu if (++drainCount == NumStages) { 11672316SN/A if (tickEvent.scheduled()) 11682316SN/A tickEvent.squash(); 11692863Sktlim@umich.edu 11702905Sktlim@umich.edu changeState(SimObject::Drained); 11712863Sktlim@umich.edu 11723126Sktlim@umich.edu BaseCPU::switchOut(); 11733126Sktlim@umich.edu 11742863Sktlim@umich.edu if (drainEvent) { 11752863Sktlim@umich.edu drainEvent->process(); 11762863Sktlim@umich.edu drainEvent = NULL; 11772863Sktlim@umich.edu } 11782310SN/A } 11792843Sktlim@umich.edu assert(drainCount <= 5); 11802843Sktlim@umich.edu} 11812843Sktlim@umich.edu 11822843Sktlim@umich.edutemplate <class Impl> 11832843Sktlim@umich.eduvoid 11842843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 11852843Sktlim@umich.edu{ 11862843Sktlim@umich.edu fetch.switchOut(); 11872843Sktlim@umich.edu rename.switchOut(); 11882325SN/A iew.switchOut(); 11892843Sktlim@umich.edu commit.switchOut(); 11902843Sktlim@umich.edu instList.clear(); 11912843Sktlim@umich.edu while (!removeList.empty()) { 11922843Sktlim@umich.edu removeList.pop(); 11932843Sktlim@umich.edu } 11942843Sktlim@umich.edu 11952843Sktlim@umich.edu _status = SwitchedOut; 11962843Sktlim@umich.edu#if USE_CHECKER 11972843Sktlim@umich.edu if (checker) 11982843Sktlim@umich.edu checker->switchOut(); 11992843Sktlim@umich.edu#endif 12003126Sktlim@umich.edu if (tickEvent.scheduled()) 12013126Sktlim@umich.edu tickEvent.squash(); 12021060SN/A} 12031060SN/A 12041060SN/Atemplate <class Impl> 12051060SN/Avoid 12061755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 12071060SN/A{ 12082325SN/A // Flush out any old data from the time buffers. 12092873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 12102307SN/A timeBuffer.advance(); 12112307SN/A fetchQueue.advance(); 12122307SN/A decodeQueue.advance(); 12132307SN/A renameQueue.advance(); 12142307SN/A iewQueue.advance(); 12152307SN/A } 12162307SN/A 12172325SN/A activityRec.reset(); 12182307SN/A 12198707Sandreas.hansson@arm.com BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 12201060SN/A 12212307SN/A fetch.takeOverFrom(); 12222307SN/A decode.takeOverFrom(); 12232307SN/A rename.takeOverFrom(); 12242307SN/A iew.takeOverFrom(); 12252307SN/A commit.takeOverFrom(); 12262307SN/A 12277507Stjones1@inf.ed.ac.uk assert(!tickEvent.scheduled() || tickEvent.squashed()); 12281060SN/A 12292325SN/A // @todo: Figure out how to properly select the tid to put onto 12302325SN/A // the active threads list. 12316221Snate@binkert.org ThreadID tid = 0; 12322307SN/A 12336221Snate@binkert.org list<ThreadID>::iterator isActive = 12345314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 12352307SN/A 12362307SN/A if (isActive == activeThreads.end()) { 12372325SN/A //May Need to Re-code this if the delay variable is the delay 12382325SN/A //needed for thread to activate 12392733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 12402307SN/A tid); 12412307SN/A 12422307SN/A activeThreads.push_back(tid); 12432307SN/A } 12442307SN/A 12452325SN/A // Set all statuses to active, schedule the CPU's tick event. 12462307SN/A // @todo: Fix up statuses so this is handled properly 12476221Snate@binkert.org ThreadID size = threadContexts.size(); 12486221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 12492680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 12502680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 12511681SN/A _status = Running; 12527507Stjones1@inf.ed.ac.uk reschedule(tickEvent, nextCycle(), true); 12531681SN/A } 12541060SN/A } 12552307SN/A if (!tickEvent.scheduled()) 12565606Snate@binkert.org schedule(tickEvent, nextCycle()); 12578627SAli.Saidi@ARM.com 12588627SAli.Saidi@ARM.com lastRunningCycle = curTick(); 12591060SN/A} 12601060SN/A 12611060SN/Atemplate <class Impl> 12625595Sgblack@eecs.umich.eduTheISA::MiscReg 12636221Snate@binkert.orgFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) 12645595Sgblack@eecs.umich.edu{ 12656313Sgblack@eecs.umich.edu return this->isa[tid].readMiscRegNoEffect(misc_reg); 12665595Sgblack@eecs.umich.edu} 12675595Sgblack@eecs.umich.edu 12685595Sgblack@eecs.umich.edutemplate <class Impl> 12695595Sgblack@eecs.umich.eduTheISA::MiscReg 12706221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 12715595Sgblack@eecs.umich.edu{ 12727897Shestness@cs.utexas.edu miscRegfileReads++; 12736313Sgblack@eecs.umich.edu return this->isa[tid].readMiscReg(misc_reg, tcBase(tid)); 12745595Sgblack@eecs.umich.edu} 12755595Sgblack@eecs.umich.edu 12765595Sgblack@eecs.umich.edutemplate <class Impl> 12775595Sgblack@eecs.umich.eduvoid 12785595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 12796221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12805595Sgblack@eecs.umich.edu{ 12816313Sgblack@eecs.umich.edu this->isa[tid].setMiscRegNoEffect(misc_reg, val); 12825595Sgblack@eecs.umich.edu} 12835595Sgblack@eecs.umich.edu 12845595Sgblack@eecs.umich.edutemplate <class Impl> 12855595Sgblack@eecs.umich.eduvoid 12865595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 12876221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12885595Sgblack@eecs.umich.edu{ 12897897Shestness@cs.utexas.edu miscRegfileWrites++; 12906313Sgblack@eecs.umich.edu this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid)); 12915595Sgblack@eecs.umich.edu} 12925595Sgblack@eecs.umich.edu 12935595Sgblack@eecs.umich.edutemplate <class Impl> 12941060SN/Auint64_t 12951755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 12961060SN/A{ 12977897Shestness@cs.utexas.edu intRegfileReads++; 12981060SN/A return regFile.readIntReg(reg_idx); 12991060SN/A} 13001060SN/A 13011060SN/Atemplate <class Impl> 13022455SN/AFloatReg 13032455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 13041060SN/A{ 13057897Shestness@cs.utexas.edu fpRegfileReads++; 13062455SN/A return regFile.readFloatReg(reg_idx); 13071060SN/A} 13081060SN/A 13091060SN/Atemplate <class Impl> 13102455SN/AFloatRegBits 13112455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 13122455SN/A{ 13137897Shestness@cs.utexas.edu fpRegfileReads++; 13142455SN/A return regFile.readFloatRegBits(reg_idx); 13151060SN/A} 13161060SN/A 13171060SN/Atemplate <class Impl> 13181060SN/Avoid 13191755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 13201060SN/A{ 13217897Shestness@cs.utexas.edu intRegfileWrites++; 13221060SN/A regFile.setIntReg(reg_idx, val); 13231060SN/A} 13241060SN/A 13251060SN/Atemplate <class Impl> 13261060SN/Avoid 13272455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 13281060SN/A{ 13297897Shestness@cs.utexas.edu fpRegfileWrites++; 13302455SN/A regFile.setFloatReg(reg_idx, val); 13311060SN/A} 13321060SN/A 13331060SN/Atemplate <class Impl> 13341060SN/Avoid 13352455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 13362455SN/A{ 13377897Shestness@cs.utexas.edu fpRegfileWrites++; 13382455SN/A regFile.setFloatRegBits(reg_idx, val); 13391060SN/A} 13401060SN/A 13411060SN/Atemplate <class Impl> 13421060SN/Auint64_t 13436221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 13441060SN/A{ 13457897Shestness@cs.utexas.edu intRegfileReads++; 13462292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13472292SN/A 13482292SN/A return regFile.readIntReg(phys_reg); 13492292SN/A} 13502292SN/A 13512292SN/Atemplate <class Impl> 13522292SN/Afloat 13536314Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 13542292SN/A{ 13557897Shestness@cs.utexas.edu fpRegfileReads++; 13566032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13572307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13582292SN/A 13592669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 13602292SN/A} 13612292SN/A 13622292SN/Atemplate <class Impl> 13632292SN/Auint64_t 13646221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 13652292SN/A{ 13667897Shestness@cs.utexas.edu fpRegfileReads++; 13676032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13682307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13692292SN/A 13702669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 13711060SN/A} 13721060SN/A 13731060SN/Atemplate <class Impl> 13741060SN/Avoid 13756221Snate@binkert.orgFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 13761060SN/A{ 13777897Shestness@cs.utexas.edu intRegfileWrites++; 13782292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13792292SN/A 13802292SN/A regFile.setIntReg(phys_reg, val); 13811060SN/A} 13821060SN/A 13831060SN/Atemplate <class Impl> 13841060SN/Avoid 13856314Sgblack@eecs.umich.eduFullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 13861060SN/A{ 13877897Shestness@cs.utexas.edu fpRegfileWrites++; 13886032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13892918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13902292SN/A 13912669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 13921060SN/A} 13931060SN/A 13941060SN/Atemplate <class Impl> 13951060SN/Avoid 13966221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 13971060SN/A{ 13987897Shestness@cs.utexas.edu fpRegfileWrites++; 13996032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 14002918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 14011060SN/A 14022669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 14032292SN/A} 14042292SN/A 14052292SN/Atemplate <class Impl> 14067720Sgblack@eecs.umich.eduTheISA::PCState 14077720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 14082292SN/A{ 14097720Sgblack@eecs.umich.edu return commit.pcState(tid); 14101060SN/A} 14111060SN/A 14121060SN/Atemplate <class Impl> 14131060SN/Avoid 14147720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 14151060SN/A{ 14167720Sgblack@eecs.umich.edu commit.pcState(val, tid); 14172292SN/A} 14181060SN/A 14192292SN/Atemplate <class Impl> 14207720Sgblack@eecs.umich.eduAddr 14217720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 14224636Sgblack@eecs.umich.edu{ 14237720Sgblack@eecs.umich.edu return commit.instAddr(tid); 14244636Sgblack@eecs.umich.edu} 14254636Sgblack@eecs.umich.edu 14264636Sgblack@eecs.umich.edutemplate <class Impl> 14277720Sgblack@eecs.umich.eduAddr 14287720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 14294636Sgblack@eecs.umich.edu{ 14307720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 14314636Sgblack@eecs.umich.edu} 14324636Sgblack@eecs.umich.edu 14334636Sgblack@eecs.umich.edutemplate <class Impl> 14347720Sgblack@eecs.umich.eduMicroPC 14357720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 14362292SN/A{ 14377720Sgblack@eecs.umich.edu return commit.microPC(tid); 14384636Sgblack@eecs.umich.edu} 14394636Sgblack@eecs.umich.edu 14404636Sgblack@eecs.umich.edutemplate <class Impl> 14415595Sgblack@eecs.umich.eduvoid 14426221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 14435595Sgblack@eecs.umich.edu{ 14445595Sgblack@eecs.umich.edu this->thread[tid]->inSyscall = true; 14455595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 14465595Sgblack@eecs.umich.edu} 14475595Sgblack@eecs.umich.edu 14485595Sgblack@eecs.umich.edutemplate <class Impl> 14492292SN/Atypename FullO3CPU<Impl>::ListIt 14502292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 14512292SN/A{ 14522292SN/A instList.push_back(inst); 14531060SN/A 14542292SN/A return --(instList.end()); 14552292SN/A} 14561060SN/A 14572292SN/Atemplate <class Impl> 14582292SN/Avoid 14596221Snate@binkert.orgFullO3CPU<Impl>::instDone(ThreadID tid) 14602292SN/A{ 14612292SN/A // Keep an instruction count. 14622292SN/A thread[tid]->numInst++; 14632292SN/A thread[tid]->numInsts++; 14642292SN/A committedInsts[tid]++; 14652292SN/A totalCommittedInsts++; 14667897Shestness@cs.utexas.edu system->totalNumInsts++; 14672292SN/A // Check for instruction-count-based events. 14682292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 14697897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 14702292SN/A} 14712292SN/A 14722292SN/Atemplate <class Impl> 14732292SN/Avoid 14741755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 14751060SN/A{ 14767720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 14772292SN/A "[sn:%lli]\n", 14787720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 14791060SN/A 14802292SN/A removeInstsThisCycle = true; 14811060SN/A 14821060SN/A // Remove the front instruction. 14832292SN/A removeList.push(inst->getInstListIt()); 14841060SN/A} 14851060SN/A 14861060SN/Atemplate <class Impl> 14871060SN/Avoid 14886221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 14891060SN/A{ 14902733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 14912292SN/A " list.\n", tid); 14921060SN/A 14932292SN/A ListIt end_it; 14941060SN/A 14952292SN/A bool rob_empty = false; 14962292SN/A 14972292SN/A if (instList.empty()) { 14982292SN/A return; 14992292SN/A } else if (rob.isEmpty(/*tid*/)) { 15002733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 15012292SN/A end_it = instList.begin(); 15022292SN/A rob_empty = true; 15032292SN/A } else { 15042292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 15052733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 15062292SN/A } 15072292SN/A 15082292SN/A removeInstsThisCycle = true; 15092292SN/A 15102292SN/A ListIt inst_it = instList.end(); 15112292SN/A 15122292SN/A inst_it--; 15132292SN/A 15142292SN/A // Walk through the instruction list, removing any instructions 15152292SN/A // that were inserted after the given instruction iterator, end_it. 15162292SN/A while (inst_it != end_it) { 15172292SN/A assert(!instList.empty()); 15182292SN/A 15192292SN/A squashInstIt(inst_it, tid); 15202292SN/A 15212292SN/A inst_it--; 15222292SN/A } 15232292SN/A 15242292SN/A // If the ROB was empty, then we actually need to remove the first 15252292SN/A // instruction as well. 15262292SN/A if (rob_empty) { 15272292SN/A squashInstIt(inst_it, tid); 15282292SN/A } 15291060SN/A} 15301060SN/A 15311060SN/Atemplate <class Impl> 15321060SN/Avoid 15336221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 15341062SN/A{ 15352292SN/A assert(!instList.empty()); 15362292SN/A 15372292SN/A removeInstsThisCycle = true; 15382292SN/A 15392292SN/A ListIt inst_iter = instList.end(); 15402292SN/A 15412292SN/A inst_iter--; 15422292SN/A 15432733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 15442292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 15452292SN/A tid, seq_num, (*inst_iter)->seqNum); 15461062SN/A 15472292SN/A while ((*inst_iter)->seqNum > seq_num) { 15481062SN/A 15492292SN/A bool break_loop = (inst_iter == instList.begin()); 15501062SN/A 15512292SN/A squashInstIt(inst_iter, tid); 15521062SN/A 15532292SN/A inst_iter--; 15541062SN/A 15552292SN/A if (break_loop) 15562292SN/A break; 15572292SN/A } 15582292SN/A} 15592292SN/A 15602292SN/Atemplate <class Impl> 15612292SN/Ainline void 15626221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 15632292SN/A{ 15642292SN/A if ((*instIt)->threadNumber == tid) { 15652733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 15667720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 15672292SN/A (*instIt)->threadNumber, 15682292SN/A (*instIt)->seqNum, 15697720Sgblack@eecs.umich.edu (*instIt)->pcState()); 15701062SN/A 15711062SN/A // Mark it as squashed. 15722292SN/A (*instIt)->setSquashed(); 15732292SN/A 15742325SN/A // @todo: Formulate a consistent method for deleting 15752325SN/A // instructions from the instruction list 15762292SN/A // Remove the instruction from the list. 15772292SN/A removeList.push(instIt); 15782292SN/A } 15792292SN/A} 15802292SN/A 15812292SN/Atemplate <class Impl> 15822292SN/Avoid 15832292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 15842292SN/A{ 15852292SN/A while (!removeList.empty()) { 15862733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 15877720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 15882292SN/A (*removeList.front())->threadNumber, 15892292SN/A (*removeList.front())->seqNum, 15907720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 15912292SN/A 15922292SN/A instList.erase(removeList.front()); 15932292SN/A 15942292SN/A removeList.pop(); 15951062SN/A } 15961062SN/A 15972292SN/A removeInstsThisCycle = false; 15981062SN/A} 15992325SN/A/* 16001062SN/Atemplate <class Impl> 16011062SN/Avoid 16021755SN/AFullO3CPU<Impl>::removeAllInsts() 16031060SN/A{ 16041060SN/A instList.clear(); 16051060SN/A} 16062325SN/A*/ 16071060SN/Atemplate <class Impl> 16081060SN/Avoid 16091755SN/AFullO3CPU<Impl>::dumpInsts() 16101060SN/A{ 16111060SN/A int num = 0; 16121060SN/A 16132292SN/A ListIt inst_list_it = instList.begin(); 16142292SN/A 16152292SN/A cprintf("Dumping Instruction List\n"); 16162292SN/A 16172292SN/A while (inst_list_it != instList.end()) { 16182292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 16192292SN/A "Squashed:%i\n\n", 16207720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 16212292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 16222292SN/A (*inst_list_it)->isSquashed()); 16231060SN/A inst_list_it++; 16241060SN/A ++num; 16251060SN/A } 16261060SN/A} 16272325SN/A/* 16281060SN/Atemplate <class Impl> 16291060SN/Avoid 16301755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 16311060SN/A{ 16321060SN/A iew.wakeDependents(inst); 16331060SN/A} 16342325SN/A*/ 16352292SN/Atemplate <class Impl> 16362292SN/Avoid 16372292SN/AFullO3CPU<Impl>::wakeCPU() 16382292SN/A{ 16392325SN/A if (activityRec.active() || tickEvent.scheduled()) { 16402325SN/A DPRINTF(Activity, "CPU already running.\n"); 16412292SN/A return; 16422292SN/A } 16432292SN/A 16442325SN/A DPRINTF(Activity, "Waking up CPU\n"); 16452325SN/A 16467823Ssteve.reinhardt@amd.com idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle); 16477823Ssteve.reinhardt@amd.com numCycles += tickToCycles((curTick() - 1) - lastRunningCycle); 16482292SN/A 16495606Snate@binkert.org schedule(tickEvent, nextCycle()); 16502292SN/A} 16512292SN/A 16525807Snate@binkert.orgtemplate <class Impl> 16535807Snate@binkert.orgvoid 16545807Snate@binkert.orgFullO3CPU<Impl>::wakeup() 16555807Snate@binkert.org{ 16565807Snate@binkert.org if (this->thread[0]->status() != ThreadContext::Suspended) 16575807Snate@binkert.org return; 16585807Snate@binkert.org 16595807Snate@binkert.org this->wakeCPU(); 16605807Snate@binkert.org 16615807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 16625807Snate@binkert.org this->threadContexts[0]->activate(); 16635807Snate@binkert.org} 16645807Snate@binkert.org 16652292SN/Atemplate <class Impl> 16666221Snate@binkert.orgThreadID 16672292SN/AFullO3CPU<Impl>::getFreeTid() 16682292SN/A{ 16696221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 16706221Snate@binkert.org if (!tids[tid]) { 16716221Snate@binkert.org tids[tid] = true; 16726221Snate@binkert.org return tid; 16732292SN/A } 16742292SN/A } 16752292SN/A 16766221Snate@binkert.org return InvalidThreadID; 16772292SN/A} 16782292SN/A 16792292SN/Atemplate <class Impl> 16802292SN/Avoid 16812292SN/AFullO3CPU<Impl>::doContextSwitch() 16822292SN/A{ 16832292SN/A if (contextSwitch) { 16842292SN/A 16852292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 16862292SN/A 16876221Snate@binkert.org ThreadID size = cpuWaitList.size(); 16886221Snate@binkert.org for (ThreadID tid = 0; tid < size; tid++) { 16892292SN/A activateWhenReady(tid); 16902292SN/A } 16912292SN/A 16922292SN/A if (cpuWaitList.size() == 0) 16932292SN/A contextSwitch = true; 16942292SN/A } 16952292SN/A} 16962292SN/A 16972292SN/Atemplate <class Impl> 16982292SN/Avoid 16992292SN/AFullO3CPU<Impl>::updateThreadPriority() 17002292SN/A{ 17016221Snate@binkert.org if (activeThreads.size() > 1) { 17022292SN/A //DEFAULT TO ROUND ROBIN SCHEME 17032292SN/A //e.g. Move highest priority to end of thread list 17046221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 17052292SN/A 17062292SN/A unsigned high_thread = *list_begin; 17072292SN/A 17082292SN/A activeThreads.erase(list_begin); 17092292SN/A 17102292SN/A activeThreads.push_back(high_thread); 17112292SN/A } 17122292SN/A} 17131060SN/A 17141755SN/A// Forward declaration of FullO3CPU. 17152818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1716