cpu.cc revision 8779
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 37897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 41689SN/A * All rights reserved. 51689SN/A * 61689SN/A * Redistribution and use in source and binary forms, with or without 71689SN/A * modification, are permitted provided that the following conditions are 81689SN/A * met: redistributions of source code must retain the above copyright 91689SN/A * notice, this list of conditions and the following disclaimer; 101689SN/A * redistributions in binary form must reproduce the above copyright 111689SN/A * notice, this list of conditions and the following disclaimer in the 121689SN/A * documentation and/or other materials provided with the distribution; 131689SN/A * neither the name of the copyright holders nor the names of its 141689SN/A * contributors may be used to endorse or promote products derived from 151689SN/A * this software without specific prior written permission. 161689SN/A * 171689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 302756Sksewell@umich.edu * Korey Sewell 317897Shestness@cs.utexas.edu * Rick Strong 321689SN/A */ 331689SN/A 348779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 351858SN/A#include "config/full_system.hh" 366658Snate@binkert.org#include "config/the_isa.hh" 372733Sktlim@umich.edu#include "config/use_checker.hh" 388229Snate@binkert.org#include "cpu/o3/cpu.hh" 398229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 408229Snate@binkert.org#include "cpu/o3/thread_context.hh" 414762Snate@binkert.org#include "cpu/activity.hh" 428779Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 434762Snate@binkert.org#include "cpu/simple_thread.hh" 444762Snate@binkert.org#include "cpu/thread_context.hh" 458232Snate@binkert.org#include "debug/Activity.hh" 468232Snate@binkert.org#include "debug/O3CPU.hh" 478232Snate@binkert.org#include "debug/Quiesce.hh" 484762Snate@binkert.org#include "enums/MemoryMode.hh" 494762Snate@binkert.org#include "sim/core.hh" 508779Sgblack@eecs.umich.edu#include "sim/process.hh" 514762Snate@binkert.org#include "sim/stat_control.hh" 528460SAli.Saidi@ARM.com#include "sim/system.hh" 534762Snate@binkert.org 542794Sktlim@umich.edu#if USE_CHECKER 552794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 562794Sktlim@umich.edu#endif 572794Sktlim@umich.edu 585702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 595702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 608232Snate@binkert.org#include "debug/Activity.hh" 615702Ssaidi@eecs.umich.edu#endif 625702Ssaidi@eecs.umich.edu 635529Snate@binkert.orgclass BaseCPUParams; 645529Snate@binkert.org 652669Sktlim@umich.eduusing namespace TheISA; 666221Snate@binkert.orgusing namespace std; 671060SN/A 685529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 695712Shsul@eecs.umich.edu : BaseCPU(params) 701060SN/A{ 711060SN/A} 721060SN/A 732292SN/Avoid 742733Sktlim@umich.eduBaseO3CPU::regStats() 752292SN/A{ 762292SN/A BaseCPU::regStats(); 772292SN/A} 782292SN/A 791060SN/Atemplate <class Impl> 801755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 815606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 821060SN/A{ 831060SN/A} 841060SN/A 851060SN/Atemplate <class Impl> 861060SN/Avoid 871755SN/AFullO3CPU<Impl>::TickEvent::process() 881060SN/A{ 891060SN/A cpu->tick(); 901060SN/A} 911060SN/A 921060SN/Atemplate <class Impl> 931060SN/Aconst char * 945336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 951060SN/A{ 964873Sstever@eecs.umich.edu return "FullO3CPU tick"; 971060SN/A} 981060SN/A 991060SN/Atemplate <class Impl> 1002829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 1015606Snate@binkert.org : Event(CPU_Switch_Pri) 1022829Sksewell@umich.edu{ 1032829Sksewell@umich.edu} 1042829Sksewell@umich.edu 1052829Sksewell@umich.edutemplate <class Impl> 1062829Sksewell@umich.eduvoid 1072829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 1082829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1092829Sksewell@umich.edu{ 1102829Sksewell@umich.edu tid = thread_num; 1112829Sksewell@umich.edu cpu = thread_cpu; 1122829Sksewell@umich.edu} 1132829Sksewell@umich.edu 1142829Sksewell@umich.edutemplate <class Impl> 1152829Sksewell@umich.eduvoid 1162829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1172829Sksewell@umich.edu{ 1182829Sksewell@umich.edu cpu->activateThread(tid); 1192829Sksewell@umich.edu} 1202829Sksewell@umich.edu 1212829Sksewell@umich.edutemplate <class Impl> 1222829Sksewell@umich.educonst char * 1235336Shines@cs.fsu.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1242829Sksewell@umich.edu{ 1254873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1262829Sksewell@umich.edu} 1272829Sksewell@umich.edu 1282829Sksewell@umich.edutemplate <class Impl> 1292875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1305606Snate@binkert.org : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1312875Sksewell@umich.edu{ 1322875Sksewell@umich.edu} 1332875Sksewell@umich.edu 1342875Sksewell@umich.edutemplate <class Impl> 1352875Sksewell@umich.eduvoid 1362875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1373859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1382875Sksewell@umich.edu{ 1392875Sksewell@umich.edu tid = thread_num; 1402875Sksewell@umich.edu cpu = thread_cpu; 1413859Sbinkertn@umich.edu remove = false; 1422875Sksewell@umich.edu} 1432875Sksewell@umich.edu 1442875Sksewell@umich.edutemplate <class Impl> 1452875Sksewell@umich.eduvoid 1462875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1472875Sksewell@umich.edu{ 1482875Sksewell@umich.edu cpu->deactivateThread(tid); 1493221Sktlim@umich.edu if (remove) 1503221Sktlim@umich.edu cpu->removeThread(tid); 1512875Sksewell@umich.edu} 1522875Sksewell@umich.edu 1532875Sksewell@umich.edutemplate <class Impl> 1542875Sksewell@umich.educonst char * 1555336Shines@cs.fsu.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 1562875Sksewell@umich.edu{ 1574873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 1582875Sksewell@umich.edu} 1592875Sksewell@umich.edu 1602875Sksewell@umich.edutemplate <class Impl> 1615595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 1622733Sktlim@umich.edu : BaseO3CPU(params), 1633781Sgblack@eecs.umich.edu itb(params->itb), 1643781Sgblack@eecs.umich.edu dtb(params->dtb), 1651060SN/A tickEvent(this), 1665737Scws3k@cs.virginia.edu#ifndef NDEBUG 1675737Scws3k@cs.virginia.edu instcount(0), 1685737Scws3k@cs.virginia.edu#endif 1692292SN/A removeInstsThisCycle(false), 1705595Sgblack@eecs.umich.edu fetch(this, params), 1715595Sgblack@eecs.umich.edu decode(this, params), 1725595Sgblack@eecs.umich.edu rename(this, params), 1735595Sgblack@eecs.umich.edu iew(this, params), 1745595Sgblack@eecs.umich.edu commit(this, params), 1751060SN/A 1765595Sgblack@eecs.umich.edu regFile(this, params->numPhysIntRegs, 1774329Sktlim@umich.edu params->numPhysFloatRegs), 1781060SN/A 1795529Snate@binkert.org freeList(params->numThreads, 1802292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1812292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1821060SN/A 1835595Sgblack@eecs.umich.edu rob(this, 1844329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 1852292SN/A params->smtROBPolicy, params->smtROBThreshold, 1865529Snate@binkert.org params->numThreads), 1871060SN/A 1885529Snate@binkert.org scoreboard(params->numThreads, 1892292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1902292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1916221Snate@binkert.org TheISA::NumMiscRegs * numThreads, 1922292SN/A TheISA::ZeroReg), 1931060SN/A 1942873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1952873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1962873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1972873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1982873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1995804Snate@binkert.org activityRec(name(), NumStages, 2002873Sktlim@umich.edu params->backComSize + params->forwardComSize, 2012873Sktlim@umich.edu params->activity), 2021060SN/A 2031060SN/A globalSeqNum(1), 2042292SN/A system(params->system), 2052843Sktlim@umich.edu drainCount(0), 2066221Snate@binkert.org deferRegistration(params->defer_registration) 2071060SN/A{ 2083221Sktlim@umich.edu if (!deferRegistration) { 2093221Sktlim@umich.edu _status = Running; 2103221Sktlim@umich.edu } else { 2113221Sktlim@umich.edu _status = Idle; 2123221Sktlim@umich.edu } 2131681SN/A 2144598Sbinkertn@umich.edu#if USE_CHECKER 2152794Sktlim@umich.edu if (params->checker) { 2162316SN/A BaseCPU *temp_checker = params->checker; 2172316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2182316SN/A#if FULL_SYSTEM 2192316SN/A checker->setSystem(params->system); 2202316SN/A#endif 2214598Sbinkertn@umich.edu } else { 2224598Sbinkertn@umich.edu checker = NULL; 2234598Sbinkertn@umich.edu } 2242794Sktlim@umich.edu#endif // USE_CHECKER 2252316SN/A 2261858SN/A#if !FULL_SYSTEM 2276221Snate@binkert.org thread.resize(numThreads); 2286221Snate@binkert.org tids.resize(numThreads); 2291681SN/A#endif 2301681SN/A 2312325SN/A // The stages also need their CPU pointer setup. However this 2322325SN/A // must be done at the upper level CPU because they have pointers 2332325SN/A // to the upper level CPU, and not this FullO3CPU. 2341060SN/A 2352292SN/A // Set up Pointers to the activeThreads list for each stage 2362292SN/A fetch.setActiveThreads(&activeThreads); 2372292SN/A decode.setActiveThreads(&activeThreads); 2382292SN/A rename.setActiveThreads(&activeThreads); 2392292SN/A iew.setActiveThreads(&activeThreads); 2402292SN/A commit.setActiveThreads(&activeThreads); 2411060SN/A 2421060SN/A // Give each of the stages the time buffer they will use. 2431060SN/A fetch.setTimeBuffer(&timeBuffer); 2441060SN/A decode.setTimeBuffer(&timeBuffer); 2451060SN/A rename.setTimeBuffer(&timeBuffer); 2461060SN/A iew.setTimeBuffer(&timeBuffer); 2471060SN/A commit.setTimeBuffer(&timeBuffer); 2481060SN/A 2491060SN/A // Also setup each of the stages' queues. 2501060SN/A fetch.setFetchQueue(&fetchQueue); 2511060SN/A decode.setFetchQueue(&fetchQueue); 2522292SN/A commit.setFetchQueue(&fetchQueue); 2531060SN/A decode.setDecodeQueue(&decodeQueue); 2541060SN/A rename.setDecodeQueue(&decodeQueue); 2551060SN/A rename.setRenameQueue(&renameQueue); 2561060SN/A iew.setRenameQueue(&renameQueue); 2571060SN/A iew.setIEWQueue(&iewQueue); 2581060SN/A commit.setIEWQueue(&iewQueue); 2591060SN/A commit.setRenameQueue(&renameQueue); 2601060SN/A 2612292SN/A commit.setIEWStage(&iew); 2622292SN/A rename.setIEWStage(&iew); 2632292SN/A rename.setCommitStage(&commit); 2642292SN/A 2652292SN/A#if !FULL_SYSTEM 2666221Snate@binkert.org ThreadID active_threads = params->workload.size(); 2672831Sksewell@umich.edu 2682831Sksewell@umich.edu if (active_threads > Impl::MaxThreads) { 2692831Sksewell@umich.edu panic("Workload Size too large. Increase the 'MaxThreads'" 2702831Sksewell@umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2712831Sksewell@umich.edu "edit your workload size."); 2722831Sksewell@umich.edu } 2732292SN/A#else 2746221Snate@binkert.org ThreadID active_threads = 1; 2752292SN/A#endif 2762292SN/A 2772316SN/A //Make Sure That this a Valid Architeture 2782292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2792292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2802292SN/A 2812292SN/A rename.setScoreboard(&scoreboard); 2822292SN/A iew.setScoreboard(&scoreboard); 2832292SN/A 2841060SN/A // Setup the rename map for whichever stages need it. 2852292SN/A PhysRegIndex lreg_idx = 0; 2862292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2871060SN/A 2886221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2892307SN/A bool bindRegs = (tid <= active_threads - 1); 2902292SN/A 2912292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2922292SN/A params->numPhysIntRegs, 2932325SN/A lreg_idx, //Index for Logical. Regs 2942292SN/A 2952292SN/A TheISA::NumFloatRegs, 2962292SN/A params->numPhysFloatRegs, 2972325SN/A freg_idx, //Index for Float Regs 2982292SN/A 2992292SN/A TheISA::NumMiscRegs, 3002292SN/A 3012292SN/A TheISA::ZeroReg, 3022292SN/A TheISA::ZeroReg, 3032292SN/A 3042292SN/A tid, 3052292SN/A false); 3062292SN/A 3072292SN/A renameMap[tid].init(TheISA::NumIntRegs, 3082292SN/A params->numPhysIntRegs, 3092325SN/A lreg_idx, //Index for Logical. Regs 3102292SN/A 3112292SN/A TheISA::NumFloatRegs, 3122292SN/A params->numPhysFloatRegs, 3132325SN/A freg_idx, //Index for Float Regs 3142292SN/A 3152292SN/A TheISA::NumMiscRegs, 3162292SN/A 3172292SN/A TheISA::ZeroReg, 3182292SN/A TheISA::ZeroReg, 3192292SN/A 3202292SN/A tid, 3212292SN/A bindRegs); 3223221Sktlim@umich.edu 3233221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3243221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3252292SN/A } 3262292SN/A 3272292SN/A rename.setRenameMap(renameMap); 3282292SN/A commit.setRenameMap(commitRenameMap); 3292292SN/A 3302292SN/A // Give renameMap & rename stage access to the freeList; 3316221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3326221Snate@binkert.org renameMap[tid].setFreeList(&freeList); 3331060SN/A rename.setFreeList(&freeList); 3342292SN/A 3351060SN/A // Setup the ROB for whichever stages need it. 3361060SN/A commit.setROB(&rob); 3372292SN/A 3387823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 3392292SN/A 3402829Sksewell@umich.edu lastActivatedCycle = -1; 3416221Snate@binkert.org#if 0 3423093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3436221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3446221Snate@binkert.org globalSeqNum[tid] = 1; 3456221Snate@binkert.org#endif 3463093Sksewell@umich.edu 3472292SN/A contextSwitch = false; 3485595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3495595Sgblack@eecs.umich.edu 3505595Sgblack@eecs.umich.edu // Setup any thread state. 3515595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 3525595Sgblack@eecs.umich.edu 3536221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 3545595Sgblack@eecs.umich.edu#if FULL_SYSTEM 3555595Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 3565595Sgblack@eecs.umich.edu assert(this->numThreads == 1); 3578766Sgblack@eecs.umich.edu this->thread[tid] = new Thread(this, 0, NULL); 3585595Sgblack@eecs.umich.edu#else 3596221Snate@binkert.org if (tid < params->workload.size()) { 3605595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 3616221Snate@binkert.org tid, this->thread[tid]); 3626221Snate@binkert.org this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3635595Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3646331Sgblack@eecs.umich.edu tid, params->workload[tid]); 3655595Sgblack@eecs.umich.edu 3666221Snate@binkert.org //usedTids[tid] = true; 3676221Snate@binkert.org //threadMap[tid] = tid; 3685595Sgblack@eecs.umich.edu } else { 3695595Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 3705595Sgblack@eecs.umich.edu //when scheduling threads to CPU 3715595Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 3725595Sgblack@eecs.umich.edu 3736221Snate@binkert.org this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3745595Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3756331Sgblack@eecs.umich.edu tid, dummy_proc); 3766221Snate@binkert.org //usedTids[tid] = false; 3775595Sgblack@eecs.umich.edu } 3785595Sgblack@eecs.umich.edu#endif // !FULL_SYSTEM 3795595Sgblack@eecs.umich.edu 3805595Sgblack@eecs.umich.edu ThreadContext *tc; 3815595Sgblack@eecs.umich.edu 3825595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 3835595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 3845595Sgblack@eecs.umich.edu 3855595Sgblack@eecs.umich.edu tc = o3_tc; 3865595Sgblack@eecs.umich.edu 3875595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 3885595Sgblack@eecs.umich.edu // CheckerThreadContext. 3895595Sgblack@eecs.umich.edu#if USE_CHECKER 3905595Sgblack@eecs.umich.edu if (params->checker) { 3915595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 3925595Sgblack@eecs.umich.edu o3_tc, this->checker); 3935595Sgblack@eecs.umich.edu } 3945595Sgblack@eecs.umich.edu#endif 3955595Sgblack@eecs.umich.edu 3965595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 3975595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 3986221Snate@binkert.org o3_tc->thread = this->thread[tid]; 3995595Sgblack@eecs.umich.edu 4005595Sgblack@eecs.umich.edu#if FULL_SYSTEM 4015595Sgblack@eecs.umich.edu // Setup quiesce event. 4026221Snate@binkert.org this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 4035595Sgblack@eecs.umich.edu#endif 4045595Sgblack@eecs.umich.edu // Give the thread the TC. 4056221Snate@binkert.org this->thread[tid]->tc = tc; 4065595Sgblack@eecs.umich.edu 4075595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4085595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4095595Sgblack@eecs.umich.edu } 4105595Sgblack@eecs.umich.edu 4116221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4126221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4135595Sgblack@eecs.umich.edu 4145595Sgblack@eecs.umich.edu lockAddr = 0; 4155595Sgblack@eecs.umich.edu lockFlag = false; 4161060SN/A} 4171060SN/A 4181060SN/Atemplate <class Impl> 4191755SN/AFullO3CPU<Impl>::~FullO3CPU() 4201060SN/A{ 4211060SN/A} 4221060SN/A 4231060SN/Atemplate <class Impl> 4241060SN/Avoid 4255595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4261062SN/A{ 4272733Sktlim@umich.edu BaseO3CPU::regStats(); 4282292SN/A 4292733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4302292SN/A timesIdled 4312292SN/A .name(name() + ".timesIdled") 4322292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4332292SN/A " unscheduled itself") 4342292SN/A .prereq(timesIdled); 4352292SN/A 4362292SN/A idleCycles 4372292SN/A .name(name() + ".idleCycles") 4382292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4392292SN/A "to idling") 4402292SN/A .prereq(idleCycles); 4412292SN/A 4422292SN/A // Number of Instructions simulated 4432292SN/A // -------------------------------- 4442292SN/A // Should probably be in Base CPU but need templated 4452292SN/A // MaxThreads so put in here instead 4462292SN/A committedInsts 4472292SN/A .init(numThreads) 4482292SN/A .name(name() + ".committedInsts") 4492292SN/A .desc("Number of Instructions Simulated"); 4502292SN/A 4512292SN/A totalCommittedInsts 4522292SN/A .name(name() + ".committedInsts_total") 4532292SN/A .desc("Number of Instructions Simulated"); 4542292SN/A 4552292SN/A cpi 4562292SN/A .name(name() + ".cpi") 4572292SN/A .desc("CPI: Cycles Per Instruction") 4582292SN/A .precision(6); 4594392Sktlim@umich.edu cpi = numCycles / committedInsts; 4602292SN/A 4612292SN/A totalCpi 4622292SN/A .name(name() + ".cpi_total") 4632292SN/A .desc("CPI: Total CPI of All Threads") 4642292SN/A .precision(6); 4654392Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 4662292SN/A 4672292SN/A ipc 4682292SN/A .name(name() + ".ipc") 4692292SN/A .desc("IPC: Instructions Per Cycle") 4702292SN/A .precision(6); 4714392Sktlim@umich.edu ipc = committedInsts / numCycles; 4722292SN/A 4732292SN/A totalIpc 4742292SN/A .name(name() + ".ipc_total") 4752292SN/A .desc("IPC: Total IPC of All Threads") 4762292SN/A .precision(6); 4774392Sktlim@umich.edu totalIpc = totalCommittedInsts / numCycles; 4782292SN/A 4795595Sgblack@eecs.umich.edu this->fetch.regStats(); 4805595Sgblack@eecs.umich.edu this->decode.regStats(); 4815595Sgblack@eecs.umich.edu this->rename.regStats(); 4825595Sgblack@eecs.umich.edu this->iew.regStats(); 4835595Sgblack@eecs.umich.edu this->commit.regStats(); 4847897Shestness@cs.utexas.edu this->rob.regStats(); 4857897Shestness@cs.utexas.edu 4867897Shestness@cs.utexas.edu intRegfileReads 4877897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 4887897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 4897897Shestness@cs.utexas.edu .prereq(intRegfileReads); 4907897Shestness@cs.utexas.edu 4917897Shestness@cs.utexas.edu intRegfileWrites 4927897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 4937897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 4947897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 4957897Shestness@cs.utexas.edu 4967897Shestness@cs.utexas.edu fpRegfileReads 4977897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 4987897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 4997897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 5007897Shestness@cs.utexas.edu 5017897Shestness@cs.utexas.edu fpRegfileWrites 5027897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 5037897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 5047897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 5057897Shestness@cs.utexas.edu 5067897Shestness@cs.utexas.edu miscRegfileReads 5077897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5087897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5097897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5107897Shestness@cs.utexas.edu 5117897Shestness@cs.utexas.edu miscRegfileWrites 5127897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5137897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5147897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5151062SN/A} 5161062SN/A 5171062SN/Atemplate <class Impl> 5182871Sktlim@umich.eduPort * 5192871Sktlim@umich.eduFullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 5202871Sktlim@umich.edu{ 5212871Sktlim@umich.edu if (if_name == "dcache_port") 5222871Sktlim@umich.edu return iew.getDcachePort(); 5232871Sktlim@umich.edu else if (if_name == "icache_port") 5242871Sktlim@umich.edu return fetch.getIcachePort(); 5252871Sktlim@umich.edu else 5262871Sktlim@umich.edu panic("No Such Port\n"); 5272871Sktlim@umich.edu} 5282871Sktlim@umich.edu 5292871Sktlim@umich.edutemplate <class Impl> 5301062SN/Avoid 5311755SN/AFullO3CPU<Impl>::tick() 5321060SN/A{ 5332733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5341060SN/A 5352292SN/A ++numCycles; 5362292SN/A 5372325SN/A// activity = false; 5382292SN/A 5392292SN/A //Tick each of the stages 5401060SN/A fetch.tick(); 5411060SN/A 5421060SN/A decode.tick(); 5431060SN/A 5441060SN/A rename.tick(); 5451060SN/A 5461060SN/A iew.tick(); 5471060SN/A 5481060SN/A commit.tick(); 5491060SN/A 5502292SN/A#if !FULL_SYSTEM 5512292SN/A doContextSwitch(); 5522292SN/A#endif 5532292SN/A 5542292SN/A // Now advance the time buffers 5551060SN/A timeBuffer.advance(); 5561060SN/A 5571060SN/A fetchQueue.advance(); 5581060SN/A decodeQueue.advance(); 5591060SN/A renameQueue.advance(); 5601060SN/A iewQueue.advance(); 5611060SN/A 5622325SN/A activityRec.advance(); 5632292SN/A 5642292SN/A if (removeInstsThisCycle) { 5652292SN/A cleanUpRemovedInsts(); 5662292SN/A } 5672292SN/A 5682325SN/A if (!tickEvent.scheduled()) { 5692867Sktlim@umich.edu if (_status == SwitchedOut || 5702905Sktlim@umich.edu getState() == SimObject::Drained) { 5713226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 5722325SN/A // increment stat 5737823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 5743221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 5753226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 5767823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 5772325SN/A timesIdled++; 5782325SN/A } else { 5797823Ssteve.reinhardt@amd.com schedule(tickEvent, nextCycle(curTick() + ticks(1))); 5803226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 5812325SN/A } 5822292SN/A } 5832292SN/A 5842292SN/A#if !FULL_SYSTEM 5852292SN/A updateThreadPriority(); 5862292SN/A#endif 5871060SN/A} 5881060SN/A 5891060SN/Atemplate <class Impl> 5901060SN/Avoid 5911755SN/AFullO3CPU<Impl>::init() 5921060SN/A{ 5935714Shsul@eecs.umich.edu BaseCPU::init(); 5941060SN/A 5952292SN/A // Set inSyscall so that the CPU doesn't squash when initially 5962292SN/A // setting up registers. 5976221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 5986221Snate@binkert.org thread[tid]->inSyscall = true; 5992292SN/A 6006034Ssteve.reinhardt@amd.com#if FULL_SYSTEM 6016221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 6022680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 6036034Ssteve.reinhardt@amd.com TheISA::initCPU(src_tc, src_tc->contextId()); 6046034Ssteve.reinhardt@amd.com } 6051681SN/A#endif 6062292SN/A 6072292SN/A // Clear inSyscall. 6086221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6096221Snate@binkert.org thread[tid]->inSyscall = false; 6102292SN/A 6112316SN/A // Initialize stages. 6122292SN/A fetch.initStage(); 6132292SN/A iew.initStage(); 6142292SN/A rename.initStage(); 6152292SN/A commit.initStage(); 6162292SN/A 6172292SN/A commit.setThreads(thread); 6182292SN/A} 6192292SN/A 6202292SN/Atemplate <class Impl> 6212292SN/Avoid 6226221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 6232875Sksewell@umich.edu{ 6246221Snate@binkert.org list<ThreadID>::iterator isActive = 6255314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6262875Sksewell@umich.edu 6273226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6283226Sktlim@umich.edu 6292875Sksewell@umich.edu if (isActive == activeThreads.end()) { 6302875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6312875Sksewell@umich.edu tid); 6322875Sksewell@umich.edu 6332875Sksewell@umich.edu activeThreads.push_back(tid); 6342875Sksewell@umich.edu } 6352875Sksewell@umich.edu} 6362875Sksewell@umich.edu 6372875Sksewell@umich.edutemplate <class Impl> 6382875Sksewell@umich.eduvoid 6396221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 6402875Sksewell@umich.edu{ 6412875Sksewell@umich.edu //Remove From Active List, if Active 6426221Snate@binkert.org list<ThreadID>::iterator thread_it = 6435314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6442875Sksewell@umich.edu 6453226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 6463226Sktlim@umich.edu 6472875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 6482875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6492875Sksewell@umich.edu tid); 6502875Sksewell@umich.edu activeThreads.erase(thread_it); 6512875Sksewell@umich.edu } 6522875Sksewell@umich.edu} 6532875Sksewell@umich.edu 6542875Sksewell@umich.edutemplate <class Impl> 6556221Snate@binkert.orgCounter 6566221Snate@binkert.orgFullO3CPU<Impl>::totalInstructions() const 6576221Snate@binkert.org{ 6586221Snate@binkert.org Counter total(0); 6596221Snate@binkert.org 6606221Snate@binkert.org ThreadID size = thread.size(); 6616221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 6626221Snate@binkert.org total += thread[i]->numInst; 6636221Snate@binkert.org 6646221Snate@binkert.org return total; 6656221Snate@binkert.org} 6666221Snate@binkert.org 6676221Snate@binkert.orgtemplate <class Impl> 6682875Sksewell@umich.eduvoid 6696221Snate@binkert.orgFullO3CPU<Impl>::activateContext(ThreadID tid, int delay) 6702875Sksewell@umich.edu{ 6712875Sksewell@umich.edu // Needs to set each stage to running as well. 6722875Sksewell@umich.edu if (delay){ 6732875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 6747823Ssteve.reinhardt@amd.com "on cycle %d\n", tid, curTick() + ticks(delay)); 6752875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 6762875Sksewell@umich.edu } else { 6772875Sksewell@umich.edu activateThread(tid); 6782875Sksewell@umich.edu } 6792875Sksewell@umich.edu 6807823Ssteve.reinhardt@amd.com if (lastActivatedCycle < curTick()) { 6812875Sksewell@umich.edu scheduleTickEvent(delay); 6822875Sksewell@umich.edu 6832875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 6842875Sksewell@umich.edu // deschedule itself. 6852875Sksewell@umich.edu activityRec.activity(); 6862875Sksewell@umich.edu fetch.wakeFromQuiesce(); 6872875Sksewell@umich.edu 6887823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 6892875Sksewell@umich.edu 6902875Sksewell@umich.edu _status = Running; 6912875Sksewell@umich.edu } 6922875Sksewell@umich.edu} 6932875Sksewell@umich.edu 6942875Sksewell@umich.edutemplate <class Impl> 6953221Sktlim@umich.edubool 6966221Snate@binkert.orgFullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay) 6972875Sksewell@umich.edu{ 6982875Sksewell@umich.edu // Schedule removal of thread data from CPU 6992875Sksewell@umich.edu if (delay){ 7002875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 7017823Ssteve.reinhardt@amd.com "on cycle %d\n", tid, curTick() + ticks(delay)); 7023221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 7033221Sktlim@umich.edu return false; 7042875Sksewell@umich.edu } else { 7052875Sksewell@umich.edu deactivateThread(tid); 7063221Sktlim@umich.edu if (remove) 7073221Sktlim@umich.edu removeThread(tid); 7083221Sktlim@umich.edu return true; 7092875Sksewell@umich.edu } 7102875Sksewell@umich.edu} 7112875Sksewell@umich.edu 7122875Sksewell@umich.edutemplate <class Impl> 7132875Sksewell@umich.eduvoid 7146221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 7152875Sksewell@umich.edu{ 7162875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 7173221Sktlim@umich.edu bool deallocated = deallocateContext(tid, false, 1); 7183221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 7195570Snate@binkert.org if ((activeThreads.size() == 1 && !deallocated) || 7203859Sbinkertn@umich.edu activeThreads.size() == 0) 7212910Sksewell@umich.edu unscheduleTickEvent(); 7222875Sksewell@umich.edu _status = Idle; 7232875Sksewell@umich.edu} 7242875Sksewell@umich.edu 7252875Sksewell@umich.edutemplate <class Impl> 7262875Sksewell@umich.eduvoid 7276221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 7282875Sksewell@umich.edu{ 7292910Sksewell@umich.edu //For now, this is the same as deallocate 7302910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 7313221Sktlim@umich.edu deallocateContext(tid, true, 1); 7322875Sksewell@umich.edu} 7332875Sksewell@umich.edu 7342875Sksewell@umich.edutemplate <class Impl> 7352875Sksewell@umich.eduvoid 7366221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 7372292SN/A{ 7382847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 7392292SN/A // Will change now that the PC and thread state is internal to the CPU 7402683Sktlim@umich.edu // and not in the ThreadContext. 7412292SN/A#if FULL_SYSTEM 7422680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 7432292SN/A#else 7442847Sksewell@umich.edu ThreadContext *src_tc = tcBase(tid); 7452292SN/A#endif 7462292SN/A 7472292SN/A //Bind Int Regs to Rename Map 7482292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7492292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 7502292SN/A 7512292SN/A renameMap[tid].setEntry(ireg,phys_reg); 7522292SN/A scoreboard.setReg(phys_reg); 7532292SN/A } 7542292SN/A 7552292SN/A //Bind Float Regs to Rename Map 7562292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 7572292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 7582292SN/A 7592292SN/A renameMap[tid].setEntry(freg,phys_reg); 7602292SN/A scoreboard.setReg(phys_reg); 7612292SN/A } 7622292SN/A 7632292SN/A //Copy Thread Data Into RegFile 7642847Sksewell@umich.edu //this->copyFromTC(tid); 7652292SN/A 7662847Sksewell@umich.edu //Set PC/NPC/NNPC 7677720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 7682292SN/A 7692680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 7702292SN/A 7712292SN/A activateContext(tid,1); 7722292SN/A 7732292SN/A //Reset ROB/IQ/LSQ Entries 7742292SN/A commit.rob->resetEntries(); 7752292SN/A iew.resetEntries(); 7762292SN/A} 7772292SN/A 7782292SN/Atemplate <class Impl> 7792292SN/Avoid 7806221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 7812292SN/A{ 7822877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 7832847Sksewell@umich.edu 7842847Sksewell@umich.edu // Copy Thread Data From RegFile 7852847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 7865364Sksewell@umich.edu // this->copyToTC(tid); 7875364Sksewell@umich.edu 7885364Sksewell@umich.edu 7895364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 7905364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 7915364Sksewell@umich.edu // in SMT workloads. 7922847Sksewell@umich.edu 7932847Sksewell@umich.edu // Unbind Int Regs from Rename Map 7942292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7952292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 7962292SN/A 7972292SN/A scoreboard.unsetReg(phys_reg); 7982292SN/A freeList.addReg(phys_reg); 7992292SN/A } 8002292SN/A 8012847Sksewell@umich.edu // Unbind Float Regs from Rename Map 8025362Sksewell@umich.edu for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 8032292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 8042292SN/A 8052292SN/A scoreboard.unsetReg(phys_reg); 8062292SN/A freeList.addReg(phys_reg); 8072292SN/A } 8082292SN/A 8092847Sksewell@umich.edu // Squash Throughout Pipeline 8108138SAli.Saidi@ARM.com DynInstPtr inst = commit.rob->readHeadInst(tid); 8118138SAli.Saidi@ARM.com InstSeqNum squash_seq_num = inst->seqNum; 8128138SAli.Saidi@ARM.com fetch.squash(0, squash_seq_num, inst, tid); 8132292SN/A decode.squash(tid); 8142935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 8152875Sksewell@umich.edu iew.squash(tid); 8165363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 8172935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 8182292SN/A 8195362Sksewell@umich.edu 8205362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 8212292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 8222292SN/A 8232847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 8243229Sktlim@umich.edu 8253229Sktlim@umich.edu // Commented out for now. This should be possible to do by 8263229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 8273229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 8283229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 8293229Sktlim@umich.edu/* 8302292SN/A if (activeThreads.size() >= 1) { 8312292SN/A commit.rob->resetEntries(); 8322292SN/A iew.resetEntries(); 8332292SN/A } 8343229Sktlim@umich.edu*/ 8352292SN/A} 8362292SN/A 8372292SN/A 8382292SN/Atemplate <class Impl> 8392292SN/Avoid 8406221Snate@binkert.orgFullO3CPU<Impl>::activateWhenReady(ThreadID tid) 8412292SN/A{ 8422733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 8432292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 8442292SN/A tid); 8452292SN/A 8462292SN/A bool ready = true; 8472292SN/A 8482292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 8492733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8502292SN/A "Phys. Int. Regs.\n", 8512292SN/A tid); 8522292SN/A ready = false; 8532292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 8542733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8552292SN/A "Phys. Float. Regs.\n", 8562292SN/A tid); 8572292SN/A ready = false; 8582292SN/A } else if (commit.rob->numFreeEntries() >= 8592292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 8602733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8612292SN/A "ROB entries.\n", 8622292SN/A tid); 8632292SN/A ready = false; 8642292SN/A } else if (iew.instQueue.numFreeEntries() >= 8652292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 8662733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8672292SN/A "IQ entries.\n", 8682292SN/A tid); 8692292SN/A ready = false; 8702292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 8712292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 8722733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8732292SN/A "LSQ entries.\n", 8742292SN/A tid); 8752292SN/A ready = false; 8762292SN/A } 8772292SN/A 8782292SN/A if (ready) { 8792292SN/A insertThread(tid); 8802292SN/A 8812292SN/A contextSwitch = false; 8822292SN/A 8832292SN/A cpuWaitList.remove(tid); 8842292SN/A } else { 8852292SN/A suspendContext(tid); 8862292SN/A 8872292SN/A //blocks fetch 8882292SN/A contextSwitch = true; 8892292SN/A 8902875Sksewell@umich.edu //@todo: dont always add to waitlist 8912292SN/A //do waitlist 8922292SN/A cpuWaitList.push_back(tid); 8931060SN/A } 8941060SN/A} 8951060SN/A 8964192Sktlim@umich.edutemplate <class Impl> 8975595Sgblack@eecs.umich.eduFault 8986221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 8995702Ssaidi@eecs.umich.edu{ 9005702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9015702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 9025702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 9035702Ssaidi@eecs.umich.edu 9045702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 9055702Ssaidi@eecs.umich.edu 9065702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 9075702Ssaidi@eecs.umich.edu#endif 9085702Ssaidi@eecs.umich.edu return NoFault; 9095702Ssaidi@eecs.umich.edu} 9105702Ssaidi@eecs.umich.edu 9115702Ssaidi@eecs.umich.edutemplate <class Impl> 9125702Ssaidi@eecs.umich.edubool 9136221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 9145702Ssaidi@eecs.umich.edu{ 9155702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9165702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 9175702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 9185702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 9195702Ssaidi@eecs.umich.edu 9205702Ssaidi@eecs.umich.edu switch (palFunc) { 9215702Ssaidi@eecs.umich.edu case PAL::halt: 9225702Ssaidi@eecs.umich.edu halt(); 9235702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 9245702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 9255702Ssaidi@eecs.umich.edu break; 9265702Ssaidi@eecs.umich.edu 9275702Ssaidi@eecs.umich.edu case PAL::bpt: 9285702Ssaidi@eecs.umich.edu case PAL::bugchk: 9295702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 9305702Ssaidi@eecs.umich.edu return false; 9315702Ssaidi@eecs.umich.edu break; 9325702Ssaidi@eecs.umich.edu } 9335702Ssaidi@eecs.umich.edu#endif 9345702Ssaidi@eecs.umich.edu return true; 9355702Ssaidi@eecs.umich.edu} 9365702Ssaidi@eecs.umich.edu 9375702Ssaidi@eecs.umich.edutemplate <class Impl> 9385702Ssaidi@eecs.umich.eduFault 9395595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 9405595Sgblack@eecs.umich.edu{ 9415595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 9425647Sgblack@eecs.umich.edu return this->interrupts->getInterrupt(this->threadContexts[0]); 9435595Sgblack@eecs.umich.edu} 9445595Sgblack@eecs.umich.edu 9455595Sgblack@eecs.umich.edutemplate <class Impl> 9465595Sgblack@eecs.umich.eduvoid 9475595Sgblack@eecs.umich.eduFullO3CPU<Impl>::processInterrupts(Fault interrupt) 9485595Sgblack@eecs.umich.edu{ 9495595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 9505595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 9515595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 9525595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 9535595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 9545595Sgblack@eecs.umich.edu 9555595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 9565647Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 9575595Sgblack@eecs.umich.edu 9585595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 9597684Sgblack@eecs.umich.edu this->trap(interrupt, 0, NULL); 9605595Sgblack@eecs.umich.edu} 9615595Sgblack@eecs.umich.edu 9625595Sgblack@eecs.umich.edutemplate <class Impl> 9635595Sgblack@eecs.umich.eduvoid 9644192Sktlim@umich.eduFullO3CPU<Impl>::updateMemPorts() 9654192Sktlim@umich.edu{ 9664192Sktlim@umich.edu // Update all ThreadContext's memory ports (Functional/Virtual 9674192Sktlim@umich.edu // Ports) 9686221Snate@binkert.org ThreadID size = thread.size(); 9696221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) 9705497Ssaidi@eecs.umich.edu thread[i]->connectMemPorts(thread[i]->getTC()); 9714192Sktlim@umich.edu} 9724192Sktlim@umich.edu 9731060SN/Atemplate <class Impl> 9742852Sktlim@umich.eduvoid 9757684Sgblack@eecs.umich.eduFullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst) 9765595Sgblack@eecs.umich.edu{ 9775595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 9787684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 9795595Sgblack@eecs.umich.edu} 9805595Sgblack@eecs.umich.edu 9815595Sgblack@eecs.umich.edutemplate <class Impl> 9825595Sgblack@eecs.umich.eduvoid 9836221Snate@binkert.orgFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 9845595Sgblack@eecs.umich.edu{ 9855595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 9865595Sgblack@eecs.umich.edu 9875595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 9885595Sgblack@eecs.umich.edu 9895595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 9905595Sgblack@eecs.umich.edu // instruction. 9915595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 9925595Sgblack@eecs.umich.edu 9935595Sgblack@eecs.umich.edu // Execute the actual syscall. 9945595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 9955595Sgblack@eecs.umich.edu 9965595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 9975595Sgblack@eecs.umich.edu // incrementing it. 9985595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 9995595Sgblack@eecs.umich.edu} 10005595Sgblack@eecs.umich.edu 10015595Sgblack@eecs.umich.edutemplate <class Impl> 10025595Sgblack@eecs.umich.eduvoid 10032864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 10042864Sktlim@umich.edu{ 10052918Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 10062918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 10072864Sktlim@umich.edu BaseCPU::serialize(os); 10082864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 10092864Sktlim@umich.edu tickEvent.serialize(os); 10102864Sktlim@umich.edu 10112864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10122864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 10132864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 10142864Sktlim@umich.edu static SimpleThread temp; 10152864Sktlim@umich.edu 10166221Snate@binkert.org ThreadID size = thread.size(); 10176221Snate@binkert.org for (ThreadID i = 0; i < size; i++) { 10182864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 10192864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10202864Sktlim@umich.edu temp.serialize(os); 10212864Sktlim@umich.edu } 10222864Sktlim@umich.edu} 10232864Sktlim@umich.edu 10242864Sktlim@umich.edutemplate <class Impl> 10252864Sktlim@umich.eduvoid 10262864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 10272864Sktlim@umich.edu{ 10282918Sktlim@umich.edu SimObject::State so_state; 10292918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 10302864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 10312864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 10322864Sktlim@umich.edu 10332864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10342864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 10352864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 10362864Sktlim@umich.edu static SimpleThread temp; 10372864Sktlim@umich.edu 10386221Snate@binkert.org ThreadID size = thread.size(); 10396221Snate@binkert.org for (ThreadID i = 0; i < size; i++) { 10402864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10412864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 10422864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 10432864Sktlim@umich.edu } 10442864Sktlim@umich.edu} 10452864Sktlim@umich.edu 10462864Sktlim@umich.edutemplate <class Impl> 10472905Sktlim@umich.eduunsigned int 10482843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 10491060SN/A{ 10503125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 10513512Sktlim@umich.edu 10523512Sktlim@umich.edu // If the CPU isn't doing anything, then return immediately. 10533512Sktlim@umich.edu if (_status == Idle || _status == SwitchedOut) { 10543512Sktlim@umich.edu return 0; 10553512Sktlim@umich.edu } 10563512Sktlim@umich.edu 10572843Sktlim@umich.edu drainCount = 0; 10582843Sktlim@umich.edu fetch.drain(); 10592843Sktlim@umich.edu decode.drain(); 10602843Sktlim@umich.edu rename.drain(); 10612843Sktlim@umich.edu iew.drain(); 10622843Sktlim@umich.edu commit.drain(); 10632325SN/A 10642325SN/A // Wake the CPU and record activity so everything can drain out if 10652863Sktlim@umich.edu // the CPU was not able to immediately drain. 10662905Sktlim@umich.edu if (getState() != SimObject::Drained) { 10672864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 10682864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 10692864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 10702864Sktlim@umich.edu // process on the drain event. 10712864Sktlim@umich.edu drainEvent = drain_event; 10722843Sktlim@umich.edu 10732863Sktlim@umich.edu wakeCPU(); 10742863Sktlim@umich.edu activityRec.activity(); 10752852Sktlim@umich.edu 10762905Sktlim@umich.edu return 1; 10772863Sktlim@umich.edu } else { 10782905Sktlim@umich.edu return 0; 10792863Sktlim@umich.edu } 10802316SN/A} 10812310SN/A 10822316SN/Atemplate <class Impl> 10832316SN/Avoid 10842843Sktlim@umich.eduFullO3CPU<Impl>::resume() 10852316SN/A{ 10862843Sktlim@umich.edu fetch.resume(); 10872843Sktlim@umich.edu decode.resume(); 10882843Sktlim@umich.edu rename.resume(); 10892843Sktlim@umich.edu iew.resume(); 10902843Sktlim@umich.edu commit.resume(); 10912316SN/A 10922905Sktlim@umich.edu changeState(SimObject::Running); 10932905Sktlim@umich.edu 10942864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 10952864Sktlim@umich.edu return; 10962864Sktlim@umich.edu 10974762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 10983319Shsul@eecs.umich.edu 10992843Sktlim@umich.edu if (!tickEvent.scheduled()) 11005606Snate@binkert.org schedule(tickEvent, nextCycle()); 11012843Sktlim@umich.edu _status = Running; 11022843Sktlim@umich.edu} 11032316SN/A 11042843Sktlim@umich.edutemplate <class Impl> 11052843Sktlim@umich.eduvoid 11062843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 11072843Sktlim@umich.edu{ 11082843Sktlim@umich.edu if (++drainCount == NumStages) { 11092316SN/A if (tickEvent.scheduled()) 11102316SN/A tickEvent.squash(); 11112863Sktlim@umich.edu 11122905Sktlim@umich.edu changeState(SimObject::Drained); 11132863Sktlim@umich.edu 11143126Sktlim@umich.edu BaseCPU::switchOut(); 11153126Sktlim@umich.edu 11162863Sktlim@umich.edu if (drainEvent) { 11172863Sktlim@umich.edu drainEvent->process(); 11182863Sktlim@umich.edu drainEvent = NULL; 11192863Sktlim@umich.edu } 11202310SN/A } 11212843Sktlim@umich.edu assert(drainCount <= 5); 11222843Sktlim@umich.edu} 11232843Sktlim@umich.edu 11242843Sktlim@umich.edutemplate <class Impl> 11252843Sktlim@umich.eduvoid 11262843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 11272843Sktlim@umich.edu{ 11282843Sktlim@umich.edu fetch.switchOut(); 11292843Sktlim@umich.edu rename.switchOut(); 11302325SN/A iew.switchOut(); 11312843Sktlim@umich.edu commit.switchOut(); 11322843Sktlim@umich.edu instList.clear(); 11332843Sktlim@umich.edu while (!removeList.empty()) { 11342843Sktlim@umich.edu removeList.pop(); 11352843Sktlim@umich.edu } 11362843Sktlim@umich.edu 11372843Sktlim@umich.edu _status = SwitchedOut; 11382843Sktlim@umich.edu#if USE_CHECKER 11392843Sktlim@umich.edu if (checker) 11402843Sktlim@umich.edu checker->switchOut(); 11412843Sktlim@umich.edu#endif 11423126Sktlim@umich.edu if (tickEvent.scheduled()) 11433126Sktlim@umich.edu tickEvent.squash(); 11441060SN/A} 11451060SN/A 11461060SN/Atemplate <class Impl> 11471060SN/Avoid 11481755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 11491060SN/A{ 11502325SN/A // Flush out any old data from the time buffers. 11512873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 11522307SN/A timeBuffer.advance(); 11532307SN/A fetchQueue.advance(); 11542307SN/A decodeQueue.advance(); 11552307SN/A renameQueue.advance(); 11562307SN/A iewQueue.advance(); 11572307SN/A } 11582307SN/A 11592325SN/A activityRec.reset(); 11602307SN/A 11614192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort()); 11621060SN/A 11632307SN/A fetch.takeOverFrom(); 11642307SN/A decode.takeOverFrom(); 11652307SN/A rename.takeOverFrom(); 11662307SN/A iew.takeOverFrom(); 11672307SN/A commit.takeOverFrom(); 11682307SN/A 11697507Stjones1@inf.ed.ac.uk assert(!tickEvent.scheduled() || tickEvent.squashed()); 11701060SN/A 11712325SN/A // @todo: Figure out how to properly select the tid to put onto 11722325SN/A // the active threads list. 11736221Snate@binkert.org ThreadID tid = 0; 11742307SN/A 11756221Snate@binkert.org list<ThreadID>::iterator isActive = 11765314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 11772307SN/A 11782307SN/A if (isActive == activeThreads.end()) { 11792325SN/A //May Need to Re-code this if the delay variable is the delay 11802325SN/A //needed for thread to activate 11812733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 11822307SN/A tid); 11832307SN/A 11842307SN/A activeThreads.push_back(tid); 11852307SN/A } 11862307SN/A 11872325SN/A // Set all statuses to active, schedule the CPU's tick event. 11882307SN/A // @todo: Fix up statuses so this is handled properly 11896221Snate@binkert.org ThreadID size = threadContexts.size(); 11906221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 11912680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 11922680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 11931681SN/A _status = Running; 11947507Stjones1@inf.ed.ac.uk reschedule(tickEvent, nextCycle(), true); 11951681SN/A } 11961060SN/A } 11972307SN/A if (!tickEvent.scheduled()) 11985606Snate@binkert.org schedule(tickEvent, nextCycle()); 11991060SN/A} 12001060SN/A 12011060SN/Atemplate <class Impl> 12025595Sgblack@eecs.umich.eduTheISA::MiscReg 12036221Snate@binkert.orgFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) 12045595Sgblack@eecs.umich.edu{ 12056313Sgblack@eecs.umich.edu return this->isa[tid].readMiscRegNoEffect(misc_reg); 12065595Sgblack@eecs.umich.edu} 12075595Sgblack@eecs.umich.edu 12085595Sgblack@eecs.umich.edutemplate <class Impl> 12095595Sgblack@eecs.umich.eduTheISA::MiscReg 12106221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 12115595Sgblack@eecs.umich.edu{ 12127897Shestness@cs.utexas.edu miscRegfileReads++; 12136313Sgblack@eecs.umich.edu return this->isa[tid].readMiscReg(misc_reg, tcBase(tid)); 12145595Sgblack@eecs.umich.edu} 12155595Sgblack@eecs.umich.edu 12165595Sgblack@eecs.umich.edutemplate <class Impl> 12175595Sgblack@eecs.umich.eduvoid 12185595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 12196221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12205595Sgblack@eecs.umich.edu{ 12216313Sgblack@eecs.umich.edu this->isa[tid].setMiscRegNoEffect(misc_reg, val); 12225595Sgblack@eecs.umich.edu} 12235595Sgblack@eecs.umich.edu 12245595Sgblack@eecs.umich.edutemplate <class Impl> 12255595Sgblack@eecs.umich.eduvoid 12265595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 12276221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12285595Sgblack@eecs.umich.edu{ 12297897Shestness@cs.utexas.edu miscRegfileWrites++; 12306313Sgblack@eecs.umich.edu this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid)); 12315595Sgblack@eecs.umich.edu} 12325595Sgblack@eecs.umich.edu 12335595Sgblack@eecs.umich.edutemplate <class Impl> 12341060SN/Auint64_t 12351755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 12361060SN/A{ 12377897Shestness@cs.utexas.edu intRegfileReads++; 12381060SN/A return regFile.readIntReg(reg_idx); 12391060SN/A} 12401060SN/A 12411060SN/Atemplate <class Impl> 12422455SN/AFloatReg 12432455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 12441060SN/A{ 12457897Shestness@cs.utexas.edu fpRegfileReads++; 12462455SN/A return regFile.readFloatReg(reg_idx); 12471060SN/A} 12481060SN/A 12491060SN/Atemplate <class Impl> 12502455SN/AFloatRegBits 12512455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 12522455SN/A{ 12537897Shestness@cs.utexas.edu fpRegfileReads++; 12542455SN/A return regFile.readFloatRegBits(reg_idx); 12551060SN/A} 12561060SN/A 12571060SN/Atemplate <class Impl> 12581060SN/Avoid 12591755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 12601060SN/A{ 12617897Shestness@cs.utexas.edu intRegfileWrites++; 12621060SN/A regFile.setIntReg(reg_idx, val); 12631060SN/A} 12641060SN/A 12651060SN/Atemplate <class Impl> 12661060SN/Avoid 12672455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 12681060SN/A{ 12697897Shestness@cs.utexas.edu fpRegfileWrites++; 12702455SN/A regFile.setFloatReg(reg_idx, val); 12711060SN/A} 12721060SN/A 12731060SN/Atemplate <class Impl> 12741060SN/Avoid 12752455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 12762455SN/A{ 12777897Shestness@cs.utexas.edu fpRegfileWrites++; 12782455SN/A regFile.setFloatRegBits(reg_idx, val); 12791060SN/A} 12801060SN/A 12811060SN/Atemplate <class Impl> 12821060SN/Auint64_t 12836221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 12841060SN/A{ 12857897Shestness@cs.utexas.edu intRegfileReads++; 12862292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 12872292SN/A 12882292SN/A return regFile.readIntReg(phys_reg); 12892292SN/A} 12902292SN/A 12912292SN/Atemplate <class Impl> 12922292SN/Afloat 12936314Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 12942292SN/A{ 12957897Shestness@cs.utexas.edu fpRegfileReads++; 12966032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 12972307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 12982292SN/A 12992669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 13002292SN/A} 13012292SN/A 13022292SN/Atemplate <class Impl> 13032292SN/Auint64_t 13046221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 13052292SN/A{ 13067897Shestness@cs.utexas.edu fpRegfileReads++; 13076032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13082307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13092292SN/A 13102669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 13111060SN/A} 13121060SN/A 13131060SN/Atemplate <class Impl> 13141060SN/Avoid 13156221Snate@binkert.orgFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 13161060SN/A{ 13177897Shestness@cs.utexas.edu intRegfileWrites++; 13182292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13192292SN/A 13202292SN/A regFile.setIntReg(phys_reg, val); 13211060SN/A} 13221060SN/A 13231060SN/Atemplate <class Impl> 13241060SN/Avoid 13256314Sgblack@eecs.umich.eduFullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 13261060SN/A{ 13277897Shestness@cs.utexas.edu fpRegfileWrites++; 13286032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13292918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13302292SN/A 13312669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 13321060SN/A} 13331060SN/A 13341060SN/Atemplate <class Impl> 13351060SN/Avoid 13366221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 13371060SN/A{ 13387897Shestness@cs.utexas.edu fpRegfileWrites++; 13396032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13402918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13411060SN/A 13422669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 13432292SN/A} 13442292SN/A 13452292SN/Atemplate <class Impl> 13467720Sgblack@eecs.umich.eduTheISA::PCState 13477720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 13482292SN/A{ 13497720Sgblack@eecs.umich.edu return commit.pcState(tid); 13501060SN/A} 13511060SN/A 13521060SN/Atemplate <class Impl> 13531060SN/Avoid 13547720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 13551060SN/A{ 13567720Sgblack@eecs.umich.edu commit.pcState(val, tid); 13572292SN/A} 13581060SN/A 13592292SN/Atemplate <class Impl> 13607720Sgblack@eecs.umich.eduAddr 13617720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 13624636Sgblack@eecs.umich.edu{ 13637720Sgblack@eecs.umich.edu return commit.instAddr(tid); 13644636Sgblack@eecs.umich.edu} 13654636Sgblack@eecs.umich.edu 13664636Sgblack@eecs.umich.edutemplate <class Impl> 13677720Sgblack@eecs.umich.eduAddr 13687720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 13694636Sgblack@eecs.umich.edu{ 13707720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 13714636Sgblack@eecs.umich.edu} 13724636Sgblack@eecs.umich.edu 13734636Sgblack@eecs.umich.edutemplate <class Impl> 13747720Sgblack@eecs.umich.eduMicroPC 13757720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 13762292SN/A{ 13777720Sgblack@eecs.umich.edu return commit.microPC(tid); 13784636Sgblack@eecs.umich.edu} 13794636Sgblack@eecs.umich.edu 13804636Sgblack@eecs.umich.edutemplate <class Impl> 13815595Sgblack@eecs.umich.eduvoid 13826221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 13835595Sgblack@eecs.umich.edu{ 13845595Sgblack@eecs.umich.edu this->thread[tid]->inSyscall = true; 13855595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 13865595Sgblack@eecs.umich.edu} 13875595Sgblack@eecs.umich.edu 13885595Sgblack@eecs.umich.edutemplate <class Impl> 13892292SN/Atypename FullO3CPU<Impl>::ListIt 13902292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 13912292SN/A{ 13922292SN/A instList.push_back(inst); 13931060SN/A 13942292SN/A return --(instList.end()); 13952292SN/A} 13961060SN/A 13972292SN/Atemplate <class Impl> 13982292SN/Avoid 13996221Snate@binkert.orgFullO3CPU<Impl>::instDone(ThreadID tid) 14002292SN/A{ 14012292SN/A // Keep an instruction count. 14022292SN/A thread[tid]->numInst++; 14032292SN/A thread[tid]->numInsts++; 14042292SN/A committedInsts[tid]++; 14052292SN/A totalCommittedInsts++; 14067897Shestness@cs.utexas.edu system->totalNumInsts++; 14072292SN/A // Check for instruction-count-based events. 14082292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 14097897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 14102292SN/A} 14112292SN/A 14122292SN/Atemplate <class Impl> 14132292SN/Avoid 14141755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 14151060SN/A{ 14167720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 14172292SN/A "[sn:%lli]\n", 14187720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 14191060SN/A 14202292SN/A removeInstsThisCycle = true; 14211060SN/A 14221060SN/A // Remove the front instruction. 14232292SN/A removeList.push(inst->getInstListIt()); 14241060SN/A} 14251060SN/A 14261060SN/Atemplate <class Impl> 14271060SN/Avoid 14286221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 14291060SN/A{ 14302733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 14312292SN/A " list.\n", tid); 14321060SN/A 14332292SN/A ListIt end_it; 14341060SN/A 14352292SN/A bool rob_empty = false; 14362292SN/A 14372292SN/A if (instList.empty()) { 14382292SN/A return; 14392292SN/A } else if (rob.isEmpty(/*tid*/)) { 14402733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 14412292SN/A end_it = instList.begin(); 14422292SN/A rob_empty = true; 14432292SN/A } else { 14442292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 14452733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 14462292SN/A } 14472292SN/A 14482292SN/A removeInstsThisCycle = true; 14492292SN/A 14502292SN/A ListIt inst_it = instList.end(); 14512292SN/A 14522292SN/A inst_it--; 14532292SN/A 14542292SN/A // Walk through the instruction list, removing any instructions 14552292SN/A // that were inserted after the given instruction iterator, end_it. 14562292SN/A while (inst_it != end_it) { 14572292SN/A assert(!instList.empty()); 14582292SN/A 14592292SN/A squashInstIt(inst_it, tid); 14602292SN/A 14612292SN/A inst_it--; 14622292SN/A } 14632292SN/A 14642292SN/A // If the ROB was empty, then we actually need to remove the first 14652292SN/A // instruction as well. 14662292SN/A if (rob_empty) { 14672292SN/A squashInstIt(inst_it, tid); 14682292SN/A } 14691060SN/A} 14701060SN/A 14711060SN/Atemplate <class Impl> 14721060SN/Avoid 14736221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 14741062SN/A{ 14752292SN/A assert(!instList.empty()); 14762292SN/A 14772292SN/A removeInstsThisCycle = true; 14782292SN/A 14792292SN/A ListIt inst_iter = instList.end(); 14802292SN/A 14812292SN/A inst_iter--; 14822292SN/A 14832733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 14842292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 14852292SN/A tid, seq_num, (*inst_iter)->seqNum); 14861062SN/A 14872292SN/A while ((*inst_iter)->seqNum > seq_num) { 14881062SN/A 14892292SN/A bool break_loop = (inst_iter == instList.begin()); 14901062SN/A 14912292SN/A squashInstIt(inst_iter, tid); 14921062SN/A 14932292SN/A inst_iter--; 14941062SN/A 14952292SN/A if (break_loop) 14962292SN/A break; 14972292SN/A } 14982292SN/A} 14992292SN/A 15002292SN/Atemplate <class Impl> 15012292SN/Ainline void 15026221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 15032292SN/A{ 15042292SN/A if ((*instIt)->threadNumber == tid) { 15052733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 15067720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 15072292SN/A (*instIt)->threadNumber, 15082292SN/A (*instIt)->seqNum, 15097720Sgblack@eecs.umich.edu (*instIt)->pcState()); 15101062SN/A 15111062SN/A // Mark it as squashed. 15122292SN/A (*instIt)->setSquashed(); 15132292SN/A 15142325SN/A // @todo: Formulate a consistent method for deleting 15152325SN/A // instructions from the instruction list 15162292SN/A // Remove the instruction from the list. 15172292SN/A removeList.push(instIt); 15182292SN/A } 15192292SN/A} 15202292SN/A 15212292SN/Atemplate <class Impl> 15222292SN/Avoid 15232292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 15242292SN/A{ 15252292SN/A while (!removeList.empty()) { 15262733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 15277720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 15282292SN/A (*removeList.front())->threadNumber, 15292292SN/A (*removeList.front())->seqNum, 15307720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 15312292SN/A 15322292SN/A instList.erase(removeList.front()); 15332292SN/A 15342292SN/A removeList.pop(); 15351062SN/A } 15361062SN/A 15372292SN/A removeInstsThisCycle = false; 15381062SN/A} 15392325SN/A/* 15401062SN/Atemplate <class Impl> 15411062SN/Avoid 15421755SN/AFullO3CPU<Impl>::removeAllInsts() 15431060SN/A{ 15441060SN/A instList.clear(); 15451060SN/A} 15462325SN/A*/ 15471060SN/Atemplate <class Impl> 15481060SN/Avoid 15491755SN/AFullO3CPU<Impl>::dumpInsts() 15501060SN/A{ 15511060SN/A int num = 0; 15521060SN/A 15532292SN/A ListIt inst_list_it = instList.begin(); 15542292SN/A 15552292SN/A cprintf("Dumping Instruction List\n"); 15562292SN/A 15572292SN/A while (inst_list_it != instList.end()) { 15582292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 15592292SN/A "Squashed:%i\n\n", 15607720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 15612292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 15622292SN/A (*inst_list_it)->isSquashed()); 15631060SN/A inst_list_it++; 15641060SN/A ++num; 15651060SN/A } 15661060SN/A} 15672325SN/A/* 15681060SN/Atemplate <class Impl> 15691060SN/Avoid 15701755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 15711060SN/A{ 15721060SN/A iew.wakeDependents(inst); 15731060SN/A} 15742325SN/A*/ 15752292SN/Atemplate <class Impl> 15762292SN/Avoid 15772292SN/AFullO3CPU<Impl>::wakeCPU() 15782292SN/A{ 15792325SN/A if (activityRec.active() || tickEvent.scheduled()) { 15802325SN/A DPRINTF(Activity, "CPU already running.\n"); 15812292SN/A return; 15822292SN/A } 15832292SN/A 15842325SN/A DPRINTF(Activity, "Waking up CPU\n"); 15852325SN/A 15867823Ssteve.reinhardt@amd.com idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle); 15877823Ssteve.reinhardt@amd.com numCycles += tickToCycles((curTick() - 1) - lastRunningCycle); 15882292SN/A 15895606Snate@binkert.org schedule(tickEvent, nextCycle()); 15902292SN/A} 15912292SN/A 15925807Snate@binkert.orgtemplate <class Impl> 15935807Snate@binkert.orgvoid 15945807Snate@binkert.orgFullO3CPU<Impl>::wakeup() 15955807Snate@binkert.org{ 15965807Snate@binkert.org if (this->thread[0]->status() != ThreadContext::Suspended) 15975807Snate@binkert.org return; 15985807Snate@binkert.org 15995807Snate@binkert.org this->wakeCPU(); 16005807Snate@binkert.org 16015807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 16025807Snate@binkert.org this->threadContexts[0]->activate(); 16035807Snate@binkert.org} 16045807Snate@binkert.org 16052292SN/Atemplate <class Impl> 16066221Snate@binkert.orgThreadID 16072292SN/AFullO3CPU<Impl>::getFreeTid() 16082292SN/A{ 16096221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 16106221Snate@binkert.org if (!tids[tid]) { 16116221Snate@binkert.org tids[tid] = true; 16126221Snate@binkert.org return tid; 16132292SN/A } 16142292SN/A } 16152292SN/A 16166221Snate@binkert.org return InvalidThreadID; 16172292SN/A} 16182292SN/A 16192292SN/Atemplate <class Impl> 16202292SN/Avoid 16212292SN/AFullO3CPU<Impl>::doContextSwitch() 16222292SN/A{ 16232292SN/A if (contextSwitch) { 16242292SN/A 16252292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 16262292SN/A 16276221Snate@binkert.org ThreadID size = cpuWaitList.size(); 16286221Snate@binkert.org for (ThreadID tid = 0; tid < size; tid++) { 16292292SN/A activateWhenReady(tid); 16302292SN/A } 16312292SN/A 16322292SN/A if (cpuWaitList.size() == 0) 16332292SN/A contextSwitch = true; 16342292SN/A } 16352292SN/A} 16362292SN/A 16372292SN/Atemplate <class Impl> 16382292SN/Avoid 16392292SN/AFullO3CPU<Impl>::updateThreadPriority() 16402292SN/A{ 16416221Snate@binkert.org if (activeThreads.size() > 1) { 16422292SN/A //DEFAULT TO ROUND ROBIN SCHEME 16432292SN/A //e.g. Move highest priority to end of thread list 16446221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 16456221Snate@binkert.org list<ThreadID>::iterator list_end = activeThreads.end(); 16462292SN/A 16472292SN/A unsigned high_thread = *list_begin; 16482292SN/A 16492292SN/A activeThreads.erase(list_begin); 16502292SN/A 16512292SN/A activeThreads.push_back(high_thread); 16522292SN/A } 16532292SN/A} 16541060SN/A 16551755SN/A// Forward declaration of FullO3CPU. 16562818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1657