cpu.cc revision 8229
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 37897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 41689SN/A * All rights reserved. 51689SN/A * 61689SN/A * Redistribution and use in source and binary forms, with or without 71689SN/A * modification, are permitted provided that the following conditions are 81689SN/A * met: redistributions of source code must retain the above copyright 91689SN/A * notice, this list of conditions and the following disclaimer; 101689SN/A * redistributions in binary form must reproduce the above copyright 111689SN/A * notice, this list of conditions and the following disclaimer in the 121689SN/A * documentation and/or other materials provided with the distribution; 131689SN/A * neither the name of the copyright holders nor the names of its 141689SN/A * contributors may be used to endorse or promote products derived from 151689SN/A * this software without specific prior written permission. 161689SN/A * 171689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 302756Sksewell@umich.edu * Korey Sewell 317897Shestness@cs.utexas.edu * Rick Strong 321689SN/A */ 331689SN/A 341858SN/A#include "config/full_system.hh" 356658Snate@binkert.org#include "config/the_isa.hh" 362733Sktlim@umich.edu#include "config/use_checker.hh" 378229Snate@binkert.org#include "cpu/o3/cpu.hh" 388229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 398229Snate@binkert.org#include "cpu/o3/thread_context.hh" 404762Snate@binkert.org#include "cpu/activity.hh" 414762Snate@binkert.org#include "cpu/simple_thread.hh" 424762Snate@binkert.org#include "cpu/thread_context.hh" 434762Snate@binkert.org#include "enums/MemoryMode.hh" 444762Snate@binkert.org#include "sim/core.hh" 454762Snate@binkert.org#include "sim/stat_control.hh" 464762Snate@binkert.org 471858SN/A#if FULL_SYSTEM 482356SN/A#include "cpu/quiesce_event.hh" 491060SN/A#include "sim/system.hh" 501060SN/A#else 511060SN/A#include "sim/process.hh" 521060SN/A#endif 531060SN/A 542794Sktlim@umich.edu#if USE_CHECKER 552794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 562794Sktlim@umich.edu#endif 572794Sktlim@umich.edu 585702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 595702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 605702Ssaidi@eecs.umich.edu#endif 615702Ssaidi@eecs.umich.edu 625529Snate@binkert.orgclass BaseCPUParams; 635529Snate@binkert.org 642669Sktlim@umich.eduusing namespace TheISA; 656221Snate@binkert.orgusing namespace std; 661060SN/A 675529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 685712Shsul@eecs.umich.edu : BaseCPU(params) 691060SN/A{ 701060SN/A} 711060SN/A 722292SN/Avoid 732733Sktlim@umich.eduBaseO3CPU::regStats() 742292SN/A{ 752292SN/A BaseCPU::regStats(); 762292SN/A} 772292SN/A 781060SN/Atemplate <class Impl> 791755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 805606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 811060SN/A{ 821060SN/A} 831060SN/A 841060SN/Atemplate <class Impl> 851060SN/Avoid 861755SN/AFullO3CPU<Impl>::TickEvent::process() 871060SN/A{ 881060SN/A cpu->tick(); 891060SN/A} 901060SN/A 911060SN/Atemplate <class Impl> 921060SN/Aconst char * 935336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 941060SN/A{ 954873Sstever@eecs.umich.edu return "FullO3CPU tick"; 961060SN/A} 971060SN/A 981060SN/Atemplate <class Impl> 992829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 1005606Snate@binkert.org : Event(CPU_Switch_Pri) 1012829Sksewell@umich.edu{ 1022829Sksewell@umich.edu} 1032829Sksewell@umich.edu 1042829Sksewell@umich.edutemplate <class Impl> 1052829Sksewell@umich.eduvoid 1062829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 1072829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1082829Sksewell@umich.edu{ 1092829Sksewell@umich.edu tid = thread_num; 1102829Sksewell@umich.edu cpu = thread_cpu; 1112829Sksewell@umich.edu} 1122829Sksewell@umich.edu 1132829Sksewell@umich.edutemplate <class Impl> 1142829Sksewell@umich.eduvoid 1152829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1162829Sksewell@umich.edu{ 1172829Sksewell@umich.edu cpu->activateThread(tid); 1182829Sksewell@umich.edu} 1192829Sksewell@umich.edu 1202829Sksewell@umich.edutemplate <class Impl> 1212829Sksewell@umich.educonst char * 1225336Shines@cs.fsu.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1232829Sksewell@umich.edu{ 1244873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1252829Sksewell@umich.edu} 1262829Sksewell@umich.edu 1272829Sksewell@umich.edutemplate <class Impl> 1282875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1295606Snate@binkert.org : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1302875Sksewell@umich.edu{ 1312875Sksewell@umich.edu} 1322875Sksewell@umich.edu 1332875Sksewell@umich.edutemplate <class Impl> 1342875Sksewell@umich.eduvoid 1352875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1363859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1372875Sksewell@umich.edu{ 1382875Sksewell@umich.edu tid = thread_num; 1392875Sksewell@umich.edu cpu = thread_cpu; 1403859Sbinkertn@umich.edu remove = false; 1412875Sksewell@umich.edu} 1422875Sksewell@umich.edu 1432875Sksewell@umich.edutemplate <class Impl> 1442875Sksewell@umich.eduvoid 1452875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1462875Sksewell@umich.edu{ 1472875Sksewell@umich.edu cpu->deactivateThread(tid); 1483221Sktlim@umich.edu if (remove) 1493221Sktlim@umich.edu cpu->removeThread(tid); 1502875Sksewell@umich.edu} 1512875Sksewell@umich.edu 1522875Sksewell@umich.edutemplate <class Impl> 1532875Sksewell@umich.educonst char * 1545336Shines@cs.fsu.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 1552875Sksewell@umich.edu{ 1564873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 1572875Sksewell@umich.edu} 1582875Sksewell@umich.edu 1592875Sksewell@umich.edutemplate <class Impl> 1605595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 1612733Sktlim@umich.edu : BaseO3CPU(params), 1623781Sgblack@eecs.umich.edu itb(params->itb), 1633781Sgblack@eecs.umich.edu dtb(params->dtb), 1641060SN/A tickEvent(this), 1655737Scws3k@cs.virginia.edu#ifndef NDEBUG 1665737Scws3k@cs.virginia.edu instcount(0), 1675737Scws3k@cs.virginia.edu#endif 1682292SN/A removeInstsThisCycle(false), 1695595Sgblack@eecs.umich.edu fetch(this, params), 1705595Sgblack@eecs.umich.edu decode(this, params), 1715595Sgblack@eecs.umich.edu rename(this, params), 1725595Sgblack@eecs.umich.edu iew(this, params), 1735595Sgblack@eecs.umich.edu commit(this, params), 1741060SN/A 1755595Sgblack@eecs.umich.edu regFile(this, params->numPhysIntRegs, 1764329Sktlim@umich.edu params->numPhysFloatRegs), 1771060SN/A 1785529Snate@binkert.org freeList(params->numThreads, 1792292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1802292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1811060SN/A 1825595Sgblack@eecs.umich.edu rob(this, 1834329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 1842292SN/A params->smtROBPolicy, params->smtROBThreshold, 1855529Snate@binkert.org params->numThreads), 1861060SN/A 1875529Snate@binkert.org scoreboard(params->numThreads, 1882292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1892292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1906221Snate@binkert.org TheISA::NumMiscRegs * numThreads, 1912292SN/A TheISA::ZeroReg), 1921060SN/A 1932873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1942873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1952873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1962873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1972873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1985804Snate@binkert.org activityRec(name(), NumStages, 1992873Sktlim@umich.edu params->backComSize + params->forwardComSize, 2002873Sktlim@umich.edu params->activity), 2011060SN/A 2021060SN/A globalSeqNum(1), 2031858SN/A#if FULL_SYSTEM 2042292SN/A system(params->system), 2051060SN/A#endif // FULL_SYSTEM 2062843Sktlim@umich.edu drainCount(0), 2076221Snate@binkert.org deferRegistration(params->defer_registration) 2081060SN/A{ 2093221Sktlim@umich.edu if (!deferRegistration) { 2103221Sktlim@umich.edu _status = Running; 2113221Sktlim@umich.edu } else { 2123221Sktlim@umich.edu _status = Idle; 2133221Sktlim@umich.edu } 2141681SN/A 2154598Sbinkertn@umich.edu#if USE_CHECKER 2162794Sktlim@umich.edu if (params->checker) { 2172316SN/A BaseCPU *temp_checker = params->checker; 2182316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2192316SN/A#if FULL_SYSTEM 2202316SN/A checker->setSystem(params->system); 2212316SN/A#endif 2224598Sbinkertn@umich.edu } else { 2234598Sbinkertn@umich.edu checker = NULL; 2244598Sbinkertn@umich.edu } 2252794Sktlim@umich.edu#endif // USE_CHECKER 2262316SN/A 2271858SN/A#if !FULL_SYSTEM 2286221Snate@binkert.org thread.resize(numThreads); 2296221Snate@binkert.org tids.resize(numThreads); 2301681SN/A#endif 2311681SN/A 2322325SN/A // The stages also need their CPU pointer setup. However this 2332325SN/A // must be done at the upper level CPU because they have pointers 2342325SN/A // to the upper level CPU, and not this FullO3CPU. 2351060SN/A 2362292SN/A // Set up Pointers to the activeThreads list for each stage 2372292SN/A fetch.setActiveThreads(&activeThreads); 2382292SN/A decode.setActiveThreads(&activeThreads); 2392292SN/A rename.setActiveThreads(&activeThreads); 2402292SN/A iew.setActiveThreads(&activeThreads); 2412292SN/A commit.setActiveThreads(&activeThreads); 2421060SN/A 2431060SN/A // Give each of the stages the time buffer they will use. 2441060SN/A fetch.setTimeBuffer(&timeBuffer); 2451060SN/A decode.setTimeBuffer(&timeBuffer); 2461060SN/A rename.setTimeBuffer(&timeBuffer); 2471060SN/A iew.setTimeBuffer(&timeBuffer); 2481060SN/A commit.setTimeBuffer(&timeBuffer); 2491060SN/A 2501060SN/A // Also setup each of the stages' queues. 2511060SN/A fetch.setFetchQueue(&fetchQueue); 2521060SN/A decode.setFetchQueue(&fetchQueue); 2532292SN/A commit.setFetchQueue(&fetchQueue); 2541060SN/A decode.setDecodeQueue(&decodeQueue); 2551060SN/A rename.setDecodeQueue(&decodeQueue); 2561060SN/A rename.setRenameQueue(&renameQueue); 2571060SN/A iew.setRenameQueue(&renameQueue); 2581060SN/A iew.setIEWQueue(&iewQueue); 2591060SN/A commit.setIEWQueue(&iewQueue); 2601060SN/A commit.setRenameQueue(&renameQueue); 2611060SN/A 2622292SN/A commit.setIEWStage(&iew); 2632292SN/A rename.setIEWStage(&iew); 2642292SN/A rename.setCommitStage(&commit); 2652292SN/A 2662292SN/A#if !FULL_SYSTEM 2676221Snate@binkert.org ThreadID active_threads = params->workload.size(); 2682831Sksewell@umich.edu 2692831Sksewell@umich.edu if (active_threads > Impl::MaxThreads) { 2702831Sksewell@umich.edu panic("Workload Size too large. Increase the 'MaxThreads'" 2712831Sksewell@umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2722831Sksewell@umich.edu "edit your workload size."); 2732831Sksewell@umich.edu } 2742292SN/A#else 2756221Snate@binkert.org ThreadID active_threads = 1; 2762292SN/A#endif 2772292SN/A 2782316SN/A //Make Sure That this a Valid Architeture 2792292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2802292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2812292SN/A 2822292SN/A rename.setScoreboard(&scoreboard); 2832292SN/A iew.setScoreboard(&scoreboard); 2842292SN/A 2851060SN/A // Setup the rename map for whichever stages need it. 2862292SN/A PhysRegIndex lreg_idx = 0; 2872292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2881060SN/A 2896221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2902307SN/A bool bindRegs = (tid <= active_threads - 1); 2912292SN/A 2922292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2932292SN/A params->numPhysIntRegs, 2942325SN/A lreg_idx, //Index for Logical. Regs 2952292SN/A 2962292SN/A TheISA::NumFloatRegs, 2972292SN/A params->numPhysFloatRegs, 2982325SN/A freg_idx, //Index for Float Regs 2992292SN/A 3002292SN/A TheISA::NumMiscRegs, 3012292SN/A 3022292SN/A TheISA::ZeroReg, 3032292SN/A TheISA::ZeroReg, 3042292SN/A 3052292SN/A tid, 3062292SN/A false); 3072292SN/A 3082292SN/A renameMap[tid].init(TheISA::NumIntRegs, 3092292SN/A params->numPhysIntRegs, 3102325SN/A lreg_idx, //Index for Logical. Regs 3112292SN/A 3122292SN/A TheISA::NumFloatRegs, 3132292SN/A params->numPhysFloatRegs, 3142325SN/A freg_idx, //Index for Float Regs 3152292SN/A 3162292SN/A TheISA::NumMiscRegs, 3172292SN/A 3182292SN/A TheISA::ZeroReg, 3192292SN/A TheISA::ZeroReg, 3202292SN/A 3212292SN/A tid, 3222292SN/A bindRegs); 3233221Sktlim@umich.edu 3243221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3253221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3262292SN/A } 3272292SN/A 3282292SN/A rename.setRenameMap(renameMap); 3292292SN/A commit.setRenameMap(commitRenameMap); 3302292SN/A 3312292SN/A // Give renameMap & rename stage access to the freeList; 3326221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3336221Snate@binkert.org renameMap[tid].setFreeList(&freeList); 3341060SN/A rename.setFreeList(&freeList); 3352292SN/A 3361060SN/A // Setup the ROB for whichever stages need it. 3371060SN/A commit.setROB(&rob); 3382292SN/A 3397823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 3402292SN/A 3412829Sksewell@umich.edu lastActivatedCycle = -1; 3426221Snate@binkert.org#if 0 3433093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3446221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3456221Snate@binkert.org globalSeqNum[tid] = 1; 3466221Snate@binkert.org#endif 3473093Sksewell@umich.edu 3482292SN/A contextSwitch = false; 3495595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3505595Sgblack@eecs.umich.edu 3515595Sgblack@eecs.umich.edu // Setup any thread state. 3525595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 3535595Sgblack@eecs.umich.edu 3546221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 3555595Sgblack@eecs.umich.edu#if FULL_SYSTEM 3565595Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 3575595Sgblack@eecs.umich.edu assert(this->numThreads == 1); 3586221Snate@binkert.org this->thread[tid] = new Thread(this, 0); 3595595Sgblack@eecs.umich.edu#else 3606221Snate@binkert.org if (tid < params->workload.size()) { 3615595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 3626221Snate@binkert.org tid, this->thread[tid]); 3636221Snate@binkert.org this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3645595Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3656331Sgblack@eecs.umich.edu tid, params->workload[tid]); 3665595Sgblack@eecs.umich.edu 3676221Snate@binkert.org //usedTids[tid] = true; 3686221Snate@binkert.org //threadMap[tid] = tid; 3695595Sgblack@eecs.umich.edu } else { 3705595Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 3715595Sgblack@eecs.umich.edu //when scheduling threads to CPU 3725595Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 3735595Sgblack@eecs.umich.edu 3746221Snate@binkert.org this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3755595Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3766331Sgblack@eecs.umich.edu tid, dummy_proc); 3776221Snate@binkert.org //usedTids[tid] = false; 3785595Sgblack@eecs.umich.edu } 3795595Sgblack@eecs.umich.edu#endif // !FULL_SYSTEM 3805595Sgblack@eecs.umich.edu 3815595Sgblack@eecs.umich.edu ThreadContext *tc; 3825595Sgblack@eecs.umich.edu 3835595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 3845595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 3855595Sgblack@eecs.umich.edu 3865595Sgblack@eecs.umich.edu tc = o3_tc; 3875595Sgblack@eecs.umich.edu 3885595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 3895595Sgblack@eecs.umich.edu // CheckerThreadContext. 3905595Sgblack@eecs.umich.edu#if USE_CHECKER 3915595Sgblack@eecs.umich.edu if (params->checker) { 3925595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 3935595Sgblack@eecs.umich.edu o3_tc, this->checker); 3945595Sgblack@eecs.umich.edu } 3955595Sgblack@eecs.umich.edu#endif 3965595Sgblack@eecs.umich.edu 3975595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 3985595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 3996221Snate@binkert.org o3_tc->thread = this->thread[tid]; 4005595Sgblack@eecs.umich.edu 4015595Sgblack@eecs.umich.edu#if FULL_SYSTEM 4025595Sgblack@eecs.umich.edu // Setup quiesce event. 4036221Snate@binkert.org this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 4045595Sgblack@eecs.umich.edu#endif 4055595Sgblack@eecs.umich.edu // Give the thread the TC. 4066221Snate@binkert.org this->thread[tid]->tc = tc; 4075595Sgblack@eecs.umich.edu 4085595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4095595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4105595Sgblack@eecs.umich.edu } 4115595Sgblack@eecs.umich.edu 4126221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4136221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4145595Sgblack@eecs.umich.edu 4155595Sgblack@eecs.umich.edu lockAddr = 0; 4165595Sgblack@eecs.umich.edu lockFlag = false; 4171060SN/A} 4181060SN/A 4191060SN/Atemplate <class Impl> 4201755SN/AFullO3CPU<Impl>::~FullO3CPU() 4211060SN/A{ 4221060SN/A} 4231060SN/A 4241060SN/Atemplate <class Impl> 4251060SN/Avoid 4265595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4271062SN/A{ 4282733Sktlim@umich.edu BaseO3CPU::regStats(); 4292292SN/A 4302733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4312292SN/A timesIdled 4322292SN/A .name(name() + ".timesIdled") 4332292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4342292SN/A " unscheduled itself") 4352292SN/A .prereq(timesIdled); 4362292SN/A 4372292SN/A idleCycles 4382292SN/A .name(name() + ".idleCycles") 4392292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4402292SN/A "to idling") 4412292SN/A .prereq(idleCycles); 4422292SN/A 4432292SN/A // Number of Instructions simulated 4442292SN/A // -------------------------------- 4452292SN/A // Should probably be in Base CPU but need templated 4462292SN/A // MaxThreads so put in here instead 4472292SN/A committedInsts 4482292SN/A .init(numThreads) 4492292SN/A .name(name() + ".committedInsts") 4502292SN/A .desc("Number of Instructions Simulated"); 4512292SN/A 4522292SN/A totalCommittedInsts 4532292SN/A .name(name() + ".committedInsts_total") 4542292SN/A .desc("Number of Instructions Simulated"); 4552292SN/A 4562292SN/A cpi 4572292SN/A .name(name() + ".cpi") 4582292SN/A .desc("CPI: Cycles Per Instruction") 4592292SN/A .precision(6); 4604392Sktlim@umich.edu cpi = numCycles / committedInsts; 4612292SN/A 4622292SN/A totalCpi 4632292SN/A .name(name() + ".cpi_total") 4642292SN/A .desc("CPI: Total CPI of All Threads") 4652292SN/A .precision(6); 4664392Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 4672292SN/A 4682292SN/A ipc 4692292SN/A .name(name() + ".ipc") 4702292SN/A .desc("IPC: Instructions Per Cycle") 4712292SN/A .precision(6); 4724392Sktlim@umich.edu ipc = committedInsts / numCycles; 4732292SN/A 4742292SN/A totalIpc 4752292SN/A .name(name() + ".ipc_total") 4762292SN/A .desc("IPC: Total IPC of All Threads") 4772292SN/A .precision(6); 4784392Sktlim@umich.edu totalIpc = totalCommittedInsts / numCycles; 4792292SN/A 4805595Sgblack@eecs.umich.edu this->fetch.regStats(); 4815595Sgblack@eecs.umich.edu this->decode.regStats(); 4825595Sgblack@eecs.umich.edu this->rename.regStats(); 4835595Sgblack@eecs.umich.edu this->iew.regStats(); 4845595Sgblack@eecs.umich.edu this->commit.regStats(); 4857897Shestness@cs.utexas.edu this->rob.regStats(); 4867897Shestness@cs.utexas.edu 4877897Shestness@cs.utexas.edu intRegfileReads 4887897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 4897897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 4907897Shestness@cs.utexas.edu .prereq(intRegfileReads); 4917897Shestness@cs.utexas.edu 4927897Shestness@cs.utexas.edu intRegfileWrites 4937897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 4947897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 4957897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 4967897Shestness@cs.utexas.edu 4977897Shestness@cs.utexas.edu fpRegfileReads 4987897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 4997897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 5007897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 5017897Shestness@cs.utexas.edu 5027897Shestness@cs.utexas.edu fpRegfileWrites 5037897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 5047897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 5057897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 5067897Shestness@cs.utexas.edu 5077897Shestness@cs.utexas.edu miscRegfileReads 5087897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5097897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5107897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5117897Shestness@cs.utexas.edu 5127897Shestness@cs.utexas.edu miscRegfileWrites 5137897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5147897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5157897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5161062SN/A} 5171062SN/A 5181062SN/Atemplate <class Impl> 5192871Sktlim@umich.eduPort * 5202871Sktlim@umich.eduFullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 5212871Sktlim@umich.edu{ 5222871Sktlim@umich.edu if (if_name == "dcache_port") 5232871Sktlim@umich.edu return iew.getDcachePort(); 5242871Sktlim@umich.edu else if (if_name == "icache_port") 5252871Sktlim@umich.edu return fetch.getIcachePort(); 5262871Sktlim@umich.edu else 5272871Sktlim@umich.edu panic("No Such Port\n"); 5282871Sktlim@umich.edu} 5292871Sktlim@umich.edu 5302871Sktlim@umich.edutemplate <class Impl> 5311062SN/Avoid 5321755SN/AFullO3CPU<Impl>::tick() 5331060SN/A{ 5342733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5351060SN/A 5362292SN/A ++numCycles; 5372292SN/A 5382325SN/A// activity = false; 5392292SN/A 5402292SN/A //Tick each of the stages 5411060SN/A fetch.tick(); 5421060SN/A 5431060SN/A decode.tick(); 5441060SN/A 5451060SN/A rename.tick(); 5461060SN/A 5471060SN/A iew.tick(); 5481060SN/A 5491060SN/A commit.tick(); 5501060SN/A 5512292SN/A#if !FULL_SYSTEM 5522292SN/A doContextSwitch(); 5532292SN/A#endif 5542292SN/A 5552292SN/A // Now advance the time buffers 5561060SN/A timeBuffer.advance(); 5571060SN/A 5581060SN/A fetchQueue.advance(); 5591060SN/A decodeQueue.advance(); 5601060SN/A renameQueue.advance(); 5611060SN/A iewQueue.advance(); 5621060SN/A 5632325SN/A activityRec.advance(); 5642292SN/A 5652292SN/A if (removeInstsThisCycle) { 5662292SN/A cleanUpRemovedInsts(); 5672292SN/A } 5682292SN/A 5692325SN/A if (!tickEvent.scheduled()) { 5702867Sktlim@umich.edu if (_status == SwitchedOut || 5712905Sktlim@umich.edu getState() == SimObject::Drained) { 5723226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 5732325SN/A // increment stat 5747823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 5753221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 5763226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 5777823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 5782325SN/A timesIdled++; 5792325SN/A } else { 5807823Ssteve.reinhardt@amd.com schedule(tickEvent, nextCycle(curTick() + ticks(1))); 5813226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 5822325SN/A } 5832292SN/A } 5842292SN/A 5852292SN/A#if !FULL_SYSTEM 5862292SN/A updateThreadPriority(); 5872292SN/A#endif 5881060SN/A} 5891060SN/A 5901060SN/Atemplate <class Impl> 5911060SN/Avoid 5921755SN/AFullO3CPU<Impl>::init() 5931060SN/A{ 5945714Shsul@eecs.umich.edu BaseCPU::init(); 5951060SN/A 5962292SN/A // Set inSyscall so that the CPU doesn't squash when initially 5972292SN/A // setting up registers. 5986221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 5996221Snate@binkert.org thread[tid]->inSyscall = true; 6002292SN/A 6016034Ssteve.reinhardt@amd.com#if FULL_SYSTEM 6026221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 6032680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 6046034Ssteve.reinhardt@amd.com TheISA::initCPU(src_tc, src_tc->contextId()); 6056034Ssteve.reinhardt@amd.com } 6061681SN/A#endif 6072292SN/A 6082292SN/A // Clear inSyscall. 6096221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6106221Snate@binkert.org thread[tid]->inSyscall = false; 6112292SN/A 6122316SN/A // Initialize stages. 6132292SN/A fetch.initStage(); 6142292SN/A iew.initStage(); 6152292SN/A rename.initStage(); 6162292SN/A commit.initStage(); 6172292SN/A 6182292SN/A commit.setThreads(thread); 6192292SN/A} 6202292SN/A 6212292SN/Atemplate <class Impl> 6222292SN/Avoid 6236221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 6242875Sksewell@umich.edu{ 6256221Snate@binkert.org list<ThreadID>::iterator isActive = 6265314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6272875Sksewell@umich.edu 6283226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6293226Sktlim@umich.edu 6302875Sksewell@umich.edu if (isActive == activeThreads.end()) { 6312875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6322875Sksewell@umich.edu tid); 6332875Sksewell@umich.edu 6342875Sksewell@umich.edu activeThreads.push_back(tid); 6352875Sksewell@umich.edu } 6362875Sksewell@umich.edu} 6372875Sksewell@umich.edu 6382875Sksewell@umich.edutemplate <class Impl> 6392875Sksewell@umich.eduvoid 6406221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 6412875Sksewell@umich.edu{ 6422875Sksewell@umich.edu //Remove From Active List, if Active 6436221Snate@binkert.org list<ThreadID>::iterator thread_it = 6445314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6452875Sksewell@umich.edu 6463226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 6473226Sktlim@umich.edu 6482875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 6492875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6502875Sksewell@umich.edu tid); 6512875Sksewell@umich.edu activeThreads.erase(thread_it); 6522875Sksewell@umich.edu } 6532875Sksewell@umich.edu} 6542875Sksewell@umich.edu 6552875Sksewell@umich.edutemplate <class Impl> 6566221Snate@binkert.orgCounter 6576221Snate@binkert.orgFullO3CPU<Impl>::totalInstructions() const 6586221Snate@binkert.org{ 6596221Snate@binkert.org Counter total(0); 6606221Snate@binkert.org 6616221Snate@binkert.org ThreadID size = thread.size(); 6626221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 6636221Snate@binkert.org total += thread[i]->numInst; 6646221Snate@binkert.org 6656221Snate@binkert.org return total; 6666221Snate@binkert.org} 6676221Snate@binkert.org 6686221Snate@binkert.orgtemplate <class Impl> 6692875Sksewell@umich.eduvoid 6706221Snate@binkert.orgFullO3CPU<Impl>::activateContext(ThreadID tid, int delay) 6712875Sksewell@umich.edu{ 6722875Sksewell@umich.edu // Needs to set each stage to running as well. 6732875Sksewell@umich.edu if (delay){ 6742875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 6757823Ssteve.reinhardt@amd.com "on cycle %d\n", tid, curTick() + ticks(delay)); 6762875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 6772875Sksewell@umich.edu } else { 6782875Sksewell@umich.edu activateThread(tid); 6792875Sksewell@umich.edu } 6802875Sksewell@umich.edu 6817823Ssteve.reinhardt@amd.com if (lastActivatedCycle < curTick()) { 6822875Sksewell@umich.edu scheduleTickEvent(delay); 6832875Sksewell@umich.edu 6842875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 6852875Sksewell@umich.edu // deschedule itself. 6862875Sksewell@umich.edu activityRec.activity(); 6872875Sksewell@umich.edu fetch.wakeFromQuiesce(); 6882875Sksewell@umich.edu 6897823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 6902875Sksewell@umich.edu 6912875Sksewell@umich.edu _status = Running; 6922875Sksewell@umich.edu } 6932875Sksewell@umich.edu} 6942875Sksewell@umich.edu 6952875Sksewell@umich.edutemplate <class Impl> 6963221Sktlim@umich.edubool 6976221Snate@binkert.orgFullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay) 6982875Sksewell@umich.edu{ 6992875Sksewell@umich.edu // Schedule removal of thread data from CPU 7002875Sksewell@umich.edu if (delay){ 7012875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 7027823Ssteve.reinhardt@amd.com "on cycle %d\n", tid, curTick() + ticks(delay)); 7033221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 7043221Sktlim@umich.edu return false; 7052875Sksewell@umich.edu } else { 7062875Sksewell@umich.edu deactivateThread(tid); 7073221Sktlim@umich.edu if (remove) 7083221Sktlim@umich.edu removeThread(tid); 7093221Sktlim@umich.edu return true; 7102875Sksewell@umich.edu } 7112875Sksewell@umich.edu} 7122875Sksewell@umich.edu 7132875Sksewell@umich.edutemplate <class Impl> 7142875Sksewell@umich.eduvoid 7156221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 7162875Sksewell@umich.edu{ 7172875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 7183221Sktlim@umich.edu bool deallocated = deallocateContext(tid, false, 1); 7193221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 7205570Snate@binkert.org if ((activeThreads.size() == 1 && !deallocated) || 7213859Sbinkertn@umich.edu activeThreads.size() == 0) 7222910Sksewell@umich.edu unscheduleTickEvent(); 7232875Sksewell@umich.edu _status = Idle; 7242875Sksewell@umich.edu} 7252875Sksewell@umich.edu 7262875Sksewell@umich.edutemplate <class Impl> 7272875Sksewell@umich.eduvoid 7286221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 7292875Sksewell@umich.edu{ 7302910Sksewell@umich.edu //For now, this is the same as deallocate 7312910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 7323221Sktlim@umich.edu deallocateContext(tid, true, 1); 7332875Sksewell@umich.edu} 7342875Sksewell@umich.edu 7352875Sksewell@umich.edutemplate <class Impl> 7362875Sksewell@umich.eduvoid 7376221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 7382292SN/A{ 7392847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 7402292SN/A // Will change now that the PC and thread state is internal to the CPU 7412683Sktlim@umich.edu // and not in the ThreadContext. 7422292SN/A#if FULL_SYSTEM 7432680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 7442292SN/A#else 7452847Sksewell@umich.edu ThreadContext *src_tc = tcBase(tid); 7462292SN/A#endif 7472292SN/A 7482292SN/A //Bind Int Regs to Rename Map 7492292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7502292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 7512292SN/A 7522292SN/A renameMap[tid].setEntry(ireg,phys_reg); 7532292SN/A scoreboard.setReg(phys_reg); 7542292SN/A } 7552292SN/A 7562292SN/A //Bind Float Regs to Rename Map 7572292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 7582292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 7592292SN/A 7602292SN/A renameMap[tid].setEntry(freg,phys_reg); 7612292SN/A scoreboard.setReg(phys_reg); 7622292SN/A } 7632292SN/A 7642292SN/A //Copy Thread Data Into RegFile 7652847Sksewell@umich.edu //this->copyFromTC(tid); 7662292SN/A 7672847Sksewell@umich.edu //Set PC/NPC/NNPC 7687720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 7692292SN/A 7702680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 7712292SN/A 7722292SN/A activateContext(tid,1); 7732292SN/A 7742292SN/A //Reset ROB/IQ/LSQ Entries 7752292SN/A commit.rob->resetEntries(); 7762292SN/A iew.resetEntries(); 7772292SN/A} 7782292SN/A 7792292SN/Atemplate <class Impl> 7802292SN/Avoid 7816221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 7822292SN/A{ 7832877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 7842847Sksewell@umich.edu 7852847Sksewell@umich.edu // Copy Thread Data From RegFile 7862847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 7875364Sksewell@umich.edu // this->copyToTC(tid); 7885364Sksewell@umich.edu 7895364Sksewell@umich.edu 7905364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 7915364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 7925364Sksewell@umich.edu // in SMT workloads. 7932847Sksewell@umich.edu 7942847Sksewell@umich.edu // Unbind Int Regs from Rename Map 7952292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7962292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 7972292SN/A 7982292SN/A scoreboard.unsetReg(phys_reg); 7992292SN/A freeList.addReg(phys_reg); 8002292SN/A } 8012292SN/A 8022847Sksewell@umich.edu // Unbind Float Regs from Rename Map 8035362Sksewell@umich.edu for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 8042292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 8052292SN/A 8062292SN/A scoreboard.unsetReg(phys_reg); 8072292SN/A freeList.addReg(phys_reg); 8082292SN/A } 8092292SN/A 8102847Sksewell@umich.edu // Squash Throughout Pipeline 8118138SAli.Saidi@ARM.com DynInstPtr inst = commit.rob->readHeadInst(tid); 8128138SAli.Saidi@ARM.com InstSeqNum squash_seq_num = inst->seqNum; 8138138SAli.Saidi@ARM.com fetch.squash(0, squash_seq_num, inst, tid); 8142292SN/A decode.squash(tid); 8152935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 8162875Sksewell@umich.edu iew.squash(tid); 8175363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 8182935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 8192292SN/A 8205362Sksewell@umich.edu 8215362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 8222292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 8232292SN/A 8242847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 8253229Sktlim@umich.edu 8263229Sktlim@umich.edu // Commented out for now. This should be possible to do by 8273229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 8283229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 8293229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 8303229Sktlim@umich.edu/* 8312292SN/A if (activeThreads.size() >= 1) { 8322292SN/A commit.rob->resetEntries(); 8332292SN/A iew.resetEntries(); 8342292SN/A } 8353229Sktlim@umich.edu*/ 8362292SN/A} 8372292SN/A 8382292SN/A 8392292SN/Atemplate <class Impl> 8402292SN/Avoid 8416221Snate@binkert.orgFullO3CPU<Impl>::activateWhenReady(ThreadID tid) 8422292SN/A{ 8432733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 8442292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 8452292SN/A tid); 8462292SN/A 8472292SN/A bool ready = true; 8482292SN/A 8492292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 8502733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8512292SN/A "Phys. Int. Regs.\n", 8522292SN/A tid); 8532292SN/A ready = false; 8542292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 8552733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8562292SN/A "Phys. Float. Regs.\n", 8572292SN/A tid); 8582292SN/A ready = false; 8592292SN/A } else if (commit.rob->numFreeEntries() >= 8602292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 8612733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8622292SN/A "ROB entries.\n", 8632292SN/A tid); 8642292SN/A ready = false; 8652292SN/A } else if (iew.instQueue.numFreeEntries() >= 8662292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 8672733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8682292SN/A "IQ entries.\n", 8692292SN/A tid); 8702292SN/A ready = false; 8712292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 8722292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 8732733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8742292SN/A "LSQ entries.\n", 8752292SN/A tid); 8762292SN/A ready = false; 8772292SN/A } 8782292SN/A 8792292SN/A if (ready) { 8802292SN/A insertThread(tid); 8812292SN/A 8822292SN/A contextSwitch = false; 8832292SN/A 8842292SN/A cpuWaitList.remove(tid); 8852292SN/A } else { 8862292SN/A suspendContext(tid); 8872292SN/A 8882292SN/A //blocks fetch 8892292SN/A contextSwitch = true; 8902292SN/A 8912875Sksewell@umich.edu //@todo: dont always add to waitlist 8922292SN/A //do waitlist 8932292SN/A cpuWaitList.push_back(tid); 8941060SN/A } 8951060SN/A} 8961060SN/A 8974192Sktlim@umich.edu#if FULL_SYSTEM 8984192Sktlim@umich.edutemplate <class Impl> 8995595Sgblack@eecs.umich.eduFault 9006221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 9015702Ssaidi@eecs.umich.edu{ 9025702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9035702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 9045702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 9055702Ssaidi@eecs.umich.edu 9065702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 9075702Ssaidi@eecs.umich.edu 9085702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 9095702Ssaidi@eecs.umich.edu#endif 9105702Ssaidi@eecs.umich.edu return NoFault; 9115702Ssaidi@eecs.umich.edu} 9125702Ssaidi@eecs.umich.edu 9135702Ssaidi@eecs.umich.edutemplate <class Impl> 9145702Ssaidi@eecs.umich.edubool 9156221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 9165702Ssaidi@eecs.umich.edu{ 9175702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9185702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 9195702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 9205702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 9215702Ssaidi@eecs.umich.edu 9225702Ssaidi@eecs.umich.edu switch (palFunc) { 9235702Ssaidi@eecs.umich.edu case PAL::halt: 9245702Ssaidi@eecs.umich.edu halt(); 9255702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 9265702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 9275702Ssaidi@eecs.umich.edu break; 9285702Ssaidi@eecs.umich.edu 9295702Ssaidi@eecs.umich.edu case PAL::bpt: 9305702Ssaidi@eecs.umich.edu case PAL::bugchk: 9315702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 9325702Ssaidi@eecs.umich.edu return false; 9335702Ssaidi@eecs.umich.edu break; 9345702Ssaidi@eecs.umich.edu } 9355702Ssaidi@eecs.umich.edu#endif 9365702Ssaidi@eecs.umich.edu return true; 9375702Ssaidi@eecs.umich.edu} 9385702Ssaidi@eecs.umich.edu 9395702Ssaidi@eecs.umich.edutemplate <class Impl> 9405702Ssaidi@eecs.umich.eduFault 9415595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 9425595Sgblack@eecs.umich.edu{ 9435595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 9445647Sgblack@eecs.umich.edu return this->interrupts->getInterrupt(this->threadContexts[0]); 9455595Sgblack@eecs.umich.edu} 9465595Sgblack@eecs.umich.edu 9475595Sgblack@eecs.umich.edutemplate <class Impl> 9485595Sgblack@eecs.umich.eduvoid 9495595Sgblack@eecs.umich.eduFullO3CPU<Impl>::processInterrupts(Fault interrupt) 9505595Sgblack@eecs.umich.edu{ 9515595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 9525595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 9535595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 9545595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 9555595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 9565595Sgblack@eecs.umich.edu 9575595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 9585647Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 9595595Sgblack@eecs.umich.edu 9605595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 9617684Sgblack@eecs.umich.edu this->trap(interrupt, 0, NULL); 9625595Sgblack@eecs.umich.edu} 9635595Sgblack@eecs.umich.edu 9645595Sgblack@eecs.umich.edutemplate <class Impl> 9655595Sgblack@eecs.umich.eduvoid 9664192Sktlim@umich.eduFullO3CPU<Impl>::updateMemPorts() 9674192Sktlim@umich.edu{ 9684192Sktlim@umich.edu // Update all ThreadContext's memory ports (Functional/Virtual 9694192Sktlim@umich.edu // Ports) 9706221Snate@binkert.org ThreadID size = thread.size(); 9716221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) 9725497Ssaidi@eecs.umich.edu thread[i]->connectMemPorts(thread[i]->getTC()); 9734192Sktlim@umich.edu} 9744192Sktlim@umich.edu#endif 9754192Sktlim@umich.edu 9761060SN/Atemplate <class Impl> 9772852Sktlim@umich.eduvoid 9787684Sgblack@eecs.umich.eduFullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst) 9795595Sgblack@eecs.umich.edu{ 9805595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 9817684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 9825595Sgblack@eecs.umich.edu} 9835595Sgblack@eecs.umich.edu 9845595Sgblack@eecs.umich.edu#if !FULL_SYSTEM 9855595Sgblack@eecs.umich.edu 9865595Sgblack@eecs.umich.edutemplate <class Impl> 9875595Sgblack@eecs.umich.eduvoid 9886221Snate@binkert.orgFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 9895595Sgblack@eecs.umich.edu{ 9905595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 9915595Sgblack@eecs.umich.edu 9925595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 9935595Sgblack@eecs.umich.edu 9945595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 9955595Sgblack@eecs.umich.edu // instruction. 9965595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 9975595Sgblack@eecs.umich.edu 9985595Sgblack@eecs.umich.edu // Execute the actual syscall. 9995595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 10005595Sgblack@eecs.umich.edu 10015595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 10025595Sgblack@eecs.umich.edu // incrementing it. 10035595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 10045595Sgblack@eecs.umich.edu} 10055595Sgblack@eecs.umich.edu 10065595Sgblack@eecs.umich.edu#endif 10075595Sgblack@eecs.umich.edu 10085595Sgblack@eecs.umich.edutemplate <class Impl> 10095595Sgblack@eecs.umich.eduvoid 10102864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 10112864Sktlim@umich.edu{ 10122918Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 10132918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 10142864Sktlim@umich.edu BaseCPU::serialize(os); 10152864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 10162864Sktlim@umich.edu tickEvent.serialize(os); 10172864Sktlim@umich.edu 10182864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10192864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 10202864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 10212864Sktlim@umich.edu static SimpleThread temp; 10222864Sktlim@umich.edu 10236221Snate@binkert.org ThreadID size = thread.size(); 10246221Snate@binkert.org for (ThreadID i = 0; i < size; i++) { 10252864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 10262864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10272864Sktlim@umich.edu temp.serialize(os); 10282864Sktlim@umich.edu } 10292864Sktlim@umich.edu} 10302864Sktlim@umich.edu 10312864Sktlim@umich.edutemplate <class Impl> 10322864Sktlim@umich.eduvoid 10332864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 10342864Sktlim@umich.edu{ 10352918Sktlim@umich.edu SimObject::State so_state; 10362918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 10372864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 10382864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 10392864Sktlim@umich.edu 10402864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10412864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 10422864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 10432864Sktlim@umich.edu static SimpleThread temp; 10442864Sktlim@umich.edu 10456221Snate@binkert.org ThreadID size = thread.size(); 10466221Snate@binkert.org for (ThreadID i = 0; i < size; i++) { 10472864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10482864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 10492864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 10502864Sktlim@umich.edu } 10512864Sktlim@umich.edu} 10522864Sktlim@umich.edu 10532864Sktlim@umich.edutemplate <class Impl> 10542905Sktlim@umich.eduunsigned int 10552843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 10561060SN/A{ 10573125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 10583512Sktlim@umich.edu 10593512Sktlim@umich.edu // If the CPU isn't doing anything, then return immediately. 10603512Sktlim@umich.edu if (_status == Idle || _status == SwitchedOut) { 10613512Sktlim@umich.edu return 0; 10623512Sktlim@umich.edu } 10633512Sktlim@umich.edu 10642843Sktlim@umich.edu drainCount = 0; 10652843Sktlim@umich.edu fetch.drain(); 10662843Sktlim@umich.edu decode.drain(); 10672843Sktlim@umich.edu rename.drain(); 10682843Sktlim@umich.edu iew.drain(); 10692843Sktlim@umich.edu commit.drain(); 10702325SN/A 10712325SN/A // Wake the CPU and record activity so everything can drain out if 10722863Sktlim@umich.edu // the CPU was not able to immediately drain. 10732905Sktlim@umich.edu if (getState() != SimObject::Drained) { 10742864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 10752864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 10762864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 10772864Sktlim@umich.edu // process on the drain event. 10782864Sktlim@umich.edu drainEvent = drain_event; 10792843Sktlim@umich.edu 10802863Sktlim@umich.edu wakeCPU(); 10812863Sktlim@umich.edu activityRec.activity(); 10822852Sktlim@umich.edu 10832905Sktlim@umich.edu return 1; 10842863Sktlim@umich.edu } else { 10852905Sktlim@umich.edu return 0; 10862863Sktlim@umich.edu } 10872316SN/A} 10882310SN/A 10892316SN/Atemplate <class Impl> 10902316SN/Avoid 10912843Sktlim@umich.eduFullO3CPU<Impl>::resume() 10922316SN/A{ 10932843Sktlim@umich.edu fetch.resume(); 10942843Sktlim@umich.edu decode.resume(); 10952843Sktlim@umich.edu rename.resume(); 10962843Sktlim@umich.edu iew.resume(); 10972843Sktlim@umich.edu commit.resume(); 10982316SN/A 10992905Sktlim@umich.edu changeState(SimObject::Running); 11002905Sktlim@umich.edu 11012864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 11022864Sktlim@umich.edu return; 11032864Sktlim@umich.edu 11043319Shsul@eecs.umich.edu#if FULL_SYSTEM 11054762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 11063319Shsul@eecs.umich.edu#endif 11073319Shsul@eecs.umich.edu 11082843Sktlim@umich.edu if (!tickEvent.scheduled()) 11095606Snate@binkert.org schedule(tickEvent, nextCycle()); 11102843Sktlim@umich.edu _status = Running; 11112843Sktlim@umich.edu} 11122316SN/A 11132843Sktlim@umich.edutemplate <class Impl> 11142843Sktlim@umich.eduvoid 11152843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 11162843Sktlim@umich.edu{ 11172843Sktlim@umich.edu if (++drainCount == NumStages) { 11182316SN/A if (tickEvent.scheduled()) 11192316SN/A tickEvent.squash(); 11202863Sktlim@umich.edu 11212905Sktlim@umich.edu changeState(SimObject::Drained); 11222863Sktlim@umich.edu 11233126Sktlim@umich.edu BaseCPU::switchOut(); 11243126Sktlim@umich.edu 11252863Sktlim@umich.edu if (drainEvent) { 11262863Sktlim@umich.edu drainEvent->process(); 11272863Sktlim@umich.edu drainEvent = NULL; 11282863Sktlim@umich.edu } 11292310SN/A } 11302843Sktlim@umich.edu assert(drainCount <= 5); 11312843Sktlim@umich.edu} 11322843Sktlim@umich.edu 11332843Sktlim@umich.edutemplate <class Impl> 11342843Sktlim@umich.eduvoid 11352843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 11362843Sktlim@umich.edu{ 11372843Sktlim@umich.edu fetch.switchOut(); 11382843Sktlim@umich.edu rename.switchOut(); 11392325SN/A iew.switchOut(); 11402843Sktlim@umich.edu commit.switchOut(); 11412843Sktlim@umich.edu instList.clear(); 11422843Sktlim@umich.edu while (!removeList.empty()) { 11432843Sktlim@umich.edu removeList.pop(); 11442843Sktlim@umich.edu } 11452843Sktlim@umich.edu 11462843Sktlim@umich.edu _status = SwitchedOut; 11472843Sktlim@umich.edu#if USE_CHECKER 11482843Sktlim@umich.edu if (checker) 11492843Sktlim@umich.edu checker->switchOut(); 11502843Sktlim@umich.edu#endif 11513126Sktlim@umich.edu if (tickEvent.scheduled()) 11523126Sktlim@umich.edu tickEvent.squash(); 11531060SN/A} 11541060SN/A 11551060SN/Atemplate <class Impl> 11561060SN/Avoid 11571755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 11581060SN/A{ 11592325SN/A // Flush out any old data from the time buffers. 11602873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 11612307SN/A timeBuffer.advance(); 11622307SN/A fetchQueue.advance(); 11632307SN/A decodeQueue.advance(); 11642307SN/A renameQueue.advance(); 11652307SN/A iewQueue.advance(); 11662307SN/A } 11672307SN/A 11682325SN/A activityRec.reset(); 11692307SN/A 11704192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort()); 11711060SN/A 11722307SN/A fetch.takeOverFrom(); 11732307SN/A decode.takeOverFrom(); 11742307SN/A rename.takeOverFrom(); 11752307SN/A iew.takeOverFrom(); 11762307SN/A commit.takeOverFrom(); 11772307SN/A 11787507Stjones1@inf.ed.ac.uk assert(!tickEvent.scheduled() || tickEvent.squashed()); 11791060SN/A 11802325SN/A // @todo: Figure out how to properly select the tid to put onto 11812325SN/A // the active threads list. 11826221Snate@binkert.org ThreadID tid = 0; 11832307SN/A 11846221Snate@binkert.org list<ThreadID>::iterator isActive = 11855314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 11862307SN/A 11872307SN/A if (isActive == activeThreads.end()) { 11882325SN/A //May Need to Re-code this if the delay variable is the delay 11892325SN/A //needed for thread to activate 11902733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 11912307SN/A tid); 11922307SN/A 11932307SN/A activeThreads.push_back(tid); 11942307SN/A } 11952307SN/A 11962325SN/A // Set all statuses to active, schedule the CPU's tick event. 11972307SN/A // @todo: Fix up statuses so this is handled properly 11986221Snate@binkert.org ThreadID size = threadContexts.size(); 11996221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 12002680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 12012680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 12021681SN/A _status = Running; 12037507Stjones1@inf.ed.ac.uk reschedule(tickEvent, nextCycle(), true); 12041681SN/A } 12051060SN/A } 12062307SN/A if (!tickEvent.scheduled()) 12075606Snate@binkert.org schedule(tickEvent, nextCycle()); 12081060SN/A} 12091060SN/A 12101060SN/Atemplate <class Impl> 12115595Sgblack@eecs.umich.eduTheISA::MiscReg 12126221Snate@binkert.orgFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) 12135595Sgblack@eecs.umich.edu{ 12146313Sgblack@eecs.umich.edu return this->isa[tid].readMiscRegNoEffect(misc_reg); 12155595Sgblack@eecs.umich.edu} 12165595Sgblack@eecs.umich.edu 12175595Sgblack@eecs.umich.edutemplate <class Impl> 12185595Sgblack@eecs.umich.eduTheISA::MiscReg 12196221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 12205595Sgblack@eecs.umich.edu{ 12217897Shestness@cs.utexas.edu miscRegfileReads++; 12226313Sgblack@eecs.umich.edu return this->isa[tid].readMiscReg(misc_reg, tcBase(tid)); 12235595Sgblack@eecs.umich.edu} 12245595Sgblack@eecs.umich.edu 12255595Sgblack@eecs.umich.edutemplate <class Impl> 12265595Sgblack@eecs.umich.eduvoid 12275595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 12286221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12295595Sgblack@eecs.umich.edu{ 12306313Sgblack@eecs.umich.edu this->isa[tid].setMiscRegNoEffect(misc_reg, val); 12315595Sgblack@eecs.umich.edu} 12325595Sgblack@eecs.umich.edu 12335595Sgblack@eecs.umich.edutemplate <class Impl> 12345595Sgblack@eecs.umich.eduvoid 12355595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 12366221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12375595Sgblack@eecs.umich.edu{ 12387897Shestness@cs.utexas.edu miscRegfileWrites++; 12396313Sgblack@eecs.umich.edu this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid)); 12405595Sgblack@eecs.umich.edu} 12415595Sgblack@eecs.umich.edu 12425595Sgblack@eecs.umich.edutemplate <class Impl> 12431060SN/Auint64_t 12441755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 12451060SN/A{ 12467897Shestness@cs.utexas.edu intRegfileReads++; 12471060SN/A return regFile.readIntReg(reg_idx); 12481060SN/A} 12491060SN/A 12501060SN/Atemplate <class Impl> 12512455SN/AFloatReg 12522455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 12531060SN/A{ 12547897Shestness@cs.utexas.edu fpRegfileReads++; 12552455SN/A return regFile.readFloatReg(reg_idx); 12561060SN/A} 12571060SN/A 12581060SN/Atemplate <class Impl> 12592455SN/AFloatRegBits 12602455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 12612455SN/A{ 12627897Shestness@cs.utexas.edu fpRegfileReads++; 12632455SN/A return regFile.readFloatRegBits(reg_idx); 12641060SN/A} 12651060SN/A 12661060SN/Atemplate <class Impl> 12671060SN/Avoid 12681755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 12691060SN/A{ 12707897Shestness@cs.utexas.edu intRegfileWrites++; 12711060SN/A regFile.setIntReg(reg_idx, val); 12721060SN/A} 12731060SN/A 12741060SN/Atemplate <class Impl> 12751060SN/Avoid 12762455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 12771060SN/A{ 12787897Shestness@cs.utexas.edu fpRegfileWrites++; 12792455SN/A regFile.setFloatReg(reg_idx, val); 12801060SN/A} 12811060SN/A 12821060SN/Atemplate <class Impl> 12831060SN/Avoid 12842455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 12852455SN/A{ 12867897Shestness@cs.utexas.edu fpRegfileWrites++; 12872455SN/A regFile.setFloatRegBits(reg_idx, val); 12881060SN/A} 12891060SN/A 12901060SN/Atemplate <class Impl> 12911060SN/Auint64_t 12926221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 12931060SN/A{ 12947897Shestness@cs.utexas.edu intRegfileReads++; 12952292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 12962292SN/A 12972292SN/A return regFile.readIntReg(phys_reg); 12982292SN/A} 12992292SN/A 13002292SN/Atemplate <class Impl> 13012292SN/Afloat 13026314Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 13032292SN/A{ 13047897Shestness@cs.utexas.edu fpRegfileReads++; 13056032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13062307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13072292SN/A 13082669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 13092292SN/A} 13102292SN/A 13112292SN/Atemplate <class Impl> 13122292SN/Auint64_t 13136221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 13142292SN/A{ 13157897Shestness@cs.utexas.edu fpRegfileReads++; 13166032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13172307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13182292SN/A 13192669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 13201060SN/A} 13211060SN/A 13221060SN/Atemplate <class Impl> 13231060SN/Avoid 13246221Snate@binkert.orgFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 13251060SN/A{ 13267897Shestness@cs.utexas.edu intRegfileWrites++; 13272292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13282292SN/A 13292292SN/A regFile.setIntReg(phys_reg, val); 13301060SN/A} 13311060SN/A 13321060SN/Atemplate <class Impl> 13331060SN/Avoid 13346314Sgblack@eecs.umich.eduFullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 13351060SN/A{ 13367897Shestness@cs.utexas.edu fpRegfileWrites++; 13376032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13382918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13392292SN/A 13402669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 13411060SN/A} 13421060SN/A 13431060SN/Atemplate <class Impl> 13441060SN/Avoid 13456221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 13461060SN/A{ 13477897Shestness@cs.utexas.edu fpRegfileWrites++; 13486032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13492918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13501060SN/A 13512669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 13522292SN/A} 13532292SN/A 13542292SN/Atemplate <class Impl> 13557720Sgblack@eecs.umich.eduTheISA::PCState 13567720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 13572292SN/A{ 13587720Sgblack@eecs.umich.edu return commit.pcState(tid); 13591060SN/A} 13601060SN/A 13611060SN/Atemplate <class Impl> 13621060SN/Avoid 13637720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 13641060SN/A{ 13657720Sgblack@eecs.umich.edu commit.pcState(val, tid); 13662292SN/A} 13671060SN/A 13682292SN/Atemplate <class Impl> 13697720Sgblack@eecs.umich.eduAddr 13707720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 13714636Sgblack@eecs.umich.edu{ 13727720Sgblack@eecs.umich.edu return commit.instAddr(tid); 13734636Sgblack@eecs.umich.edu} 13744636Sgblack@eecs.umich.edu 13754636Sgblack@eecs.umich.edutemplate <class Impl> 13767720Sgblack@eecs.umich.eduAddr 13777720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 13784636Sgblack@eecs.umich.edu{ 13797720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 13804636Sgblack@eecs.umich.edu} 13814636Sgblack@eecs.umich.edu 13824636Sgblack@eecs.umich.edutemplate <class Impl> 13837720Sgblack@eecs.umich.eduMicroPC 13847720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 13852292SN/A{ 13867720Sgblack@eecs.umich.edu return commit.microPC(tid); 13874636Sgblack@eecs.umich.edu} 13884636Sgblack@eecs.umich.edu 13894636Sgblack@eecs.umich.edutemplate <class Impl> 13905595Sgblack@eecs.umich.eduvoid 13916221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 13925595Sgblack@eecs.umich.edu{ 13935595Sgblack@eecs.umich.edu this->thread[tid]->inSyscall = true; 13945595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 13955595Sgblack@eecs.umich.edu} 13965595Sgblack@eecs.umich.edu 13975595Sgblack@eecs.umich.edutemplate <class Impl> 13982292SN/Atypename FullO3CPU<Impl>::ListIt 13992292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 14002292SN/A{ 14012292SN/A instList.push_back(inst); 14021060SN/A 14032292SN/A return --(instList.end()); 14042292SN/A} 14051060SN/A 14062292SN/Atemplate <class Impl> 14072292SN/Avoid 14086221Snate@binkert.orgFullO3CPU<Impl>::instDone(ThreadID tid) 14092292SN/A{ 14102292SN/A // Keep an instruction count. 14112292SN/A thread[tid]->numInst++; 14122292SN/A thread[tid]->numInsts++; 14132292SN/A committedInsts[tid]++; 14142292SN/A totalCommittedInsts++; 14157897Shestness@cs.utexas.edu system->totalNumInsts++; 14162292SN/A // Check for instruction-count-based events. 14172292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 14187897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 14192292SN/A} 14202292SN/A 14212292SN/Atemplate <class Impl> 14222292SN/Avoid 14232292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 14242292SN/A{ 14252292SN/A removeInstsThisCycle = true; 14262292SN/A 14272292SN/A removeList.push(inst->getInstListIt()); 14281060SN/A} 14291060SN/A 14301060SN/Atemplate <class Impl> 14311060SN/Avoid 14321755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 14331060SN/A{ 14347720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 14352292SN/A "[sn:%lli]\n", 14367720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 14371060SN/A 14382292SN/A removeInstsThisCycle = true; 14391060SN/A 14401060SN/A // Remove the front instruction. 14412292SN/A removeList.push(inst->getInstListIt()); 14421060SN/A} 14431060SN/A 14441060SN/Atemplate <class Impl> 14451060SN/Avoid 14466221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 14471060SN/A{ 14482733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 14492292SN/A " list.\n", tid); 14501060SN/A 14512292SN/A ListIt end_it; 14521060SN/A 14532292SN/A bool rob_empty = false; 14542292SN/A 14552292SN/A if (instList.empty()) { 14562292SN/A return; 14572292SN/A } else if (rob.isEmpty(/*tid*/)) { 14582733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 14592292SN/A end_it = instList.begin(); 14602292SN/A rob_empty = true; 14612292SN/A } else { 14622292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 14632733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 14642292SN/A } 14652292SN/A 14662292SN/A removeInstsThisCycle = true; 14672292SN/A 14682292SN/A ListIt inst_it = instList.end(); 14692292SN/A 14702292SN/A inst_it--; 14712292SN/A 14722292SN/A // Walk through the instruction list, removing any instructions 14732292SN/A // that were inserted after the given instruction iterator, end_it. 14742292SN/A while (inst_it != end_it) { 14752292SN/A assert(!instList.empty()); 14762292SN/A 14772292SN/A squashInstIt(inst_it, tid); 14782292SN/A 14792292SN/A inst_it--; 14802292SN/A } 14812292SN/A 14822292SN/A // If the ROB was empty, then we actually need to remove the first 14832292SN/A // instruction as well. 14842292SN/A if (rob_empty) { 14852292SN/A squashInstIt(inst_it, tid); 14862292SN/A } 14871060SN/A} 14881060SN/A 14891060SN/Atemplate <class Impl> 14901060SN/Avoid 14916221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 14921062SN/A{ 14932292SN/A assert(!instList.empty()); 14942292SN/A 14952292SN/A removeInstsThisCycle = true; 14962292SN/A 14972292SN/A ListIt inst_iter = instList.end(); 14982292SN/A 14992292SN/A inst_iter--; 15002292SN/A 15012733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 15022292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 15032292SN/A tid, seq_num, (*inst_iter)->seqNum); 15041062SN/A 15052292SN/A while ((*inst_iter)->seqNum > seq_num) { 15061062SN/A 15072292SN/A bool break_loop = (inst_iter == instList.begin()); 15081062SN/A 15092292SN/A squashInstIt(inst_iter, tid); 15101062SN/A 15112292SN/A inst_iter--; 15121062SN/A 15132292SN/A if (break_loop) 15142292SN/A break; 15152292SN/A } 15162292SN/A} 15172292SN/A 15182292SN/Atemplate <class Impl> 15192292SN/Ainline void 15206221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 15212292SN/A{ 15222292SN/A if ((*instIt)->threadNumber == tid) { 15232733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 15247720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 15252292SN/A (*instIt)->threadNumber, 15262292SN/A (*instIt)->seqNum, 15277720Sgblack@eecs.umich.edu (*instIt)->pcState()); 15281062SN/A 15291062SN/A // Mark it as squashed. 15302292SN/A (*instIt)->setSquashed(); 15312292SN/A 15322325SN/A // @todo: Formulate a consistent method for deleting 15332325SN/A // instructions from the instruction list 15342292SN/A // Remove the instruction from the list. 15352292SN/A removeList.push(instIt); 15362292SN/A } 15372292SN/A} 15382292SN/A 15392292SN/Atemplate <class Impl> 15402292SN/Avoid 15412292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 15422292SN/A{ 15432292SN/A while (!removeList.empty()) { 15442733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 15457720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 15462292SN/A (*removeList.front())->threadNumber, 15472292SN/A (*removeList.front())->seqNum, 15487720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 15492292SN/A 15502292SN/A instList.erase(removeList.front()); 15512292SN/A 15522292SN/A removeList.pop(); 15531062SN/A } 15541062SN/A 15552292SN/A removeInstsThisCycle = false; 15561062SN/A} 15572325SN/A/* 15581062SN/Atemplate <class Impl> 15591062SN/Avoid 15601755SN/AFullO3CPU<Impl>::removeAllInsts() 15611060SN/A{ 15621060SN/A instList.clear(); 15631060SN/A} 15642325SN/A*/ 15651060SN/Atemplate <class Impl> 15661060SN/Avoid 15671755SN/AFullO3CPU<Impl>::dumpInsts() 15681060SN/A{ 15691060SN/A int num = 0; 15701060SN/A 15712292SN/A ListIt inst_list_it = instList.begin(); 15722292SN/A 15732292SN/A cprintf("Dumping Instruction List\n"); 15742292SN/A 15752292SN/A while (inst_list_it != instList.end()) { 15762292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 15772292SN/A "Squashed:%i\n\n", 15787720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 15792292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 15802292SN/A (*inst_list_it)->isSquashed()); 15811060SN/A inst_list_it++; 15821060SN/A ++num; 15831060SN/A } 15841060SN/A} 15852325SN/A/* 15861060SN/Atemplate <class Impl> 15871060SN/Avoid 15881755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 15891060SN/A{ 15901060SN/A iew.wakeDependents(inst); 15911060SN/A} 15922325SN/A*/ 15932292SN/Atemplate <class Impl> 15942292SN/Avoid 15952292SN/AFullO3CPU<Impl>::wakeCPU() 15962292SN/A{ 15972325SN/A if (activityRec.active() || tickEvent.scheduled()) { 15982325SN/A DPRINTF(Activity, "CPU already running.\n"); 15992292SN/A return; 16002292SN/A } 16012292SN/A 16022325SN/A DPRINTF(Activity, "Waking up CPU\n"); 16032325SN/A 16047823Ssteve.reinhardt@amd.com idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle); 16057823Ssteve.reinhardt@amd.com numCycles += tickToCycles((curTick() - 1) - lastRunningCycle); 16062292SN/A 16075606Snate@binkert.org schedule(tickEvent, nextCycle()); 16082292SN/A} 16092292SN/A 16105807Snate@binkert.org#if FULL_SYSTEM 16115807Snate@binkert.orgtemplate <class Impl> 16125807Snate@binkert.orgvoid 16135807Snate@binkert.orgFullO3CPU<Impl>::wakeup() 16145807Snate@binkert.org{ 16155807Snate@binkert.org if (this->thread[0]->status() != ThreadContext::Suspended) 16165807Snate@binkert.org return; 16175807Snate@binkert.org 16185807Snate@binkert.org this->wakeCPU(); 16195807Snate@binkert.org 16205807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 16215807Snate@binkert.org this->threadContexts[0]->activate(); 16225807Snate@binkert.org} 16235807Snate@binkert.org#endif 16245807Snate@binkert.org 16252292SN/Atemplate <class Impl> 16266221Snate@binkert.orgThreadID 16272292SN/AFullO3CPU<Impl>::getFreeTid() 16282292SN/A{ 16296221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 16306221Snate@binkert.org if (!tids[tid]) { 16316221Snate@binkert.org tids[tid] = true; 16326221Snate@binkert.org return tid; 16332292SN/A } 16342292SN/A } 16352292SN/A 16366221Snate@binkert.org return InvalidThreadID; 16372292SN/A} 16382292SN/A 16392292SN/Atemplate <class Impl> 16402292SN/Avoid 16412292SN/AFullO3CPU<Impl>::doContextSwitch() 16422292SN/A{ 16432292SN/A if (contextSwitch) { 16442292SN/A 16452292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 16462292SN/A 16476221Snate@binkert.org ThreadID size = cpuWaitList.size(); 16486221Snate@binkert.org for (ThreadID tid = 0; tid < size; tid++) { 16492292SN/A activateWhenReady(tid); 16502292SN/A } 16512292SN/A 16522292SN/A if (cpuWaitList.size() == 0) 16532292SN/A contextSwitch = true; 16542292SN/A } 16552292SN/A} 16562292SN/A 16572292SN/Atemplate <class Impl> 16582292SN/Avoid 16592292SN/AFullO3CPU<Impl>::updateThreadPriority() 16602292SN/A{ 16616221Snate@binkert.org if (activeThreads.size() > 1) { 16622292SN/A //DEFAULT TO ROUND ROBIN SCHEME 16632292SN/A //e.g. Move highest priority to end of thread list 16646221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 16656221Snate@binkert.org list<ThreadID>::iterator list_end = activeThreads.end(); 16662292SN/A 16672292SN/A unsigned high_thread = *list_begin; 16682292SN/A 16692292SN/A activeThreads.erase(list_begin); 16702292SN/A 16712292SN/A activeThreads.push_back(high_thread); 16722292SN/A } 16732292SN/A} 16741060SN/A 16751755SN/A// Forward declaration of FullO3CPU. 16762818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1677