cpu.cc revision 7823
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 336658Snate@binkert.org#include "config/the_isa.hh" 342733Sktlim@umich.edu#include "config/use_checker.hh" 354762Snate@binkert.org#include "cpu/activity.hh" 364762Snate@binkert.org#include "cpu/simple_thread.hh" 374762Snate@binkert.org#include "cpu/thread_context.hh" 384762Snate@binkert.org#include "cpu/o3/isa_specific.hh" 394762Snate@binkert.org#include "cpu/o3/cpu.hh" 405595Sgblack@eecs.umich.edu#include "cpu/o3/thread_context.hh" 414762Snate@binkert.org#include "enums/MemoryMode.hh" 424762Snate@binkert.org#include "sim/core.hh" 434762Snate@binkert.org#include "sim/stat_control.hh" 444762Snate@binkert.org 451858SN/A#if FULL_SYSTEM 462356SN/A#include "cpu/quiesce_event.hh" 471060SN/A#include "sim/system.hh" 481060SN/A#else 491060SN/A#include "sim/process.hh" 501060SN/A#endif 511060SN/A 522794Sktlim@umich.edu#if USE_CHECKER 532794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 542794Sktlim@umich.edu#endif 552794Sktlim@umich.edu 565702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 575702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 585702Ssaidi@eecs.umich.edu#endif 595702Ssaidi@eecs.umich.edu 605529Snate@binkert.orgclass BaseCPUParams; 615529Snate@binkert.org 622669Sktlim@umich.eduusing namespace TheISA; 636221Snate@binkert.orgusing namespace std; 641060SN/A 655529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 665712Shsul@eecs.umich.edu : BaseCPU(params) 671060SN/A{ 681060SN/A} 691060SN/A 702292SN/Avoid 712733Sktlim@umich.eduBaseO3CPU::regStats() 722292SN/A{ 732292SN/A BaseCPU::regStats(); 742292SN/A} 752292SN/A 761060SN/Atemplate <class Impl> 771755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 785606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 791060SN/A{ 801060SN/A} 811060SN/A 821060SN/Atemplate <class Impl> 831060SN/Avoid 841755SN/AFullO3CPU<Impl>::TickEvent::process() 851060SN/A{ 861060SN/A cpu->tick(); 871060SN/A} 881060SN/A 891060SN/Atemplate <class Impl> 901060SN/Aconst char * 915336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 921060SN/A{ 934873Sstever@eecs.umich.edu return "FullO3CPU tick"; 941060SN/A} 951060SN/A 961060SN/Atemplate <class Impl> 972829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 985606Snate@binkert.org : Event(CPU_Switch_Pri) 992829Sksewell@umich.edu{ 1002829Sksewell@umich.edu} 1012829Sksewell@umich.edu 1022829Sksewell@umich.edutemplate <class Impl> 1032829Sksewell@umich.eduvoid 1042829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 1052829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1062829Sksewell@umich.edu{ 1072829Sksewell@umich.edu tid = thread_num; 1082829Sksewell@umich.edu cpu = thread_cpu; 1092829Sksewell@umich.edu} 1102829Sksewell@umich.edu 1112829Sksewell@umich.edutemplate <class Impl> 1122829Sksewell@umich.eduvoid 1132829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1142829Sksewell@umich.edu{ 1152829Sksewell@umich.edu cpu->activateThread(tid); 1162829Sksewell@umich.edu} 1172829Sksewell@umich.edu 1182829Sksewell@umich.edutemplate <class Impl> 1192829Sksewell@umich.educonst char * 1205336Shines@cs.fsu.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1212829Sksewell@umich.edu{ 1224873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1232829Sksewell@umich.edu} 1242829Sksewell@umich.edu 1252829Sksewell@umich.edutemplate <class Impl> 1262875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1275606Snate@binkert.org : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1282875Sksewell@umich.edu{ 1292875Sksewell@umich.edu} 1302875Sksewell@umich.edu 1312875Sksewell@umich.edutemplate <class Impl> 1322875Sksewell@umich.eduvoid 1332875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1343859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1352875Sksewell@umich.edu{ 1362875Sksewell@umich.edu tid = thread_num; 1372875Sksewell@umich.edu cpu = thread_cpu; 1383859Sbinkertn@umich.edu remove = false; 1392875Sksewell@umich.edu} 1402875Sksewell@umich.edu 1412875Sksewell@umich.edutemplate <class Impl> 1422875Sksewell@umich.eduvoid 1432875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1442875Sksewell@umich.edu{ 1452875Sksewell@umich.edu cpu->deactivateThread(tid); 1463221Sktlim@umich.edu if (remove) 1473221Sktlim@umich.edu cpu->removeThread(tid); 1482875Sksewell@umich.edu} 1492875Sksewell@umich.edu 1502875Sksewell@umich.edutemplate <class Impl> 1512875Sksewell@umich.educonst char * 1525336Shines@cs.fsu.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 1532875Sksewell@umich.edu{ 1544873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 1552875Sksewell@umich.edu} 1562875Sksewell@umich.edu 1572875Sksewell@umich.edutemplate <class Impl> 1585595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 1592733Sktlim@umich.edu : BaseO3CPU(params), 1603781Sgblack@eecs.umich.edu itb(params->itb), 1613781Sgblack@eecs.umich.edu dtb(params->dtb), 1621060SN/A tickEvent(this), 1635737Scws3k@cs.virginia.edu#ifndef NDEBUG 1645737Scws3k@cs.virginia.edu instcount(0), 1655737Scws3k@cs.virginia.edu#endif 1662292SN/A removeInstsThisCycle(false), 1675595Sgblack@eecs.umich.edu fetch(this, params), 1685595Sgblack@eecs.umich.edu decode(this, params), 1695595Sgblack@eecs.umich.edu rename(this, params), 1705595Sgblack@eecs.umich.edu iew(this, params), 1715595Sgblack@eecs.umich.edu commit(this, params), 1721060SN/A 1735595Sgblack@eecs.umich.edu regFile(this, params->numPhysIntRegs, 1744329Sktlim@umich.edu params->numPhysFloatRegs), 1751060SN/A 1765529Snate@binkert.org freeList(params->numThreads, 1772292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1782292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1791060SN/A 1805595Sgblack@eecs.umich.edu rob(this, 1814329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 1822292SN/A params->smtROBPolicy, params->smtROBThreshold, 1835529Snate@binkert.org params->numThreads), 1841060SN/A 1855529Snate@binkert.org scoreboard(params->numThreads, 1862292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1872292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1886221Snate@binkert.org TheISA::NumMiscRegs * numThreads, 1892292SN/A TheISA::ZeroReg), 1901060SN/A 1912873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1922873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1932873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1942873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1952873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1965804Snate@binkert.org activityRec(name(), NumStages, 1972873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1982873Sktlim@umich.edu params->activity), 1991060SN/A 2001060SN/A globalSeqNum(1), 2011858SN/A#if FULL_SYSTEM 2022292SN/A system(params->system), 2031060SN/A#endif // FULL_SYSTEM 2042843Sktlim@umich.edu drainCount(0), 2056221Snate@binkert.org deferRegistration(params->defer_registration) 2061060SN/A{ 2073221Sktlim@umich.edu if (!deferRegistration) { 2083221Sktlim@umich.edu _status = Running; 2093221Sktlim@umich.edu } else { 2103221Sktlim@umich.edu _status = Idle; 2113221Sktlim@umich.edu } 2121681SN/A 2134598Sbinkertn@umich.edu#if USE_CHECKER 2142794Sktlim@umich.edu if (params->checker) { 2152316SN/A BaseCPU *temp_checker = params->checker; 2162316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2172316SN/A#if FULL_SYSTEM 2182316SN/A checker->setSystem(params->system); 2192316SN/A#endif 2204598Sbinkertn@umich.edu } else { 2214598Sbinkertn@umich.edu checker = NULL; 2224598Sbinkertn@umich.edu } 2232794Sktlim@umich.edu#endif // USE_CHECKER 2242316SN/A 2251858SN/A#if !FULL_SYSTEM 2266221Snate@binkert.org thread.resize(numThreads); 2276221Snate@binkert.org tids.resize(numThreads); 2281681SN/A#endif 2291681SN/A 2302325SN/A // The stages also need their CPU pointer setup. However this 2312325SN/A // must be done at the upper level CPU because they have pointers 2322325SN/A // to the upper level CPU, and not this FullO3CPU. 2331060SN/A 2342292SN/A // Set up Pointers to the activeThreads list for each stage 2352292SN/A fetch.setActiveThreads(&activeThreads); 2362292SN/A decode.setActiveThreads(&activeThreads); 2372292SN/A rename.setActiveThreads(&activeThreads); 2382292SN/A iew.setActiveThreads(&activeThreads); 2392292SN/A commit.setActiveThreads(&activeThreads); 2401060SN/A 2411060SN/A // Give each of the stages the time buffer they will use. 2421060SN/A fetch.setTimeBuffer(&timeBuffer); 2431060SN/A decode.setTimeBuffer(&timeBuffer); 2441060SN/A rename.setTimeBuffer(&timeBuffer); 2451060SN/A iew.setTimeBuffer(&timeBuffer); 2461060SN/A commit.setTimeBuffer(&timeBuffer); 2471060SN/A 2481060SN/A // Also setup each of the stages' queues. 2491060SN/A fetch.setFetchQueue(&fetchQueue); 2501060SN/A decode.setFetchQueue(&fetchQueue); 2512292SN/A commit.setFetchQueue(&fetchQueue); 2521060SN/A decode.setDecodeQueue(&decodeQueue); 2531060SN/A rename.setDecodeQueue(&decodeQueue); 2541060SN/A rename.setRenameQueue(&renameQueue); 2551060SN/A iew.setRenameQueue(&renameQueue); 2561060SN/A iew.setIEWQueue(&iewQueue); 2571060SN/A commit.setIEWQueue(&iewQueue); 2581060SN/A commit.setRenameQueue(&renameQueue); 2591060SN/A 2602292SN/A commit.setIEWStage(&iew); 2612292SN/A rename.setIEWStage(&iew); 2622292SN/A rename.setCommitStage(&commit); 2632292SN/A 2642292SN/A#if !FULL_SYSTEM 2656221Snate@binkert.org ThreadID active_threads = params->workload.size(); 2662831Sksewell@umich.edu 2672831Sksewell@umich.edu if (active_threads > Impl::MaxThreads) { 2682831Sksewell@umich.edu panic("Workload Size too large. Increase the 'MaxThreads'" 2692831Sksewell@umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2702831Sksewell@umich.edu "edit your workload size."); 2712831Sksewell@umich.edu } 2722292SN/A#else 2736221Snate@binkert.org ThreadID active_threads = 1; 2742292SN/A#endif 2752292SN/A 2762316SN/A //Make Sure That this a Valid Architeture 2772292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2782292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2792292SN/A 2802292SN/A rename.setScoreboard(&scoreboard); 2812292SN/A iew.setScoreboard(&scoreboard); 2822292SN/A 2831060SN/A // Setup the rename map for whichever stages need it. 2842292SN/A PhysRegIndex lreg_idx = 0; 2852292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2861060SN/A 2876221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2882307SN/A bool bindRegs = (tid <= active_threads - 1); 2892292SN/A 2902292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2912292SN/A params->numPhysIntRegs, 2922325SN/A lreg_idx, //Index for Logical. Regs 2932292SN/A 2942292SN/A TheISA::NumFloatRegs, 2952292SN/A params->numPhysFloatRegs, 2962325SN/A freg_idx, //Index for Float Regs 2972292SN/A 2982292SN/A TheISA::NumMiscRegs, 2992292SN/A 3002292SN/A TheISA::ZeroReg, 3012292SN/A TheISA::ZeroReg, 3022292SN/A 3032292SN/A tid, 3042292SN/A false); 3052292SN/A 3062292SN/A renameMap[tid].init(TheISA::NumIntRegs, 3072292SN/A params->numPhysIntRegs, 3082325SN/A lreg_idx, //Index for Logical. Regs 3092292SN/A 3102292SN/A TheISA::NumFloatRegs, 3112292SN/A params->numPhysFloatRegs, 3122325SN/A freg_idx, //Index for Float Regs 3132292SN/A 3142292SN/A TheISA::NumMiscRegs, 3152292SN/A 3162292SN/A TheISA::ZeroReg, 3172292SN/A TheISA::ZeroReg, 3182292SN/A 3192292SN/A tid, 3202292SN/A bindRegs); 3213221Sktlim@umich.edu 3223221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3233221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3242292SN/A } 3252292SN/A 3262292SN/A rename.setRenameMap(renameMap); 3272292SN/A commit.setRenameMap(commitRenameMap); 3282292SN/A 3292292SN/A // Give renameMap & rename stage access to the freeList; 3306221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3316221Snate@binkert.org renameMap[tid].setFreeList(&freeList); 3321060SN/A rename.setFreeList(&freeList); 3332292SN/A 3341060SN/A // Setup the ROB for whichever stages need it. 3351060SN/A commit.setROB(&rob); 3362292SN/A 3377823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 3382292SN/A 3392829Sksewell@umich.edu lastActivatedCycle = -1; 3406221Snate@binkert.org#if 0 3413093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3426221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3436221Snate@binkert.org globalSeqNum[tid] = 1; 3446221Snate@binkert.org#endif 3453093Sksewell@umich.edu 3462292SN/A contextSwitch = false; 3475595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3485595Sgblack@eecs.umich.edu 3495595Sgblack@eecs.umich.edu // Setup any thread state. 3505595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 3515595Sgblack@eecs.umich.edu 3526221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 3535595Sgblack@eecs.umich.edu#if FULL_SYSTEM 3545595Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 3555595Sgblack@eecs.umich.edu assert(this->numThreads == 1); 3566221Snate@binkert.org this->thread[tid] = new Thread(this, 0); 3575595Sgblack@eecs.umich.edu#else 3586221Snate@binkert.org if (tid < params->workload.size()) { 3595595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 3606221Snate@binkert.org tid, this->thread[tid]); 3616221Snate@binkert.org this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3625595Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3636331Sgblack@eecs.umich.edu tid, params->workload[tid]); 3645595Sgblack@eecs.umich.edu 3656221Snate@binkert.org //usedTids[tid] = true; 3666221Snate@binkert.org //threadMap[tid] = tid; 3675595Sgblack@eecs.umich.edu } else { 3685595Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 3695595Sgblack@eecs.umich.edu //when scheduling threads to CPU 3705595Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 3715595Sgblack@eecs.umich.edu 3726221Snate@binkert.org this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3735595Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3746331Sgblack@eecs.umich.edu tid, dummy_proc); 3756221Snate@binkert.org //usedTids[tid] = false; 3765595Sgblack@eecs.umich.edu } 3775595Sgblack@eecs.umich.edu#endif // !FULL_SYSTEM 3785595Sgblack@eecs.umich.edu 3795595Sgblack@eecs.umich.edu ThreadContext *tc; 3805595Sgblack@eecs.umich.edu 3815595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 3825595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 3835595Sgblack@eecs.umich.edu 3845595Sgblack@eecs.umich.edu tc = o3_tc; 3855595Sgblack@eecs.umich.edu 3865595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 3875595Sgblack@eecs.umich.edu // CheckerThreadContext. 3885595Sgblack@eecs.umich.edu#if USE_CHECKER 3895595Sgblack@eecs.umich.edu if (params->checker) { 3905595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 3915595Sgblack@eecs.umich.edu o3_tc, this->checker); 3925595Sgblack@eecs.umich.edu } 3935595Sgblack@eecs.umich.edu#endif 3945595Sgblack@eecs.umich.edu 3955595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 3965595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 3976221Snate@binkert.org o3_tc->thread = this->thread[tid]; 3985595Sgblack@eecs.umich.edu 3995595Sgblack@eecs.umich.edu#if FULL_SYSTEM 4005595Sgblack@eecs.umich.edu // Setup quiesce event. 4016221Snate@binkert.org this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 4025595Sgblack@eecs.umich.edu#endif 4035595Sgblack@eecs.umich.edu // Give the thread the TC. 4046221Snate@binkert.org this->thread[tid]->tc = tc; 4055595Sgblack@eecs.umich.edu 4065595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4075595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4085595Sgblack@eecs.umich.edu } 4095595Sgblack@eecs.umich.edu 4106221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4116221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4125595Sgblack@eecs.umich.edu 4135595Sgblack@eecs.umich.edu lockAddr = 0; 4145595Sgblack@eecs.umich.edu lockFlag = false; 4151060SN/A} 4161060SN/A 4171060SN/Atemplate <class Impl> 4181755SN/AFullO3CPU<Impl>::~FullO3CPU() 4191060SN/A{ 4201060SN/A} 4211060SN/A 4221060SN/Atemplate <class Impl> 4231060SN/Avoid 4245595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4251062SN/A{ 4262733Sktlim@umich.edu BaseO3CPU::regStats(); 4272292SN/A 4282733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4292292SN/A timesIdled 4302292SN/A .name(name() + ".timesIdled") 4312292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4322292SN/A " unscheduled itself") 4332292SN/A .prereq(timesIdled); 4342292SN/A 4352292SN/A idleCycles 4362292SN/A .name(name() + ".idleCycles") 4372292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4382292SN/A "to idling") 4392292SN/A .prereq(idleCycles); 4402292SN/A 4412292SN/A // Number of Instructions simulated 4422292SN/A // -------------------------------- 4432292SN/A // Should probably be in Base CPU but need templated 4442292SN/A // MaxThreads so put in here instead 4452292SN/A committedInsts 4462292SN/A .init(numThreads) 4472292SN/A .name(name() + ".committedInsts") 4482292SN/A .desc("Number of Instructions Simulated"); 4492292SN/A 4502292SN/A totalCommittedInsts 4512292SN/A .name(name() + ".committedInsts_total") 4522292SN/A .desc("Number of Instructions Simulated"); 4532292SN/A 4542292SN/A cpi 4552292SN/A .name(name() + ".cpi") 4562292SN/A .desc("CPI: Cycles Per Instruction") 4572292SN/A .precision(6); 4584392Sktlim@umich.edu cpi = numCycles / committedInsts; 4592292SN/A 4602292SN/A totalCpi 4612292SN/A .name(name() + ".cpi_total") 4622292SN/A .desc("CPI: Total CPI of All Threads") 4632292SN/A .precision(6); 4644392Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 4652292SN/A 4662292SN/A ipc 4672292SN/A .name(name() + ".ipc") 4682292SN/A .desc("IPC: Instructions Per Cycle") 4692292SN/A .precision(6); 4704392Sktlim@umich.edu ipc = committedInsts / numCycles; 4712292SN/A 4722292SN/A totalIpc 4732292SN/A .name(name() + ".ipc_total") 4742292SN/A .desc("IPC: Total IPC of All Threads") 4752292SN/A .precision(6); 4764392Sktlim@umich.edu totalIpc = totalCommittedInsts / numCycles; 4772292SN/A 4785595Sgblack@eecs.umich.edu this->fetch.regStats(); 4795595Sgblack@eecs.umich.edu this->decode.regStats(); 4805595Sgblack@eecs.umich.edu this->rename.regStats(); 4815595Sgblack@eecs.umich.edu this->iew.regStats(); 4825595Sgblack@eecs.umich.edu this->commit.regStats(); 4831062SN/A} 4841062SN/A 4851062SN/Atemplate <class Impl> 4862871Sktlim@umich.eduPort * 4872871Sktlim@umich.eduFullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 4882871Sktlim@umich.edu{ 4892871Sktlim@umich.edu if (if_name == "dcache_port") 4902871Sktlim@umich.edu return iew.getDcachePort(); 4912871Sktlim@umich.edu else if (if_name == "icache_port") 4922871Sktlim@umich.edu return fetch.getIcachePort(); 4932871Sktlim@umich.edu else 4942871Sktlim@umich.edu panic("No Such Port\n"); 4952871Sktlim@umich.edu} 4962871Sktlim@umich.edu 4972871Sktlim@umich.edutemplate <class Impl> 4981062SN/Avoid 4991755SN/AFullO3CPU<Impl>::tick() 5001060SN/A{ 5012733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5021060SN/A 5032292SN/A ++numCycles; 5042292SN/A 5052325SN/A// activity = false; 5062292SN/A 5072292SN/A //Tick each of the stages 5081060SN/A fetch.tick(); 5091060SN/A 5101060SN/A decode.tick(); 5111060SN/A 5121060SN/A rename.tick(); 5131060SN/A 5141060SN/A iew.tick(); 5151060SN/A 5161060SN/A commit.tick(); 5171060SN/A 5182292SN/A#if !FULL_SYSTEM 5192292SN/A doContextSwitch(); 5202292SN/A#endif 5212292SN/A 5222292SN/A // Now advance the time buffers 5231060SN/A timeBuffer.advance(); 5241060SN/A 5251060SN/A fetchQueue.advance(); 5261060SN/A decodeQueue.advance(); 5271060SN/A renameQueue.advance(); 5281060SN/A iewQueue.advance(); 5291060SN/A 5302325SN/A activityRec.advance(); 5312292SN/A 5322292SN/A if (removeInstsThisCycle) { 5332292SN/A cleanUpRemovedInsts(); 5342292SN/A } 5352292SN/A 5362325SN/A if (!tickEvent.scheduled()) { 5372867Sktlim@umich.edu if (_status == SwitchedOut || 5382905Sktlim@umich.edu getState() == SimObject::Drained) { 5393226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 5402325SN/A // increment stat 5417823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 5423221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 5433226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 5447823Ssteve.reinhardt@amd.com lastRunningCycle = curTick(); 5452325SN/A timesIdled++; 5462325SN/A } else { 5477823Ssteve.reinhardt@amd.com schedule(tickEvent, nextCycle(curTick() + ticks(1))); 5483226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 5492325SN/A } 5502292SN/A } 5512292SN/A 5522292SN/A#if !FULL_SYSTEM 5532292SN/A updateThreadPriority(); 5542292SN/A#endif 5551060SN/A} 5561060SN/A 5571060SN/Atemplate <class Impl> 5581060SN/Avoid 5591755SN/AFullO3CPU<Impl>::init() 5601060SN/A{ 5615714Shsul@eecs.umich.edu BaseCPU::init(); 5621060SN/A 5632292SN/A // Set inSyscall so that the CPU doesn't squash when initially 5642292SN/A // setting up registers. 5656221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) 5666221Snate@binkert.org thread[tid]->inSyscall = true; 5672292SN/A 5686034Ssteve.reinhardt@amd.com#if FULL_SYSTEM 5696221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 5702680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 5716034Ssteve.reinhardt@amd.com TheISA::initCPU(src_tc, src_tc->contextId()); 5726034Ssteve.reinhardt@amd.com } 5731681SN/A#endif 5742292SN/A 5752292SN/A // Clear inSyscall. 5766221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 5776221Snate@binkert.org thread[tid]->inSyscall = false; 5782292SN/A 5792316SN/A // Initialize stages. 5802292SN/A fetch.initStage(); 5812292SN/A iew.initStage(); 5822292SN/A rename.initStage(); 5832292SN/A commit.initStage(); 5842292SN/A 5852292SN/A commit.setThreads(thread); 5862292SN/A} 5872292SN/A 5882292SN/Atemplate <class Impl> 5892292SN/Avoid 5906221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 5912875Sksewell@umich.edu{ 5926221Snate@binkert.org list<ThreadID>::iterator isActive = 5935314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 5942875Sksewell@umich.edu 5953226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 5963226Sktlim@umich.edu 5972875Sksewell@umich.edu if (isActive == activeThreads.end()) { 5982875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 5992875Sksewell@umich.edu tid); 6002875Sksewell@umich.edu 6012875Sksewell@umich.edu activeThreads.push_back(tid); 6022875Sksewell@umich.edu } 6032875Sksewell@umich.edu} 6042875Sksewell@umich.edu 6052875Sksewell@umich.edutemplate <class Impl> 6062875Sksewell@umich.eduvoid 6076221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 6082875Sksewell@umich.edu{ 6092875Sksewell@umich.edu //Remove From Active List, if Active 6106221Snate@binkert.org list<ThreadID>::iterator thread_it = 6115314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6122875Sksewell@umich.edu 6133226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 6143226Sktlim@umich.edu 6152875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 6162875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6172875Sksewell@umich.edu tid); 6182875Sksewell@umich.edu activeThreads.erase(thread_it); 6192875Sksewell@umich.edu } 6202875Sksewell@umich.edu} 6212875Sksewell@umich.edu 6222875Sksewell@umich.edutemplate <class Impl> 6236221Snate@binkert.orgCounter 6246221Snate@binkert.orgFullO3CPU<Impl>::totalInstructions() const 6256221Snate@binkert.org{ 6266221Snate@binkert.org Counter total(0); 6276221Snate@binkert.org 6286221Snate@binkert.org ThreadID size = thread.size(); 6296221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 6306221Snate@binkert.org total += thread[i]->numInst; 6316221Snate@binkert.org 6326221Snate@binkert.org return total; 6336221Snate@binkert.org} 6346221Snate@binkert.org 6356221Snate@binkert.orgtemplate <class Impl> 6362875Sksewell@umich.eduvoid 6376221Snate@binkert.orgFullO3CPU<Impl>::activateContext(ThreadID tid, int delay) 6382875Sksewell@umich.edu{ 6392875Sksewell@umich.edu // Needs to set each stage to running as well. 6402875Sksewell@umich.edu if (delay){ 6412875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 6427823Ssteve.reinhardt@amd.com "on cycle %d\n", tid, curTick() + ticks(delay)); 6432875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 6442875Sksewell@umich.edu } else { 6452875Sksewell@umich.edu activateThread(tid); 6462875Sksewell@umich.edu } 6472875Sksewell@umich.edu 6487823Ssteve.reinhardt@amd.com if (lastActivatedCycle < curTick()) { 6492875Sksewell@umich.edu scheduleTickEvent(delay); 6502875Sksewell@umich.edu 6512875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 6522875Sksewell@umich.edu // deschedule itself. 6532875Sksewell@umich.edu activityRec.activity(); 6542875Sksewell@umich.edu fetch.wakeFromQuiesce(); 6552875Sksewell@umich.edu 6567823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 6572875Sksewell@umich.edu 6582875Sksewell@umich.edu _status = Running; 6592875Sksewell@umich.edu } 6602875Sksewell@umich.edu} 6612875Sksewell@umich.edu 6622875Sksewell@umich.edutemplate <class Impl> 6633221Sktlim@umich.edubool 6646221Snate@binkert.orgFullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay) 6652875Sksewell@umich.edu{ 6662875Sksewell@umich.edu // Schedule removal of thread data from CPU 6672875Sksewell@umich.edu if (delay){ 6682875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 6697823Ssteve.reinhardt@amd.com "on cycle %d\n", tid, curTick() + ticks(delay)); 6703221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 6713221Sktlim@umich.edu return false; 6722875Sksewell@umich.edu } else { 6732875Sksewell@umich.edu deactivateThread(tid); 6743221Sktlim@umich.edu if (remove) 6753221Sktlim@umich.edu removeThread(tid); 6763221Sktlim@umich.edu return true; 6772875Sksewell@umich.edu } 6782875Sksewell@umich.edu} 6792875Sksewell@umich.edu 6802875Sksewell@umich.edutemplate <class Impl> 6812875Sksewell@umich.eduvoid 6826221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 6832875Sksewell@umich.edu{ 6842875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 6853221Sktlim@umich.edu bool deallocated = deallocateContext(tid, false, 1); 6863221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 6875570Snate@binkert.org if ((activeThreads.size() == 1 && !deallocated) || 6883859Sbinkertn@umich.edu activeThreads.size() == 0) 6892910Sksewell@umich.edu unscheduleTickEvent(); 6902875Sksewell@umich.edu _status = Idle; 6912875Sksewell@umich.edu} 6922875Sksewell@umich.edu 6932875Sksewell@umich.edutemplate <class Impl> 6942875Sksewell@umich.eduvoid 6956221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 6962875Sksewell@umich.edu{ 6972910Sksewell@umich.edu //For now, this is the same as deallocate 6982910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 6993221Sktlim@umich.edu deallocateContext(tid, true, 1); 7002875Sksewell@umich.edu} 7012875Sksewell@umich.edu 7022875Sksewell@umich.edutemplate <class Impl> 7032875Sksewell@umich.eduvoid 7046221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 7052292SN/A{ 7062847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 7072292SN/A // Will change now that the PC and thread state is internal to the CPU 7082683Sktlim@umich.edu // and not in the ThreadContext. 7092292SN/A#if FULL_SYSTEM 7102680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 7112292SN/A#else 7122847Sksewell@umich.edu ThreadContext *src_tc = tcBase(tid); 7132292SN/A#endif 7142292SN/A 7152292SN/A //Bind Int Regs to Rename Map 7162292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7172292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 7182292SN/A 7192292SN/A renameMap[tid].setEntry(ireg,phys_reg); 7202292SN/A scoreboard.setReg(phys_reg); 7212292SN/A } 7222292SN/A 7232292SN/A //Bind Float Regs to Rename Map 7242292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 7252292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 7262292SN/A 7272292SN/A renameMap[tid].setEntry(freg,phys_reg); 7282292SN/A scoreboard.setReg(phys_reg); 7292292SN/A } 7302292SN/A 7312292SN/A //Copy Thread Data Into RegFile 7322847Sksewell@umich.edu //this->copyFromTC(tid); 7332292SN/A 7342847Sksewell@umich.edu //Set PC/NPC/NNPC 7357720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 7362292SN/A 7372680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 7382292SN/A 7392292SN/A activateContext(tid,1); 7402292SN/A 7412292SN/A //Reset ROB/IQ/LSQ Entries 7422292SN/A commit.rob->resetEntries(); 7432292SN/A iew.resetEntries(); 7442292SN/A} 7452292SN/A 7462292SN/Atemplate <class Impl> 7472292SN/Avoid 7486221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 7492292SN/A{ 7502877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 7512847Sksewell@umich.edu 7522847Sksewell@umich.edu // Copy Thread Data From RegFile 7532847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 7545364Sksewell@umich.edu // this->copyToTC(tid); 7555364Sksewell@umich.edu 7565364Sksewell@umich.edu 7575364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 7585364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 7595364Sksewell@umich.edu // in SMT workloads. 7602847Sksewell@umich.edu 7612847Sksewell@umich.edu // Unbind Int Regs from Rename Map 7622292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7632292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 7642292SN/A 7652292SN/A scoreboard.unsetReg(phys_reg); 7662292SN/A freeList.addReg(phys_reg); 7672292SN/A } 7682292SN/A 7692847Sksewell@umich.edu // Unbind Float Regs from Rename Map 7705362Sksewell@umich.edu for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 7712292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 7722292SN/A 7732292SN/A scoreboard.unsetReg(phys_reg); 7742292SN/A freeList.addReg(phys_reg); 7752292SN/A } 7762292SN/A 7772847Sksewell@umich.edu // Squash Throughout Pipeline 7782935Sksewell@umich.edu InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; 7797720Sgblack@eecs.umich.edu fetch.squash(0, squash_seq_num, tid); 7802292SN/A decode.squash(tid); 7812935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 7822875Sksewell@umich.edu iew.squash(tid); 7835363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 7842935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 7852292SN/A 7865362Sksewell@umich.edu 7875362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 7882292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 7892292SN/A 7902847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 7913229Sktlim@umich.edu 7923229Sktlim@umich.edu // Commented out for now. This should be possible to do by 7933229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 7943229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 7953229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 7963229Sktlim@umich.edu/* 7972292SN/A if (activeThreads.size() >= 1) { 7982292SN/A commit.rob->resetEntries(); 7992292SN/A iew.resetEntries(); 8002292SN/A } 8013229Sktlim@umich.edu*/ 8022292SN/A} 8032292SN/A 8042292SN/A 8052292SN/Atemplate <class Impl> 8062292SN/Avoid 8076221Snate@binkert.orgFullO3CPU<Impl>::activateWhenReady(ThreadID tid) 8082292SN/A{ 8092733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 8102292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 8112292SN/A tid); 8122292SN/A 8132292SN/A bool ready = true; 8142292SN/A 8152292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 8162733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8172292SN/A "Phys. Int. Regs.\n", 8182292SN/A tid); 8192292SN/A ready = false; 8202292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 8212733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8222292SN/A "Phys. Float. Regs.\n", 8232292SN/A tid); 8242292SN/A ready = false; 8252292SN/A } else if (commit.rob->numFreeEntries() >= 8262292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 8272733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8282292SN/A "ROB entries.\n", 8292292SN/A tid); 8302292SN/A ready = false; 8312292SN/A } else if (iew.instQueue.numFreeEntries() >= 8322292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 8332733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8342292SN/A "IQ entries.\n", 8352292SN/A tid); 8362292SN/A ready = false; 8372292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 8382292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 8392733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8402292SN/A "LSQ entries.\n", 8412292SN/A tid); 8422292SN/A ready = false; 8432292SN/A } 8442292SN/A 8452292SN/A if (ready) { 8462292SN/A insertThread(tid); 8472292SN/A 8482292SN/A contextSwitch = false; 8492292SN/A 8502292SN/A cpuWaitList.remove(tid); 8512292SN/A } else { 8522292SN/A suspendContext(tid); 8532292SN/A 8542292SN/A //blocks fetch 8552292SN/A contextSwitch = true; 8562292SN/A 8572875Sksewell@umich.edu //@todo: dont always add to waitlist 8582292SN/A //do waitlist 8592292SN/A cpuWaitList.push_back(tid); 8601060SN/A } 8611060SN/A} 8621060SN/A 8634192Sktlim@umich.edu#if FULL_SYSTEM 8644192Sktlim@umich.edutemplate <class Impl> 8655595Sgblack@eecs.umich.eduFault 8666221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 8675702Ssaidi@eecs.umich.edu{ 8685702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 8695702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 8705702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 8715702Ssaidi@eecs.umich.edu 8725702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 8735702Ssaidi@eecs.umich.edu 8745702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 8755702Ssaidi@eecs.umich.edu#endif 8765702Ssaidi@eecs.umich.edu return NoFault; 8775702Ssaidi@eecs.umich.edu} 8785702Ssaidi@eecs.umich.edu 8795702Ssaidi@eecs.umich.edutemplate <class Impl> 8805702Ssaidi@eecs.umich.edubool 8816221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 8825702Ssaidi@eecs.umich.edu{ 8835702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 8845702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 8855702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 8865702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 8875702Ssaidi@eecs.umich.edu 8885702Ssaidi@eecs.umich.edu switch (palFunc) { 8895702Ssaidi@eecs.umich.edu case PAL::halt: 8905702Ssaidi@eecs.umich.edu halt(); 8915702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 8925702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 8935702Ssaidi@eecs.umich.edu break; 8945702Ssaidi@eecs.umich.edu 8955702Ssaidi@eecs.umich.edu case PAL::bpt: 8965702Ssaidi@eecs.umich.edu case PAL::bugchk: 8975702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 8985702Ssaidi@eecs.umich.edu return false; 8995702Ssaidi@eecs.umich.edu break; 9005702Ssaidi@eecs.umich.edu } 9015702Ssaidi@eecs.umich.edu#endif 9025702Ssaidi@eecs.umich.edu return true; 9035702Ssaidi@eecs.umich.edu} 9045702Ssaidi@eecs.umich.edu 9055702Ssaidi@eecs.umich.edutemplate <class Impl> 9065702Ssaidi@eecs.umich.eduFault 9075595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 9085595Sgblack@eecs.umich.edu{ 9095595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 9105647Sgblack@eecs.umich.edu return this->interrupts->getInterrupt(this->threadContexts[0]); 9115595Sgblack@eecs.umich.edu} 9125595Sgblack@eecs.umich.edu 9135595Sgblack@eecs.umich.edutemplate <class Impl> 9145595Sgblack@eecs.umich.eduvoid 9155595Sgblack@eecs.umich.eduFullO3CPU<Impl>::processInterrupts(Fault interrupt) 9165595Sgblack@eecs.umich.edu{ 9175595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 9185595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 9195595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 9205595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 9215595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 9225595Sgblack@eecs.umich.edu 9235595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 9245647Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 9255595Sgblack@eecs.umich.edu 9265595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 9277684Sgblack@eecs.umich.edu this->trap(interrupt, 0, NULL); 9285595Sgblack@eecs.umich.edu} 9295595Sgblack@eecs.umich.edu 9305595Sgblack@eecs.umich.edutemplate <class Impl> 9315595Sgblack@eecs.umich.eduvoid 9324192Sktlim@umich.eduFullO3CPU<Impl>::updateMemPorts() 9334192Sktlim@umich.edu{ 9344192Sktlim@umich.edu // Update all ThreadContext's memory ports (Functional/Virtual 9354192Sktlim@umich.edu // Ports) 9366221Snate@binkert.org ThreadID size = thread.size(); 9376221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) 9385497Ssaidi@eecs.umich.edu thread[i]->connectMemPorts(thread[i]->getTC()); 9394192Sktlim@umich.edu} 9404192Sktlim@umich.edu#endif 9414192Sktlim@umich.edu 9421060SN/Atemplate <class Impl> 9432852Sktlim@umich.eduvoid 9447684Sgblack@eecs.umich.eduFullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst) 9455595Sgblack@eecs.umich.edu{ 9465595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 9477684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 9485595Sgblack@eecs.umich.edu} 9495595Sgblack@eecs.umich.edu 9505595Sgblack@eecs.umich.edu#if !FULL_SYSTEM 9515595Sgblack@eecs.umich.edu 9525595Sgblack@eecs.umich.edutemplate <class Impl> 9535595Sgblack@eecs.umich.eduvoid 9546221Snate@binkert.orgFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 9555595Sgblack@eecs.umich.edu{ 9565595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 9575595Sgblack@eecs.umich.edu 9585595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 9595595Sgblack@eecs.umich.edu 9605595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 9615595Sgblack@eecs.umich.edu // instruction. 9625595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 9635595Sgblack@eecs.umich.edu 9645595Sgblack@eecs.umich.edu // Execute the actual syscall. 9655595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 9665595Sgblack@eecs.umich.edu 9675595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 9685595Sgblack@eecs.umich.edu // incrementing it. 9695595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 9705595Sgblack@eecs.umich.edu} 9715595Sgblack@eecs.umich.edu 9725595Sgblack@eecs.umich.edu#endif 9735595Sgblack@eecs.umich.edu 9745595Sgblack@eecs.umich.edutemplate <class Impl> 9755595Sgblack@eecs.umich.eduvoid 9762864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 9772864Sktlim@umich.edu{ 9782918Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 9792918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 9802864Sktlim@umich.edu BaseCPU::serialize(os); 9812864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 9822864Sktlim@umich.edu tickEvent.serialize(os); 9832864Sktlim@umich.edu 9842864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 9852864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 9862864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 9872864Sktlim@umich.edu static SimpleThread temp; 9882864Sktlim@umich.edu 9896221Snate@binkert.org ThreadID size = thread.size(); 9906221Snate@binkert.org for (ThreadID i = 0; i < size; i++) { 9912864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 9922864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 9932864Sktlim@umich.edu temp.serialize(os); 9942864Sktlim@umich.edu } 9952864Sktlim@umich.edu} 9962864Sktlim@umich.edu 9972864Sktlim@umich.edutemplate <class Impl> 9982864Sktlim@umich.eduvoid 9992864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 10002864Sktlim@umich.edu{ 10012918Sktlim@umich.edu SimObject::State so_state; 10022918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 10032864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 10042864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 10052864Sktlim@umich.edu 10062864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10072864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 10082864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 10092864Sktlim@umich.edu static SimpleThread temp; 10102864Sktlim@umich.edu 10116221Snate@binkert.org ThreadID size = thread.size(); 10126221Snate@binkert.org for (ThreadID i = 0; i < size; i++) { 10132864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10142864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 10152864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 10162864Sktlim@umich.edu } 10172864Sktlim@umich.edu} 10182864Sktlim@umich.edu 10192864Sktlim@umich.edutemplate <class Impl> 10202905Sktlim@umich.eduunsigned int 10212843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 10221060SN/A{ 10233125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 10243512Sktlim@umich.edu 10253512Sktlim@umich.edu // If the CPU isn't doing anything, then return immediately. 10263512Sktlim@umich.edu if (_status == Idle || _status == SwitchedOut) { 10273512Sktlim@umich.edu return 0; 10283512Sktlim@umich.edu } 10293512Sktlim@umich.edu 10302843Sktlim@umich.edu drainCount = 0; 10312843Sktlim@umich.edu fetch.drain(); 10322843Sktlim@umich.edu decode.drain(); 10332843Sktlim@umich.edu rename.drain(); 10342843Sktlim@umich.edu iew.drain(); 10352843Sktlim@umich.edu commit.drain(); 10362325SN/A 10372325SN/A // Wake the CPU and record activity so everything can drain out if 10382863Sktlim@umich.edu // the CPU was not able to immediately drain. 10392905Sktlim@umich.edu if (getState() != SimObject::Drained) { 10402864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 10412864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 10422864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 10432864Sktlim@umich.edu // process on the drain event. 10442864Sktlim@umich.edu drainEvent = drain_event; 10452843Sktlim@umich.edu 10462863Sktlim@umich.edu wakeCPU(); 10472863Sktlim@umich.edu activityRec.activity(); 10482852Sktlim@umich.edu 10492905Sktlim@umich.edu return 1; 10502863Sktlim@umich.edu } else { 10512905Sktlim@umich.edu return 0; 10522863Sktlim@umich.edu } 10532316SN/A} 10542310SN/A 10552316SN/Atemplate <class Impl> 10562316SN/Avoid 10572843Sktlim@umich.eduFullO3CPU<Impl>::resume() 10582316SN/A{ 10592843Sktlim@umich.edu fetch.resume(); 10602843Sktlim@umich.edu decode.resume(); 10612843Sktlim@umich.edu rename.resume(); 10622843Sktlim@umich.edu iew.resume(); 10632843Sktlim@umich.edu commit.resume(); 10642316SN/A 10652905Sktlim@umich.edu changeState(SimObject::Running); 10662905Sktlim@umich.edu 10672864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 10682864Sktlim@umich.edu return; 10692864Sktlim@umich.edu 10703319Shsul@eecs.umich.edu#if FULL_SYSTEM 10714762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 10723319Shsul@eecs.umich.edu#endif 10733319Shsul@eecs.umich.edu 10742843Sktlim@umich.edu if (!tickEvent.scheduled()) 10755606Snate@binkert.org schedule(tickEvent, nextCycle()); 10762843Sktlim@umich.edu _status = Running; 10772843Sktlim@umich.edu} 10782316SN/A 10792843Sktlim@umich.edutemplate <class Impl> 10802843Sktlim@umich.eduvoid 10812843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 10822843Sktlim@umich.edu{ 10832843Sktlim@umich.edu if (++drainCount == NumStages) { 10842316SN/A if (tickEvent.scheduled()) 10852316SN/A tickEvent.squash(); 10862863Sktlim@umich.edu 10872905Sktlim@umich.edu changeState(SimObject::Drained); 10882863Sktlim@umich.edu 10893126Sktlim@umich.edu BaseCPU::switchOut(); 10903126Sktlim@umich.edu 10912863Sktlim@umich.edu if (drainEvent) { 10922863Sktlim@umich.edu drainEvent->process(); 10932863Sktlim@umich.edu drainEvent = NULL; 10942863Sktlim@umich.edu } 10952310SN/A } 10962843Sktlim@umich.edu assert(drainCount <= 5); 10972843Sktlim@umich.edu} 10982843Sktlim@umich.edu 10992843Sktlim@umich.edutemplate <class Impl> 11002843Sktlim@umich.eduvoid 11012843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 11022843Sktlim@umich.edu{ 11032843Sktlim@umich.edu fetch.switchOut(); 11042843Sktlim@umich.edu rename.switchOut(); 11052325SN/A iew.switchOut(); 11062843Sktlim@umich.edu commit.switchOut(); 11072843Sktlim@umich.edu instList.clear(); 11082843Sktlim@umich.edu while (!removeList.empty()) { 11092843Sktlim@umich.edu removeList.pop(); 11102843Sktlim@umich.edu } 11112843Sktlim@umich.edu 11122843Sktlim@umich.edu _status = SwitchedOut; 11132843Sktlim@umich.edu#if USE_CHECKER 11142843Sktlim@umich.edu if (checker) 11152843Sktlim@umich.edu checker->switchOut(); 11162843Sktlim@umich.edu#endif 11173126Sktlim@umich.edu if (tickEvent.scheduled()) 11183126Sktlim@umich.edu tickEvent.squash(); 11191060SN/A} 11201060SN/A 11211060SN/Atemplate <class Impl> 11221060SN/Avoid 11231755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 11241060SN/A{ 11252325SN/A // Flush out any old data from the time buffers. 11262873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 11272307SN/A timeBuffer.advance(); 11282307SN/A fetchQueue.advance(); 11292307SN/A decodeQueue.advance(); 11302307SN/A renameQueue.advance(); 11312307SN/A iewQueue.advance(); 11322307SN/A } 11332307SN/A 11342325SN/A activityRec.reset(); 11352307SN/A 11364192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort()); 11371060SN/A 11382307SN/A fetch.takeOverFrom(); 11392307SN/A decode.takeOverFrom(); 11402307SN/A rename.takeOverFrom(); 11412307SN/A iew.takeOverFrom(); 11422307SN/A commit.takeOverFrom(); 11432307SN/A 11447507Stjones1@inf.ed.ac.uk assert(!tickEvent.scheduled() || tickEvent.squashed()); 11451060SN/A 11462325SN/A // @todo: Figure out how to properly select the tid to put onto 11472325SN/A // the active threads list. 11486221Snate@binkert.org ThreadID tid = 0; 11492307SN/A 11506221Snate@binkert.org list<ThreadID>::iterator isActive = 11515314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 11522307SN/A 11532307SN/A if (isActive == activeThreads.end()) { 11542325SN/A //May Need to Re-code this if the delay variable is the delay 11552325SN/A //needed for thread to activate 11562733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 11572307SN/A tid); 11582307SN/A 11592307SN/A activeThreads.push_back(tid); 11602307SN/A } 11612307SN/A 11622325SN/A // Set all statuses to active, schedule the CPU's tick event. 11632307SN/A // @todo: Fix up statuses so this is handled properly 11646221Snate@binkert.org ThreadID size = threadContexts.size(); 11656221Snate@binkert.org for (ThreadID i = 0; i < size; ++i) { 11662680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 11672680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 11681681SN/A _status = Running; 11697507Stjones1@inf.ed.ac.uk reschedule(tickEvent, nextCycle(), true); 11701681SN/A } 11711060SN/A } 11722307SN/A if (!tickEvent.scheduled()) 11735606Snate@binkert.org schedule(tickEvent, nextCycle()); 11741060SN/A} 11751060SN/A 11761060SN/Atemplate <class Impl> 11775595Sgblack@eecs.umich.eduTheISA::MiscReg 11786221Snate@binkert.orgFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) 11795595Sgblack@eecs.umich.edu{ 11806313Sgblack@eecs.umich.edu return this->isa[tid].readMiscRegNoEffect(misc_reg); 11815595Sgblack@eecs.umich.edu} 11825595Sgblack@eecs.umich.edu 11835595Sgblack@eecs.umich.edutemplate <class Impl> 11845595Sgblack@eecs.umich.eduTheISA::MiscReg 11856221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 11865595Sgblack@eecs.umich.edu{ 11876313Sgblack@eecs.umich.edu return this->isa[tid].readMiscReg(misc_reg, tcBase(tid)); 11885595Sgblack@eecs.umich.edu} 11895595Sgblack@eecs.umich.edu 11905595Sgblack@eecs.umich.edutemplate <class Impl> 11915595Sgblack@eecs.umich.eduvoid 11925595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 11936221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 11945595Sgblack@eecs.umich.edu{ 11956313Sgblack@eecs.umich.edu this->isa[tid].setMiscRegNoEffect(misc_reg, val); 11965595Sgblack@eecs.umich.edu} 11975595Sgblack@eecs.umich.edu 11985595Sgblack@eecs.umich.edutemplate <class Impl> 11995595Sgblack@eecs.umich.eduvoid 12005595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 12016221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12025595Sgblack@eecs.umich.edu{ 12036313Sgblack@eecs.umich.edu this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid)); 12045595Sgblack@eecs.umich.edu} 12055595Sgblack@eecs.umich.edu 12065595Sgblack@eecs.umich.edutemplate <class Impl> 12071060SN/Auint64_t 12081755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 12091060SN/A{ 12101060SN/A return regFile.readIntReg(reg_idx); 12111060SN/A} 12121060SN/A 12131060SN/Atemplate <class Impl> 12142455SN/AFloatReg 12152455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 12161060SN/A{ 12172455SN/A return regFile.readFloatReg(reg_idx); 12181060SN/A} 12191060SN/A 12201060SN/Atemplate <class Impl> 12212455SN/AFloatRegBits 12222455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 12232455SN/A{ 12242455SN/A return regFile.readFloatRegBits(reg_idx); 12251060SN/A} 12261060SN/A 12271060SN/Atemplate <class Impl> 12281060SN/Avoid 12291755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 12301060SN/A{ 12311060SN/A regFile.setIntReg(reg_idx, val); 12321060SN/A} 12331060SN/A 12341060SN/Atemplate <class Impl> 12351060SN/Avoid 12362455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 12371060SN/A{ 12382455SN/A regFile.setFloatReg(reg_idx, val); 12391060SN/A} 12401060SN/A 12411060SN/Atemplate <class Impl> 12421060SN/Avoid 12432455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 12442455SN/A{ 12452455SN/A regFile.setFloatRegBits(reg_idx, val); 12461060SN/A} 12471060SN/A 12481060SN/Atemplate <class Impl> 12491060SN/Auint64_t 12506221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 12511060SN/A{ 12522292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 12532292SN/A 12542292SN/A return regFile.readIntReg(phys_reg); 12552292SN/A} 12562292SN/A 12572292SN/Atemplate <class Impl> 12582292SN/Afloat 12596314Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 12602292SN/A{ 12616032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 12622307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 12632292SN/A 12642669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 12652292SN/A} 12662292SN/A 12672292SN/Atemplate <class Impl> 12682292SN/Auint64_t 12696221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 12702292SN/A{ 12716032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 12722307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 12732292SN/A 12742669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 12751060SN/A} 12761060SN/A 12771060SN/Atemplate <class Impl> 12781060SN/Avoid 12796221Snate@binkert.orgFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 12801060SN/A{ 12812292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 12822292SN/A 12832292SN/A regFile.setIntReg(phys_reg, val); 12841060SN/A} 12851060SN/A 12861060SN/Atemplate <class Impl> 12871060SN/Avoid 12886314Sgblack@eecs.umich.eduFullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 12891060SN/A{ 12906032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 12912918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 12922292SN/A 12932669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 12941060SN/A} 12951060SN/A 12961060SN/Atemplate <class Impl> 12971060SN/Avoid 12986221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 12991060SN/A{ 13006032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13012918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13021060SN/A 13032669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 13042292SN/A} 13052292SN/A 13062292SN/Atemplate <class Impl> 13077720Sgblack@eecs.umich.eduTheISA::PCState 13087720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 13092292SN/A{ 13107720Sgblack@eecs.umich.edu return commit.pcState(tid); 13111060SN/A} 13121060SN/A 13131060SN/Atemplate <class Impl> 13141060SN/Avoid 13157720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 13161060SN/A{ 13177720Sgblack@eecs.umich.edu commit.pcState(val, tid); 13182292SN/A} 13191060SN/A 13202292SN/Atemplate <class Impl> 13217720Sgblack@eecs.umich.eduAddr 13227720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 13234636Sgblack@eecs.umich.edu{ 13247720Sgblack@eecs.umich.edu return commit.instAddr(tid); 13254636Sgblack@eecs.umich.edu} 13264636Sgblack@eecs.umich.edu 13274636Sgblack@eecs.umich.edutemplate <class Impl> 13287720Sgblack@eecs.umich.eduAddr 13297720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 13304636Sgblack@eecs.umich.edu{ 13317720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 13324636Sgblack@eecs.umich.edu} 13334636Sgblack@eecs.umich.edu 13344636Sgblack@eecs.umich.edutemplate <class Impl> 13357720Sgblack@eecs.umich.eduMicroPC 13367720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 13372292SN/A{ 13387720Sgblack@eecs.umich.edu return commit.microPC(tid); 13394636Sgblack@eecs.umich.edu} 13404636Sgblack@eecs.umich.edu 13414636Sgblack@eecs.umich.edutemplate <class Impl> 13425595Sgblack@eecs.umich.eduvoid 13436221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 13445595Sgblack@eecs.umich.edu{ 13455595Sgblack@eecs.umich.edu this->thread[tid]->inSyscall = true; 13465595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 13475595Sgblack@eecs.umich.edu} 13485595Sgblack@eecs.umich.edu 13495595Sgblack@eecs.umich.edutemplate <class Impl> 13502292SN/Atypename FullO3CPU<Impl>::ListIt 13512292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 13522292SN/A{ 13532292SN/A instList.push_back(inst); 13541060SN/A 13552292SN/A return --(instList.end()); 13562292SN/A} 13571060SN/A 13582292SN/Atemplate <class Impl> 13592292SN/Avoid 13606221Snate@binkert.orgFullO3CPU<Impl>::instDone(ThreadID tid) 13612292SN/A{ 13622292SN/A // Keep an instruction count. 13632292SN/A thread[tid]->numInst++; 13642292SN/A thread[tid]->numInsts++; 13652292SN/A committedInsts[tid]++; 13662292SN/A totalCommittedInsts++; 13672292SN/A 13682292SN/A // Check for instruction-count-based events. 13692292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 13702292SN/A} 13712292SN/A 13722292SN/Atemplate <class Impl> 13732292SN/Avoid 13742292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 13752292SN/A{ 13762292SN/A removeInstsThisCycle = true; 13772292SN/A 13782292SN/A removeList.push(inst->getInstListIt()); 13791060SN/A} 13801060SN/A 13811060SN/Atemplate <class Impl> 13821060SN/Avoid 13831755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 13841060SN/A{ 13857720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 13862292SN/A "[sn:%lli]\n", 13877720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 13881060SN/A 13892292SN/A removeInstsThisCycle = true; 13901060SN/A 13911060SN/A // Remove the front instruction. 13922292SN/A removeList.push(inst->getInstListIt()); 13931060SN/A} 13941060SN/A 13951060SN/Atemplate <class Impl> 13961060SN/Avoid 13976221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 13981060SN/A{ 13992733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 14002292SN/A " list.\n", tid); 14011060SN/A 14022292SN/A ListIt end_it; 14031060SN/A 14042292SN/A bool rob_empty = false; 14052292SN/A 14062292SN/A if (instList.empty()) { 14072292SN/A return; 14082292SN/A } else if (rob.isEmpty(/*tid*/)) { 14092733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 14102292SN/A end_it = instList.begin(); 14112292SN/A rob_empty = true; 14122292SN/A } else { 14132292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 14142733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 14152292SN/A } 14162292SN/A 14172292SN/A removeInstsThisCycle = true; 14182292SN/A 14192292SN/A ListIt inst_it = instList.end(); 14202292SN/A 14212292SN/A inst_it--; 14222292SN/A 14232292SN/A // Walk through the instruction list, removing any instructions 14242292SN/A // that were inserted after the given instruction iterator, end_it. 14252292SN/A while (inst_it != end_it) { 14262292SN/A assert(!instList.empty()); 14272292SN/A 14282292SN/A squashInstIt(inst_it, tid); 14292292SN/A 14302292SN/A inst_it--; 14312292SN/A } 14322292SN/A 14332292SN/A // If the ROB was empty, then we actually need to remove the first 14342292SN/A // instruction as well. 14352292SN/A if (rob_empty) { 14362292SN/A squashInstIt(inst_it, tid); 14372292SN/A } 14381060SN/A} 14391060SN/A 14401060SN/Atemplate <class Impl> 14411060SN/Avoid 14426221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 14431062SN/A{ 14442292SN/A assert(!instList.empty()); 14452292SN/A 14462292SN/A removeInstsThisCycle = true; 14472292SN/A 14482292SN/A ListIt inst_iter = instList.end(); 14492292SN/A 14502292SN/A inst_iter--; 14512292SN/A 14522733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 14532292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 14542292SN/A tid, seq_num, (*inst_iter)->seqNum); 14551062SN/A 14562292SN/A while ((*inst_iter)->seqNum > seq_num) { 14571062SN/A 14582292SN/A bool break_loop = (inst_iter == instList.begin()); 14591062SN/A 14602292SN/A squashInstIt(inst_iter, tid); 14611062SN/A 14622292SN/A inst_iter--; 14631062SN/A 14642292SN/A if (break_loop) 14652292SN/A break; 14662292SN/A } 14672292SN/A} 14682292SN/A 14692292SN/Atemplate <class Impl> 14702292SN/Ainline void 14716221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 14722292SN/A{ 14732292SN/A if ((*instIt)->threadNumber == tid) { 14742733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 14757720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 14762292SN/A (*instIt)->threadNumber, 14772292SN/A (*instIt)->seqNum, 14787720Sgblack@eecs.umich.edu (*instIt)->pcState()); 14791062SN/A 14801062SN/A // Mark it as squashed. 14812292SN/A (*instIt)->setSquashed(); 14822292SN/A 14832325SN/A // @todo: Formulate a consistent method for deleting 14842325SN/A // instructions from the instruction list 14852292SN/A // Remove the instruction from the list. 14862292SN/A removeList.push(instIt); 14872292SN/A } 14882292SN/A} 14892292SN/A 14902292SN/Atemplate <class Impl> 14912292SN/Avoid 14922292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 14932292SN/A{ 14942292SN/A while (!removeList.empty()) { 14952733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 14967720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 14972292SN/A (*removeList.front())->threadNumber, 14982292SN/A (*removeList.front())->seqNum, 14997720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 15002292SN/A 15012292SN/A instList.erase(removeList.front()); 15022292SN/A 15032292SN/A removeList.pop(); 15041062SN/A } 15051062SN/A 15062292SN/A removeInstsThisCycle = false; 15071062SN/A} 15082325SN/A/* 15091062SN/Atemplate <class Impl> 15101062SN/Avoid 15111755SN/AFullO3CPU<Impl>::removeAllInsts() 15121060SN/A{ 15131060SN/A instList.clear(); 15141060SN/A} 15152325SN/A*/ 15161060SN/Atemplate <class Impl> 15171060SN/Avoid 15181755SN/AFullO3CPU<Impl>::dumpInsts() 15191060SN/A{ 15201060SN/A int num = 0; 15211060SN/A 15222292SN/A ListIt inst_list_it = instList.begin(); 15232292SN/A 15242292SN/A cprintf("Dumping Instruction List\n"); 15252292SN/A 15262292SN/A while (inst_list_it != instList.end()) { 15272292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 15282292SN/A "Squashed:%i\n\n", 15297720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 15302292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 15312292SN/A (*inst_list_it)->isSquashed()); 15321060SN/A inst_list_it++; 15331060SN/A ++num; 15341060SN/A } 15351060SN/A} 15362325SN/A/* 15371060SN/Atemplate <class Impl> 15381060SN/Avoid 15391755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 15401060SN/A{ 15411060SN/A iew.wakeDependents(inst); 15421060SN/A} 15432325SN/A*/ 15442292SN/Atemplate <class Impl> 15452292SN/Avoid 15462292SN/AFullO3CPU<Impl>::wakeCPU() 15472292SN/A{ 15482325SN/A if (activityRec.active() || tickEvent.scheduled()) { 15492325SN/A DPRINTF(Activity, "CPU already running.\n"); 15502292SN/A return; 15512292SN/A } 15522292SN/A 15532325SN/A DPRINTF(Activity, "Waking up CPU\n"); 15542325SN/A 15557823Ssteve.reinhardt@amd.com idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle); 15567823Ssteve.reinhardt@amd.com numCycles += tickToCycles((curTick() - 1) - lastRunningCycle); 15572292SN/A 15585606Snate@binkert.org schedule(tickEvent, nextCycle()); 15592292SN/A} 15602292SN/A 15615807Snate@binkert.org#if FULL_SYSTEM 15625807Snate@binkert.orgtemplate <class Impl> 15635807Snate@binkert.orgvoid 15645807Snate@binkert.orgFullO3CPU<Impl>::wakeup() 15655807Snate@binkert.org{ 15665807Snate@binkert.org if (this->thread[0]->status() != ThreadContext::Suspended) 15675807Snate@binkert.org return; 15685807Snate@binkert.org 15695807Snate@binkert.org this->wakeCPU(); 15705807Snate@binkert.org 15715807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 15725807Snate@binkert.org this->threadContexts[0]->activate(); 15735807Snate@binkert.org} 15745807Snate@binkert.org#endif 15755807Snate@binkert.org 15762292SN/Atemplate <class Impl> 15776221Snate@binkert.orgThreadID 15782292SN/AFullO3CPU<Impl>::getFreeTid() 15792292SN/A{ 15806221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 15816221Snate@binkert.org if (!tids[tid]) { 15826221Snate@binkert.org tids[tid] = true; 15836221Snate@binkert.org return tid; 15842292SN/A } 15852292SN/A } 15862292SN/A 15876221Snate@binkert.org return InvalidThreadID; 15882292SN/A} 15892292SN/A 15902292SN/Atemplate <class Impl> 15912292SN/Avoid 15922292SN/AFullO3CPU<Impl>::doContextSwitch() 15932292SN/A{ 15942292SN/A if (contextSwitch) { 15952292SN/A 15962292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 15972292SN/A 15986221Snate@binkert.org ThreadID size = cpuWaitList.size(); 15996221Snate@binkert.org for (ThreadID tid = 0; tid < size; tid++) { 16002292SN/A activateWhenReady(tid); 16012292SN/A } 16022292SN/A 16032292SN/A if (cpuWaitList.size() == 0) 16042292SN/A contextSwitch = true; 16052292SN/A } 16062292SN/A} 16072292SN/A 16082292SN/Atemplate <class Impl> 16092292SN/Avoid 16102292SN/AFullO3CPU<Impl>::updateThreadPriority() 16112292SN/A{ 16126221Snate@binkert.org if (activeThreads.size() > 1) { 16132292SN/A //DEFAULT TO ROUND ROBIN SCHEME 16142292SN/A //e.g. Move highest priority to end of thread list 16156221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 16166221Snate@binkert.org list<ThreadID>::iterator list_end = activeThreads.end(); 16172292SN/A 16182292SN/A unsigned high_thread = *list_begin; 16192292SN/A 16202292SN/A activeThreads.erase(list_begin); 16212292SN/A 16222292SN/A activeThreads.push_back(high_thread); 16232292SN/A } 16242292SN/A} 16251060SN/A 16261755SN/A// Forward declaration of FullO3CPU. 16272818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1628