cpu.cc revision 6032
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 341858SN/A 354762Snate@binkert.org#include "cpu/activity.hh" 364762Snate@binkert.org#include "cpu/simple_thread.hh" 374762Snate@binkert.org#include "cpu/thread_context.hh" 384762Snate@binkert.org#include "cpu/o3/isa_specific.hh" 394762Snate@binkert.org#include "cpu/o3/cpu.hh" 405595Sgblack@eecs.umich.edu#include "cpu/o3/thread_context.hh" 414762Snate@binkert.org#include "enums/MemoryMode.hh" 424762Snate@binkert.org#include "sim/core.hh" 434762Snate@binkert.org#include "sim/stat_control.hh" 444762Snate@binkert.org 451858SN/A#if FULL_SYSTEM 462356SN/A#include "cpu/quiesce_event.hh" 471060SN/A#include "sim/system.hh" 481060SN/A#else 491060SN/A#include "sim/process.hh" 501060SN/A#endif 511060SN/A 522794Sktlim@umich.edu#if USE_CHECKER 532794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 542794Sktlim@umich.edu#endif 552794Sktlim@umich.edu 565702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 575702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 585702Ssaidi@eecs.umich.edu#endif 595702Ssaidi@eecs.umich.edu 605529Snate@binkert.orgclass BaseCPUParams; 615529Snate@binkert.org 622669Sktlim@umich.eduusing namespace TheISA; 631060SN/A 645529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 655712Shsul@eecs.umich.edu : BaseCPU(params) 661060SN/A{ 671060SN/A} 681060SN/A 692292SN/Avoid 702733Sktlim@umich.eduBaseO3CPU::regStats() 712292SN/A{ 722292SN/A BaseCPU::regStats(); 732292SN/A} 742292SN/A 751060SN/Atemplate <class Impl> 761755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 775606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 781060SN/A{ 791060SN/A} 801060SN/A 811060SN/Atemplate <class Impl> 821060SN/Avoid 831755SN/AFullO3CPU<Impl>::TickEvent::process() 841060SN/A{ 851060SN/A cpu->tick(); 861060SN/A} 871060SN/A 881060SN/Atemplate <class Impl> 891060SN/Aconst char * 905336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 911060SN/A{ 924873Sstever@eecs.umich.edu return "FullO3CPU tick"; 931060SN/A} 941060SN/A 951060SN/Atemplate <class Impl> 962829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 975606Snate@binkert.org : Event(CPU_Switch_Pri) 982829Sksewell@umich.edu{ 992829Sksewell@umich.edu} 1002829Sksewell@umich.edu 1012829Sksewell@umich.edutemplate <class Impl> 1022829Sksewell@umich.eduvoid 1032829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 1042829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1052829Sksewell@umich.edu{ 1062829Sksewell@umich.edu tid = thread_num; 1072829Sksewell@umich.edu cpu = thread_cpu; 1082829Sksewell@umich.edu} 1092829Sksewell@umich.edu 1102829Sksewell@umich.edutemplate <class Impl> 1112829Sksewell@umich.eduvoid 1122829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1132829Sksewell@umich.edu{ 1142829Sksewell@umich.edu cpu->activateThread(tid); 1152829Sksewell@umich.edu} 1162829Sksewell@umich.edu 1172829Sksewell@umich.edutemplate <class Impl> 1182829Sksewell@umich.educonst char * 1195336Shines@cs.fsu.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1202829Sksewell@umich.edu{ 1214873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1222829Sksewell@umich.edu} 1232829Sksewell@umich.edu 1242829Sksewell@umich.edutemplate <class Impl> 1252875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1265606Snate@binkert.org : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1272875Sksewell@umich.edu{ 1282875Sksewell@umich.edu} 1292875Sksewell@umich.edu 1302875Sksewell@umich.edutemplate <class Impl> 1312875Sksewell@umich.eduvoid 1322875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1333859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1342875Sksewell@umich.edu{ 1352875Sksewell@umich.edu tid = thread_num; 1362875Sksewell@umich.edu cpu = thread_cpu; 1373859Sbinkertn@umich.edu remove = false; 1382875Sksewell@umich.edu} 1392875Sksewell@umich.edu 1402875Sksewell@umich.edutemplate <class Impl> 1412875Sksewell@umich.eduvoid 1422875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1432875Sksewell@umich.edu{ 1442875Sksewell@umich.edu cpu->deactivateThread(tid); 1453221Sktlim@umich.edu if (remove) 1463221Sktlim@umich.edu cpu->removeThread(tid); 1472875Sksewell@umich.edu} 1482875Sksewell@umich.edu 1492875Sksewell@umich.edutemplate <class Impl> 1502875Sksewell@umich.educonst char * 1515336Shines@cs.fsu.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 1522875Sksewell@umich.edu{ 1534873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 1542875Sksewell@umich.edu} 1552875Sksewell@umich.edu 1562875Sksewell@umich.edutemplate <class Impl> 1575595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 1582733Sktlim@umich.edu : BaseO3CPU(params), 1593781Sgblack@eecs.umich.edu itb(params->itb), 1603781Sgblack@eecs.umich.edu dtb(params->dtb), 1611060SN/A tickEvent(this), 1625737Scws3k@cs.virginia.edu#ifndef NDEBUG 1635737Scws3k@cs.virginia.edu instcount(0), 1645737Scws3k@cs.virginia.edu#endif 1652292SN/A removeInstsThisCycle(false), 1665595Sgblack@eecs.umich.edu fetch(this, params), 1675595Sgblack@eecs.umich.edu decode(this, params), 1685595Sgblack@eecs.umich.edu rename(this, params), 1695595Sgblack@eecs.umich.edu iew(this, params), 1705595Sgblack@eecs.umich.edu commit(this, params), 1711060SN/A 1725595Sgblack@eecs.umich.edu regFile(this, params->numPhysIntRegs, 1734329Sktlim@umich.edu params->numPhysFloatRegs), 1741060SN/A 1755529Snate@binkert.org freeList(params->numThreads, 1762292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1772292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1781060SN/A 1795595Sgblack@eecs.umich.edu rob(this, 1804329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 1812292SN/A params->smtROBPolicy, params->smtROBThreshold, 1825529Snate@binkert.org params->numThreads), 1831060SN/A 1845529Snate@binkert.org scoreboard(params->numThreads, 1852292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1862292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1872292SN/A TheISA::NumMiscRegs * number_of_threads, 1882292SN/A TheISA::ZeroReg), 1891060SN/A 1902873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1912873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1922873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1932873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1942873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1955804Snate@binkert.org activityRec(name(), NumStages, 1962873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1972873Sktlim@umich.edu params->activity), 1981060SN/A 1991060SN/A globalSeqNum(1), 2001858SN/A#if FULL_SYSTEM 2012292SN/A system(params->system), 2021060SN/A physmem(system->physmem), 2031060SN/A#endif // FULL_SYSTEM 2042843Sktlim@umich.edu drainCount(0), 2055529Snate@binkert.org deferRegistration(params->defer_registration), 2062316SN/A numThreads(number_of_threads) 2071060SN/A{ 2083221Sktlim@umich.edu if (!deferRegistration) { 2093221Sktlim@umich.edu _status = Running; 2103221Sktlim@umich.edu } else { 2113221Sktlim@umich.edu _status = Idle; 2123221Sktlim@umich.edu } 2131681SN/A 2144598Sbinkertn@umich.edu#if USE_CHECKER 2152794Sktlim@umich.edu if (params->checker) { 2162316SN/A BaseCPU *temp_checker = params->checker; 2172316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2182316SN/A#if FULL_SYSTEM 2192316SN/A checker->setSystem(params->system); 2202316SN/A#endif 2214598Sbinkertn@umich.edu } else { 2224598Sbinkertn@umich.edu checker = NULL; 2234598Sbinkertn@umich.edu } 2242794Sktlim@umich.edu#endif // USE_CHECKER 2252316SN/A 2261858SN/A#if !FULL_SYSTEM 2272292SN/A thread.resize(number_of_threads); 2282292SN/A tids.resize(number_of_threads); 2291681SN/A#endif 2301681SN/A 2312325SN/A // The stages also need their CPU pointer setup. However this 2322325SN/A // must be done at the upper level CPU because they have pointers 2332325SN/A // to the upper level CPU, and not this FullO3CPU. 2341060SN/A 2352292SN/A // Set up Pointers to the activeThreads list for each stage 2362292SN/A fetch.setActiveThreads(&activeThreads); 2372292SN/A decode.setActiveThreads(&activeThreads); 2382292SN/A rename.setActiveThreads(&activeThreads); 2392292SN/A iew.setActiveThreads(&activeThreads); 2402292SN/A commit.setActiveThreads(&activeThreads); 2411060SN/A 2421060SN/A // Give each of the stages the time buffer they will use. 2431060SN/A fetch.setTimeBuffer(&timeBuffer); 2441060SN/A decode.setTimeBuffer(&timeBuffer); 2451060SN/A rename.setTimeBuffer(&timeBuffer); 2461060SN/A iew.setTimeBuffer(&timeBuffer); 2471060SN/A commit.setTimeBuffer(&timeBuffer); 2481060SN/A 2491060SN/A // Also setup each of the stages' queues. 2501060SN/A fetch.setFetchQueue(&fetchQueue); 2511060SN/A decode.setFetchQueue(&fetchQueue); 2522292SN/A commit.setFetchQueue(&fetchQueue); 2531060SN/A decode.setDecodeQueue(&decodeQueue); 2541060SN/A rename.setDecodeQueue(&decodeQueue); 2551060SN/A rename.setRenameQueue(&renameQueue); 2561060SN/A iew.setRenameQueue(&renameQueue); 2571060SN/A iew.setIEWQueue(&iewQueue); 2581060SN/A commit.setIEWQueue(&iewQueue); 2591060SN/A commit.setRenameQueue(&renameQueue); 2601060SN/A 2612292SN/A commit.setIEWStage(&iew); 2622292SN/A rename.setIEWStage(&iew); 2632292SN/A rename.setCommitStage(&commit); 2642292SN/A 2652292SN/A#if !FULL_SYSTEM 2662307SN/A int active_threads = params->workload.size(); 2672831Sksewell@umich.edu 2682831Sksewell@umich.edu if (active_threads > Impl::MaxThreads) { 2692831Sksewell@umich.edu panic("Workload Size too large. Increase the 'MaxThreads'" 2702831Sksewell@umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2712831Sksewell@umich.edu "edit your workload size."); 2722831Sksewell@umich.edu } 2732292SN/A#else 2742307SN/A int active_threads = 1; 2752292SN/A#endif 2762292SN/A 2772316SN/A //Make Sure That this a Valid Architeture 2782292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2792292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2802292SN/A 2812292SN/A rename.setScoreboard(&scoreboard); 2822292SN/A iew.setScoreboard(&scoreboard); 2832292SN/A 2841060SN/A // Setup the rename map for whichever stages need it. 2852292SN/A PhysRegIndex lreg_idx = 0; 2862292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2871060SN/A 2882292SN/A for (int tid=0; tid < numThreads; tid++) { 2892307SN/A bool bindRegs = (tid <= active_threads - 1); 2902292SN/A 2912292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2922292SN/A params->numPhysIntRegs, 2932325SN/A lreg_idx, //Index for Logical. Regs 2942292SN/A 2952292SN/A TheISA::NumFloatRegs, 2962292SN/A params->numPhysFloatRegs, 2972325SN/A freg_idx, //Index for Float Regs 2982292SN/A 2992292SN/A TheISA::NumMiscRegs, 3002292SN/A 3012292SN/A TheISA::ZeroReg, 3022292SN/A TheISA::ZeroReg, 3032292SN/A 3042292SN/A tid, 3052292SN/A false); 3062292SN/A 3072292SN/A renameMap[tid].init(TheISA::NumIntRegs, 3082292SN/A params->numPhysIntRegs, 3092325SN/A lreg_idx, //Index for Logical. Regs 3102292SN/A 3112292SN/A TheISA::NumFloatRegs, 3122292SN/A params->numPhysFloatRegs, 3132325SN/A freg_idx, //Index for Float Regs 3142292SN/A 3152292SN/A TheISA::NumMiscRegs, 3162292SN/A 3172292SN/A TheISA::ZeroReg, 3182292SN/A TheISA::ZeroReg, 3192292SN/A 3202292SN/A tid, 3212292SN/A bindRegs); 3223221Sktlim@umich.edu 3233221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3243221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3252292SN/A } 3262292SN/A 3272292SN/A rename.setRenameMap(renameMap); 3282292SN/A commit.setRenameMap(commitRenameMap); 3292292SN/A 3302292SN/A // Give renameMap & rename stage access to the freeList; 3312292SN/A for (int i=0; i < numThreads; i++) { 3322292SN/A renameMap[i].setFreeList(&freeList); 3332292SN/A } 3341060SN/A rename.setFreeList(&freeList); 3352292SN/A 3361060SN/A // Setup the ROB for whichever stages need it. 3371060SN/A commit.setROB(&rob); 3382292SN/A 3392292SN/A lastRunningCycle = curTick; 3402292SN/A 3412829Sksewell@umich.edu lastActivatedCycle = -1; 3422829Sksewell@umich.edu 3433093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3443093Sksewell@umich.edu //for (int i=0; i < numThreads; i++) { 3453093Sksewell@umich.edu //globalSeqNum[i] = 1; 3463093Sksewell@umich.edu //} 3473093Sksewell@umich.edu 3482292SN/A contextSwitch = false; 3495595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3505595Sgblack@eecs.umich.edu 3515595Sgblack@eecs.umich.edu // Setup any thread state. 3525595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 3535595Sgblack@eecs.umich.edu 3545595Sgblack@eecs.umich.edu for (int i = 0; i < this->numThreads; ++i) { 3555595Sgblack@eecs.umich.edu#if FULL_SYSTEM 3565595Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 3575595Sgblack@eecs.umich.edu assert(this->numThreads == 1); 3585595Sgblack@eecs.umich.edu this->thread[i] = new Thread(this, 0); 3595595Sgblack@eecs.umich.edu#else 3605595Sgblack@eecs.umich.edu if (i < params->workload.size()) { 3615595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 3625595Sgblack@eecs.umich.edu i, this->thread[i]); 3635595Sgblack@eecs.umich.edu this->thread[i] = new typename FullO3CPU<Impl>::Thread( 3645595Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3655595Sgblack@eecs.umich.edu i, params->workload[i], i); 3665595Sgblack@eecs.umich.edu 3675595Sgblack@eecs.umich.edu //usedTids[i] = true; 3685595Sgblack@eecs.umich.edu //threadMap[i] = i; 3695595Sgblack@eecs.umich.edu } else { 3705595Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 3715595Sgblack@eecs.umich.edu //when scheduling threads to CPU 3725595Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 3735595Sgblack@eecs.umich.edu 3745595Sgblack@eecs.umich.edu this->thread[i] = new typename FullO3CPU<Impl>::Thread( 3755595Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3765595Sgblack@eecs.umich.edu i, dummy_proc, i); 3775595Sgblack@eecs.umich.edu //usedTids[i] = false; 3785595Sgblack@eecs.umich.edu } 3795595Sgblack@eecs.umich.edu#endif // !FULL_SYSTEM 3805595Sgblack@eecs.umich.edu 3815595Sgblack@eecs.umich.edu ThreadContext *tc; 3825595Sgblack@eecs.umich.edu 3835595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 3845595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 3855595Sgblack@eecs.umich.edu 3865595Sgblack@eecs.umich.edu tc = o3_tc; 3875595Sgblack@eecs.umich.edu 3885595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 3895595Sgblack@eecs.umich.edu // CheckerThreadContext. 3905595Sgblack@eecs.umich.edu#if USE_CHECKER 3915595Sgblack@eecs.umich.edu if (params->checker) { 3925595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 3935595Sgblack@eecs.umich.edu o3_tc, this->checker); 3945595Sgblack@eecs.umich.edu } 3955595Sgblack@eecs.umich.edu#endif 3965595Sgblack@eecs.umich.edu 3975595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 3985595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 3995595Sgblack@eecs.umich.edu o3_tc->thread = this->thread[i]; 4005595Sgblack@eecs.umich.edu 4015595Sgblack@eecs.umich.edu#if FULL_SYSTEM 4025595Sgblack@eecs.umich.edu // Setup quiesce event. 4035595Sgblack@eecs.umich.edu this->thread[i]->quiesceEvent = new EndQuiesceEvent(tc); 4045595Sgblack@eecs.umich.edu#endif 4055595Sgblack@eecs.umich.edu // Give the thread the TC. 4065595Sgblack@eecs.umich.edu this->thread[i]->tc = tc; 4075595Sgblack@eecs.umich.edu 4085595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4095595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4105595Sgblack@eecs.umich.edu } 4115595Sgblack@eecs.umich.edu 4125595Sgblack@eecs.umich.edu for (int i=0; i < this->numThreads; i++) { 4135595Sgblack@eecs.umich.edu this->thread[i]->setFuncExeInst(0); 4145595Sgblack@eecs.umich.edu } 4155595Sgblack@eecs.umich.edu 4165595Sgblack@eecs.umich.edu lockAddr = 0; 4175595Sgblack@eecs.umich.edu lockFlag = false; 4181060SN/A} 4191060SN/A 4201060SN/Atemplate <class Impl> 4211755SN/AFullO3CPU<Impl>::~FullO3CPU() 4221060SN/A{ 4231060SN/A} 4241060SN/A 4251060SN/Atemplate <class Impl> 4261060SN/Avoid 4275595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4281062SN/A{ 4292733Sktlim@umich.edu BaseO3CPU::regStats(); 4302292SN/A 4312733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4322292SN/A timesIdled 4332292SN/A .name(name() + ".timesIdled") 4342292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4352292SN/A " unscheduled itself") 4362292SN/A .prereq(timesIdled); 4372292SN/A 4382292SN/A idleCycles 4392292SN/A .name(name() + ".idleCycles") 4402292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4412292SN/A "to idling") 4422292SN/A .prereq(idleCycles); 4432292SN/A 4442292SN/A // Number of Instructions simulated 4452292SN/A // -------------------------------- 4462292SN/A // Should probably be in Base CPU but need templated 4472292SN/A // MaxThreads so put in here instead 4482292SN/A committedInsts 4492292SN/A .init(numThreads) 4502292SN/A .name(name() + ".committedInsts") 4512292SN/A .desc("Number of Instructions Simulated"); 4522292SN/A 4532292SN/A totalCommittedInsts 4542292SN/A .name(name() + ".committedInsts_total") 4552292SN/A .desc("Number of Instructions Simulated"); 4562292SN/A 4572292SN/A cpi 4582292SN/A .name(name() + ".cpi") 4592292SN/A .desc("CPI: Cycles Per Instruction") 4602292SN/A .precision(6); 4614392Sktlim@umich.edu cpi = numCycles / committedInsts; 4622292SN/A 4632292SN/A totalCpi 4642292SN/A .name(name() + ".cpi_total") 4652292SN/A .desc("CPI: Total CPI of All Threads") 4662292SN/A .precision(6); 4674392Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 4682292SN/A 4692292SN/A ipc 4702292SN/A .name(name() + ".ipc") 4712292SN/A .desc("IPC: Instructions Per Cycle") 4722292SN/A .precision(6); 4734392Sktlim@umich.edu ipc = committedInsts / numCycles; 4742292SN/A 4752292SN/A totalIpc 4762292SN/A .name(name() + ".ipc_total") 4772292SN/A .desc("IPC: Total IPC of All Threads") 4782292SN/A .precision(6); 4794392Sktlim@umich.edu totalIpc = totalCommittedInsts / numCycles; 4802292SN/A 4815595Sgblack@eecs.umich.edu this->fetch.regStats(); 4825595Sgblack@eecs.umich.edu this->decode.regStats(); 4835595Sgblack@eecs.umich.edu this->rename.regStats(); 4845595Sgblack@eecs.umich.edu this->iew.regStats(); 4855595Sgblack@eecs.umich.edu this->commit.regStats(); 4861062SN/A} 4871062SN/A 4881062SN/Atemplate <class Impl> 4892871Sktlim@umich.eduPort * 4902871Sktlim@umich.eduFullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 4912871Sktlim@umich.edu{ 4922871Sktlim@umich.edu if (if_name == "dcache_port") 4932871Sktlim@umich.edu return iew.getDcachePort(); 4942871Sktlim@umich.edu else if (if_name == "icache_port") 4952871Sktlim@umich.edu return fetch.getIcachePort(); 4962871Sktlim@umich.edu else 4972871Sktlim@umich.edu panic("No Such Port\n"); 4982871Sktlim@umich.edu} 4992871Sktlim@umich.edu 5002871Sktlim@umich.edutemplate <class Impl> 5011062SN/Avoid 5021755SN/AFullO3CPU<Impl>::tick() 5031060SN/A{ 5042733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5051060SN/A 5062292SN/A ++numCycles; 5072292SN/A 5082325SN/A// activity = false; 5092292SN/A 5102292SN/A //Tick each of the stages 5111060SN/A fetch.tick(); 5121060SN/A 5131060SN/A decode.tick(); 5141060SN/A 5151060SN/A rename.tick(); 5161060SN/A 5171060SN/A iew.tick(); 5181060SN/A 5191060SN/A commit.tick(); 5201060SN/A 5212292SN/A#if !FULL_SYSTEM 5222292SN/A doContextSwitch(); 5232292SN/A#endif 5242292SN/A 5252292SN/A // Now advance the time buffers 5261060SN/A timeBuffer.advance(); 5271060SN/A 5281060SN/A fetchQueue.advance(); 5291060SN/A decodeQueue.advance(); 5301060SN/A renameQueue.advance(); 5311060SN/A iewQueue.advance(); 5321060SN/A 5332325SN/A activityRec.advance(); 5342292SN/A 5352292SN/A if (removeInstsThisCycle) { 5362292SN/A cleanUpRemovedInsts(); 5372292SN/A } 5382292SN/A 5392325SN/A if (!tickEvent.scheduled()) { 5402867Sktlim@umich.edu if (_status == SwitchedOut || 5412905Sktlim@umich.edu getState() == SimObject::Drained) { 5423226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 5432325SN/A // increment stat 5442325SN/A lastRunningCycle = curTick; 5453221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 5463226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 5472325SN/A lastRunningCycle = curTick; 5482325SN/A timesIdled++; 5492325SN/A } else { 5505606Snate@binkert.org schedule(tickEvent, nextCycle(curTick + ticks(1))); 5513226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 5522325SN/A } 5532292SN/A } 5542292SN/A 5552292SN/A#if !FULL_SYSTEM 5562292SN/A updateThreadPriority(); 5572292SN/A#endif 5581060SN/A} 5591060SN/A 5601060SN/Atemplate <class Impl> 5611060SN/Avoid 5621755SN/AFullO3CPU<Impl>::init() 5631060SN/A{ 5645714Shsul@eecs.umich.edu BaseCPU::init(); 5651060SN/A 5662292SN/A // Set inSyscall so that the CPU doesn't squash when initially 5672292SN/A // setting up registers. 5682292SN/A for (int i = 0; i < number_of_threads; ++i) 5692292SN/A thread[i]->inSyscall = true; 5702292SN/A 5712292SN/A for (int tid=0; tid < number_of_threads; tid++) { 5721858SN/A#if FULL_SYSTEM 5732680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 5741681SN/A#else 5752680Sktlim@umich.edu ThreadContext *src_tc = thread[tid]->getTC(); 5761681SN/A#endif 5772292SN/A // Threads start in the Suspended State 5782680Sktlim@umich.edu if (src_tc->status() != ThreadContext::Suspended) { 5792292SN/A continue; 5801060SN/A } 5811060SN/A 5822292SN/A#if FULL_SYSTEM 5835714Shsul@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 5842292SN/A#endif 5852292SN/A } 5862292SN/A 5872292SN/A // Clear inSyscall. 5882292SN/A for (int i = 0; i < number_of_threads; ++i) 5892292SN/A thread[i]->inSyscall = false; 5902292SN/A 5912316SN/A // Initialize stages. 5922292SN/A fetch.initStage(); 5932292SN/A iew.initStage(); 5942292SN/A rename.initStage(); 5952292SN/A commit.initStage(); 5962292SN/A 5972292SN/A commit.setThreads(thread); 5982292SN/A} 5992292SN/A 6002292SN/Atemplate <class Impl> 6012292SN/Avoid 6022875Sksewell@umich.eduFullO3CPU<Impl>::activateThread(unsigned tid) 6032875Sksewell@umich.edu{ 6045314Sstever@gmail.com std::list<unsigned>::iterator isActive = 6055314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6062875Sksewell@umich.edu 6073226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6083226Sktlim@umich.edu 6092875Sksewell@umich.edu if (isActive == activeThreads.end()) { 6102875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6112875Sksewell@umich.edu tid); 6122875Sksewell@umich.edu 6132875Sksewell@umich.edu activeThreads.push_back(tid); 6142875Sksewell@umich.edu } 6152875Sksewell@umich.edu} 6162875Sksewell@umich.edu 6172875Sksewell@umich.edutemplate <class Impl> 6182875Sksewell@umich.eduvoid 6192875Sksewell@umich.eduFullO3CPU<Impl>::deactivateThread(unsigned tid) 6202875Sksewell@umich.edu{ 6212875Sksewell@umich.edu //Remove From Active List, if Active 6225314Sstever@gmail.com std::list<unsigned>::iterator thread_it = 6235314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6242875Sksewell@umich.edu 6253226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 6263226Sktlim@umich.edu 6272875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 6282875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6292875Sksewell@umich.edu tid); 6302875Sksewell@umich.edu activeThreads.erase(thread_it); 6312875Sksewell@umich.edu } 6322875Sksewell@umich.edu} 6332875Sksewell@umich.edu 6342875Sksewell@umich.edutemplate <class Impl> 6352875Sksewell@umich.eduvoid 6362875Sksewell@umich.eduFullO3CPU<Impl>::activateContext(int tid, int delay) 6372875Sksewell@umich.edu{ 6382875Sksewell@umich.edu // Needs to set each stage to running as well. 6392875Sksewell@umich.edu if (delay){ 6402875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 6415100Ssaidi@eecs.umich.edu "on cycle %d\n", tid, curTick + ticks(delay)); 6422875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 6432875Sksewell@umich.edu } else { 6442875Sksewell@umich.edu activateThread(tid); 6452875Sksewell@umich.edu } 6462875Sksewell@umich.edu 6473221Sktlim@umich.edu if (lastActivatedCycle < curTick) { 6482875Sksewell@umich.edu scheduleTickEvent(delay); 6492875Sksewell@umich.edu 6502875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 6512875Sksewell@umich.edu // deschedule itself. 6522875Sksewell@umich.edu activityRec.activity(); 6532875Sksewell@umich.edu fetch.wakeFromQuiesce(); 6542875Sksewell@umich.edu 6552875Sksewell@umich.edu lastActivatedCycle = curTick; 6562875Sksewell@umich.edu 6572875Sksewell@umich.edu _status = Running; 6582875Sksewell@umich.edu } 6592875Sksewell@umich.edu} 6602875Sksewell@umich.edu 6612875Sksewell@umich.edutemplate <class Impl> 6623221Sktlim@umich.edubool 6633221Sktlim@umich.eduFullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay) 6642875Sksewell@umich.edu{ 6652875Sksewell@umich.edu // Schedule removal of thread data from CPU 6662875Sksewell@umich.edu if (delay){ 6672875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 6685100Ssaidi@eecs.umich.edu "on cycle %d\n", tid, curTick + ticks(delay)); 6693221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 6703221Sktlim@umich.edu return false; 6712875Sksewell@umich.edu } else { 6722875Sksewell@umich.edu deactivateThread(tid); 6733221Sktlim@umich.edu if (remove) 6743221Sktlim@umich.edu removeThread(tid); 6753221Sktlim@umich.edu return true; 6762875Sksewell@umich.edu } 6772875Sksewell@umich.edu} 6782875Sksewell@umich.edu 6792875Sksewell@umich.edutemplate <class Impl> 6802875Sksewell@umich.eduvoid 6812875Sksewell@umich.eduFullO3CPU<Impl>::suspendContext(int tid) 6822875Sksewell@umich.edu{ 6832875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 6843221Sktlim@umich.edu bool deallocated = deallocateContext(tid, false, 1); 6853221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 6865570Snate@binkert.org if ((activeThreads.size() == 1 && !deallocated) || 6873859Sbinkertn@umich.edu activeThreads.size() == 0) 6882910Sksewell@umich.edu unscheduleTickEvent(); 6892875Sksewell@umich.edu _status = Idle; 6902875Sksewell@umich.edu} 6912875Sksewell@umich.edu 6922875Sksewell@umich.edutemplate <class Impl> 6932875Sksewell@umich.eduvoid 6942875Sksewell@umich.eduFullO3CPU<Impl>::haltContext(int tid) 6952875Sksewell@umich.edu{ 6962910Sksewell@umich.edu //For now, this is the same as deallocate 6972910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 6983221Sktlim@umich.edu deallocateContext(tid, true, 1); 6992875Sksewell@umich.edu} 7002875Sksewell@umich.edu 7012875Sksewell@umich.edutemplate <class Impl> 7022875Sksewell@umich.eduvoid 7032292SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 7042292SN/A{ 7052847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 7062292SN/A // Will change now that the PC and thread state is internal to the CPU 7072683Sktlim@umich.edu // and not in the ThreadContext. 7082292SN/A#if FULL_SYSTEM 7092680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 7102292SN/A#else 7112847Sksewell@umich.edu ThreadContext *src_tc = tcBase(tid); 7122292SN/A#endif 7132292SN/A 7142292SN/A //Bind Int Regs to Rename Map 7152292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7162292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 7172292SN/A 7182292SN/A renameMap[tid].setEntry(ireg,phys_reg); 7192292SN/A scoreboard.setReg(phys_reg); 7202292SN/A } 7212292SN/A 7222292SN/A //Bind Float Regs to Rename Map 7232292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 7242292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 7252292SN/A 7262292SN/A renameMap[tid].setEntry(freg,phys_reg); 7272292SN/A scoreboard.setReg(phys_reg); 7282292SN/A } 7292292SN/A 7302292SN/A //Copy Thread Data Into RegFile 7312847Sksewell@umich.edu //this->copyFromTC(tid); 7322292SN/A 7332847Sksewell@umich.edu //Set PC/NPC/NNPC 7342847Sksewell@umich.edu setPC(src_tc->readPC(), tid); 7352847Sksewell@umich.edu setNextPC(src_tc->readNextPC(), tid); 7362847Sksewell@umich.edu setNextNPC(src_tc->readNextNPC(), tid); 7372292SN/A 7382680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 7392292SN/A 7402292SN/A activateContext(tid,1); 7412292SN/A 7422292SN/A //Reset ROB/IQ/LSQ Entries 7432292SN/A commit.rob->resetEntries(); 7442292SN/A iew.resetEntries(); 7452292SN/A} 7462292SN/A 7472292SN/Atemplate <class Impl> 7482292SN/Avoid 7492292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 7502292SN/A{ 7512877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 7522847Sksewell@umich.edu 7532847Sksewell@umich.edu // Copy Thread Data From RegFile 7542847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 7555364Sksewell@umich.edu // this->copyToTC(tid); 7565364Sksewell@umich.edu 7575364Sksewell@umich.edu 7585364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 7595364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 7605364Sksewell@umich.edu // in SMT workloads. 7612847Sksewell@umich.edu 7622847Sksewell@umich.edu // Unbind Int Regs from Rename Map 7632292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7642292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 7652292SN/A 7662292SN/A scoreboard.unsetReg(phys_reg); 7672292SN/A freeList.addReg(phys_reg); 7682292SN/A } 7692292SN/A 7702847Sksewell@umich.edu // Unbind Float Regs from Rename Map 7715362Sksewell@umich.edu for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 7722292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 7732292SN/A 7742292SN/A scoreboard.unsetReg(phys_reg); 7752292SN/A freeList.addReg(phys_reg); 7762292SN/A } 7772292SN/A 7782847Sksewell@umich.edu // Squash Throughout Pipeline 7792935Sksewell@umich.edu InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; 7804636Sgblack@eecs.umich.edu fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid); 7812292SN/A decode.squash(tid); 7822935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 7832875Sksewell@umich.edu iew.squash(tid); 7845363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 7852935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 7862292SN/A 7875362Sksewell@umich.edu 7885362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 7892292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 7902292SN/A 7912847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 7923229Sktlim@umich.edu 7933229Sktlim@umich.edu // Commented out for now. This should be possible to do by 7943229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 7953229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 7963229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 7973229Sktlim@umich.edu/* 7982292SN/A if (activeThreads.size() >= 1) { 7992292SN/A commit.rob->resetEntries(); 8002292SN/A iew.resetEntries(); 8012292SN/A } 8023229Sktlim@umich.edu*/ 8032292SN/A} 8042292SN/A 8052292SN/A 8062292SN/Atemplate <class Impl> 8072292SN/Avoid 8082292SN/AFullO3CPU<Impl>::activateWhenReady(int tid) 8092292SN/A{ 8102733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 8112292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 8122292SN/A tid); 8132292SN/A 8142292SN/A bool ready = true; 8152292SN/A 8162292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 8172733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8182292SN/A "Phys. Int. Regs.\n", 8192292SN/A tid); 8202292SN/A ready = false; 8212292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 8222733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8232292SN/A "Phys. Float. Regs.\n", 8242292SN/A tid); 8252292SN/A ready = false; 8262292SN/A } else if (commit.rob->numFreeEntries() >= 8272292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 8282733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8292292SN/A "ROB entries.\n", 8302292SN/A tid); 8312292SN/A ready = false; 8322292SN/A } else if (iew.instQueue.numFreeEntries() >= 8332292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 8342733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8352292SN/A "IQ entries.\n", 8362292SN/A tid); 8372292SN/A ready = false; 8382292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 8392292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 8402733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8412292SN/A "LSQ entries.\n", 8422292SN/A tid); 8432292SN/A ready = false; 8442292SN/A } 8452292SN/A 8462292SN/A if (ready) { 8472292SN/A insertThread(tid); 8482292SN/A 8492292SN/A contextSwitch = false; 8502292SN/A 8512292SN/A cpuWaitList.remove(tid); 8522292SN/A } else { 8532292SN/A suspendContext(tid); 8542292SN/A 8552292SN/A //blocks fetch 8562292SN/A contextSwitch = true; 8572292SN/A 8582875Sksewell@umich.edu //@todo: dont always add to waitlist 8592292SN/A //do waitlist 8602292SN/A cpuWaitList.push_back(tid); 8611060SN/A } 8621060SN/A} 8631060SN/A 8644192Sktlim@umich.edu#if FULL_SYSTEM 8654192Sktlim@umich.edutemplate <class Impl> 8665595Sgblack@eecs.umich.eduFault 8675702Ssaidi@eecs.umich.eduFullO3CPU<Impl>::hwrei(unsigned tid) 8685702Ssaidi@eecs.umich.edu{ 8695702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 8705702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 8715702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 8725702Ssaidi@eecs.umich.edu 8735702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 8745702Ssaidi@eecs.umich.edu 8755702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 8765702Ssaidi@eecs.umich.edu#endif 8775702Ssaidi@eecs.umich.edu return NoFault; 8785702Ssaidi@eecs.umich.edu} 8795702Ssaidi@eecs.umich.edu 8805702Ssaidi@eecs.umich.edutemplate <class Impl> 8815702Ssaidi@eecs.umich.edubool 8825702Ssaidi@eecs.umich.eduFullO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid) 8835702Ssaidi@eecs.umich.edu{ 8845702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 8855702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 8865702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 8875702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 8885702Ssaidi@eecs.umich.edu 8895702Ssaidi@eecs.umich.edu switch (palFunc) { 8905702Ssaidi@eecs.umich.edu case PAL::halt: 8915702Ssaidi@eecs.umich.edu halt(); 8925702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 8935702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 8945702Ssaidi@eecs.umich.edu break; 8955702Ssaidi@eecs.umich.edu 8965702Ssaidi@eecs.umich.edu case PAL::bpt: 8975702Ssaidi@eecs.umich.edu case PAL::bugchk: 8985702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 8995702Ssaidi@eecs.umich.edu return false; 9005702Ssaidi@eecs.umich.edu break; 9015702Ssaidi@eecs.umich.edu } 9025702Ssaidi@eecs.umich.edu#endif 9035702Ssaidi@eecs.umich.edu return true; 9045702Ssaidi@eecs.umich.edu} 9055702Ssaidi@eecs.umich.edu 9065702Ssaidi@eecs.umich.edutemplate <class Impl> 9075702Ssaidi@eecs.umich.eduFault 9085595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 9095595Sgblack@eecs.umich.edu{ 9105595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 9115647Sgblack@eecs.umich.edu return this->interrupts->getInterrupt(this->threadContexts[0]); 9125595Sgblack@eecs.umich.edu} 9135595Sgblack@eecs.umich.edu 9145595Sgblack@eecs.umich.edutemplate <class Impl> 9155595Sgblack@eecs.umich.eduvoid 9165595Sgblack@eecs.umich.eduFullO3CPU<Impl>::processInterrupts(Fault interrupt) 9175595Sgblack@eecs.umich.edu{ 9185595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 9195595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 9205595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 9215595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 9225595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 9235595Sgblack@eecs.umich.edu 9245595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 9255647Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 9265595Sgblack@eecs.umich.edu 9275595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 9285595Sgblack@eecs.umich.edu this->trap(interrupt, 0); 9295595Sgblack@eecs.umich.edu} 9305595Sgblack@eecs.umich.edu 9315595Sgblack@eecs.umich.edutemplate <class Impl> 9325595Sgblack@eecs.umich.eduvoid 9334192Sktlim@umich.eduFullO3CPU<Impl>::updateMemPorts() 9344192Sktlim@umich.edu{ 9354192Sktlim@umich.edu // Update all ThreadContext's memory ports (Functional/Virtual 9364192Sktlim@umich.edu // Ports) 9374192Sktlim@umich.edu for (int i = 0; i < thread.size(); ++i) 9385497Ssaidi@eecs.umich.edu thread[i]->connectMemPorts(thread[i]->getTC()); 9394192Sktlim@umich.edu} 9404192Sktlim@umich.edu#endif 9414192Sktlim@umich.edu 9421060SN/Atemplate <class Impl> 9432852Sktlim@umich.eduvoid 9445595Sgblack@eecs.umich.eduFullO3CPU<Impl>::trap(Fault fault, unsigned tid) 9455595Sgblack@eecs.umich.edu{ 9465595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 9475595Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid]); 9485595Sgblack@eecs.umich.edu} 9495595Sgblack@eecs.umich.edu 9505595Sgblack@eecs.umich.edu#if !FULL_SYSTEM 9515595Sgblack@eecs.umich.edu 9525595Sgblack@eecs.umich.edutemplate <class Impl> 9535595Sgblack@eecs.umich.eduvoid 9545595Sgblack@eecs.umich.eduFullO3CPU<Impl>::syscall(int64_t callnum, int tid) 9555595Sgblack@eecs.umich.edu{ 9565595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 9575595Sgblack@eecs.umich.edu 9585595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 9595595Sgblack@eecs.umich.edu 9605595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 9615595Sgblack@eecs.umich.edu // instruction. 9625595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 9635595Sgblack@eecs.umich.edu 9645595Sgblack@eecs.umich.edu // Execute the actual syscall. 9655595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 9665595Sgblack@eecs.umich.edu 9675595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 9685595Sgblack@eecs.umich.edu // incrementing it. 9695595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 9705595Sgblack@eecs.umich.edu} 9715595Sgblack@eecs.umich.edu 9725595Sgblack@eecs.umich.edu#endif 9735595Sgblack@eecs.umich.edu 9745595Sgblack@eecs.umich.edutemplate <class Impl> 9755595Sgblack@eecs.umich.eduvoid 9762864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 9772864Sktlim@umich.edu{ 9782918Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 9792918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 9802864Sktlim@umich.edu BaseCPU::serialize(os); 9812864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 9822864Sktlim@umich.edu tickEvent.serialize(os); 9832864Sktlim@umich.edu 9842864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 9852864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 9862864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 9872864Sktlim@umich.edu static SimpleThread temp; 9882864Sktlim@umich.edu 9892864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 9902864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 9912864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 9922864Sktlim@umich.edu temp.serialize(os); 9932864Sktlim@umich.edu } 9942864Sktlim@umich.edu} 9952864Sktlim@umich.edu 9962864Sktlim@umich.edutemplate <class Impl> 9972864Sktlim@umich.eduvoid 9982864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 9992864Sktlim@umich.edu{ 10002918Sktlim@umich.edu SimObject::State so_state; 10012918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 10022864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 10032864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 10042864Sktlim@umich.edu 10052864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10062864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 10072864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 10082864Sktlim@umich.edu static SimpleThread temp; 10092864Sktlim@umich.edu 10102864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 10112864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10122864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 10132864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 10142864Sktlim@umich.edu } 10152864Sktlim@umich.edu} 10162864Sktlim@umich.edu 10172864Sktlim@umich.edutemplate <class Impl> 10182905Sktlim@umich.eduunsigned int 10192843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 10201060SN/A{ 10213125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 10223512Sktlim@umich.edu 10233512Sktlim@umich.edu // If the CPU isn't doing anything, then return immediately. 10243512Sktlim@umich.edu if (_status == Idle || _status == SwitchedOut) { 10253512Sktlim@umich.edu return 0; 10263512Sktlim@umich.edu } 10273512Sktlim@umich.edu 10282843Sktlim@umich.edu drainCount = 0; 10292843Sktlim@umich.edu fetch.drain(); 10302843Sktlim@umich.edu decode.drain(); 10312843Sktlim@umich.edu rename.drain(); 10322843Sktlim@umich.edu iew.drain(); 10332843Sktlim@umich.edu commit.drain(); 10342325SN/A 10352325SN/A // Wake the CPU and record activity so everything can drain out if 10362863Sktlim@umich.edu // the CPU was not able to immediately drain. 10372905Sktlim@umich.edu if (getState() != SimObject::Drained) { 10382864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 10392864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 10402864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 10412864Sktlim@umich.edu // process on the drain event. 10422864Sktlim@umich.edu drainEvent = drain_event; 10432843Sktlim@umich.edu 10442863Sktlim@umich.edu wakeCPU(); 10452863Sktlim@umich.edu activityRec.activity(); 10462852Sktlim@umich.edu 10472905Sktlim@umich.edu return 1; 10482863Sktlim@umich.edu } else { 10492905Sktlim@umich.edu return 0; 10502863Sktlim@umich.edu } 10512316SN/A} 10522310SN/A 10532316SN/Atemplate <class Impl> 10542316SN/Avoid 10552843Sktlim@umich.eduFullO3CPU<Impl>::resume() 10562316SN/A{ 10572843Sktlim@umich.edu fetch.resume(); 10582843Sktlim@umich.edu decode.resume(); 10592843Sktlim@umich.edu rename.resume(); 10602843Sktlim@umich.edu iew.resume(); 10612843Sktlim@umich.edu commit.resume(); 10622316SN/A 10632905Sktlim@umich.edu changeState(SimObject::Running); 10642905Sktlim@umich.edu 10652864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 10662864Sktlim@umich.edu return; 10672864Sktlim@umich.edu 10683319Shsul@eecs.umich.edu#if FULL_SYSTEM 10694762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 10703319Shsul@eecs.umich.edu#endif 10713319Shsul@eecs.umich.edu 10722843Sktlim@umich.edu if (!tickEvent.scheduled()) 10735606Snate@binkert.org schedule(tickEvent, nextCycle()); 10742843Sktlim@umich.edu _status = Running; 10752843Sktlim@umich.edu} 10762316SN/A 10772843Sktlim@umich.edutemplate <class Impl> 10782843Sktlim@umich.eduvoid 10792843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 10802843Sktlim@umich.edu{ 10812843Sktlim@umich.edu if (++drainCount == NumStages) { 10822316SN/A if (tickEvent.scheduled()) 10832316SN/A tickEvent.squash(); 10842863Sktlim@umich.edu 10852905Sktlim@umich.edu changeState(SimObject::Drained); 10862863Sktlim@umich.edu 10873126Sktlim@umich.edu BaseCPU::switchOut(); 10883126Sktlim@umich.edu 10892863Sktlim@umich.edu if (drainEvent) { 10902863Sktlim@umich.edu drainEvent->process(); 10912863Sktlim@umich.edu drainEvent = NULL; 10922863Sktlim@umich.edu } 10932310SN/A } 10942843Sktlim@umich.edu assert(drainCount <= 5); 10952843Sktlim@umich.edu} 10962843Sktlim@umich.edu 10972843Sktlim@umich.edutemplate <class Impl> 10982843Sktlim@umich.eduvoid 10992843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 11002843Sktlim@umich.edu{ 11012843Sktlim@umich.edu fetch.switchOut(); 11022843Sktlim@umich.edu rename.switchOut(); 11032325SN/A iew.switchOut(); 11042843Sktlim@umich.edu commit.switchOut(); 11052843Sktlim@umich.edu instList.clear(); 11062843Sktlim@umich.edu while (!removeList.empty()) { 11072843Sktlim@umich.edu removeList.pop(); 11082843Sktlim@umich.edu } 11092843Sktlim@umich.edu 11102843Sktlim@umich.edu _status = SwitchedOut; 11112843Sktlim@umich.edu#if USE_CHECKER 11122843Sktlim@umich.edu if (checker) 11132843Sktlim@umich.edu checker->switchOut(); 11142843Sktlim@umich.edu#endif 11153126Sktlim@umich.edu if (tickEvent.scheduled()) 11163126Sktlim@umich.edu tickEvent.squash(); 11171060SN/A} 11181060SN/A 11191060SN/Atemplate <class Impl> 11201060SN/Avoid 11211755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 11221060SN/A{ 11232325SN/A // Flush out any old data from the time buffers. 11242873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 11252307SN/A timeBuffer.advance(); 11262307SN/A fetchQueue.advance(); 11272307SN/A decodeQueue.advance(); 11282307SN/A renameQueue.advance(); 11292307SN/A iewQueue.advance(); 11302307SN/A } 11312307SN/A 11322325SN/A activityRec.reset(); 11332307SN/A 11344192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort()); 11351060SN/A 11362307SN/A fetch.takeOverFrom(); 11372307SN/A decode.takeOverFrom(); 11382307SN/A rename.takeOverFrom(); 11392307SN/A iew.takeOverFrom(); 11402307SN/A commit.takeOverFrom(); 11412307SN/A 11421060SN/A assert(!tickEvent.scheduled()); 11431060SN/A 11442325SN/A // @todo: Figure out how to properly select the tid to put onto 11452325SN/A // the active threads list. 11462307SN/A int tid = 0; 11472307SN/A 11485314Sstever@gmail.com std::list<unsigned>::iterator isActive = 11495314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 11502307SN/A 11512307SN/A if (isActive == activeThreads.end()) { 11522325SN/A //May Need to Re-code this if the delay variable is the delay 11532325SN/A //needed for thread to activate 11542733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 11552307SN/A tid); 11562307SN/A 11572307SN/A activeThreads.push_back(tid); 11582307SN/A } 11592307SN/A 11602325SN/A // Set all statuses to active, schedule the CPU's tick event. 11612307SN/A // @todo: Fix up statuses so this is handled properly 11622680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 11632680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 11642680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 11651681SN/A _status = Running; 11665606Snate@binkert.org schedule(tickEvent, nextCycle()); 11671681SN/A } 11681060SN/A } 11692307SN/A if (!tickEvent.scheduled()) 11705606Snate@binkert.org schedule(tickEvent, nextCycle()); 11711060SN/A} 11721060SN/A 11731060SN/Atemplate <class Impl> 11745595Sgblack@eecs.umich.eduTheISA::MiscReg 11755595Sgblack@eecs.umich.eduFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid) 11765595Sgblack@eecs.umich.edu{ 11775595Sgblack@eecs.umich.edu return this->regFile.readMiscRegNoEffect(misc_reg, tid); 11785595Sgblack@eecs.umich.edu} 11795595Sgblack@eecs.umich.edu 11805595Sgblack@eecs.umich.edutemplate <class Impl> 11815595Sgblack@eecs.umich.eduTheISA::MiscReg 11825595Sgblack@eecs.umich.eduFullO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) 11835595Sgblack@eecs.umich.edu{ 11845595Sgblack@eecs.umich.edu return this->regFile.readMiscReg(misc_reg, tid); 11855595Sgblack@eecs.umich.edu} 11865595Sgblack@eecs.umich.edu 11875595Sgblack@eecs.umich.edutemplate <class Impl> 11885595Sgblack@eecs.umich.eduvoid 11895595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 11905595Sgblack@eecs.umich.edu const TheISA::MiscReg &val, unsigned tid) 11915595Sgblack@eecs.umich.edu{ 11925595Sgblack@eecs.umich.edu this->regFile.setMiscRegNoEffect(misc_reg, val, tid); 11935595Sgblack@eecs.umich.edu} 11945595Sgblack@eecs.umich.edu 11955595Sgblack@eecs.umich.edutemplate <class Impl> 11965595Sgblack@eecs.umich.eduvoid 11975595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 11985595Sgblack@eecs.umich.edu const TheISA::MiscReg &val, unsigned tid) 11995595Sgblack@eecs.umich.edu{ 12005595Sgblack@eecs.umich.edu this->regFile.setMiscReg(misc_reg, val, tid); 12015595Sgblack@eecs.umich.edu} 12025595Sgblack@eecs.umich.edu 12035595Sgblack@eecs.umich.edutemplate <class Impl> 12041060SN/Auint64_t 12051755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 12061060SN/A{ 12071060SN/A return regFile.readIntReg(reg_idx); 12081060SN/A} 12091060SN/A 12101060SN/Atemplate <class Impl> 12112455SN/AFloatReg 12122455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 12131060SN/A{ 12142455SN/A return regFile.readFloatReg(reg_idx, width); 12151060SN/A} 12161060SN/A 12171060SN/Atemplate <class Impl> 12182455SN/AFloatReg 12192455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 12201060SN/A{ 12212455SN/A return regFile.readFloatReg(reg_idx); 12221060SN/A} 12231060SN/A 12241060SN/Atemplate <class Impl> 12252455SN/AFloatRegBits 12262455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 12271060SN/A{ 12282455SN/A return regFile.readFloatRegBits(reg_idx, width); 12292455SN/A} 12302455SN/A 12312455SN/Atemplate <class Impl> 12322455SN/AFloatRegBits 12332455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 12342455SN/A{ 12352455SN/A return regFile.readFloatRegBits(reg_idx); 12361060SN/A} 12371060SN/A 12381060SN/Atemplate <class Impl> 12391060SN/Avoid 12401755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 12411060SN/A{ 12421060SN/A regFile.setIntReg(reg_idx, val); 12431060SN/A} 12441060SN/A 12451060SN/Atemplate <class Impl> 12461060SN/Avoid 12472455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 12481060SN/A{ 12492455SN/A regFile.setFloatReg(reg_idx, val, width); 12501060SN/A} 12511060SN/A 12521060SN/Atemplate <class Impl> 12531060SN/Avoid 12542455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 12551060SN/A{ 12562455SN/A regFile.setFloatReg(reg_idx, val); 12571060SN/A} 12581060SN/A 12591060SN/Atemplate <class Impl> 12601060SN/Avoid 12612455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 12621060SN/A{ 12632455SN/A regFile.setFloatRegBits(reg_idx, val, width); 12642455SN/A} 12652455SN/A 12662455SN/Atemplate <class Impl> 12672455SN/Avoid 12682455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 12692455SN/A{ 12702455SN/A regFile.setFloatRegBits(reg_idx, val); 12711060SN/A} 12721060SN/A 12731060SN/Atemplate <class Impl> 12741060SN/Auint64_t 12752292SN/AFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 12761060SN/A{ 12772292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 12782292SN/A 12792292SN/A return regFile.readIntReg(phys_reg); 12802292SN/A} 12812292SN/A 12822292SN/Atemplate <class Impl> 12832292SN/Afloat 12842292SN/AFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 12852292SN/A{ 12866032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 12872307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 12882292SN/A 12892669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 12902292SN/A} 12912292SN/A 12922292SN/Atemplate <class Impl> 12932292SN/Adouble 12942292SN/AFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 12952292SN/A{ 12966032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 12972307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 12982292SN/A 12992669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 13002292SN/A} 13012292SN/A 13022292SN/Atemplate <class Impl> 13032292SN/Auint64_t 13042292SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 13052292SN/A{ 13066032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13072307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13082292SN/A 13092669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 13101060SN/A} 13111060SN/A 13121060SN/Atemplate <class Impl> 13131060SN/Avoid 13142292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 13151060SN/A{ 13162292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13172292SN/A 13182292SN/A regFile.setIntReg(phys_reg, val); 13191060SN/A} 13201060SN/A 13211060SN/Atemplate <class Impl> 13221060SN/Avoid 13232292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 13241060SN/A{ 13256032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13262918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13272292SN/A 13282669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 13291060SN/A} 13301060SN/A 13311060SN/Atemplate <class Impl> 13321060SN/Avoid 13332292SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 13341060SN/A{ 13356032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13362918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13372292SN/A 13382669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 13391060SN/A} 13401060SN/A 13411060SN/Atemplate <class Impl> 13421060SN/Avoid 13432292SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 13441060SN/A{ 13456032Ssteve.reinhardt@amd.com int idx = reg_idx + TheISA::NumIntRegs; 13462918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13471060SN/A 13482669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 13492292SN/A} 13502292SN/A 13512292SN/Atemplate <class Impl> 13522292SN/Auint64_t 13532292SN/AFullO3CPU<Impl>::readPC(unsigned tid) 13542292SN/A{ 13552292SN/A return commit.readPC(tid); 13561060SN/A} 13571060SN/A 13581060SN/Atemplate <class Impl> 13591060SN/Avoid 13602292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 13611060SN/A{ 13622292SN/A commit.setPC(new_PC, tid); 13632292SN/A} 13641060SN/A 13652292SN/Atemplate <class Impl> 13662292SN/Auint64_t 13674636Sgblack@eecs.umich.eduFullO3CPU<Impl>::readMicroPC(unsigned tid) 13684636Sgblack@eecs.umich.edu{ 13694636Sgblack@eecs.umich.edu return commit.readMicroPC(tid); 13704636Sgblack@eecs.umich.edu} 13714636Sgblack@eecs.umich.edu 13724636Sgblack@eecs.umich.edutemplate <class Impl> 13734636Sgblack@eecs.umich.eduvoid 13744636Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMicroPC(Addr new_PC,unsigned tid) 13754636Sgblack@eecs.umich.edu{ 13764636Sgblack@eecs.umich.edu commit.setMicroPC(new_PC, tid); 13774636Sgblack@eecs.umich.edu} 13784636Sgblack@eecs.umich.edu 13794636Sgblack@eecs.umich.edutemplate <class Impl> 13804636Sgblack@eecs.umich.eduuint64_t 13812292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 13822292SN/A{ 13832292SN/A return commit.readNextPC(tid); 13842292SN/A} 13851060SN/A 13862292SN/Atemplate <class Impl> 13872292SN/Avoid 13882292SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 13892292SN/A{ 13902292SN/A commit.setNextPC(val, tid); 13912292SN/A} 13921060SN/A 13932756Sksewell@umich.edutemplate <class Impl> 13942756Sksewell@umich.eduuint64_t 13952756Sksewell@umich.eduFullO3CPU<Impl>::readNextNPC(unsigned tid) 13962756Sksewell@umich.edu{ 13972756Sksewell@umich.edu return commit.readNextNPC(tid); 13982756Sksewell@umich.edu} 13992756Sksewell@umich.edu 14002756Sksewell@umich.edutemplate <class Impl> 14012756Sksewell@umich.eduvoid 14022935Sksewell@umich.eduFullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid) 14032756Sksewell@umich.edu{ 14042756Sksewell@umich.edu commit.setNextNPC(val, tid); 14052756Sksewell@umich.edu} 14062756Sksewell@umich.edu 14072292SN/Atemplate <class Impl> 14084636Sgblack@eecs.umich.eduuint64_t 14094636Sgblack@eecs.umich.eduFullO3CPU<Impl>::readNextMicroPC(unsigned tid) 14104636Sgblack@eecs.umich.edu{ 14114636Sgblack@eecs.umich.edu return commit.readNextMicroPC(tid); 14124636Sgblack@eecs.umich.edu} 14134636Sgblack@eecs.umich.edu 14144636Sgblack@eecs.umich.edutemplate <class Impl> 14154636Sgblack@eecs.umich.eduvoid 14164636Sgblack@eecs.umich.eduFullO3CPU<Impl>::setNextMicroPC(Addr new_PC,unsigned tid) 14174636Sgblack@eecs.umich.edu{ 14184636Sgblack@eecs.umich.edu commit.setNextMicroPC(new_PC, tid); 14194636Sgblack@eecs.umich.edu} 14204636Sgblack@eecs.umich.edu 14214636Sgblack@eecs.umich.edutemplate <class Impl> 14225595Sgblack@eecs.umich.eduvoid 14235595Sgblack@eecs.umich.eduFullO3CPU<Impl>::squashFromTC(unsigned tid) 14245595Sgblack@eecs.umich.edu{ 14255595Sgblack@eecs.umich.edu this->thread[tid]->inSyscall = true; 14265595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 14275595Sgblack@eecs.umich.edu} 14285595Sgblack@eecs.umich.edu 14295595Sgblack@eecs.umich.edutemplate <class Impl> 14302292SN/Atypename FullO3CPU<Impl>::ListIt 14312292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 14322292SN/A{ 14332292SN/A instList.push_back(inst); 14341060SN/A 14352292SN/A return --(instList.end()); 14362292SN/A} 14371060SN/A 14382292SN/Atemplate <class Impl> 14392292SN/Avoid 14402292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 14412292SN/A{ 14422292SN/A // Keep an instruction count. 14432292SN/A thread[tid]->numInst++; 14442292SN/A thread[tid]->numInsts++; 14452292SN/A committedInsts[tid]++; 14462292SN/A totalCommittedInsts++; 14472292SN/A 14482292SN/A // Check for instruction-count-based events. 14492292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 14502292SN/A} 14512292SN/A 14522292SN/Atemplate <class Impl> 14532292SN/Avoid 14542292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 14552292SN/A{ 14562292SN/A removeInstsThisCycle = true; 14572292SN/A 14582292SN/A removeList.push(inst->getInstListIt()); 14591060SN/A} 14601060SN/A 14611060SN/Atemplate <class Impl> 14621060SN/Avoid 14631755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 14641060SN/A{ 14652733Sktlim@umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 14662292SN/A "[sn:%lli]\n", 14672303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 14681060SN/A 14692292SN/A removeInstsThisCycle = true; 14701060SN/A 14711060SN/A // Remove the front instruction. 14722292SN/A removeList.push(inst->getInstListIt()); 14731060SN/A} 14741060SN/A 14751060SN/Atemplate <class Impl> 14761060SN/Avoid 14774632Sgblack@eecs.umich.eduFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 14781060SN/A{ 14792733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 14802292SN/A " list.\n", tid); 14811060SN/A 14822292SN/A ListIt end_it; 14831060SN/A 14842292SN/A bool rob_empty = false; 14852292SN/A 14862292SN/A if (instList.empty()) { 14872292SN/A return; 14882292SN/A } else if (rob.isEmpty(/*tid*/)) { 14892733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 14902292SN/A end_it = instList.begin(); 14912292SN/A rob_empty = true; 14922292SN/A } else { 14932292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 14942733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 14952292SN/A } 14962292SN/A 14972292SN/A removeInstsThisCycle = true; 14982292SN/A 14992292SN/A ListIt inst_it = instList.end(); 15002292SN/A 15012292SN/A inst_it--; 15022292SN/A 15032292SN/A // Walk through the instruction list, removing any instructions 15042292SN/A // that were inserted after the given instruction iterator, end_it. 15052292SN/A while (inst_it != end_it) { 15062292SN/A assert(!instList.empty()); 15072292SN/A 15082292SN/A squashInstIt(inst_it, tid); 15092292SN/A 15102292SN/A inst_it--; 15112292SN/A } 15122292SN/A 15132292SN/A // If the ROB was empty, then we actually need to remove the first 15142292SN/A // instruction as well. 15152292SN/A if (rob_empty) { 15162292SN/A squashInstIt(inst_it, tid); 15172292SN/A } 15181060SN/A} 15191060SN/A 15201060SN/Atemplate <class Impl> 15211060SN/Avoid 15222292SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 15232292SN/A unsigned tid) 15241062SN/A{ 15252292SN/A assert(!instList.empty()); 15262292SN/A 15272292SN/A removeInstsThisCycle = true; 15282292SN/A 15292292SN/A ListIt inst_iter = instList.end(); 15302292SN/A 15312292SN/A inst_iter--; 15322292SN/A 15332733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 15342292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 15352292SN/A tid, seq_num, (*inst_iter)->seqNum); 15361062SN/A 15372292SN/A while ((*inst_iter)->seqNum > seq_num) { 15381062SN/A 15392292SN/A bool break_loop = (inst_iter == instList.begin()); 15401062SN/A 15412292SN/A squashInstIt(inst_iter, tid); 15421062SN/A 15432292SN/A inst_iter--; 15441062SN/A 15452292SN/A if (break_loop) 15462292SN/A break; 15472292SN/A } 15482292SN/A} 15492292SN/A 15502292SN/Atemplate <class Impl> 15512292SN/Ainline void 15522292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 15532292SN/A{ 15542292SN/A if ((*instIt)->threadNumber == tid) { 15552733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 15562292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 15572292SN/A (*instIt)->threadNumber, 15582292SN/A (*instIt)->seqNum, 15592292SN/A (*instIt)->readPC()); 15601062SN/A 15611062SN/A // Mark it as squashed. 15622292SN/A (*instIt)->setSquashed(); 15632292SN/A 15642325SN/A // @todo: Formulate a consistent method for deleting 15652325SN/A // instructions from the instruction list 15662292SN/A // Remove the instruction from the list. 15672292SN/A removeList.push(instIt); 15682292SN/A } 15692292SN/A} 15702292SN/A 15712292SN/Atemplate <class Impl> 15722292SN/Avoid 15732292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 15742292SN/A{ 15752292SN/A while (!removeList.empty()) { 15762733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 15772292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 15782292SN/A (*removeList.front())->threadNumber, 15792292SN/A (*removeList.front())->seqNum, 15802292SN/A (*removeList.front())->readPC()); 15812292SN/A 15822292SN/A instList.erase(removeList.front()); 15832292SN/A 15842292SN/A removeList.pop(); 15851062SN/A } 15861062SN/A 15872292SN/A removeInstsThisCycle = false; 15881062SN/A} 15892325SN/A/* 15901062SN/Atemplate <class Impl> 15911062SN/Avoid 15921755SN/AFullO3CPU<Impl>::removeAllInsts() 15931060SN/A{ 15941060SN/A instList.clear(); 15951060SN/A} 15962325SN/A*/ 15971060SN/Atemplate <class Impl> 15981060SN/Avoid 15991755SN/AFullO3CPU<Impl>::dumpInsts() 16001060SN/A{ 16011060SN/A int num = 0; 16021060SN/A 16032292SN/A ListIt inst_list_it = instList.begin(); 16042292SN/A 16052292SN/A cprintf("Dumping Instruction List\n"); 16062292SN/A 16072292SN/A while (inst_list_it != instList.end()) { 16082292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 16092292SN/A "Squashed:%i\n\n", 16102292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 16112292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 16122292SN/A (*inst_list_it)->isSquashed()); 16131060SN/A inst_list_it++; 16141060SN/A ++num; 16151060SN/A } 16161060SN/A} 16172325SN/A/* 16181060SN/Atemplate <class Impl> 16191060SN/Avoid 16201755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 16211060SN/A{ 16221060SN/A iew.wakeDependents(inst); 16231060SN/A} 16242325SN/A*/ 16252292SN/Atemplate <class Impl> 16262292SN/Avoid 16272292SN/AFullO3CPU<Impl>::wakeCPU() 16282292SN/A{ 16292325SN/A if (activityRec.active() || tickEvent.scheduled()) { 16302325SN/A DPRINTF(Activity, "CPU already running.\n"); 16312292SN/A return; 16322292SN/A } 16332292SN/A 16342325SN/A DPRINTF(Activity, "Waking up CPU\n"); 16352325SN/A 16365099Ssaidi@eecs.umich.edu idleCycles += tickToCycles((curTick - 1) - lastRunningCycle); 16375099Ssaidi@eecs.umich.edu numCycles += tickToCycles((curTick - 1) - lastRunningCycle); 16382292SN/A 16395606Snate@binkert.org schedule(tickEvent, nextCycle()); 16402292SN/A} 16412292SN/A 16425807Snate@binkert.org#if FULL_SYSTEM 16435807Snate@binkert.orgtemplate <class Impl> 16445807Snate@binkert.orgvoid 16455807Snate@binkert.orgFullO3CPU<Impl>::wakeup() 16465807Snate@binkert.org{ 16475807Snate@binkert.org if (this->thread[0]->status() != ThreadContext::Suspended) 16485807Snate@binkert.org return; 16495807Snate@binkert.org 16505807Snate@binkert.org this->wakeCPU(); 16515807Snate@binkert.org 16525807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 16535807Snate@binkert.org this->threadContexts[0]->activate(); 16545807Snate@binkert.org} 16555807Snate@binkert.org#endif 16565807Snate@binkert.org 16572292SN/Atemplate <class Impl> 16582292SN/Aint 16592292SN/AFullO3CPU<Impl>::getFreeTid() 16602292SN/A{ 16612292SN/A for (int i=0; i < numThreads; i++) { 16622292SN/A if (!tids[i]) { 16632292SN/A tids[i] = true; 16642292SN/A return i; 16652292SN/A } 16662292SN/A } 16672292SN/A 16682292SN/A return -1; 16692292SN/A} 16702292SN/A 16712292SN/Atemplate <class Impl> 16722292SN/Avoid 16732292SN/AFullO3CPU<Impl>::doContextSwitch() 16742292SN/A{ 16752292SN/A if (contextSwitch) { 16762292SN/A 16772292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 16782292SN/A 16792292SN/A for (int tid=0; tid < cpuWaitList.size(); tid++) { 16802292SN/A activateWhenReady(tid); 16812292SN/A } 16822292SN/A 16832292SN/A if (cpuWaitList.size() == 0) 16842292SN/A contextSwitch = true; 16852292SN/A } 16862292SN/A} 16872292SN/A 16882292SN/Atemplate <class Impl> 16892292SN/Avoid 16902292SN/AFullO3CPU<Impl>::updateThreadPriority() 16912292SN/A{ 16922292SN/A if (activeThreads.size() > 1) 16932292SN/A { 16942292SN/A //DEFAULT TO ROUND ROBIN SCHEME 16952292SN/A //e.g. Move highest priority to end of thread list 16965314Sstever@gmail.com std::list<unsigned>::iterator list_begin = activeThreads.begin(); 16975314Sstever@gmail.com std::list<unsigned>::iterator list_end = activeThreads.end(); 16982292SN/A 16992292SN/A unsigned high_thread = *list_begin; 17002292SN/A 17012292SN/A activeThreads.erase(list_begin); 17022292SN/A 17032292SN/A activeThreads.push_back(high_thread); 17042292SN/A } 17052292SN/A} 17061060SN/A 17071755SN/A// Forward declaration of FullO3CPU. 17082818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1709