cpu.cc revision 5804
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 341858SN/A 354762Snate@binkert.org#include "cpu/activity.hh" 364762Snate@binkert.org#include "cpu/simple_thread.hh" 374762Snate@binkert.org#include "cpu/thread_context.hh" 384762Snate@binkert.org#include "cpu/o3/isa_specific.hh" 394762Snate@binkert.org#include "cpu/o3/cpu.hh" 405595Sgblack@eecs.umich.edu#include "cpu/o3/thread_context.hh" 414762Snate@binkert.org#include "enums/MemoryMode.hh" 424762Snate@binkert.org#include "sim/core.hh" 434762Snate@binkert.org#include "sim/stat_control.hh" 444762Snate@binkert.org 451858SN/A#if FULL_SYSTEM 462356SN/A#include "cpu/quiesce_event.hh" 471060SN/A#include "sim/system.hh" 481060SN/A#else 491060SN/A#include "sim/process.hh" 501060SN/A#endif 511060SN/A 522794Sktlim@umich.edu#if USE_CHECKER 532794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 542794Sktlim@umich.edu#endif 552794Sktlim@umich.edu 565702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 575702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 585702Ssaidi@eecs.umich.edu#endif 595702Ssaidi@eecs.umich.edu 605529Snate@binkert.orgclass BaseCPUParams; 615529Snate@binkert.org 622669Sktlim@umich.eduusing namespace TheISA; 631060SN/A 645529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 655712Shsul@eecs.umich.edu : BaseCPU(params) 661060SN/A{ 671060SN/A} 681060SN/A 692292SN/Avoid 702733Sktlim@umich.eduBaseO3CPU::regStats() 712292SN/A{ 722292SN/A BaseCPU::regStats(); 732292SN/A} 742292SN/A 751060SN/Atemplate <class Impl> 761755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 775606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 781060SN/A{ 791060SN/A} 801060SN/A 811060SN/Atemplate <class Impl> 821060SN/Avoid 831755SN/AFullO3CPU<Impl>::TickEvent::process() 841060SN/A{ 851060SN/A cpu->tick(); 861060SN/A} 871060SN/A 881060SN/Atemplate <class Impl> 891060SN/Aconst char * 905336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 911060SN/A{ 924873Sstever@eecs.umich.edu return "FullO3CPU tick"; 931060SN/A} 941060SN/A 951060SN/Atemplate <class Impl> 962829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 975606Snate@binkert.org : Event(CPU_Switch_Pri) 982829Sksewell@umich.edu{ 992829Sksewell@umich.edu} 1002829Sksewell@umich.edu 1012829Sksewell@umich.edutemplate <class Impl> 1022829Sksewell@umich.eduvoid 1032829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 1042829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1052829Sksewell@umich.edu{ 1062829Sksewell@umich.edu tid = thread_num; 1072829Sksewell@umich.edu cpu = thread_cpu; 1082829Sksewell@umich.edu} 1092829Sksewell@umich.edu 1102829Sksewell@umich.edutemplate <class Impl> 1112829Sksewell@umich.eduvoid 1122829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1132829Sksewell@umich.edu{ 1142829Sksewell@umich.edu cpu->activateThread(tid); 1152829Sksewell@umich.edu} 1162829Sksewell@umich.edu 1172829Sksewell@umich.edutemplate <class Impl> 1182829Sksewell@umich.educonst char * 1195336Shines@cs.fsu.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1202829Sksewell@umich.edu{ 1214873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1222829Sksewell@umich.edu} 1232829Sksewell@umich.edu 1242829Sksewell@umich.edutemplate <class Impl> 1252875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1265606Snate@binkert.org : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1272875Sksewell@umich.edu{ 1282875Sksewell@umich.edu} 1292875Sksewell@umich.edu 1302875Sksewell@umich.edutemplate <class Impl> 1312875Sksewell@umich.eduvoid 1322875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1333859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1342875Sksewell@umich.edu{ 1352875Sksewell@umich.edu tid = thread_num; 1362875Sksewell@umich.edu cpu = thread_cpu; 1373859Sbinkertn@umich.edu remove = false; 1382875Sksewell@umich.edu} 1392875Sksewell@umich.edu 1402875Sksewell@umich.edutemplate <class Impl> 1412875Sksewell@umich.eduvoid 1422875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1432875Sksewell@umich.edu{ 1442875Sksewell@umich.edu cpu->deactivateThread(tid); 1453221Sktlim@umich.edu if (remove) 1463221Sktlim@umich.edu cpu->removeThread(tid); 1472875Sksewell@umich.edu} 1482875Sksewell@umich.edu 1492875Sksewell@umich.edutemplate <class Impl> 1502875Sksewell@umich.educonst char * 1515336Shines@cs.fsu.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 1522875Sksewell@umich.edu{ 1534873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 1542875Sksewell@umich.edu} 1552875Sksewell@umich.edu 1562875Sksewell@umich.edutemplate <class Impl> 1575595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 1582733Sktlim@umich.edu : BaseO3CPU(params), 1593781Sgblack@eecs.umich.edu itb(params->itb), 1603781Sgblack@eecs.umich.edu dtb(params->dtb), 1611060SN/A tickEvent(this), 1625737Scws3k@cs.virginia.edu#ifndef NDEBUG 1635737Scws3k@cs.virginia.edu instcount(0), 1645737Scws3k@cs.virginia.edu#endif 1652292SN/A removeInstsThisCycle(false), 1665595Sgblack@eecs.umich.edu fetch(this, params), 1675595Sgblack@eecs.umich.edu decode(this, params), 1685595Sgblack@eecs.umich.edu rename(this, params), 1695595Sgblack@eecs.umich.edu iew(this, params), 1705595Sgblack@eecs.umich.edu commit(this, params), 1711060SN/A 1725595Sgblack@eecs.umich.edu regFile(this, params->numPhysIntRegs, 1734329Sktlim@umich.edu params->numPhysFloatRegs), 1741060SN/A 1755529Snate@binkert.org freeList(params->numThreads, 1762292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1772292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1781060SN/A 1795595Sgblack@eecs.umich.edu rob(this, 1804329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 1812292SN/A params->smtROBPolicy, params->smtROBThreshold, 1825529Snate@binkert.org params->numThreads), 1831060SN/A 1845529Snate@binkert.org scoreboard(params->numThreads, 1852292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1862292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1872292SN/A TheISA::NumMiscRegs * number_of_threads, 1882292SN/A TheISA::ZeroReg), 1891060SN/A 1902873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1912873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1922873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1932873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1942873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1955804Snate@binkert.org activityRec(name(), NumStages, 1962873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1972873Sktlim@umich.edu params->activity), 1981060SN/A 1991060SN/A globalSeqNum(1), 2001858SN/A#if FULL_SYSTEM 2012292SN/A system(params->system), 2021060SN/A physmem(system->physmem), 2031060SN/A#endif // FULL_SYSTEM 2042843Sktlim@umich.edu drainCount(0), 2055529Snate@binkert.org deferRegistration(params->defer_registration), 2062316SN/A numThreads(number_of_threads) 2071060SN/A{ 2083221Sktlim@umich.edu if (!deferRegistration) { 2093221Sktlim@umich.edu _status = Running; 2103221Sktlim@umich.edu } else { 2113221Sktlim@umich.edu _status = Idle; 2123221Sktlim@umich.edu } 2131681SN/A 2144598Sbinkertn@umich.edu#if USE_CHECKER 2152794Sktlim@umich.edu if (params->checker) { 2162316SN/A BaseCPU *temp_checker = params->checker; 2172316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2182316SN/A#if FULL_SYSTEM 2192316SN/A checker->setSystem(params->system); 2202316SN/A#endif 2214598Sbinkertn@umich.edu } else { 2224598Sbinkertn@umich.edu checker = NULL; 2234598Sbinkertn@umich.edu } 2242794Sktlim@umich.edu#endif // USE_CHECKER 2252316SN/A 2261858SN/A#if !FULL_SYSTEM 2272292SN/A thread.resize(number_of_threads); 2282292SN/A tids.resize(number_of_threads); 2291681SN/A#endif 2301681SN/A 2312325SN/A // The stages also need their CPU pointer setup. However this 2322325SN/A // must be done at the upper level CPU because they have pointers 2332325SN/A // to the upper level CPU, and not this FullO3CPU. 2341060SN/A 2352292SN/A // Set up Pointers to the activeThreads list for each stage 2362292SN/A fetch.setActiveThreads(&activeThreads); 2372292SN/A decode.setActiveThreads(&activeThreads); 2382292SN/A rename.setActiveThreads(&activeThreads); 2392292SN/A iew.setActiveThreads(&activeThreads); 2402292SN/A commit.setActiveThreads(&activeThreads); 2411060SN/A 2421060SN/A // Give each of the stages the time buffer they will use. 2431060SN/A fetch.setTimeBuffer(&timeBuffer); 2441060SN/A decode.setTimeBuffer(&timeBuffer); 2451060SN/A rename.setTimeBuffer(&timeBuffer); 2461060SN/A iew.setTimeBuffer(&timeBuffer); 2471060SN/A commit.setTimeBuffer(&timeBuffer); 2481060SN/A 2491060SN/A // Also setup each of the stages' queues. 2501060SN/A fetch.setFetchQueue(&fetchQueue); 2511060SN/A decode.setFetchQueue(&fetchQueue); 2522292SN/A commit.setFetchQueue(&fetchQueue); 2531060SN/A decode.setDecodeQueue(&decodeQueue); 2541060SN/A rename.setDecodeQueue(&decodeQueue); 2551060SN/A rename.setRenameQueue(&renameQueue); 2561060SN/A iew.setRenameQueue(&renameQueue); 2571060SN/A iew.setIEWQueue(&iewQueue); 2581060SN/A commit.setIEWQueue(&iewQueue); 2591060SN/A commit.setRenameQueue(&renameQueue); 2601060SN/A 2612292SN/A commit.setIEWStage(&iew); 2622292SN/A rename.setIEWStage(&iew); 2632292SN/A rename.setCommitStage(&commit); 2642292SN/A 2652292SN/A#if !FULL_SYSTEM 2662307SN/A int active_threads = params->workload.size(); 2672831Sksewell@umich.edu 2682831Sksewell@umich.edu if (active_threads > Impl::MaxThreads) { 2692831Sksewell@umich.edu panic("Workload Size too large. Increase the 'MaxThreads'" 2702831Sksewell@umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2712831Sksewell@umich.edu "edit your workload size."); 2722831Sksewell@umich.edu } 2732292SN/A#else 2742307SN/A int active_threads = 1; 2752292SN/A#endif 2762292SN/A 2772316SN/A //Make Sure That this a Valid Architeture 2782292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2792292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2802292SN/A 2812292SN/A rename.setScoreboard(&scoreboard); 2822292SN/A iew.setScoreboard(&scoreboard); 2832292SN/A 2841060SN/A // Setup the rename map for whichever stages need it. 2852292SN/A PhysRegIndex lreg_idx = 0; 2862292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2871060SN/A 2882292SN/A for (int tid=0; tid < numThreads; tid++) { 2892307SN/A bool bindRegs = (tid <= active_threads - 1); 2902292SN/A 2912292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2922292SN/A params->numPhysIntRegs, 2932325SN/A lreg_idx, //Index for Logical. Regs 2942292SN/A 2952292SN/A TheISA::NumFloatRegs, 2962292SN/A params->numPhysFloatRegs, 2972325SN/A freg_idx, //Index for Float Regs 2982292SN/A 2992292SN/A TheISA::NumMiscRegs, 3002292SN/A 3012292SN/A TheISA::ZeroReg, 3022292SN/A TheISA::ZeroReg, 3032292SN/A 3042292SN/A tid, 3052292SN/A false); 3062292SN/A 3072292SN/A renameMap[tid].init(TheISA::NumIntRegs, 3082292SN/A params->numPhysIntRegs, 3092325SN/A lreg_idx, //Index for Logical. Regs 3102292SN/A 3112292SN/A TheISA::NumFloatRegs, 3122292SN/A params->numPhysFloatRegs, 3132325SN/A freg_idx, //Index for Float Regs 3142292SN/A 3152292SN/A TheISA::NumMiscRegs, 3162292SN/A 3172292SN/A TheISA::ZeroReg, 3182292SN/A TheISA::ZeroReg, 3192292SN/A 3202292SN/A tid, 3212292SN/A bindRegs); 3223221Sktlim@umich.edu 3233221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3243221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3252292SN/A } 3262292SN/A 3272292SN/A rename.setRenameMap(renameMap); 3282292SN/A commit.setRenameMap(commitRenameMap); 3292292SN/A 3302292SN/A // Give renameMap & rename stage access to the freeList; 3312292SN/A for (int i=0; i < numThreads; i++) { 3322292SN/A renameMap[i].setFreeList(&freeList); 3332292SN/A } 3341060SN/A rename.setFreeList(&freeList); 3352292SN/A 3361060SN/A // Setup the ROB for whichever stages need it. 3371060SN/A commit.setROB(&rob); 3382292SN/A 3392292SN/A lastRunningCycle = curTick; 3402292SN/A 3412829Sksewell@umich.edu lastActivatedCycle = -1; 3422829Sksewell@umich.edu 3433093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3443093Sksewell@umich.edu //for (int i=0; i < numThreads; i++) { 3453093Sksewell@umich.edu //globalSeqNum[i] = 1; 3463093Sksewell@umich.edu //} 3473093Sksewell@umich.edu 3482292SN/A contextSwitch = false; 3495595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3505595Sgblack@eecs.umich.edu 3515595Sgblack@eecs.umich.edu // Setup any thread state. 3525595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 3535595Sgblack@eecs.umich.edu 3545595Sgblack@eecs.umich.edu for (int i = 0; i < this->numThreads; ++i) { 3555595Sgblack@eecs.umich.edu#if FULL_SYSTEM 3565595Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 3575595Sgblack@eecs.umich.edu assert(this->numThreads == 1); 3585595Sgblack@eecs.umich.edu this->thread[i] = new Thread(this, 0); 3595595Sgblack@eecs.umich.edu this->thread[i]->setStatus(ThreadContext::Suspended); 3605595Sgblack@eecs.umich.edu#else 3615595Sgblack@eecs.umich.edu if (i < params->workload.size()) { 3625595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 3635595Sgblack@eecs.umich.edu i, this->thread[i]); 3645595Sgblack@eecs.umich.edu this->thread[i] = new typename FullO3CPU<Impl>::Thread( 3655595Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3665595Sgblack@eecs.umich.edu i, params->workload[i], i); 3675595Sgblack@eecs.umich.edu 3685595Sgblack@eecs.umich.edu this->thread[i]->setStatus(ThreadContext::Suspended); 3695595Sgblack@eecs.umich.edu 3705595Sgblack@eecs.umich.edu //usedTids[i] = true; 3715595Sgblack@eecs.umich.edu //threadMap[i] = i; 3725595Sgblack@eecs.umich.edu } else { 3735595Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 3745595Sgblack@eecs.umich.edu //when scheduling threads to CPU 3755595Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 3765595Sgblack@eecs.umich.edu 3775595Sgblack@eecs.umich.edu this->thread[i] = new typename FullO3CPU<Impl>::Thread( 3785595Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3795595Sgblack@eecs.umich.edu i, dummy_proc, i); 3805595Sgblack@eecs.umich.edu //usedTids[i] = false; 3815595Sgblack@eecs.umich.edu } 3825595Sgblack@eecs.umich.edu#endif // !FULL_SYSTEM 3835595Sgblack@eecs.umich.edu 3845595Sgblack@eecs.umich.edu ThreadContext *tc; 3855595Sgblack@eecs.umich.edu 3865595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 3875595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 3885595Sgblack@eecs.umich.edu 3895595Sgblack@eecs.umich.edu tc = o3_tc; 3905595Sgblack@eecs.umich.edu 3915595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 3925595Sgblack@eecs.umich.edu // CheckerThreadContext. 3935595Sgblack@eecs.umich.edu#if USE_CHECKER 3945595Sgblack@eecs.umich.edu if (params->checker) { 3955595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 3965595Sgblack@eecs.umich.edu o3_tc, this->checker); 3975595Sgblack@eecs.umich.edu } 3985595Sgblack@eecs.umich.edu#endif 3995595Sgblack@eecs.umich.edu 4005595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 4015595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 4025595Sgblack@eecs.umich.edu o3_tc->thread = this->thread[i]; 4035595Sgblack@eecs.umich.edu 4045595Sgblack@eecs.umich.edu#if FULL_SYSTEM 4055595Sgblack@eecs.umich.edu // Setup quiesce event. 4065595Sgblack@eecs.umich.edu this->thread[i]->quiesceEvent = new EndQuiesceEvent(tc); 4075595Sgblack@eecs.umich.edu#endif 4085595Sgblack@eecs.umich.edu // Give the thread the TC. 4095595Sgblack@eecs.umich.edu this->thread[i]->tc = tc; 4105595Sgblack@eecs.umich.edu 4115595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4125595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4135595Sgblack@eecs.umich.edu } 4145595Sgblack@eecs.umich.edu 4155595Sgblack@eecs.umich.edu for (int i=0; i < this->numThreads; i++) { 4165595Sgblack@eecs.umich.edu this->thread[i]->setFuncExeInst(0); 4175595Sgblack@eecs.umich.edu } 4185595Sgblack@eecs.umich.edu 4195595Sgblack@eecs.umich.edu lockAddr = 0; 4205595Sgblack@eecs.umich.edu lockFlag = false; 4211060SN/A} 4221060SN/A 4235595Sgblack@eecs.umich.edu#if !FULL_SYSTEM 4245595Sgblack@eecs.umich.edu 4255595Sgblack@eecs.umich.edutemplate <class Impl> 4265595Sgblack@eecs.umich.eduTheISA::IntReg 4275595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getSyscallArg(int i, int tid) 4285595Sgblack@eecs.umich.edu{ 4295595Sgblack@eecs.umich.edu assert(i < TheISA::NumArgumentRegs); 4305595Sgblack@eecs.umich.edu TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), 4315595Sgblack@eecs.umich.edu TheISA::ArgumentReg[i]); 4325595Sgblack@eecs.umich.edu TheISA::IntReg val = this->readArchIntReg(idx, tid); 4335595Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 4345595Sgblack@eecs.umich.edu if (bits(this->readMiscRegNoEffect(SparcISA::MISCREG_PSTATE, tid), 3, 3)) 4355595Sgblack@eecs.umich.edu val = bits(val, 31, 0); 4365595Sgblack@eecs.umich.edu#endif 4375595Sgblack@eecs.umich.edu return val; 4385595Sgblack@eecs.umich.edu} 4395595Sgblack@eecs.umich.edu 4405595Sgblack@eecs.umich.edutemplate <class Impl> 4415595Sgblack@eecs.umich.eduvoid 4425595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid) 4435595Sgblack@eecs.umich.edu{ 4445595Sgblack@eecs.umich.edu assert(i < TheISA::NumArgumentRegs); 4455595Sgblack@eecs.umich.edu TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), 4465595Sgblack@eecs.umich.edu TheISA::ArgumentReg[i]); 4475595Sgblack@eecs.umich.edu this->setArchIntReg(idx, val, tid); 4485595Sgblack@eecs.umich.edu} 4495595Sgblack@eecs.umich.edu#endif 4505595Sgblack@eecs.umich.edu 4511060SN/Atemplate <class Impl> 4521755SN/AFullO3CPU<Impl>::~FullO3CPU() 4531060SN/A{ 4541060SN/A} 4551060SN/A 4561060SN/Atemplate <class Impl> 4571060SN/Avoid 4585595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4591062SN/A{ 4602733Sktlim@umich.edu BaseO3CPU::regStats(); 4612292SN/A 4622733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4632292SN/A timesIdled 4642292SN/A .name(name() + ".timesIdled") 4652292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4662292SN/A " unscheduled itself") 4672292SN/A .prereq(timesIdled); 4682292SN/A 4692292SN/A idleCycles 4702292SN/A .name(name() + ".idleCycles") 4712292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4722292SN/A "to idling") 4732292SN/A .prereq(idleCycles); 4742292SN/A 4752292SN/A // Number of Instructions simulated 4762292SN/A // -------------------------------- 4772292SN/A // Should probably be in Base CPU but need templated 4782292SN/A // MaxThreads so put in here instead 4792292SN/A committedInsts 4802292SN/A .init(numThreads) 4812292SN/A .name(name() + ".committedInsts") 4822292SN/A .desc("Number of Instructions Simulated"); 4832292SN/A 4842292SN/A totalCommittedInsts 4852292SN/A .name(name() + ".committedInsts_total") 4862292SN/A .desc("Number of Instructions Simulated"); 4872292SN/A 4882292SN/A cpi 4892292SN/A .name(name() + ".cpi") 4902292SN/A .desc("CPI: Cycles Per Instruction") 4912292SN/A .precision(6); 4924392Sktlim@umich.edu cpi = numCycles / committedInsts; 4932292SN/A 4942292SN/A totalCpi 4952292SN/A .name(name() + ".cpi_total") 4962292SN/A .desc("CPI: Total CPI of All Threads") 4972292SN/A .precision(6); 4984392Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 4992292SN/A 5002292SN/A ipc 5012292SN/A .name(name() + ".ipc") 5022292SN/A .desc("IPC: Instructions Per Cycle") 5032292SN/A .precision(6); 5044392Sktlim@umich.edu ipc = committedInsts / numCycles; 5052292SN/A 5062292SN/A totalIpc 5072292SN/A .name(name() + ".ipc_total") 5082292SN/A .desc("IPC: Total IPC of All Threads") 5092292SN/A .precision(6); 5104392Sktlim@umich.edu totalIpc = totalCommittedInsts / numCycles; 5112292SN/A 5125595Sgblack@eecs.umich.edu this->fetch.regStats(); 5135595Sgblack@eecs.umich.edu this->decode.regStats(); 5145595Sgblack@eecs.umich.edu this->rename.regStats(); 5155595Sgblack@eecs.umich.edu this->iew.regStats(); 5165595Sgblack@eecs.umich.edu this->commit.regStats(); 5171062SN/A} 5181062SN/A 5191062SN/Atemplate <class Impl> 5202871Sktlim@umich.eduPort * 5212871Sktlim@umich.eduFullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 5222871Sktlim@umich.edu{ 5232871Sktlim@umich.edu if (if_name == "dcache_port") 5242871Sktlim@umich.edu return iew.getDcachePort(); 5252871Sktlim@umich.edu else if (if_name == "icache_port") 5262871Sktlim@umich.edu return fetch.getIcachePort(); 5272871Sktlim@umich.edu else 5282871Sktlim@umich.edu panic("No Such Port\n"); 5292871Sktlim@umich.edu} 5302871Sktlim@umich.edu 5312871Sktlim@umich.edutemplate <class Impl> 5321062SN/Avoid 5331755SN/AFullO3CPU<Impl>::tick() 5341060SN/A{ 5352733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5361060SN/A 5372292SN/A ++numCycles; 5382292SN/A 5392325SN/A// activity = false; 5402292SN/A 5412292SN/A //Tick each of the stages 5421060SN/A fetch.tick(); 5431060SN/A 5441060SN/A decode.tick(); 5451060SN/A 5461060SN/A rename.tick(); 5471060SN/A 5481060SN/A iew.tick(); 5491060SN/A 5501060SN/A commit.tick(); 5511060SN/A 5522292SN/A#if !FULL_SYSTEM 5532292SN/A doContextSwitch(); 5542292SN/A#endif 5552292SN/A 5562292SN/A // Now advance the time buffers 5571060SN/A timeBuffer.advance(); 5581060SN/A 5591060SN/A fetchQueue.advance(); 5601060SN/A decodeQueue.advance(); 5611060SN/A renameQueue.advance(); 5621060SN/A iewQueue.advance(); 5631060SN/A 5642325SN/A activityRec.advance(); 5652292SN/A 5662292SN/A if (removeInstsThisCycle) { 5672292SN/A cleanUpRemovedInsts(); 5682292SN/A } 5692292SN/A 5702325SN/A if (!tickEvent.scheduled()) { 5712867Sktlim@umich.edu if (_status == SwitchedOut || 5722905Sktlim@umich.edu getState() == SimObject::Drained) { 5733226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 5742325SN/A // increment stat 5752325SN/A lastRunningCycle = curTick; 5763221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 5773226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 5782325SN/A lastRunningCycle = curTick; 5792325SN/A timesIdled++; 5802325SN/A } else { 5815606Snate@binkert.org schedule(tickEvent, nextCycle(curTick + ticks(1))); 5823226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 5832325SN/A } 5842292SN/A } 5852292SN/A 5862292SN/A#if !FULL_SYSTEM 5872292SN/A updateThreadPriority(); 5882292SN/A#endif 5891060SN/A} 5901060SN/A 5911060SN/Atemplate <class Impl> 5921060SN/Avoid 5931755SN/AFullO3CPU<Impl>::init() 5941060SN/A{ 5955714Shsul@eecs.umich.edu BaseCPU::init(); 5961060SN/A 5972292SN/A // Set inSyscall so that the CPU doesn't squash when initially 5982292SN/A // setting up registers. 5992292SN/A for (int i = 0; i < number_of_threads; ++i) 6002292SN/A thread[i]->inSyscall = true; 6012292SN/A 6022292SN/A for (int tid=0; tid < number_of_threads; tid++) { 6031858SN/A#if FULL_SYSTEM 6042680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 6051681SN/A#else 6062680Sktlim@umich.edu ThreadContext *src_tc = thread[tid]->getTC(); 6071681SN/A#endif 6082292SN/A // Threads start in the Suspended State 6092680Sktlim@umich.edu if (src_tc->status() != ThreadContext::Suspended) { 6102292SN/A continue; 6111060SN/A } 6121060SN/A 6132292SN/A#if FULL_SYSTEM 6145714Shsul@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 6152292SN/A#endif 6162292SN/A } 6172292SN/A 6182292SN/A // Clear inSyscall. 6192292SN/A for (int i = 0; i < number_of_threads; ++i) 6202292SN/A thread[i]->inSyscall = false; 6212292SN/A 6222316SN/A // Initialize stages. 6232292SN/A fetch.initStage(); 6242292SN/A iew.initStage(); 6252292SN/A rename.initStage(); 6262292SN/A commit.initStage(); 6272292SN/A 6282292SN/A commit.setThreads(thread); 6292292SN/A} 6302292SN/A 6312292SN/Atemplate <class Impl> 6322292SN/Avoid 6332875Sksewell@umich.eduFullO3CPU<Impl>::activateThread(unsigned tid) 6342875Sksewell@umich.edu{ 6355314Sstever@gmail.com std::list<unsigned>::iterator isActive = 6365314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6372875Sksewell@umich.edu 6383226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6393226Sktlim@umich.edu 6402875Sksewell@umich.edu if (isActive == activeThreads.end()) { 6412875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6422875Sksewell@umich.edu tid); 6432875Sksewell@umich.edu 6442875Sksewell@umich.edu activeThreads.push_back(tid); 6452875Sksewell@umich.edu } 6462875Sksewell@umich.edu} 6472875Sksewell@umich.edu 6482875Sksewell@umich.edutemplate <class Impl> 6492875Sksewell@umich.eduvoid 6502875Sksewell@umich.eduFullO3CPU<Impl>::deactivateThread(unsigned tid) 6512875Sksewell@umich.edu{ 6522875Sksewell@umich.edu //Remove From Active List, if Active 6535314Sstever@gmail.com std::list<unsigned>::iterator thread_it = 6545314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6552875Sksewell@umich.edu 6563226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 6573226Sktlim@umich.edu 6582875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 6592875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6602875Sksewell@umich.edu tid); 6612875Sksewell@umich.edu activeThreads.erase(thread_it); 6622875Sksewell@umich.edu } 6632875Sksewell@umich.edu} 6642875Sksewell@umich.edu 6652875Sksewell@umich.edutemplate <class Impl> 6662875Sksewell@umich.eduvoid 6672875Sksewell@umich.eduFullO3CPU<Impl>::activateContext(int tid, int delay) 6682875Sksewell@umich.edu{ 6692875Sksewell@umich.edu // Needs to set each stage to running as well. 6702875Sksewell@umich.edu if (delay){ 6712875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 6725100Ssaidi@eecs.umich.edu "on cycle %d\n", tid, curTick + ticks(delay)); 6732875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 6742875Sksewell@umich.edu } else { 6752875Sksewell@umich.edu activateThread(tid); 6762875Sksewell@umich.edu } 6772875Sksewell@umich.edu 6783221Sktlim@umich.edu if (lastActivatedCycle < curTick) { 6792875Sksewell@umich.edu scheduleTickEvent(delay); 6802875Sksewell@umich.edu 6812875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 6822875Sksewell@umich.edu // deschedule itself. 6832875Sksewell@umich.edu activityRec.activity(); 6842875Sksewell@umich.edu fetch.wakeFromQuiesce(); 6852875Sksewell@umich.edu 6862875Sksewell@umich.edu lastActivatedCycle = curTick; 6872875Sksewell@umich.edu 6882875Sksewell@umich.edu _status = Running; 6892875Sksewell@umich.edu } 6902875Sksewell@umich.edu} 6912875Sksewell@umich.edu 6922875Sksewell@umich.edutemplate <class Impl> 6933221Sktlim@umich.edubool 6943221Sktlim@umich.eduFullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay) 6952875Sksewell@umich.edu{ 6962875Sksewell@umich.edu // Schedule removal of thread data from CPU 6972875Sksewell@umich.edu if (delay){ 6982875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 6995100Ssaidi@eecs.umich.edu "on cycle %d\n", tid, curTick + ticks(delay)); 7003221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 7013221Sktlim@umich.edu return false; 7022875Sksewell@umich.edu } else { 7032875Sksewell@umich.edu deactivateThread(tid); 7043221Sktlim@umich.edu if (remove) 7053221Sktlim@umich.edu removeThread(tid); 7063221Sktlim@umich.edu return true; 7072875Sksewell@umich.edu } 7082875Sksewell@umich.edu} 7092875Sksewell@umich.edu 7102875Sksewell@umich.edutemplate <class Impl> 7112875Sksewell@umich.eduvoid 7122875Sksewell@umich.eduFullO3CPU<Impl>::suspendContext(int tid) 7132875Sksewell@umich.edu{ 7142875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 7153221Sktlim@umich.edu bool deallocated = deallocateContext(tid, false, 1); 7163221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 7175570Snate@binkert.org if ((activeThreads.size() == 1 && !deallocated) || 7183859Sbinkertn@umich.edu activeThreads.size() == 0) 7192910Sksewell@umich.edu unscheduleTickEvent(); 7202875Sksewell@umich.edu _status = Idle; 7212875Sksewell@umich.edu} 7222875Sksewell@umich.edu 7232875Sksewell@umich.edutemplate <class Impl> 7242875Sksewell@umich.eduvoid 7252875Sksewell@umich.eduFullO3CPU<Impl>::haltContext(int tid) 7262875Sksewell@umich.edu{ 7272910Sksewell@umich.edu //For now, this is the same as deallocate 7282910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 7293221Sktlim@umich.edu deallocateContext(tid, true, 1); 7302875Sksewell@umich.edu} 7312875Sksewell@umich.edu 7322875Sksewell@umich.edutemplate <class Impl> 7332875Sksewell@umich.eduvoid 7342292SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 7352292SN/A{ 7362847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 7372292SN/A // Will change now that the PC and thread state is internal to the CPU 7382683Sktlim@umich.edu // and not in the ThreadContext. 7392292SN/A#if FULL_SYSTEM 7402680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 7412292SN/A#else 7422847Sksewell@umich.edu ThreadContext *src_tc = tcBase(tid); 7432292SN/A#endif 7442292SN/A 7452292SN/A //Bind Int Regs to Rename Map 7462292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7472292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 7482292SN/A 7492292SN/A renameMap[tid].setEntry(ireg,phys_reg); 7502292SN/A scoreboard.setReg(phys_reg); 7512292SN/A } 7522292SN/A 7532292SN/A //Bind Float Regs to Rename Map 7542292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 7552292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 7562292SN/A 7572292SN/A renameMap[tid].setEntry(freg,phys_reg); 7582292SN/A scoreboard.setReg(phys_reg); 7592292SN/A } 7602292SN/A 7612292SN/A //Copy Thread Data Into RegFile 7622847Sksewell@umich.edu //this->copyFromTC(tid); 7632292SN/A 7642847Sksewell@umich.edu //Set PC/NPC/NNPC 7652847Sksewell@umich.edu setPC(src_tc->readPC(), tid); 7662847Sksewell@umich.edu setNextPC(src_tc->readNextPC(), tid); 7672847Sksewell@umich.edu setNextNPC(src_tc->readNextNPC(), tid); 7682292SN/A 7692680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 7702292SN/A 7712292SN/A activateContext(tid,1); 7722292SN/A 7732292SN/A //Reset ROB/IQ/LSQ Entries 7742292SN/A commit.rob->resetEntries(); 7752292SN/A iew.resetEntries(); 7762292SN/A} 7772292SN/A 7782292SN/Atemplate <class Impl> 7792292SN/Avoid 7802292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 7812292SN/A{ 7822877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 7832847Sksewell@umich.edu 7842847Sksewell@umich.edu // Copy Thread Data From RegFile 7852847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 7865364Sksewell@umich.edu // this->copyToTC(tid); 7875364Sksewell@umich.edu 7885364Sksewell@umich.edu 7895364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 7905364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 7915364Sksewell@umich.edu // in SMT workloads. 7922847Sksewell@umich.edu 7932847Sksewell@umich.edu // Unbind Int Regs from Rename Map 7942292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7952292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 7962292SN/A 7972292SN/A scoreboard.unsetReg(phys_reg); 7982292SN/A freeList.addReg(phys_reg); 7992292SN/A } 8002292SN/A 8012847Sksewell@umich.edu // Unbind Float Regs from Rename Map 8025362Sksewell@umich.edu for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 8032292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 8042292SN/A 8052292SN/A scoreboard.unsetReg(phys_reg); 8062292SN/A freeList.addReg(phys_reg); 8072292SN/A } 8082292SN/A 8092847Sksewell@umich.edu // Squash Throughout Pipeline 8102935Sksewell@umich.edu InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; 8114636Sgblack@eecs.umich.edu fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid); 8122292SN/A decode.squash(tid); 8132935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 8142875Sksewell@umich.edu iew.squash(tid); 8155363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 8162935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 8172292SN/A 8185362Sksewell@umich.edu 8195362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 8202292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 8212292SN/A 8222847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 8233229Sktlim@umich.edu 8243229Sktlim@umich.edu // Commented out for now. This should be possible to do by 8253229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 8263229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 8273229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 8283229Sktlim@umich.edu/* 8292292SN/A if (activeThreads.size() >= 1) { 8302292SN/A commit.rob->resetEntries(); 8312292SN/A iew.resetEntries(); 8322292SN/A } 8333229Sktlim@umich.edu*/ 8342292SN/A} 8352292SN/A 8362292SN/A 8372292SN/Atemplate <class Impl> 8382292SN/Avoid 8392292SN/AFullO3CPU<Impl>::activateWhenReady(int tid) 8402292SN/A{ 8412733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 8422292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 8432292SN/A tid); 8442292SN/A 8452292SN/A bool ready = true; 8462292SN/A 8472292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 8482733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8492292SN/A "Phys. Int. Regs.\n", 8502292SN/A tid); 8512292SN/A ready = false; 8522292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 8532733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8542292SN/A "Phys. Float. Regs.\n", 8552292SN/A tid); 8562292SN/A ready = false; 8572292SN/A } else if (commit.rob->numFreeEntries() >= 8582292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 8592733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8602292SN/A "ROB entries.\n", 8612292SN/A tid); 8622292SN/A ready = false; 8632292SN/A } else if (iew.instQueue.numFreeEntries() >= 8642292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 8652733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8662292SN/A "IQ entries.\n", 8672292SN/A tid); 8682292SN/A ready = false; 8692292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 8702292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 8712733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8722292SN/A "LSQ entries.\n", 8732292SN/A tid); 8742292SN/A ready = false; 8752292SN/A } 8762292SN/A 8772292SN/A if (ready) { 8782292SN/A insertThread(tid); 8792292SN/A 8802292SN/A contextSwitch = false; 8812292SN/A 8822292SN/A cpuWaitList.remove(tid); 8832292SN/A } else { 8842292SN/A suspendContext(tid); 8852292SN/A 8862292SN/A //blocks fetch 8872292SN/A contextSwitch = true; 8882292SN/A 8892875Sksewell@umich.edu //@todo: dont always add to waitlist 8902292SN/A //do waitlist 8912292SN/A cpuWaitList.push_back(tid); 8921060SN/A } 8931060SN/A} 8941060SN/A 8954192Sktlim@umich.edu#if FULL_SYSTEM 8964192Sktlim@umich.edutemplate <class Impl> 8974192Sktlim@umich.eduvoid 8985704Snate@binkert.orgFullO3CPU<Impl>::postInterrupt(int int_num, int index) 8995595Sgblack@eecs.umich.edu{ 9005704Snate@binkert.org BaseCPU::postInterrupt(int_num, index); 9015595Sgblack@eecs.umich.edu 9025595Sgblack@eecs.umich.edu if (this->thread[0]->status() == ThreadContext::Suspended) { 9035595Sgblack@eecs.umich.edu DPRINTF(IPI,"Suspended Processor awoke\n"); 9045595Sgblack@eecs.umich.edu this->threadContexts[0]->activate(); 9055595Sgblack@eecs.umich.edu } 9065595Sgblack@eecs.umich.edu} 9075595Sgblack@eecs.umich.edu 9085595Sgblack@eecs.umich.edutemplate <class Impl> 9095595Sgblack@eecs.umich.eduFault 9105702Ssaidi@eecs.umich.eduFullO3CPU<Impl>::hwrei(unsigned tid) 9115702Ssaidi@eecs.umich.edu{ 9125702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9135702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 9145702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 9155702Ssaidi@eecs.umich.edu 9165702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 9175702Ssaidi@eecs.umich.edu 9185702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 9195702Ssaidi@eecs.umich.edu#endif 9205702Ssaidi@eecs.umich.edu return NoFault; 9215702Ssaidi@eecs.umich.edu} 9225702Ssaidi@eecs.umich.edu 9235702Ssaidi@eecs.umich.edutemplate <class Impl> 9245702Ssaidi@eecs.umich.edubool 9255702Ssaidi@eecs.umich.eduFullO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid) 9265702Ssaidi@eecs.umich.edu{ 9275702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9285702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 9295702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 9305702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 9315702Ssaidi@eecs.umich.edu 9325702Ssaidi@eecs.umich.edu switch (palFunc) { 9335702Ssaidi@eecs.umich.edu case PAL::halt: 9345702Ssaidi@eecs.umich.edu halt(); 9355702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 9365702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 9375702Ssaidi@eecs.umich.edu break; 9385702Ssaidi@eecs.umich.edu 9395702Ssaidi@eecs.umich.edu case PAL::bpt: 9405702Ssaidi@eecs.umich.edu case PAL::bugchk: 9415702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 9425702Ssaidi@eecs.umich.edu return false; 9435702Ssaidi@eecs.umich.edu break; 9445702Ssaidi@eecs.umich.edu } 9455702Ssaidi@eecs.umich.edu#endif 9465702Ssaidi@eecs.umich.edu return true; 9475702Ssaidi@eecs.umich.edu} 9485702Ssaidi@eecs.umich.edu 9495702Ssaidi@eecs.umich.edutemplate <class Impl> 9505702Ssaidi@eecs.umich.eduFault 9515595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 9525595Sgblack@eecs.umich.edu{ 9535595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 9545647Sgblack@eecs.umich.edu return this->interrupts->getInterrupt(this->threadContexts[0]); 9555595Sgblack@eecs.umich.edu} 9565595Sgblack@eecs.umich.edu 9575595Sgblack@eecs.umich.edutemplate <class Impl> 9585595Sgblack@eecs.umich.eduvoid 9595595Sgblack@eecs.umich.eduFullO3CPU<Impl>::processInterrupts(Fault interrupt) 9605595Sgblack@eecs.umich.edu{ 9615595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 9625595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 9635595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 9645595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 9655595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 9665595Sgblack@eecs.umich.edu 9675595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 9685647Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 9695595Sgblack@eecs.umich.edu 9705595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 9715595Sgblack@eecs.umich.edu this->trap(interrupt, 0); 9725595Sgblack@eecs.umich.edu} 9735595Sgblack@eecs.umich.edu 9745595Sgblack@eecs.umich.edutemplate <class Impl> 9755595Sgblack@eecs.umich.eduvoid 9764192Sktlim@umich.eduFullO3CPU<Impl>::updateMemPorts() 9774192Sktlim@umich.edu{ 9784192Sktlim@umich.edu // Update all ThreadContext's memory ports (Functional/Virtual 9794192Sktlim@umich.edu // Ports) 9804192Sktlim@umich.edu for (int i = 0; i < thread.size(); ++i) 9815497Ssaidi@eecs.umich.edu thread[i]->connectMemPorts(thread[i]->getTC()); 9824192Sktlim@umich.edu} 9834192Sktlim@umich.edu#endif 9844192Sktlim@umich.edu 9851060SN/Atemplate <class Impl> 9862852Sktlim@umich.eduvoid 9875595Sgblack@eecs.umich.eduFullO3CPU<Impl>::trap(Fault fault, unsigned tid) 9885595Sgblack@eecs.umich.edu{ 9895595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 9905595Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid]); 9915595Sgblack@eecs.umich.edu} 9925595Sgblack@eecs.umich.edu 9935595Sgblack@eecs.umich.edu#if !FULL_SYSTEM 9945595Sgblack@eecs.umich.edu 9955595Sgblack@eecs.umich.edutemplate <class Impl> 9965595Sgblack@eecs.umich.eduvoid 9975595Sgblack@eecs.umich.eduFullO3CPU<Impl>::syscall(int64_t callnum, int tid) 9985595Sgblack@eecs.umich.edu{ 9995595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 10005595Sgblack@eecs.umich.edu 10015595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 10025595Sgblack@eecs.umich.edu 10035595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 10045595Sgblack@eecs.umich.edu // instruction. 10055595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 10065595Sgblack@eecs.umich.edu 10075595Sgblack@eecs.umich.edu // Execute the actual syscall. 10085595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 10095595Sgblack@eecs.umich.edu 10105595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 10115595Sgblack@eecs.umich.edu // incrementing it. 10125595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 10135595Sgblack@eecs.umich.edu} 10145595Sgblack@eecs.umich.edu 10155595Sgblack@eecs.umich.edutemplate <class Impl> 10165595Sgblack@eecs.umich.eduvoid 10175595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid) 10185595Sgblack@eecs.umich.edu{ 10195595Sgblack@eecs.umich.edu TheISA::setSyscallReturn(return_value, this->tcBase(tid)); 10205595Sgblack@eecs.umich.edu} 10215595Sgblack@eecs.umich.edu 10225595Sgblack@eecs.umich.edu#endif 10235595Sgblack@eecs.umich.edu 10245595Sgblack@eecs.umich.edutemplate <class Impl> 10255595Sgblack@eecs.umich.eduvoid 10262864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 10272864Sktlim@umich.edu{ 10282918Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 10292918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 10302864Sktlim@umich.edu BaseCPU::serialize(os); 10312864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 10322864Sktlim@umich.edu tickEvent.serialize(os); 10332864Sktlim@umich.edu 10342864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10352864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 10362864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 10372864Sktlim@umich.edu static SimpleThread temp; 10382864Sktlim@umich.edu 10392864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 10402864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 10412864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10422864Sktlim@umich.edu temp.serialize(os); 10432864Sktlim@umich.edu } 10442864Sktlim@umich.edu} 10452864Sktlim@umich.edu 10462864Sktlim@umich.edutemplate <class Impl> 10472864Sktlim@umich.eduvoid 10482864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 10492864Sktlim@umich.edu{ 10502918Sktlim@umich.edu SimObject::State so_state; 10512918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 10522864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 10532864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 10542864Sktlim@umich.edu 10552864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10562864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 10572864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 10582864Sktlim@umich.edu static SimpleThread temp; 10592864Sktlim@umich.edu 10602864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 10612864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10622864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 10632864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 10642864Sktlim@umich.edu } 10652864Sktlim@umich.edu} 10662864Sktlim@umich.edu 10672864Sktlim@umich.edutemplate <class Impl> 10682905Sktlim@umich.eduunsigned int 10692843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 10701060SN/A{ 10713125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 10723512Sktlim@umich.edu 10733512Sktlim@umich.edu // If the CPU isn't doing anything, then return immediately. 10743512Sktlim@umich.edu if (_status == Idle || _status == SwitchedOut) { 10753512Sktlim@umich.edu return 0; 10763512Sktlim@umich.edu } 10773512Sktlim@umich.edu 10782843Sktlim@umich.edu drainCount = 0; 10792843Sktlim@umich.edu fetch.drain(); 10802843Sktlim@umich.edu decode.drain(); 10812843Sktlim@umich.edu rename.drain(); 10822843Sktlim@umich.edu iew.drain(); 10832843Sktlim@umich.edu commit.drain(); 10842325SN/A 10852325SN/A // Wake the CPU and record activity so everything can drain out if 10862863Sktlim@umich.edu // the CPU was not able to immediately drain. 10872905Sktlim@umich.edu if (getState() != SimObject::Drained) { 10882864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 10892864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 10902864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 10912864Sktlim@umich.edu // process on the drain event. 10922864Sktlim@umich.edu drainEvent = drain_event; 10932843Sktlim@umich.edu 10942863Sktlim@umich.edu wakeCPU(); 10952863Sktlim@umich.edu activityRec.activity(); 10962852Sktlim@umich.edu 10972905Sktlim@umich.edu return 1; 10982863Sktlim@umich.edu } else { 10992905Sktlim@umich.edu return 0; 11002863Sktlim@umich.edu } 11012316SN/A} 11022310SN/A 11032316SN/Atemplate <class Impl> 11042316SN/Avoid 11052843Sktlim@umich.eduFullO3CPU<Impl>::resume() 11062316SN/A{ 11072843Sktlim@umich.edu fetch.resume(); 11082843Sktlim@umich.edu decode.resume(); 11092843Sktlim@umich.edu rename.resume(); 11102843Sktlim@umich.edu iew.resume(); 11112843Sktlim@umich.edu commit.resume(); 11122316SN/A 11132905Sktlim@umich.edu changeState(SimObject::Running); 11142905Sktlim@umich.edu 11152864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 11162864Sktlim@umich.edu return; 11172864Sktlim@umich.edu 11183319Shsul@eecs.umich.edu#if FULL_SYSTEM 11194762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 11203319Shsul@eecs.umich.edu#endif 11213319Shsul@eecs.umich.edu 11222843Sktlim@umich.edu if (!tickEvent.scheduled()) 11235606Snate@binkert.org schedule(tickEvent, nextCycle()); 11242843Sktlim@umich.edu _status = Running; 11252843Sktlim@umich.edu} 11262316SN/A 11272843Sktlim@umich.edutemplate <class Impl> 11282843Sktlim@umich.eduvoid 11292843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 11302843Sktlim@umich.edu{ 11312843Sktlim@umich.edu if (++drainCount == NumStages) { 11322316SN/A if (tickEvent.scheduled()) 11332316SN/A tickEvent.squash(); 11342863Sktlim@umich.edu 11352905Sktlim@umich.edu changeState(SimObject::Drained); 11362863Sktlim@umich.edu 11373126Sktlim@umich.edu BaseCPU::switchOut(); 11383126Sktlim@umich.edu 11392863Sktlim@umich.edu if (drainEvent) { 11402863Sktlim@umich.edu drainEvent->process(); 11412863Sktlim@umich.edu drainEvent = NULL; 11422863Sktlim@umich.edu } 11432310SN/A } 11442843Sktlim@umich.edu assert(drainCount <= 5); 11452843Sktlim@umich.edu} 11462843Sktlim@umich.edu 11472843Sktlim@umich.edutemplate <class Impl> 11482843Sktlim@umich.eduvoid 11492843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 11502843Sktlim@umich.edu{ 11512843Sktlim@umich.edu fetch.switchOut(); 11522843Sktlim@umich.edu rename.switchOut(); 11532325SN/A iew.switchOut(); 11542843Sktlim@umich.edu commit.switchOut(); 11552843Sktlim@umich.edu instList.clear(); 11562843Sktlim@umich.edu while (!removeList.empty()) { 11572843Sktlim@umich.edu removeList.pop(); 11582843Sktlim@umich.edu } 11592843Sktlim@umich.edu 11602843Sktlim@umich.edu _status = SwitchedOut; 11612843Sktlim@umich.edu#if USE_CHECKER 11622843Sktlim@umich.edu if (checker) 11632843Sktlim@umich.edu checker->switchOut(); 11642843Sktlim@umich.edu#endif 11653126Sktlim@umich.edu if (tickEvent.scheduled()) 11663126Sktlim@umich.edu tickEvent.squash(); 11671060SN/A} 11681060SN/A 11691060SN/Atemplate <class Impl> 11701060SN/Avoid 11711755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 11721060SN/A{ 11732325SN/A // Flush out any old data from the time buffers. 11742873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 11752307SN/A timeBuffer.advance(); 11762307SN/A fetchQueue.advance(); 11772307SN/A decodeQueue.advance(); 11782307SN/A renameQueue.advance(); 11792307SN/A iewQueue.advance(); 11802307SN/A } 11812307SN/A 11822325SN/A activityRec.reset(); 11832307SN/A 11844192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort()); 11851060SN/A 11862307SN/A fetch.takeOverFrom(); 11872307SN/A decode.takeOverFrom(); 11882307SN/A rename.takeOverFrom(); 11892307SN/A iew.takeOverFrom(); 11902307SN/A commit.takeOverFrom(); 11912307SN/A 11921060SN/A assert(!tickEvent.scheduled()); 11931060SN/A 11942325SN/A // @todo: Figure out how to properly select the tid to put onto 11952325SN/A // the active threads list. 11962307SN/A int tid = 0; 11972307SN/A 11985314Sstever@gmail.com std::list<unsigned>::iterator isActive = 11995314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 12002307SN/A 12012307SN/A if (isActive == activeThreads.end()) { 12022325SN/A //May Need to Re-code this if the delay variable is the delay 12032325SN/A //needed for thread to activate 12042733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 12052307SN/A tid); 12062307SN/A 12072307SN/A activeThreads.push_back(tid); 12082307SN/A } 12092307SN/A 12102325SN/A // Set all statuses to active, schedule the CPU's tick event. 12112307SN/A // @todo: Fix up statuses so this is handled properly 12122680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 12132680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 12142680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 12151681SN/A _status = Running; 12165606Snate@binkert.org schedule(tickEvent, nextCycle()); 12171681SN/A } 12181060SN/A } 12192307SN/A if (!tickEvent.scheduled()) 12205606Snate@binkert.org schedule(tickEvent, nextCycle()); 12211060SN/A} 12221060SN/A 12231060SN/Atemplate <class Impl> 12245595Sgblack@eecs.umich.eduTheISA::MiscReg 12255595Sgblack@eecs.umich.eduFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid) 12265595Sgblack@eecs.umich.edu{ 12275595Sgblack@eecs.umich.edu return this->regFile.readMiscRegNoEffect(misc_reg, tid); 12285595Sgblack@eecs.umich.edu} 12295595Sgblack@eecs.umich.edu 12305595Sgblack@eecs.umich.edutemplate <class Impl> 12315595Sgblack@eecs.umich.eduTheISA::MiscReg 12325595Sgblack@eecs.umich.eduFullO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) 12335595Sgblack@eecs.umich.edu{ 12345595Sgblack@eecs.umich.edu return this->regFile.readMiscReg(misc_reg, tid); 12355595Sgblack@eecs.umich.edu} 12365595Sgblack@eecs.umich.edu 12375595Sgblack@eecs.umich.edutemplate <class Impl> 12385595Sgblack@eecs.umich.eduvoid 12395595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 12405595Sgblack@eecs.umich.edu const TheISA::MiscReg &val, unsigned tid) 12415595Sgblack@eecs.umich.edu{ 12425595Sgblack@eecs.umich.edu this->regFile.setMiscRegNoEffect(misc_reg, val, tid); 12435595Sgblack@eecs.umich.edu} 12445595Sgblack@eecs.umich.edu 12455595Sgblack@eecs.umich.edutemplate <class Impl> 12465595Sgblack@eecs.umich.eduvoid 12475595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 12485595Sgblack@eecs.umich.edu const TheISA::MiscReg &val, unsigned tid) 12495595Sgblack@eecs.umich.edu{ 12505595Sgblack@eecs.umich.edu this->regFile.setMiscReg(misc_reg, val, tid); 12515595Sgblack@eecs.umich.edu} 12525595Sgblack@eecs.umich.edu 12535595Sgblack@eecs.umich.edutemplate <class Impl> 12541060SN/Auint64_t 12551755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 12561060SN/A{ 12571060SN/A return regFile.readIntReg(reg_idx); 12581060SN/A} 12591060SN/A 12601060SN/Atemplate <class Impl> 12612455SN/AFloatReg 12622455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 12631060SN/A{ 12642455SN/A return regFile.readFloatReg(reg_idx, width); 12651060SN/A} 12661060SN/A 12671060SN/Atemplate <class Impl> 12682455SN/AFloatReg 12692455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 12701060SN/A{ 12712455SN/A return regFile.readFloatReg(reg_idx); 12721060SN/A} 12731060SN/A 12741060SN/Atemplate <class Impl> 12752455SN/AFloatRegBits 12762455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 12771060SN/A{ 12782455SN/A return regFile.readFloatRegBits(reg_idx, width); 12792455SN/A} 12802455SN/A 12812455SN/Atemplate <class Impl> 12822455SN/AFloatRegBits 12832455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 12842455SN/A{ 12852455SN/A return regFile.readFloatRegBits(reg_idx); 12861060SN/A} 12871060SN/A 12881060SN/Atemplate <class Impl> 12891060SN/Avoid 12901755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 12911060SN/A{ 12921060SN/A regFile.setIntReg(reg_idx, val); 12931060SN/A} 12941060SN/A 12951060SN/Atemplate <class Impl> 12961060SN/Avoid 12972455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 12981060SN/A{ 12992455SN/A regFile.setFloatReg(reg_idx, val, width); 13001060SN/A} 13011060SN/A 13021060SN/Atemplate <class Impl> 13031060SN/Avoid 13042455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 13051060SN/A{ 13062455SN/A regFile.setFloatReg(reg_idx, val); 13071060SN/A} 13081060SN/A 13091060SN/Atemplate <class Impl> 13101060SN/Avoid 13112455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 13121060SN/A{ 13132455SN/A regFile.setFloatRegBits(reg_idx, val, width); 13142455SN/A} 13152455SN/A 13162455SN/Atemplate <class Impl> 13172455SN/Avoid 13182455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 13192455SN/A{ 13202455SN/A regFile.setFloatRegBits(reg_idx, val); 13211060SN/A} 13221060SN/A 13231060SN/Atemplate <class Impl> 13241060SN/Auint64_t 13252292SN/AFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 13261060SN/A{ 13272292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13282292SN/A 13292292SN/A return regFile.readIntReg(phys_reg); 13302292SN/A} 13312292SN/A 13322292SN/Atemplate <class Impl> 13332292SN/Afloat 13342292SN/AFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 13352292SN/A{ 13362307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 13372307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13382292SN/A 13392669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 13402292SN/A} 13412292SN/A 13422292SN/Atemplate <class Impl> 13432292SN/Adouble 13442292SN/AFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 13452292SN/A{ 13462307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 13472307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13482292SN/A 13492669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 13502292SN/A} 13512292SN/A 13522292SN/Atemplate <class Impl> 13532292SN/Auint64_t 13542292SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 13552292SN/A{ 13562307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 13572307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13582292SN/A 13592669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 13601060SN/A} 13611060SN/A 13621060SN/Atemplate <class Impl> 13631060SN/Avoid 13642292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 13651060SN/A{ 13662292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13672292SN/A 13682292SN/A regFile.setIntReg(phys_reg, val); 13691060SN/A} 13701060SN/A 13711060SN/Atemplate <class Impl> 13721060SN/Avoid 13732292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 13741060SN/A{ 13752918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 13762918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13772292SN/A 13782669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 13791060SN/A} 13801060SN/A 13811060SN/Atemplate <class Impl> 13821060SN/Avoid 13832292SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 13841060SN/A{ 13852918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 13862918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13872292SN/A 13882669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 13891060SN/A} 13901060SN/A 13911060SN/Atemplate <class Impl> 13921060SN/Avoid 13932292SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 13941060SN/A{ 13952918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 13962918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13971060SN/A 13982669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 13992292SN/A} 14002292SN/A 14012292SN/Atemplate <class Impl> 14022292SN/Auint64_t 14032292SN/AFullO3CPU<Impl>::readPC(unsigned tid) 14042292SN/A{ 14052292SN/A return commit.readPC(tid); 14061060SN/A} 14071060SN/A 14081060SN/Atemplate <class Impl> 14091060SN/Avoid 14102292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 14111060SN/A{ 14122292SN/A commit.setPC(new_PC, tid); 14132292SN/A} 14141060SN/A 14152292SN/Atemplate <class Impl> 14162292SN/Auint64_t 14174636Sgblack@eecs.umich.eduFullO3CPU<Impl>::readMicroPC(unsigned tid) 14184636Sgblack@eecs.umich.edu{ 14194636Sgblack@eecs.umich.edu return commit.readMicroPC(tid); 14204636Sgblack@eecs.umich.edu} 14214636Sgblack@eecs.umich.edu 14224636Sgblack@eecs.umich.edutemplate <class Impl> 14234636Sgblack@eecs.umich.eduvoid 14244636Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMicroPC(Addr new_PC,unsigned tid) 14254636Sgblack@eecs.umich.edu{ 14264636Sgblack@eecs.umich.edu commit.setMicroPC(new_PC, tid); 14274636Sgblack@eecs.umich.edu} 14284636Sgblack@eecs.umich.edu 14294636Sgblack@eecs.umich.edutemplate <class Impl> 14304636Sgblack@eecs.umich.eduuint64_t 14312292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 14322292SN/A{ 14332292SN/A return commit.readNextPC(tid); 14342292SN/A} 14351060SN/A 14362292SN/Atemplate <class Impl> 14372292SN/Avoid 14382292SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 14392292SN/A{ 14402292SN/A commit.setNextPC(val, tid); 14412292SN/A} 14421060SN/A 14432756Sksewell@umich.edutemplate <class Impl> 14442756Sksewell@umich.eduuint64_t 14452756Sksewell@umich.eduFullO3CPU<Impl>::readNextNPC(unsigned tid) 14462756Sksewell@umich.edu{ 14472756Sksewell@umich.edu return commit.readNextNPC(tid); 14482756Sksewell@umich.edu} 14492756Sksewell@umich.edu 14502756Sksewell@umich.edutemplate <class Impl> 14512756Sksewell@umich.eduvoid 14522935Sksewell@umich.eduFullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid) 14532756Sksewell@umich.edu{ 14542756Sksewell@umich.edu commit.setNextNPC(val, tid); 14552756Sksewell@umich.edu} 14562756Sksewell@umich.edu 14572292SN/Atemplate <class Impl> 14584636Sgblack@eecs.umich.eduuint64_t 14594636Sgblack@eecs.umich.eduFullO3CPU<Impl>::readNextMicroPC(unsigned tid) 14604636Sgblack@eecs.umich.edu{ 14614636Sgblack@eecs.umich.edu return commit.readNextMicroPC(tid); 14624636Sgblack@eecs.umich.edu} 14634636Sgblack@eecs.umich.edu 14644636Sgblack@eecs.umich.edutemplate <class Impl> 14654636Sgblack@eecs.umich.eduvoid 14664636Sgblack@eecs.umich.eduFullO3CPU<Impl>::setNextMicroPC(Addr new_PC,unsigned tid) 14674636Sgblack@eecs.umich.edu{ 14684636Sgblack@eecs.umich.edu commit.setNextMicroPC(new_PC, tid); 14694636Sgblack@eecs.umich.edu} 14704636Sgblack@eecs.umich.edu 14714636Sgblack@eecs.umich.edutemplate <class Impl> 14725595Sgblack@eecs.umich.eduvoid 14735595Sgblack@eecs.umich.eduFullO3CPU<Impl>::squashFromTC(unsigned tid) 14745595Sgblack@eecs.umich.edu{ 14755595Sgblack@eecs.umich.edu this->thread[tid]->inSyscall = true; 14765595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 14775595Sgblack@eecs.umich.edu} 14785595Sgblack@eecs.umich.edu 14795595Sgblack@eecs.umich.edutemplate <class Impl> 14802292SN/Atypename FullO3CPU<Impl>::ListIt 14812292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 14822292SN/A{ 14832292SN/A instList.push_back(inst); 14841060SN/A 14852292SN/A return --(instList.end()); 14862292SN/A} 14871060SN/A 14882292SN/Atemplate <class Impl> 14892292SN/Avoid 14902292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 14912292SN/A{ 14922292SN/A // Keep an instruction count. 14932292SN/A thread[tid]->numInst++; 14942292SN/A thread[tid]->numInsts++; 14952292SN/A committedInsts[tid]++; 14962292SN/A totalCommittedInsts++; 14972292SN/A 14982292SN/A // Check for instruction-count-based events. 14992292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 15002292SN/A} 15012292SN/A 15022292SN/Atemplate <class Impl> 15032292SN/Avoid 15042292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 15052292SN/A{ 15062292SN/A removeInstsThisCycle = true; 15072292SN/A 15082292SN/A removeList.push(inst->getInstListIt()); 15091060SN/A} 15101060SN/A 15111060SN/Atemplate <class Impl> 15121060SN/Avoid 15131755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 15141060SN/A{ 15152733Sktlim@umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 15162292SN/A "[sn:%lli]\n", 15172303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 15181060SN/A 15192292SN/A removeInstsThisCycle = true; 15201060SN/A 15211060SN/A // Remove the front instruction. 15222292SN/A removeList.push(inst->getInstListIt()); 15231060SN/A} 15241060SN/A 15251060SN/Atemplate <class Impl> 15261060SN/Avoid 15274632Sgblack@eecs.umich.eduFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 15281060SN/A{ 15292733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 15302292SN/A " list.\n", tid); 15311060SN/A 15322292SN/A ListIt end_it; 15331060SN/A 15342292SN/A bool rob_empty = false; 15352292SN/A 15362292SN/A if (instList.empty()) { 15372292SN/A return; 15382292SN/A } else if (rob.isEmpty(/*tid*/)) { 15392733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 15402292SN/A end_it = instList.begin(); 15412292SN/A rob_empty = true; 15422292SN/A } else { 15432292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 15442733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 15452292SN/A } 15462292SN/A 15472292SN/A removeInstsThisCycle = true; 15482292SN/A 15492292SN/A ListIt inst_it = instList.end(); 15502292SN/A 15512292SN/A inst_it--; 15522292SN/A 15532292SN/A // Walk through the instruction list, removing any instructions 15542292SN/A // that were inserted after the given instruction iterator, end_it. 15552292SN/A while (inst_it != end_it) { 15562292SN/A assert(!instList.empty()); 15572292SN/A 15582292SN/A squashInstIt(inst_it, tid); 15592292SN/A 15602292SN/A inst_it--; 15612292SN/A } 15622292SN/A 15632292SN/A // If the ROB was empty, then we actually need to remove the first 15642292SN/A // instruction as well. 15652292SN/A if (rob_empty) { 15662292SN/A squashInstIt(inst_it, tid); 15672292SN/A } 15681060SN/A} 15691060SN/A 15701060SN/Atemplate <class Impl> 15711060SN/Avoid 15722292SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 15732292SN/A unsigned tid) 15741062SN/A{ 15752292SN/A assert(!instList.empty()); 15762292SN/A 15772292SN/A removeInstsThisCycle = true; 15782292SN/A 15792292SN/A ListIt inst_iter = instList.end(); 15802292SN/A 15812292SN/A inst_iter--; 15822292SN/A 15832733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 15842292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 15852292SN/A tid, seq_num, (*inst_iter)->seqNum); 15861062SN/A 15872292SN/A while ((*inst_iter)->seqNum > seq_num) { 15881062SN/A 15892292SN/A bool break_loop = (inst_iter == instList.begin()); 15901062SN/A 15912292SN/A squashInstIt(inst_iter, tid); 15921062SN/A 15932292SN/A inst_iter--; 15941062SN/A 15952292SN/A if (break_loop) 15962292SN/A break; 15972292SN/A } 15982292SN/A} 15992292SN/A 16002292SN/Atemplate <class Impl> 16012292SN/Ainline void 16022292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 16032292SN/A{ 16042292SN/A if ((*instIt)->threadNumber == tid) { 16052733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 16062292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 16072292SN/A (*instIt)->threadNumber, 16082292SN/A (*instIt)->seqNum, 16092292SN/A (*instIt)->readPC()); 16101062SN/A 16111062SN/A // Mark it as squashed. 16122292SN/A (*instIt)->setSquashed(); 16132292SN/A 16142325SN/A // @todo: Formulate a consistent method for deleting 16152325SN/A // instructions from the instruction list 16162292SN/A // Remove the instruction from the list. 16172292SN/A removeList.push(instIt); 16182292SN/A } 16192292SN/A} 16202292SN/A 16212292SN/Atemplate <class Impl> 16222292SN/Avoid 16232292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 16242292SN/A{ 16252292SN/A while (!removeList.empty()) { 16262733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 16272292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 16282292SN/A (*removeList.front())->threadNumber, 16292292SN/A (*removeList.front())->seqNum, 16302292SN/A (*removeList.front())->readPC()); 16312292SN/A 16322292SN/A instList.erase(removeList.front()); 16332292SN/A 16342292SN/A removeList.pop(); 16351062SN/A } 16361062SN/A 16372292SN/A removeInstsThisCycle = false; 16381062SN/A} 16392325SN/A/* 16401062SN/Atemplate <class Impl> 16411062SN/Avoid 16421755SN/AFullO3CPU<Impl>::removeAllInsts() 16431060SN/A{ 16441060SN/A instList.clear(); 16451060SN/A} 16462325SN/A*/ 16471060SN/Atemplate <class Impl> 16481060SN/Avoid 16491755SN/AFullO3CPU<Impl>::dumpInsts() 16501060SN/A{ 16511060SN/A int num = 0; 16521060SN/A 16532292SN/A ListIt inst_list_it = instList.begin(); 16542292SN/A 16552292SN/A cprintf("Dumping Instruction List\n"); 16562292SN/A 16572292SN/A while (inst_list_it != instList.end()) { 16582292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 16592292SN/A "Squashed:%i\n\n", 16602292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 16612292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 16622292SN/A (*inst_list_it)->isSquashed()); 16631060SN/A inst_list_it++; 16641060SN/A ++num; 16651060SN/A } 16661060SN/A} 16672325SN/A/* 16681060SN/Atemplate <class Impl> 16691060SN/Avoid 16701755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 16711060SN/A{ 16721060SN/A iew.wakeDependents(inst); 16731060SN/A} 16742325SN/A*/ 16752292SN/Atemplate <class Impl> 16762292SN/Avoid 16772292SN/AFullO3CPU<Impl>::wakeCPU() 16782292SN/A{ 16792325SN/A if (activityRec.active() || tickEvent.scheduled()) { 16802325SN/A DPRINTF(Activity, "CPU already running.\n"); 16812292SN/A return; 16822292SN/A } 16832292SN/A 16842325SN/A DPRINTF(Activity, "Waking up CPU\n"); 16852325SN/A 16865099Ssaidi@eecs.umich.edu idleCycles += tickToCycles((curTick - 1) - lastRunningCycle); 16875099Ssaidi@eecs.umich.edu numCycles += tickToCycles((curTick - 1) - lastRunningCycle); 16882292SN/A 16895606Snate@binkert.org schedule(tickEvent, nextCycle()); 16902292SN/A} 16912292SN/A 16922292SN/Atemplate <class Impl> 16932292SN/Aint 16942292SN/AFullO3CPU<Impl>::getFreeTid() 16952292SN/A{ 16962292SN/A for (int i=0; i < numThreads; i++) { 16972292SN/A if (!tids[i]) { 16982292SN/A tids[i] = true; 16992292SN/A return i; 17002292SN/A } 17012292SN/A } 17022292SN/A 17032292SN/A return -1; 17042292SN/A} 17052292SN/A 17062292SN/Atemplate <class Impl> 17072292SN/Avoid 17082292SN/AFullO3CPU<Impl>::doContextSwitch() 17092292SN/A{ 17102292SN/A if (contextSwitch) { 17112292SN/A 17122292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 17132292SN/A 17142292SN/A for (int tid=0; tid < cpuWaitList.size(); tid++) { 17152292SN/A activateWhenReady(tid); 17162292SN/A } 17172292SN/A 17182292SN/A if (cpuWaitList.size() == 0) 17192292SN/A contextSwitch = true; 17202292SN/A } 17212292SN/A} 17222292SN/A 17232292SN/Atemplate <class Impl> 17242292SN/Avoid 17252292SN/AFullO3CPU<Impl>::updateThreadPriority() 17262292SN/A{ 17272292SN/A if (activeThreads.size() > 1) 17282292SN/A { 17292292SN/A //DEFAULT TO ROUND ROBIN SCHEME 17302292SN/A //e.g. Move highest priority to end of thread list 17315314Sstever@gmail.com std::list<unsigned>::iterator list_begin = activeThreads.begin(); 17325314Sstever@gmail.com std::list<unsigned>::iterator list_end = activeThreads.end(); 17332292SN/A 17342292SN/A unsigned high_thread = *list_begin; 17352292SN/A 17362292SN/A activeThreads.erase(list_begin); 17372292SN/A 17382292SN/A activeThreads.push_back(high_thread); 17392292SN/A } 17402292SN/A} 17411060SN/A 17421755SN/A// Forward declaration of FullO3CPU. 17432818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1744