cpu.cc revision 5712
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 341858SN/A 354762Snate@binkert.org#include "cpu/activity.hh" 364762Snate@binkert.org#include "cpu/simple_thread.hh" 374762Snate@binkert.org#include "cpu/thread_context.hh" 384762Snate@binkert.org#include "cpu/o3/isa_specific.hh" 394762Snate@binkert.org#include "cpu/o3/cpu.hh" 405595Sgblack@eecs.umich.edu#include "cpu/o3/thread_context.hh" 414762Snate@binkert.org#include "enums/MemoryMode.hh" 424762Snate@binkert.org#include "sim/core.hh" 434762Snate@binkert.org#include "sim/stat_control.hh" 444762Snate@binkert.org 451858SN/A#if FULL_SYSTEM 462356SN/A#include "cpu/quiesce_event.hh" 471060SN/A#include "sim/system.hh" 481060SN/A#else 491060SN/A#include "sim/process.hh" 501060SN/A#endif 511060SN/A 522794Sktlim@umich.edu#if USE_CHECKER 532794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 542794Sktlim@umich.edu#endif 552794Sktlim@umich.edu 565702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 575702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 585702Ssaidi@eecs.umich.edu#endif 595702Ssaidi@eecs.umich.edu 605529Snate@binkert.orgclass BaseCPUParams; 615529Snate@binkert.org 622669Sktlim@umich.eduusing namespace TheISA; 631060SN/A 645529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 655712Shsul@eecs.umich.edu : BaseCPU(params) 661060SN/A{ 671060SN/A} 681060SN/A 692292SN/Avoid 702733Sktlim@umich.eduBaseO3CPU::regStats() 712292SN/A{ 722292SN/A BaseCPU::regStats(); 732292SN/A} 742292SN/A 751060SN/Atemplate <class Impl> 761755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 775606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 781060SN/A{ 791060SN/A} 801060SN/A 811060SN/Atemplate <class Impl> 821060SN/Avoid 831755SN/AFullO3CPU<Impl>::TickEvent::process() 841060SN/A{ 851060SN/A cpu->tick(); 861060SN/A} 871060SN/A 881060SN/Atemplate <class Impl> 891060SN/Aconst char * 905336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 911060SN/A{ 924873Sstever@eecs.umich.edu return "FullO3CPU tick"; 931060SN/A} 941060SN/A 951060SN/Atemplate <class Impl> 962829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 975606Snate@binkert.org : Event(CPU_Switch_Pri) 982829Sksewell@umich.edu{ 992829Sksewell@umich.edu} 1002829Sksewell@umich.edu 1012829Sksewell@umich.edutemplate <class Impl> 1022829Sksewell@umich.eduvoid 1032829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 1042829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1052829Sksewell@umich.edu{ 1062829Sksewell@umich.edu tid = thread_num; 1072829Sksewell@umich.edu cpu = thread_cpu; 1082829Sksewell@umich.edu} 1092829Sksewell@umich.edu 1102829Sksewell@umich.edutemplate <class Impl> 1112829Sksewell@umich.eduvoid 1122829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1132829Sksewell@umich.edu{ 1142829Sksewell@umich.edu cpu->activateThread(tid); 1152829Sksewell@umich.edu} 1162829Sksewell@umich.edu 1172829Sksewell@umich.edutemplate <class Impl> 1182829Sksewell@umich.educonst char * 1195336Shines@cs.fsu.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1202829Sksewell@umich.edu{ 1214873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1222829Sksewell@umich.edu} 1232829Sksewell@umich.edu 1242829Sksewell@umich.edutemplate <class Impl> 1252875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1265606Snate@binkert.org : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1272875Sksewell@umich.edu{ 1282875Sksewell@umich.edu} 1292875Sksewell@umich.edu 1302875Sksewell@umich.edutemplate <class Impl> 1312875Sksewell@umich.eduvoid 1322875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1333859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1342875Sksewell@umich.edu{ 1352875Sksewell@umich.edu tid = thread_num; 1362875Sksewell@umich.edu cpu = thread_cpu; 1373859Sbinkertn@umich.edu remove = false; 1382875Sksewell@umich.edu} 1392875Sksewell@umich.edu 1402875Sksewell@umich.edutemplate <class Impl> 1412875Sksewell@umich.eduvoid 1422875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1432875Sksewell@umich.edu{ 1442875Sksewell@umich.edu cpu->deactivateThread(tid); 1453221Sktlim@umich.edu if (remove) 1463221Sktlim@umich.edu cpu->removeThread(tid); 1472875Sksewell@umich.edu} 1482875Sksewell@umich.edu 1492875Sksewell@umich.edutemplate <class Impl> 1502875Sksewell@umich.educonst char * 1515336Shines@cs.fsu.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 1522875Sksewell@umich.edu{ 1534873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 1542875Sksewell@umich.edu} 1552875Sksewell@umich.edu 1562875Sksewell@umich.edutemplate <class Impl> 1575595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 1582733Sktlim@umich.edu : BaseO3CPU(params), 1593781Sgblack@eecs.umich.edu itb(params->itb), 1603781Sgblack@eecs.umich.edu dtb(params->dtb), 1611060SN/A tickEvent(this), 1622292SN/A removeInstsThisCycle(false), 1635595Sgblack@eecs.umich.edu fetch(this, params), 1645595Sgblack@eecs.umich.edu decode(this, params), 1655595Sgblack@eecs.umich.edu rename(this, params), 1665595Sgblack@eecs.umich.edu iew(this, params), 1675595Sgblack@eecs.umich.edu commit(this, params), 1681060SN/A 1695595Sgblack@eecs.umich.edu regFile(this, params->numPhysIntRegs, 1704329Sktlim@umich.edu params->numPhysFloatRegs), 1711060SN/A 1725529Snate@binkert.org freeList(params->numThreads, 1732292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1742292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1751060SN/A 1765595Sgblack@eecs.umich.edu rob(this, 1774329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 1782292SN/A params->smtROBPolicy, params->smtROBThreshold, 1795529Snate@binkert.org params->numThreads), 1801060SN/A 1815529Snate@binkert.org scoreboard(params->numThreads, 1822292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1832292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1842292SN/A TheISA::NumMiscRegs * number_of_threads, 1852292SN/A TheISA::ZeroReg), 1861060SN/A 1872873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1882873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1892873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1902873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1912873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1922873Sktlim@umich.edu activityRec(NumStages, 1932873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1942873Sktlim@umich.edu params->activity), 1951060SN/A 1961060SN/A globalSeqNum(1), 1971858SN/A#if FULL_SYSTEM 1982292SN/A system(params->system), 1991060SN/A physmem(system->physmem), 2001060SN/A#endif // FULL_SYSTEM 2012843Sktlim@umich.edu drainCount(0), 2025529Snate@binkert.org deferRegistration(params->defer_registration), 2032316SN/A numThreads(number_of_threads) 2041060SN/A{ 2053221Sktlim@umich.edu if (!deferRegistration) { 2063221Sktlim@umich.edu _status = Running; 2073221Sktlim@umich.edu } else { 2083221Sktlim@umich.edu _status = Idle; 2093221Sktlim@umich.edu } 2101681SN/A 2114598Sbinkertn@umich.edu#if USE_CHECKER 2122794Sktlim@umich.edu if (params->checker) { 2132316SN/A BaseCPU *temp_checker = params->checker; 2142316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2152316SN/A#if FULL_SYSTEM 2162316SN/A checker->setSystem(params->system); 2172316SN/A#endif 2184598Sbinkertn@umich.edu } else { 2194598Sbinkertn@umich.edu checker = NULL; 2204598Sbinkertn@umich.edu } 2212794Sktlim@umich.edu#endif // USE_CHECKER 2222316SN/A 2231858SN/A#if !FULL_SYSTEM 2242292SN/A thread.resize(number_of_threads); 2252292SN/A tids.resize(number_of_threads); 2261681SN/A#endif 2271681SN/A 2282325SN/A // The stages also need their CPU pointer setup. However this 2292325SN/A // must be done at the upper level CPU because they have pointers 2302325SN/A // to the upper level CPU, and not this FullO3CPU. 2311060SN/A 2322292SN/A // Set up Pointers to the activeThreads list for each stage 2332292SN/A fetch.setActiveThreads(&activeThreads); 2342292SN/A decode.setActiveThreads(&activeThreads); 2352292SN/A rename.setActiveThreads(&activeThreads); 2362292SN/A iew.setActiveThreads(&activeThreads); 2372292SN/A commit.setActiveThreads(&activeThreads); 2381060SN/A 2391060SN/A // Give each of the stages the time buffer they will use. 2401060SN/A fetch.setTimeBuffer(&timeBuffer); 2411060SN/A decode.setTimeBuffer(&timeBuffer); 2421060SN/A rename.setTimeBuffer(&timeBuffer); 2431060SN/A iew.setTimeBuffer(&timeBuffer); 2441060SN/A commit.setTimeBuffer(&timeBuffer); 2451060SN/A 2461060SN/A // Also setup each of the stages' queues. 2471060SN/A fetch.setFetchQueue(&fetchQueue); 2481060SN/A decode.setFetchQueue(&fetchQueue); 2492292SN/A commit.setFetchQueue(&fetchQueue); 2501060SN/A decode.setDecodeQueue(&decodeQueue); 2511060SN/A rename.setDecodeQueue(&decodeQueue); 2521060SN/A rename.setRenameQueue(&renameQueue); 2531060SN/A iew.setRenameQueue(&renameQueue); 2541060SN/A iew.setIEWQueue(&iewQueue); 2551060SN/A commit.setIEWQueue(&iewQueue); 2561060SN/A commit.setRenameQueue(&renameQueue); 2571060SN/A 2582292SN/A commit.setIEWStage(&iew); 2592292SN/A rename.setIEWStage(&iew); 2602292SN/A rename.setCommitStage(&commit); 2612292SN/A 2622292SN/A#if !FULL_SYSTEM 2632307SN/A int active_threads = params->workload.size(); 2642831Sksewell@umich.edu 2652831Sksewell@umich.edu if (active_threads > Impl::MaxThreads) { 2662831Sksewell@umich.edu panic("Workload Size too large. Increase the 'MaxThreads'" 2672831Sksewell@umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2682831Sksewell@umich.edu "edit your workload size."); 2692831Sksewell@umich.edu } 2702292SN/A#else 2712307SN/A int active_threads = 1; 2722292SN/A#endif 2732292SN/A 2742316SN/A //Make Sure That this a Valid Architeture 2752292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2762292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2772292SN/A 2782292SN/A rename.setScoreboard(&scoreboard); 2792292SN/A iew.setScoreboard(&scoreboard); 2802292SN/A 2811060SN/A // Setup the rename map for whichever stages need it. 2822292SN/A PhysRegIndex lreg_idx = 0; 2832292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2841060SN/A 2852292SN/A for (int tid=0; tid < numThreads; tid++) { 2862307SN/A bool bindRegs = (tid <= active_threads - 1); 2872292SN/A 2882292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2892292SN/A params->numPhysIntRegs, 2902325SN/A lreg_idx, //Index for Logical. Regs 2912292SN/A 2922292SN/A TheISA::NumFloatRegs, 2932292SN/A params->numPhysFloatRegs, 2942325SN/A freg_idx, //Index for Float Regs 2952292SN/A 2962292SN/A TheISA::NumMiscRegs, 2972292SN/A 2982292SN/A TheISA::ZeroReg, 2992292SN/A TheISA::ZeroReg, 3002292SN/A 3012292SN/A tid, 3022292SN/A false); 3032292SN/A 3042292SN/A renameMap[tid].init(TheISA::NumIntRegs, 3052292SN/A params->numPhysIntRegs, 3062325SN/A lreg_idx, //Index for Logical. Regs 3072292SN/A 3082292SN/A TheISA::NumFloatRegs, 3092292SN/A params->numPhysFloatRegs, 3102325SN/A freg_idx, //Index for Float Regs 3112292SN/A 3122292SN/A TheISA::NumMiscRegs, 3132292SN/A 3142292SN/A TheISA::ZeroReg, 3152292SN/A TheISA::ZeroReg, 3162292SN/A 3172292SN/A tid, 3182292SN/A bindRegs); 3193221Sktlim@umich.edu 3203221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3213221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3222292SN/A } 3232292SN/A 3242292SN/A rename.setRenameMap(renameMap); 3252292SN/A commit.setRenameMap(commitRenameMap); 3262292SN/A 3272292SN/A // Give renameMap & rename stage access to the freeList; 3282292SN/A for (int i=0; i < numThreads; i++) { 3292292SN/A renameMap[i].setFreeList(&freeList); 3302292SN/A } 3311060SN/A rename.setFreeList(&freeList); 3322292SN/A 3331060SN/A // Setup the ROB for whichever stages need it. 3341060SN/A commit.setROB(&rob); 3352292SN/A 3362292SN/A lastRunningCycle = curTick; 3372292SN/A 3382829Sksewell@umich.edu lastActivatedCycle = -1; 3392829Sksewell@umich.edu 3403093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3413093Sksewell@umich.edu //for (int i=0; i < numThreads; i++) { 3423093Sksewell@umich.edu //globalSeqNum[i] = 1; 3433093Sksewell@umich.edu //} 3443093Sksewell@umich.edu 3452292SN/A contextSwitch = false; 3465595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3475595Sgblack@eecs.umich.edu 3485595Sgblack@eecs.umich.edu // Setup any thread state. 3495595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 3505595Sgblack@eecs.umich.edu 3515595Sgblack@eecs.umich.edu for (int i = 0; i < this->numThreads; ++i) { 3525595Sgblack@eecs.umich.edu#if FULL_SYSTEM 3535595Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 3545595Sgblack@eecs.umich.edu assert(this->numThreads == 1); 3555595Sgblack@eecs.umich.edu this->thread[i] = new Thread(this, 0); 3565595Sgblack@eecs.umich.edu this->thread[i]->setStatus(ThreadContext::Suspended); 3575595Sgblack@eecs.umich.edu#else 3585595Sgblack@eecs.umich.edu if (i < params->workload.size()) { 3595595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 3605595Sgblack@eecs.umich.edu i, this->thread[i]); 3615595Sgblack@eecs.umich.edu this->thread[i] = new typename FullO3CPU<Impl>::Thread( 3625595Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3635595Sgblack@eecs.umich.edu i, params->workload[i], i); 3645595Sgblack@eecs.umich.edu 3655595Sgblack@eecs.umich.edu this->thread[i]->setStatus(ThreadContext::Suspended); 3665595Sgblack@eecs.umich.edu 3675595Sgblack@eecs.umich.edu //usedTids[i] = true; 3685595Sgblack@eecs.umich.edu //threadMap[i] = i; 3695595Sgblack@eecs.umich.edu } else { 3705595Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 3715595Sgblack@eecs.umich.edu //when scheduling threads to CPU 3725595Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 3735595Sgblack@eecs.umich.edu 3745595Sgblack@eecs.umich.edu this->thread[i] = new typename FullO3CPU<Impl>::Thread( 3755595Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3765595Sgblack@eecs.umich.edu i, dummy_proc, i); 3775595Sgblack@eecs.umich.edu //usedTids[i] = false; 3785595Sgblack@eecs.umich.edu } 3795595Sgblack@eecs.umich.edu#endif // !FULL_SYSTEM 3805595Sgblack@eecs.umich.edu 3815595Sgblack@eecs.umich.edu ThreadContext *tc; 3825595Sgblack@eecs.umich.edu 3835595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 3845595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 3855595Sgblack@eecs.umich.edu 3865595Sgblack@eecs.umich.edu tc = o3_tc; 3875595Sgblack@eecs.umich.edu 3885595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 3895595Sgblack@eecs.umich.edu // CheckerThreadContext. 3905595Sgblack@eecs.umich.edu#if USE_CHECKER 3915595Sgblack@eecs.umich.edu if (params->checker) { 3925595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 3935595Sgblack@eecs.umich.edu o3_tc, this->checker); 3945595Sgblack@eecs.umich.edu } 3955595Sgblack@eecs.umich.edu#endif 3965595Sgblack@eecs.umich.edu 3975595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 3985595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 3995595Sgblack@eecs.umich.edu o3_tc->thread = this->thread[i]; 4005595Sgblack@eecs.umich.edu 4015595Sgblack@eecs.umich.edu#if FULL_SYSTEM 4025595Sgblack@eecs.umich.edu // Setup quiesce event. 4035595Sgblack@eecs.umich.edu this->thread[i]->quiesceEvent = new EndQuiesceEvent(tc); 4045595Sgblack@eecs.umich.edu#endif 4055595Sgblack@eecs.umich.edu // Give the thread the TC. 4065595Sgblack@eecs.umich.edu this->thread[i]->tc = tc; 4075595Sgblack@eecs.umich.edu 4085595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4095595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4105595Sgblack@eecs.umich.edu } 4115595Sgblack@eecs.umich.edu 4125595Sgblack@eecs.umich.edu for (int i=0; i < this->numThreads; i++) { 4135595Sgblack@eecs.umich.edu this->thread[i]->setFuncExeInst(0); 4145595Sgblack@eecs.umich.edu } 4155595Sgblack@eecs.umich.edu 4165595Sgblack@eecs.umich.edu lockAddr = 0; 4175595Sgblack@eecs.umich.edu lockFlag = false; 4181060SN/A} 4191060SN/A 4205595Sgblack@eecs.umich.edu#if !FULL_SYSTEM 4215595Sgblack@eecs.umich.edu 4225595Sgblack@eecs.umich.edutemplate <class Impl> 4235595Sgblack@eecs.umich.eduTheISA::IntReg 4245595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getSyscallArg(int i, int tid) 4255595Sgblack@eecs.umich.edu{ 4265595Sgblack@eecs.umich.edu assert(i < TheISA::NumArgumentRegs); 4275595Sgblack@eecs.umich.edu TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), 4285595Sgblack@eecs.umich.edu TheISA::ArgumentReg[i]); 4295595Sgblack@eecs.umich.edu TheISA::IntReg val = this->readArchIntReg(idx, tid); 4305595Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 4315595Sgblack@eecs.umich.edu if (bits(this->readMiscRegNoEffect(SparcISA::MISCREG_PSTATE, tid), 3, 3)) 4325595Sgblack@eecs.umich.edu val = bits(val, 31, 0); 4335595Sgblack@eecs.umich.edu#endif 4345595Sgblack@eecs.umich.edu return val; 4355595Sgblack@eecs.umich.edu} 4365595Sgblack@eecs.umich.edu 4375595Sgblack@eecs.umich.edutemplate <class Impl> 4385595Sgblack@eecs.umich.eduvoid 4395595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid) 4405595Sgblack@eecs.umich.edu{ 4415595Sgblack@eecs.umich.edu assert(i < TheISA::NumArgumentRegs); 4425595Sgblack@eecs.umich.edu TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), 4435595Sgblack@eecs.umich.edu TheISA::ArgumentReg[i]); 4445595Sgblack@eecs.umich.edu this->setArchIntReg(idx, val, tid); 4455595Sgblack@eecs.umich.edu} 4465595Sgblack@eecs.umich.edu#endif 4475595Sgblack@eecs.umich.edu 4481060SN/Atemplate <class Impl> 4491755SN/AFullO3CPU<Impl>::~FullO3CPU() 4501060SN/A{ 4511060SN/A} 4521060SN/A 4531060SN/Atemplate <class Impl> 4541060SN/Avoid 4555595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4561062SN/A{ 4572733Sktlim@umich.edu BaseO3CPU::regStats(); 4582292SN/A 4592733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4602292SN/A timesIdled 4612292SN/A .name(name() + ".timesIdled") 4622292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4632292SN/A " unscheduled itself") 4642292SN/A .prereq(timesIdled); 4652292SN/A 4662292SN/A idleCycles 4672292SN/A .name(name() + ".idleCycles") 4682292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4692292SN/A "to idling") 4702292SN/A .prereq(idleCycles); 4712292SN/A 4722292SN/A // Number of Instructions simulated 4732292SN/A // -------------------------------- 4742292SN/A // Should probably be in Base CPU but need templated 4752292SN/A // MaxThreads so put in here instead 4762292SN/A committedInsts 4772292SN/A .init(numThreads) 4782292SN/A .name(name() + ".committedInsts") 4792292SN/A .desc("Number of Instructions Simulated"); 4802292SN/A 4812292SN/A totalCommittedInsts 4822292SN/A .name(name() + ".committedInsts_total") 4832292SN/A .desc("Number of Instructions Simulated"); 4842292SN/A 4852292SN/A cpi 4862292SN/A .name(name() + ".cpi") 4872292SN/A .desc("CPI: Cycles Per Instruction") 4882292SN/A .precision(6); 4894392Sktlim@umich.edu cpi = numCycles / committedInsts; 4902292SN/A 4912292SN/A totalCpi 4922292SN/A .name(name() + ".cpi_total") 4932292SN/A .desc("CPI: Total CPI of All Threads") 4942292SN/A .precision(6); 4954392Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 4962292SN/A 4972292SN/A ipc 4982292SN/A .name(name() + ".ipc") 4992292SN/A .desc("IPC: Instructions Per Cycle") 5002292SN/A .precision(6); 5014392Sktlim@umich.edu ipc = committedInsts / numCycles; 5022292SN/A 5032292SN/A totalIpc 5042292SN/A .name(name() + ".ipc_total") 5052292SN/A .desc("IPC: Total IPC of All Threads") 5062292SN/A .precision(6); 5074392Sktlim@umich.edu totalIpc = totalCommittedInsts / numCycles; 5082292SN/A 5095595Sgblack@eecs.umich.edu this->fetch.regStats(); 5105595Sgblack@eecs.umich.edu this->decode.regStats(); 5115595Sgblack@eecs.umich.edu this->rename.regStats(); 5125595Sgblack@eecs.umich.edu this->iew.regStats(); 5135595Sgblack@eecs.umich.edu this->commit.regStats(); 5141062SN/A} 5151062SN/A 5161062SN/Atemplate <class Impl> 5172871Sktlim@umich.eduPort * 5182871Sktlim@umich.eduFullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 5192871Sktlim@umich.edu{ 5202871Sktlim@umich.edu if (if_name == "dcache_port") 5212871Sktlim@umich.edu return iew.getDcachePort(); 5222871Sktlim@umich.edu else if (if_name == "icache_port") 5232871Sktlim@umich.edu return fetch.getIcachePort(); 5242871Sktlim@umich.edu else 5252871Sktlim@umich.edu panic("No Such Port\n"); 5262871Sktlim@umich.edu} 5272871Sktlim@umich.edu 5282871Sktlim@umich.edutemplate <class Impl> 5291062SN/Avoid 5301755SN/AFullO3CPU<Impl>::tick() 5311060SN/A{ 5322733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5331060SN/A 5342292SN/A ++numCycles; 5352292SN/A 5362325SN/A// activity = false; 5372292SN/A 5382292SN/A //Tick each of the stages 5391060SN/A fetch.tick(); 5401060SN/A 5411060SN/A decode.tick(); 5421060SN/A 5431060SN/A rename.tick(); 5441060SN/A 5451060SN/A iew.tick(); 5461060SN/A 5471060SN/A commit.tick(); 5481060SN/A 5492292SN/A#if !FULL_SYSTEM 5502292SN/A doContextSwitch(); 5512292SN/A#endif 5522292SN/A 5532292SN/A // Now advance the time buffers 5541060SN/A timeBuffer.advance(); 5551060SN/A 5561060SN/A fetchQueue.advance(); 5571060SN/A decodeQueue.advance(); 5581060SN/A renameQueue.advance(); 5591060SN/A iewQueue.advance(); 5601060SN/A 5612325SN/A activityRec.advance(); 5622292SN/A 5632292SN/A if (removeInstsThisCycle) { 5642292SN/A cleanUpRemovedInsts(); 5652292SN/A } 5662292SN/A 5672325SN/A if (!tickEvent.scheduled()) { 5682867Sktlim@umich.edu if (_status == SwitchedOut || 5692905Sktlim@umich.edu getState() == SimObject::Drained) { 5703226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 5712325SN/A // increment stat 5722325SN/A lastRunningCycle = curTick; 5733221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 5743226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 5752325SN/A lastRunningCycle = curTick; 5762325SN/A timesIdled++; 5772325SN/A } else { 5785606Snate@binkert.org schedule(tickEvent, nextCycle(curTick + ticks(1))); 5793226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 5802325SN/A } 5812292SN/A } 5822292SN/A 5832292SN/A#if !FULL_SYSTEM 5842292SN/A updateThreadPriority(); 5852292SN/A#endif 5861060SN/A} 5871060SN/A 5881060SN/Atemplate <class Impl> 5891060SN/Avoid 5901755SN/AFullO3CPU<Impl>::init() 5911060SN/A{ 5922307SN/A if (!deferRegistration) { 5932680Sktlim@umich.edu registerThreadContexts(); 5942292SN/A } 5951060SN/A 5962292SN/A // Set inSyscall so that the CPU doesn't squash when initially 5972292SN/A // setting up registers. 5982292SN/A for (int i = 0; i < number_of_threads; ++i) 5992292SN/A thread[i]->inSyscall = true; 6002292SN/A 6012292SN/A for (int tid=0; tid < number_of_threads; tid++) { 6021858SN/A#if FULL_SYSTEM 6032680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 6041681SN/A#else 6052680Sktlim@umich.edu ThreadContext *src_tc = thread[tid]->getTC(); 6061681SN/A#endif 6072292SN/A // Threads start in the Suspended State 6082680Sktlim@umich.edu if (src_tc->status() != ThreadContext::Suspended) { 6092292SN/A continue; 6101060SN/A } 6111060SN/A 6122292SN/A#if FULL_SYSTEM 6135712Shsul@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->cpuId()); 6142292SN/A#endif 6152292SN/A } 6162292SN/A 6172292SN/A // Clear inSyscall. 6182292SN/A for (int i = 0; i < number_of_threads; ++i) 6192292SN/A thread[i]->inSyscall = false; 6202292SN/A 6212316SN/A // Initialize stages. 6222292SN/A fetch.initStage(); 6232292SN/A iew.initStage(); 6242292SN/A rename.initStage(); 6252292SN/A commit.initStage(); 6262292SN/A 6272292SN/A commit.setThreads(thread); 6282292SN/A} 6292292SN/A 6302292SN/Atemplate <class Impl> 6312292SN/Avoid 6322875Sksewell@umich.eduFullO3CPU<Impl>::activateThread(unsigned tid) 6332875Sksewell@umich.edu{ 6345314Sstever@gmail.com std::list<unsigned>::iterator isActive = 6355314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6362875Sksewell@umich.edu 6373226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6383226Sktlim@umich.edu 6392875Sksewell@umich.edu if (isActive == activeThreads.end()) { 6402875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6412875Sksewell@umich.edu tid); 6422875Sksewell@umich.edu 6432875Sksewell@umich.edu activeThreads.push_back(tid); 6442875Sksewell@umich.edu } 6452875Sksewell@umich.edu} 6462875Sksewell@umich.edu 6472875Sksewell@umich.edutemplate <class Impl> 6482875Sksewell@umich.eduvoid 6492875Sksewell@umich.eduFullO3CPU<Impl>::deactivateThread(unsigned tid) 6502875Sksewell@umich.edu{ 6512875Sksewell@umich.edu //Remove From Active List, if Active 6525314Sstever@gmail.com std::list<unsigned>::iterator thread_it = 6535314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6542875Sksewell@umich.edu 6553226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 6563226Sktlim@umich.edu 6572875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 6582875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6592875Sksewell@umich.edu tid); 6602875Sksewell@umich.edu activeThreads.erase(thread_it); 6612875Sksewell@umich.edu } 6622875Sksewell@umich.edu} 6632875Sksewell@umich.edu 6642875Sksewell@umich.edutemplate <class Impl> 6652875Sksewell@umich.eduvoid 6662875Sksewell@umich.eduFullO3CPU<Impl>::activateContext(int tid, int delay) 6672875Sksewell@umich.edu{ 6682875Sksewell@umich.edu // Needs to set each stage to running as well. 6692875Sksewell@umich.edu if (delay){ 6702875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 6715100Ssaidi@eecs.umich.edu "on cycle %d\n", tid, curTick + ticks(delay)); 6722875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 6732875Sksewell@umich.edu } else { 6742875Sksewell@umich.edu activateThread(tid); 6752875Sksewell@umich.edu } 6762875Sksewell@umich.edu 6773221Sktlim@umich.edu if (lastActivatedCycle < curTick) { 6782875Sksewell@umich.edu scheduleTickEvent(delay); 6792875Sksewell@umich.edu 6802875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 6812875Sksewell@umich.edu // deschedule itself. 6822875Sksewell@umich.edu activityRec.activity(); 6832875Sksewell@umich.edu fetch.wakeFromQuiesce(); 6842875Sksewell@umich.edu 6852875Sksewell@umich.edu lastActivatedCycle = curTick; 6862875Sksewell@umich.edu 6872875Sksewell@umich.edu _status = Running; 6882875Sksewell@umich.edu } 6892875Sksewell@umich.edu} 6902875Sksewell@umich.edu 6912875Sksewell@umich.edutemplate <class Impl> 6923221Sktlim@umich.edubool 6933221Sktlim@umich.eduFullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay) 6942875Sksewell@umich.edu{ 6952875Sksewell@umich.edu // Schedule removal of thread data from CPU 6962875Sksewell@umich.edu if (delay){ 6972875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 6985100Ssaidi@eecs.umich.edu "on cycle %d\n", tid, curTick + ticks(delay)); 6993221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 7003221Sktlim@umich.edu return false; 7012875Sksewell@umich.edu } else { 7022875Sksewell@umich.edu deactivateThread(tid); 7033221Sktlim@umich.edu if (remove) 7043221Sktlim@umich.edu removeThread(tid); 7053221Sktlim@umich.edu return true; 7062875Sksewell@umich.edu } 7072875Sksewell@umich.edu} 7082875Sksewell@umich.edu 7092875Sksewell@umich.edutemplate <class Impl> 7102875Sksewell@umich.eduvoid 7112875Sksewell@umich.eduFullO3CPU<Impl>::suspendContext(int tid) 7122875Sksewell@umich.edu{ 7132875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 7143221Sktlim@umich.edu bool deallocated = deallocateContext(tid, false, 1); 7153221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 7165570Snate@binkert.org if ((activeThreads.size() == 1 && !deallocated) || 7173859Sbinkertn@umich.edu activeThreads.size() == 0) 7182910Sksewell@umich.edu unscheduleTickEvent(); 7192875Sksewell@umich.edu _status = Idle; 7202875Sksewell@umich.edu} 7212875Sksewell@umich.edu 7222875Sksewell@umich.edutemplate <class Impl> 7232875Sksewell@umich.eduvoid 7242875Sksewell@umich.eduFullO3CPU<Impl>::haltContext(int tid) 7252875Sksewell@umich.edu{ 7262910Sksewell@umich.edu //For now, this is the same as deallocate 7272910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 7283221Sktlim@umich.edu deallocateContext(tid, true, 1); 7292875Sksewell@umich.edu} 7302875Sksewell@umich.edu 7312875Sksewell@umich.edutemplate <class Impl> 7322875Sksewell@umich.eduvoid 7332292SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 7342292SN/A{ 7352847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 7362292SN/A // Will change now that the PC and thread state is internal to the CPU 7372683Sktlim@umich.edu // and not in the ThreadContext. 7382292SN/A#if FULL_SYSTEM 7392680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 7402292SN/A#else 7412847Sksewell@umich.edu ThreadContext *src_tc = tcBase(tid); 7422292SN/A#endif 7432292SN/A 7442292SN/A //Bind Int Regs to Rename Map 7452292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7462292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 7472292SN/A 7482292SN/A renameMap[tid].setEntry(ireg,phys_reg); 7492292SN/A scoreboard.setReg(phys_reg); 7502292SN/A } 7512292SN/A 7522292SN/A //Bind Float Regs to Rename Map 7532292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 7542292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 7552292SN/A 7562292SN/A renameMap[tid].setEntry(freg,phys_reg); 7572292SN/A scoreboard.setReg(phys_reg); 7582292SN/A } 7592292SN/A 7602292SN/A //Copy Thread Data Into RegFile 7612847Sksewell@umich.edu //this->copyFromTC(tid); 7622292SN/A 7632847Sksewell@umich.edu //Set PC/NPC/NNPC 7642847Sksewell@umich.edu setPC(src_tc->readPC(), tid); 7652847Sksewell@umich.edu setNextPC(src_tc->readNextPC(), tid); 7662847Sksewell@umich.edu setNextNPC(src_tc->readNextNPC(), tid); 7672292SN/A 7682680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 7692292SN/A 7702292SN/A activateContext(tid,1); 7712292SN/A 7722292SN/A //Reset ROB/IQ/LSQ Entries 7732292SN/A commit.rob->resetEntries(); 7742292SN/A iew.resetEntries(); 7752292SN/A} 7762292SN/A 7772292SN/Atemplate <class Impl> 7782292SN/Avoid 7792292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 7802292SN/A{ 7812877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 7822847Sksewell@umich.edu 7832847Sksewell@umich.edu // Copy Thread Data From RegFile 7842847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 7855364Sksewell@umich.edu // this->copyToTC(tid); 7865364Sksewell@umich.edu 7875364Sksewell@umich.edu 7885364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 7895364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 7905364Sksewell@umich.edu // in SMT workloads. 7912847Sksewell@umich.edu 7922847Sksewell@umich.edu // Unbind Int Regs from Rename Map 7932292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7942292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 7952292SN/A 7962292SN/A scoreboard.unsetReg(phys_reg); 7972292SN/A freeList.addReg(phys_reg); 7982292SN/A } 7992292SN/A 8002847Sksewell@umich.edu // Unbind Float Regs from Rename Map 8015362Sksewell@umich.edu for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 8022292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 8032292SN/A 8042292SN/A scoreboard.unsetReg(phys_reg); 8052292SN/A freeList.addReg(phys_reg); 8062292SN/A } 8072292SN/A 8082847Sksewell@umich.edu // Squash Throughout Pipeline 8092935Sksewell@umich.edu InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; 8104636Sgblack@eecs.umich.edu fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid); 8112292SN/A decode.squash(tid); 8122935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 8132875Sksewell@umich.edu iew.squash(tid); 8145363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 8152935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 8162292SN/A 8175362Sksewell@umich.edu 8185362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 8192292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 8202292SN/A 8212847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 8223229Sktlim@umich.edu 8233229Sktlim@umich.edu // Commented out for now. This should be possible to do by 8243229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 8253229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 8263229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 8273229Sktlim@umich.edu/* 8282292SN/A if (activeThreads.size() >= 1) { 8292292SN/A commit.rob->resetEntries(); 8302292SN/A iew.resetEntries(); 8312292SN/A } 8323229Sktlim@umich.edu*/ 8332292SN/A} 8342292SN/A 8352292SN/A 8362292SN/Atemplate <class Impl> 8372292SN/Avoid 8382292SN/AFullO3CPU<Impl>::activateWhenReady(int tid) 8392292SN/A{ 8402733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 8412292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 8422292SN/A tid); 8432292SN/A 8442292SN/A bool ready = true; 8452292SN/A 8462292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 8472733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8482292SN/A "Phys. Int. Regs.\n", 8492292SN/A tid); 8502292SN/A ready = false; 8512292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 8522733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8532292SN/A "Phys. Float. Regs.\n", 8542292SN/A tid); 8552292SN/A ready = false; 8562292SN/A } else if (commit.rob->numFreeEntries() >= 8572292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 8582733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8592292SN/A "ROB entries.\n", 8602292SN/A tid); 8612292SN/A ready = false; 8622292SN/A } else if (iew.instQueue.numFreeEntries() >= 8632292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 8642733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8652292SN/A "IQ entries.\n", 8662292SN/A tid); 8672292SN/A ready = false; 8682292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 8692292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 8702733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8712292SN/A "LSQ entries.\n", 8722292SN/A tid); 8732292SN/A ready = false; 8742292SN/A } 8752292SN/A 8762292SN/A if (ready) { 8772292SN/A insertThread(tid); 8782292SN/A 8792292SN/A contextSwitch = false; 8802292SN/A 8812292SN/A cpuWaitList.remove(tid); 8822292SN/A } else { 8832292SN/A suspendContext(tid); 8842292SN/A 8852292SN/A //blocks fetch 8862292SN/A contextSwitch = true; 8872292SN/A 8882875Sksewell@umich.edu //@todo: dont always add to waitlist 8892292SN/A //do waitlist 8902292SN/A cpuWaitList.push_back(tid); 8911060SN/A } 8921060SN/A} 8931060SN/A 8944192Sktlim@umich.edu#if FULL_SYSTEM 8954192Sktlim@umich.edutemplate <class Impl> 8964192Sktlim@umich.eduvoid 8975704Snate@binkert.orgFullO3CPU<Impl>::postInterrupt(int int_num, int index) 8985595Sgblack@eecs.umich.edu{ 8995704Snate@binkert.org BaseCPU::postInterrupt(int_num, index); 9005595Sgblack@eecs.umich.edu 9015595Sgblack@eecs.umich.edu if (this->thread[0]->status() == ThreadContext::Suspended) { 9025595Sgblack@eecs.umich.edu DPRINTF(IPI,"Suspended Processor awoke\n"); 9035595Sgblack@eecs.umich.edu this->threadContexts[0]->activate(); 9045595Sgblack@eecs.umich.edu } 9055595Sgblack@eecs.umich.edu} 9065595Sgblack@eecs.umich.edu 9075595Sgblack@eecs.umich.edutemplate <class Impl> 9085595Sgblack@eecs.umich.eduFault 9095702Ssaidi@eecs.umich.eduFullO3CPU<Impl>::hwrei(unsigned tid) 9105702Ssaidi@eecs.umich.edu{ 9115702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9125702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 9135702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 9145702Ssaidi@eecs.umich.edu 9155702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 9165702Ssaidi@eecs.umich.edu 9175702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 9185702Ssaidi@eecs.umich.edu#endif 9195702Ssaidi@eecs.umich.edu return NoFault; 9205702Ssaidi@eecs.umich.edu} 9215702Ssaidi@eecs.umich.edu 9225702Ssaidi@eecs.umich.edutemplate <class Impl> 9235702Ssaidi@eecs.umich.edubool 9245702Ssaidi@eecs.umich.eduFullO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid) 9255702Ssaidi@eecs.umich.edu{ 9265702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9275702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 9285702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 9295702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 9305702Ssaidi@eecs.umich.edu 9315702Ssaidi@eecs.umich.edu switch (palFunc) { 9325702Ssaidi@eecs.umich.edu case PAL::halt: 9335702Ssaidi@eecs.umich.edu halt(); 9345702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 9355702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 9365702Ssaidi@eecs.umich.edu break; 9375702Ssaidi@eecs.umich.edu 9385702Ssaidi@eecs.umich.edu case PAL::bpt: 9395702Ssaidi@eecs.umich.edu case PAL::bugchk: 9405702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 9415702Ssaidi@eecs.umich.edu return false; 9425702Ssaidi@eecs.umich.edu break; 9435702Ssaidi@eecs.umich.edu } 9445702Ssaidi@eecs.umich.edu#endif 9455702Ssaidi@eecs.umich.edu return true; 9465702Ssaidi@eecs.umich.edu} 9475702Ssaidi@eecs.umich.edu 9485702Ssaidi@eecs.umich.edutemplate <class Impl> 9495702Ssaidi@eecs.umich.eduFault 9505595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 9515595Sgblack@eecs.umich.edu{ 9525595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 9535647Sgblack@eecs.umich.edu return this->interrupts->getInterrupt(this->threadContexts[0]); 9545595Sgblack@eecs.umich.edu} 9555595Sgblack@eecs.umich.edu 9565595Sgblack@eecs.umich.edutemplate <class Impl> 9575595Sgblack@eecs.umich.eduvoid 9585595Sgblack@eecs.umich.eduFullO3CPU<Impl>::processInterrupts(Fault interrupt) 9595595Sgblack@eecs.umich.edu{ 9605595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 9615595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 9625595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 9635595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 9645595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 9655595Sgblack@eecs.umich.edu 9665595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 9675647Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 9685595Sgblack@eecs.umich.edu 9695595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 9705595Sgblack@eecs.umich.edu this->trap(interrupt, 0); 9715595Sgblack@eecs.umich.edu} 9725595Sgblack@eecs.umich.edu 9735595Sgblack@eecs.umich.edutemplate <class Impl> 9745595Sgblack@eecs.umich.eduvoid 9754192Sktlim@umich.eduFullO3CPU<Impl>::updateMemPorts() 9764192Sktlim@umich.edu{ 9774192Sktlim@umich.edu // Update all ThreadContext's memory ports (Functional/Virtual 9784192Sktlim@umich.edu // Ports) 9794192Sktlim@umich.edu for (int i = 0; i < thread.size(); ++i) 9805497Ssaidi@eecs.umich.edu thread[i]->connectMemPorts(thread[i]->getTC()); 9814192Sktlim@umich.edu} 9824192Sktlim@umich.edu#endif 9834192Sktlim@umich.edu 9841060SN/Atemplate <class Impl> 9852852Sktlim@umich.eduvoid 9865595Sgblack@eecs.umich.eduFullO3CPU<Impl>::trap(Fault fault, unsigned tid) 9875595Sgblack@eecs.umich.edu{ 9885595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 9895595Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid]); 9905595Sgblack@eecs.umich.edu} 9915595Sgblack@eecs.umich.edu 9925595Sgblack@eecs.umich.edu#if !FULL_SYSTEM 9935595Sgblack@eecs.umich.edu 9945595Sgblack@eecs.umich.edutemplate <class Impl> 9955595Sgblack@eecs.umich.eduvoid 9965595Sgblack@eecs.umich.eduFullO3CPU<Impl>::syscall(int64_t callnum, int tid) 9975595Sgblack@eecs.umich.edu{ 9985595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 9995595Sgblack@eecs.umich.edu 10005595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 10015595Sgblack@eecs.umich.edu 10025595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 10035595Sgblack@eecs.umich.edu // instruction. 10045595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 10055595Sgblack@eecs.umich.edu 10065595Sgblack@eecs.umich.edu // Execute the actual syscall. 10075595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 10085595Sgblack@eecs.umich.edu 10095595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 10105595Sgblack@eecs.umich.edu // incrementing it. 10115595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 10125595Sgblack@eecs.umich.edu} 10135595Sgblack@eecs.umich.edu 10145595Sgblack@eecs.umich.edutemplate <class Impl> 10155595Sgblack@eecs.umich.eduvoid 10165595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid) 10175595Sgblack@eecs.umich.edu{ 10185595Sgblack@eecs.umich.edu TheISA::setSyscallReturn(return_value, this->tcBase(tid)); 10195595Sgblack@eecs.umich.edu} 10205595Sgblack@eecs.umich.edu 10215595Sgblack@eecs.umich.edu#endif 10225595Sgblack@eecs.umich.edu 10235595Sgblack@eecs.umich.edutemplate <class Impl> 10245595Sgblack@eecs.umich.eduvoid 10252864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 10262864Sktlim@umich.edu{ 10272918Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 10282918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 10292864Sktlim@umich.edu BaseCPU::serialize(os); 10302864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 10312864Sktlim@umich.edu tickEvent.serialize(os); 10322864Sktlim@umich.edu 10332864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10342864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 10352864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 10362864Sktlim@umich.edu static SimpleThread temp; 10372864Sktlim@umich.edu 10382864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 10392864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 10402864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10412864Sktlim@umich.edu temp.serialize(os); 10422864Sktlim@umich.edu } 10432864Sktlim@umich.edu} 10442864Sktlim@umich.edu 10452864Sktlim@umich.edutemplate <class Impl> 10462864Sktlim@umich.eduvoid 10472864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 10482864Sktlim@umich.edu{ 10492918Sktlim@umich.edu SimObject::State so_state; 10502918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 10512864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 10522864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 10532864Sktlim@umich.edu 10542864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10552864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 10562864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 10572864Sktlim@umich.edu static SimpleThread temp; 10582864Sktlim@umich.edu 10592864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 10602864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10612864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 10622864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 10632864Sktlim@umich.edu } 10642864Sktlim@umich.edu} 10652864Sktlim@umich.edu 10662864Sktlim@umich.edutemplate <class Impl> 10672905Sktlim@umich.eduunsigned int 10682843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 10691060SN/A{ 10703125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 10713512Sktlim@umich.edu 10723512Sktlim@umich.edu // If the CPU isn't doing anything, then return immediately. 10733512Sktlim@umich.edu if (_status == Idle || _status == SwitchedOut) { 10743512Sktlim@umich.edu return 0; 10753512Sktlim@umich.edu } 10763512Sktlim@umich.edu 10772843Sktlim@umich.edu drainCount = 0; 10782843Sktlim@umich.edu fetch.drain(); 10792843Sktlim@umich.edu decode.drain(); 10802843Sktlim@umich.edu rename.drain(); 10812843Sktlim@umich.edu iew.drain(); 10822843Sktlim@umich.edu commit.drain(); 10832325SN/A 10842325SN/A // Wake the CPU and record activity so everything can drain out if 10852863Sktlim@umich.edu // the CPU was not able to immediately drain. 10862905Sktlim@umich.edu if (getState() != SimObject::Drained) { 10872864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 10882864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 10892864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 10902864Sktlim@umich.edu // process on the drain event. 10912864Sktlim@umich.edu drainEvent = drain_event; 10922843Sktlim@umich.edu 10932863Sktlim@umich.edu wakeCPU(); 10942863Sktlim@umich.edu activityRec.activity(); 10952852Sktlim@umich.edu 10962905Sktlim@umich.edu return 1; 10972863Sktlim@umich.edu } else { 10982905Sktlim@umich.edu return 0; 10992863Sktlim@umich.edu } 11002316SN/A} 11012310SN/A 11022316SN/Atemplate <class Impl> 11032316SN/Avoid 11042843Sktlim@umich.eduFullO3CPU<Impl>::resume() 11052316SN/A{ 11062843Sktlim@umich.edu fetch.resume(); 11072843Sktlim@umich.edu decode.resume(); 11082843Sktlim@umich.edu rename.resume(); 11092843Sktlim@umich.edu iew.resume(); 11102843Sktlim@umich.edu commit.resume(); 11112316SN/A 11122905Sktlim@umich.edu changeState(SimObject::Running); 11132905Sktlim@umich.edu 11142864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 11152864Sktlim@umich.edu return; 11162864Sktlim@umich.edu 11173319Shsul@eecs.umich.edu#if FULL_SYSTEM 11184762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 11193319Shsul@eecs.umich.edu#endif 11203319Shsul@eecs.umich.edu 11212843Sktlim@umich.edu if (!tickEvent.scheduled()) 11225606Snate@binkert.org schedule(tickEvent, nextCycle()); 11232843Sktlim@umich.edu _status = Running; 11242843Sktlim@umich.edu} 11252316SN/A 11262843Sktlim@umich.edutemplate <class Impl> 11272843Sktlim@umich.eduvoid 11282843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 11292843Sktlim@umich.edu{ 11302843Sktlim@umich.edu if (++drainCount == NumStages) { 11312316SN/A if (tickEvent.scheduled()) 11322316SN/A tickEvent.squash(); 11332863Sktlim@umich.edu 11342905Sktlim@umich.edu changeState(SimObject::Drained); 11352863Sktlim@umich.edu 11363126Sktlim@umich.edu BaseCPU::switchOut(); 11373126Sktlim@umich.edu 11382863Sktlim@umich.edu if (drainEvent) { 11392863Sktlim@umich.edu drainEvent->process(); 11402863Sktlim@umich.edu drainEvent = NULL; 11412863Sktlim@umich.edu } 11422310SN/A } 11432843Sktlim@umich.edu assert(drainCount <= 5); 11442843Sktlim@umich.edu} 11452843Sktlim@umich.edu 11462843Sktlim@umich.edutemplate <class Impl> 11472843Sktlim@umich.eduvoid 11482843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 11492843Sktlim@umich.edu{ 11502843Sktlim@umich.edu fetch.switchOut(); 11512843Sktlim@umich.edu rename.switchOut(); 11522325SN/A iew.switchOut(); 11532843Sktlim@umich.edu commit.switchOut(); 11542843Sktlim@umich.edu instList.clear(); 11552843Sktlim@umich.edu while (!removeList.empty()) { 11562843Sktlim@umich.edu removeList.pop(); 11572843Sktlim@umich.edu } 11582843Sktlim@umich.edu 11592843Sktlim@umich.edu _status = SwitchedOut; 11602843Sktlim@umich.edu#if USE_CHECKER 11612843Sktlim@umich.edu if (checker) 11622843Sktlim@umich.edu checker->switchOut(); 11632843Sktlim@umich.edu#endif 11643126Sktlim@umich.edu if (tickEvent.scheduled()) 11653126Sktlim@umich.edu tickEvent.squash(); 11661060SN/A} 11671060SN/A 11681060SN/Atemplate <class Impl> 11691060SN/Avoid 11701755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 11711060SN/A{ 11722325SN/A // Flush out any old data from the time buffers. 11732873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 11742307SN/A timeBuffer.advance(); 11752307SN/A fetchQueue.advance(); 11762307SN/A decodeQueue.advance(); 11772307SN/A renameQueue.advance(); 11782307SN/A iewQueue.advance(); 11792307SN/A } 11802307SN/A 11812325SN/A activityRec.reset(); 11822307SN/A 11834192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort()); 11841060SN/A 11852307SN/A fetch.takeOverFrom(); 11862307SN/A decode.takeOverFrom(); 11872307SN/A rename.takeOverFrom(); 11882307SN/A iew.takeOverFrom(); 11892307SN/A commit.takeOverFrom(); 11902307SN/A 11911060SN/A assert(!tickEvent.scheduled()); 11921060SN/A 11932325SN/A // @todo: Figure out how to properly select the tid to put onto 11942325SN/A // the active threads list. 11952307SN/A int tid = 0; 11962307SN/A 11975314Sstever@gmail.com std::list<unsigned>::iterator isActive = 11985314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 11992307SN/A 12002307SN/A if (isActive == activeThreads.end()) { 12012325SN/A //May Need to Re-code this if the delay variable is the delay 12022325SN/A //needed for thread to activate 12032733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 12042307SN/A tid); 12052307SN/A 12062307SN/A activeThreads.push_back(tid); 12072307SN/A } 12082307SN/A 12092325SN/A // Set all statuses to active, schedule the CPU's tick event. 12102307SN/A // @todo: Fix up statuses so this is handled properly 12112680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 12122680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 12132680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 12141681SN/A _status = Running; 12155606Snate@binkert.org schedule(tickEvent, nextCycle()); 12161681SN/A } 12171060SN/A } 12182307SN/A if (!tickEvent.scheduled()) 12195606Snate@binkert.org schedule(tickEvent, nextCycle()); 12201060SN/A} 12211060SN/A 12221060SN/Atemplate <class Impl> 12235595Sgblack@eecs.umich.eduTheISA::MiscReg 12245595Sgblack@eecs.umich.eduFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid) 12255595Sgblack@eecs.umich.edu{ 12265595Sgblack@eecs.umich.edu return this->regFile.readMiscRegNoEffect(misc_reg, tid); 12275595Sgblack@eecs.umich.edu} 12285595Sgblack@eecs.umich.edu 12295595Sgblack@eecs.umich.edutemplate <class Impl> 12305595Sgblack@eecs.umich.eduTheISA::MiscReg 12315595Sgblack@eecs.umich.eduFullO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) 12325595Sgblack@eecs.umich.edu{ 12335595Sgblack@eecs.umich.edu return this->regFile.readMiscReg(misc_reg, tid); 12345595Sgblack@eecs.umich.edu} 12355595Sgblack@eecs.umich.edu 12365595Sgblack@eecs.umich.edutemplate <class Impl> 12375595Sgblack@eecs.umich.eduvoid 12385595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 12395595Sgblack@eecs.umich.edu const TheISA::MiscReg &val, unsigned tid) 12405595Sgblack@eecs.umich.edu{ 12415595Sgblack@eecs.umich.edu this->regFile.setMiscRegNoEffect(misc_reg, val, tid); 12425595Sgblack@eecs.umich.edu} 12435595Sgblack@eecs.umich.edu 12445595Sgblack@eecs.umich.edutemplate <class Impl> 12455595Sgblack@eecs.umich.eduvoid 12465595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 12475595Sgblack@eecs.umich.edu const TheISA::MiscReg &val, unsigned tid) 12485595Sgblack@eecs.umich.edu{ 12495595Sgblack@eecs.umich.edu this->regFile.setMiscReg(misc_reg, val, tid); 12505595Sgblack@eecs.umich.edu} 12515595Sgblack@eecs.umich.edu 12525595Sgblack@eecs.umich.edutemplate <class Impl> 12531060SN/Auint64_t 12541755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 12551060SN/A{ 12561060SN/A return regFile.readIntReg(reg_idx); 12571060SN/A} 12581060SN/A 12591060SN/Atemplate <class Impl> 12602455SN/AFloatReg 12612455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 12621060SN/A{ 12632455SN/A return regFile.readFloatReg(reg_idx, width); 12641060SN/A} 12651060SN/A 12661060SN/Atemplate <class Impl> 12672455SN/AFloatReg 12682455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 12691060SN/A{ 12702455SN/A return regFile.readFloatReg(reg_idx); 12711060SN/A} 12721060SN/A 12731060SN/Atemplate <class Impl> 12742455SN/AFloatRegBits 12752455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 12761060SN/A{ 12772455SN/A return regFile.readFloatRegBits(reg_idx, width); 12782455SN/A} 12792455SN/A 12802455SN/Atemplate <class Impl> 12812455SN/AFloatRegBits 12822455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 12832455SN/A{ 12842455SN/A return regFile.readFloatRegBits(reg_idx); 12851060SN/A} 12861060SN/A 12871060SN/Atemplate <class Impl> 12881060SN/Avoid 12891755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 12901060SN/A{ 12911060SN/A regFile.setIntReg(reg_idx, val); 12921060SN/A} 12931060SN/A 12941060SN/Atemplate <class Impl> 12951060SN/Avoid 12962455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 12971060SN/A{ 12982455SN/A regFile.setFloatReg(reg_idx, val, width); 12991060SN/A} 13001060SN/A 13011060SN/Atemplate <class Impl> 13021060SN/Avoid 13032455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 13041060SN/A{ 13052455SN/A regFile.setFloatReg(reg_idx, val); 13061060SN/A} 13071060SN/A 13081060SN/Atemplate <class Impl> 13091060SN/Avoid 13102455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 13111060SN/A{ 13122455SN/A regFile.setFloatRegBits(reg_idx, val, width); 13132455SN/A} 13142455SN/A 13152455SN/Atemplate <class Impl> 13162455SN/Avoid 13172455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 13182455SN/A{ 13192455SN/A regFile.setFloatRegBits(reg_idx, val); 13201060SN/A} 13211060SN/A 13221060SN/Atemplate <class Impl> 13231060SN/Auint64_t 13242292SN/AFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 13251060SN/A{ 13262292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13272292SN/A 13282292SN/A return regFile.readIntReg(phys_reg); 13292292SN/A} 13302292SN/A 13312292SN/Atemplate <class Impl> 13322292SN/Afloat 13332292SN/AFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 13342292SN/A{ 13352307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 13362307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13372292SN/A 13382669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 13392292SN/A} 13402292SN/A 13412292SN/Atemplate <class Impl> 13422292SN/Adouble 13432292SN/AFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 13442292SN/A{ 13452307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 13462307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13472292SN/A 13482669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 13492292SN/A} 13502292SN/A 13512292SN/Atemplate <class Impl> 13522292SN/Auint64_t 13532292SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 13542292SN/A{ 13552307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 13562307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13572292SN/A 13582669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 13591060SN/A} 13601060SN/A 13611060SN/Atemplate <class Impl> 13621060SN/Avoid 13632292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 13641060SN/A{ 13652292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13662292SN/A 13672292SN/A regFile.setIntReg(phys_reg, val); 13681060SN/A} 13691060SN/A 13701060SN/Atemplate <class Impl> 13711060SN/Avoid 13722292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 13731060SN/A{ 13742918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 13752918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13762292SN/A 13772669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 13781060SN/A} 13791060SN/A 13801060SN/Atemplate <class Impl> 13811060SN/Avoid 13822292SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 13831060SN/A{ 13842918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 13852918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13862292SN/A 13872669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 13881060SN/A} 13891060SN/A 13901060SN/Atemplate <class Impl> 13911060SN/Avoid 13922292SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 13931060SN/A{ 13942918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 13952918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13961060SN/A 13972669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 13982292SN/A} 13992292SN/A 14002292SN/Atemplate <class Impl> 14012292SN/Auint64_t 14022292SN/AFullO3CPU<Impl>::readPC(unsigned tid) 14032292SN/A{ 14042292SN/A return commit.readPC(tid); 14051060SN/A} 14061060SN/A 14071060SN/Atemplate <class Impl> 14081060SN/Avoid 14092292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 14101060SN/A{ 14112292SN/A commit.setPC(new_PC, tid); 14122292SN/A} 14131060SN/A 14142292SN/Atemplate <class Impl> 14152292SN/Auint64_t 14164636Sgblack@eecs.umich.eduFullO3CPU<Impl>::readMicroPC(unsigned tid) 14174636Sgblack@eecs.umich.edu{ 14184636Sgblack@eecs.umich.edu return commit.readMicroPC(tid); 14194636Sgblack@eecs.umich.edu} 14204636Sgblack@eecs.umich.edu 14214636Sgblack@eecs.umich.edutemplate <class Impl> 14224636Sgblack@eecs.umich.eduvoid 14234636Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMicroPC(Addr new_PC,unsigned tid) 14244636Sgblack@eecs.umich.edu{ 14254636Sgblack@eecs.umich.edu commit.setMicroPC(new_PC, tid); 14264636Sgblack@eecs.umich.edu} 14274636Sgblack@eecs.umich.edu 14284636Sgblack@eecs.umich.edutemplate <class Impl> 14294636Sgblack@eecs.umich.eduuint64_t 14302292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 14312292SN/A{ 14322292SN/A return commit.readNextPC(tid); 14332292SN/A} 14341060SN/A 14352292SN/Atemplate <class Impl> 14362292SN/Avoid 14372292SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 14382292SN/A{ 14392292SN/A commit.setNextPC(val, tid); 14402292SN/A} 14411060SN/A 14422756Sksewell@umich.edutemplate <class Impl> 14432756Sksewell@umich.eduuint64_t 14442756Sksewell@umich.eduFullO3CPU<Impl>::readNextNPC(unsigned tid) 14452756Sksewell@umich.edu{ 14462756Sksewell@umich.edu return commit.readNextNPC(tid); 14472756Sksewell@umich.edu} 14482756Sksewell@umich.edu 14492756Sksewell@umich.edutemplate <class Impl> 14502756Sksewell@umich.eduvoid 14512935Sksewell@umich.eduFullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid) 14522756Sksewell@umich.edu{ 14532756Sksewell@umich.edu commit.setNextNPC(val, tid); 14542756Sksewell@umich.edu} 14552756Sksewell@umich.edu 14562292SN/Atemplate <class Impl> 14574636Sgblack@eecs.umich.eduuint64_t 14584636Sgblack@eecs.umich.eduFullO3CPU<Impl>::readNextMicroPC(unsigned tid) 14594636Sgblack@eecs.umich.edu{ 14604636Sgblack@eecs.umich.edu return commit.readNextMicroPC(tid); 14614636Sgblack@eecs.umich.edu} 14624636Sgblack@eecs.umich.edu 14634636Sgblack@eecs.umich.edutemplate <class Impl> 14644636Sgblack@eecs.umich.eduvoid 14654636Sgblack@eecs.umich.eduFullO3CPU<Impl>::setNextMicroPC(Addr new_PC,unsigned tid) 14664636Sgblack@eecs.umich.edu{ 14674636Sgblack@eecs.umich.edu commit.setNextMicroPC(new_PC, tid); 14684636Sgblack@eecs.umich.edu} 14694636Sgblack@eecs.umich.edu 14704636Sgblack@eecs.umich.edutemplate <class Impl> 14715595Sgblack@eecs.umich.eduvoid 14725595Sgblack@eecs.umich.eduFullO3CPU<Impl>::squashFromTC(unsigned tid) 14735595Sgblack@eecs.umich.edu{ 14745595Sgblack@eecs.umich.edu this->thread[tid]->inSyscall = true; 14755595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 14765595Sgblack@eecs.umich.edu} 14775595Sgblack@eecs.umich.edu 14785595Sgblack@eecs.umich.edutemplate <class Impl> 14792292SN/Atypename FullO3CPU<Impl>::ListIt 14802292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 14812292SN/A{ 14822292SN/A instList.push_back(inst); 14831060SN/A 14842292SN/A return --(instList.end()); 14852292SN/A} 14861060SN/A 14872292SN/Atemplate <class Impl> 14882292SN/Avoid 14892292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 14902292SN/A{ 14912292SN/A // Keep an instruction count. 14922292SN/A thread[tid]->numInst++; 14932292SN/A thread[tid]->numInsts++; 14942292SN/A committedInsts[tid]++; 14952292SN/A totalCommittedInsts++; 14962292SN/A 14972292SN/A // Check for instruction-count-based events. 14982292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 14992292SN/A} 15002292SN/A 15012292SN/Atemplate <class Impl> 15022292SN/Avoid 15032292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 15042292SN/A{ 15052292SN/A removeInstsThisCycle = true; 15062292SN/A 15072292SN/A removeList.push(inst->getInstListIt()); 15081060SN/A} 15091060SN/A 15101060SN/Atemplate <class Impl> 15111060SN/Avoid 15121755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 15131060SN/A{ 15142733Sktlim@umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 15152292SN/A "[sn:%lli]\n", 15162303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 15171060SN/A 15182292SN/A removeInstsThisCycle = true; 15191060SN/A 15201060SN/A // Remove the front instruction. 15212292SN/A removeList.push(inst->getInstListIt()); 15221060SN/A} 15231060SN/A 15241060SN/Atemplate <class Impl> 15251060SN/Avoid 15264632Sgblack@eecs.umich.eduFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 15271060SN/A{ 15282733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 15292292SN/A " list.\n", tid); 15301060SN/A 15312292SN/A ListIt end_it; 15321060SN/A 15332292SN/A bool rob_empty = false; 15342292SN/A 15352292SN/A if (instList.empty()) { 15362292SN/A return; 15372292SN/A } else if (rob.isEmpty(/*tid*/)) { 15382733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 15392292SN/A end_it = instList.begin(); 15402292SN/A rob_empty = true; 15412292SN/A } else { 15422292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 15432733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 15442292SN/A } 15452292SN/A 15462292SN/A removeInstsThisCycle = true; 15472292SN/A 15482292SN/A ListIt inst_it = instList.end(); 15492292SN/A 15502292SN/A inst_it--; 15512292SN/A 15522292SN/A // Walk through the instruction list, removing any instructions 15532292SN/A // that were inserted after the given instruction iterator, end_it. 15542292SN/A while (inst_it != end_it) { 15552292SN/A assert(!instList.empty()); 15562292SN/A 15572292SN/A squashInstIt(inst_it, tid); 15582292SN/A 15592292SN/A inst_it--; 15602292SN/A } 15612292SN/A 15622292SN/A // If the ROB was empty, then we actually need to remove the first 15632292SN/A // instruction as well. 15642292SN/A if (rob_empty) { 15652292SN/A squashInstIt(inst_it, tid); 15662292SN/A } 15671060SN/A} 15681060SN/A 15691060SN/Atemplate <class Impl> 15701060SN/Avoid 15712292SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 15722292SN/A unsigned tid) 15731062SN/A{ 15742292SN/A assert(!instList.empty()); 15752292SN/A 15762292SN/A removeInstsThisCycle = true; 15772292SN/A 15782292SN/A ListIt inst_iter = instList.end(); 15792292SN/A 15802292SN/A inst_iter--; 15812292SN/A 15822733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 15832292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 15842292SN/A tid, seq_num, (*inst_iter)->seqNum); 15851062SN/A 15862292SN/A while ((*inst_iter)->seqNum > seq_num) { 15871062SN/A 15882292SN/A bool break_loop = (inst_iter == instList.begin()); 15891062SN/A 15902292SN/A squashInstIt(inst_iter, tid); 15911062SN/A 15922292SN/A inst_iter--; 15931062SN/A 15942292SN/A if (break_loop) 15952292SN/A break; 15962292SN/A } 15972292SN/A} 15982292SN/A 15992292SN/Atemplate <class Impl> 16002292SN/Ainline void 16012292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 16022292SN/A{ 16032292SN/A if ((*instIt)->threadNumber == tid) { 16042733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 16052292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 16062292SN/A (*instIt)->threadNumber, 16072292SN/A (*instIt)->seqNum, 16082292SN/A (*instIt)->readPC()); 16091062SN/A 16101062SN/A // Mark it as squashed. 16112292SN/A (*instIt)->setSquashed(); 16122292SN/A 16132325SN/A // @todo: Formulate a consistent method for deleting 16142325SN/A // instructions from the instruction list 16152292SN/A // Remove the instruction from the list. 16162292SN/A removeList.push(instIt); 16172292SN/A } 16182292SN/A} 16192292SN/A 16202292SN/Atemplate <class Impl> 16212292SN/Avoid 16222292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 16232292SN/A{ 16242292SN/A while (!removeList.empty()) { 16252733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 16262292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 16272292SN/A (*removeList.front())->threadNumber, 16282292SN/A (*removeList.front())->seqNum, 16292292SN/A (*removeList.front())->readPC()); 16302292SN/A 16312292SN/A instList.erase(removeList.front()); 16322292SN/A 16332292SN/A removeList.pop(); 16341062SN/A } 16351062SN/A 16362292SN/A removeInstsThisCycle = false; 16371062SN/A} 16382325SN/A/* 16391062SN/Atemplate <class Impl> 16401062SN/Avoid 16411755SN/AFullO3CPU<Impl>::removeAllInsts() 16421060SN/A{ 16431060SN/A instList.clear(); 16441060SN/A} 16452325SN/A*/ 16461060SN/Atemplate <class Impl> 16471060SN/Avoid 16481755SN/AFullO3CPU<Impl>::dumpInsts() 16491060SN/A{ 16501060SN/A int num = 0; 16511060SN/A 16522292SN/A ListIt inst_list_it = instList.begin(); 16532292SN/A 16542292SN/A cprintf("Dumping Instruction List\n"); 16552292SN/A 16562292SN/A while (inst_list_it != instList.end()) { 16572292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 16582292SN/A "Squashed:%i\n\n", 16592292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 16602292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 16612292SN/A (*inst_list_it)->isSquashed()); 16621060SN/A inst_list_it++; 16631060SN/A ++num; 16641060SN/A } 16651060SN/A} 16662325SN/A/* 16671060SN/Atemplate <class Impl> 16681060SN/Avoid 16691755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 16701060SN/A{ 16711060SN/A iew.wakeDependents(inst); 16721060SN/A} 16732325SN/A*/ 16742292SN/Atemplate <class Impl> 16752292SN/Avoid 16762292SN/AFullO3CPU<Impl>::wakeCPU() 16772292SN/A{ 16782325SN/A if (activityRec.active() || tickEvent.scheduled()) { 16792325SN/A DPRINTF(Activity, "CPU already running.\n"); 16802292SN/A return; 16812292SN/A } 16822292SN/A 16832325SN/A DPRINTF(Activity, "Waking up CPU\n"); 16842325SN/A 16855099Ssaidi@eecs.umich.edu idleCycles += tickToCycles((curTick - 1) - lastRunningCycle); 16865099Ssaidi@eecs.umich.edu numCycles += tickToCycles((curTick - 1) - lastRunningCycle); 16872292SN/A 16885606Snate@binkert.org schedule(tickEvent, nextCycle()); 16892292SN/A} 16902292SN/A 16912292SN/Atemplate <class Impl> 16922292SN/Aint 16932292SN/AFullO3CPU<Impl>::getFreeTid() 16942292SN/A{ 16952292SN/A for (int i=0; i < numThreads; i++) { 16962292SN/A if (!tids[i]) { 16972292SN/A tids[i] = true; 16982292SN/A return i; 16992292SN/A } 17002292SN/A } 17012292SN/A 17022292SN/A return -1; 17032292SN/A} 17042292SN/A 17052292SN/Atemplate <class Impl> 17062292SN/Avoid 17072292SN/AFullO3CPU<Impl>::doContextSwitch() 17082292SN/A{ 17092292SN/A if (contextSwitch) { 17102292SN/A 17112292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 17122292SN/A 17132292SN/A for (int tid=0; tid < cpuWaitList.size(); tid++) { 17142292SN/A activateWhenReady(tid); 17152292SN/A } 17162292SN/A 17172292SN/A if (cpuWaitList.size() == 0) 17182292SN/A contextSwitch = true; 17192292SN/A } 17202292SN/A} 17212292SN/A 17222292SN/Atemplate <class Impl> 17232292SN/Avoid 17242292SN/AFullO3CPU<Impl>::updateThreadPriority() 17252292SN/A{ 17262292SN/A if (activeThreads.size() > 1) 17272292SN/A { 17282292SN/A //DEFAULT TO ROUND ROBIN SCHEME 17292292SN/A //e.g. Move highest priority to end of thread list 17305314Sstever@gmail.com std::list<unsigned>::iterator list_begin = activeThreads.begin(); 17315314Sstever@gmail.com std::list<unsigned>::iterator list_end = activeThreads.end(); 17322292SN/A 17332292SN/A unsigned high_thread = *list_begin; 17342292SN/A 17352292SN/A activeThreads.erase(list_begin); 17362292SN/A 17372292SN/A activeThreads.push_back(high_thread); 17382292SN/A } 17392292SN/A} 17401060SN/A 17411755SN/A// Forward declaration of FullO3CPU. 17422818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1743