cpu.cc revision 5702
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 336658Snate@binkert.org#include "config/use_checker.hh" 342733Sktlim@umich.edu 354762Snate@binkert.org#include "cpu/activity.hh" 364762Snate@binkert.org#include "cpu/simple_thread.hh" 374762Snate@binkert.org#include "cpu/thread_context.hh" 384762Snate@binkert.org#include "cpu/o3/isa_specific.hh" 394762Snate@binkert.org#include "cpu/o3/cpu.hh" 405595Sgblack@eecs.umich.edu#include "cpu/o3/thread_context.hh" 414762Snate@binkert.org#include "enums/MemoryMode.hh" 424762Snate@binkert.org#include "sim/core.hh" 434762Snate@binkert.org#include "sim/stat_control.hh" 444762Snate@binkert.org 451858SN/A#if FULL_SYSTEM 462356SN/A#include "cpu/quiesce_event.hh" 471060SN/A#include "sim/system.hh" 481060SN/A#else 491060SN/A#include "sim/process.hh" 501060SN/A#endif 511060SN/A 522794Sktlim@umich.edu#if USE_CHECKER 532794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 542794Sktlim@umich.edu#endif 552794Sktlim@umich.edu 565702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 575702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 585702Ssaidi@eecs.umich.edu#endif 595702Ssaidi@eecs.umich.edu 605529Snate@binkert.orgclass BaseCPUParams; 615529Snate@binkert.org 622669Sktlim@umich.eduusing namespace TheISA; 636221Snate@binkert.org 641060SN/ABaseO3CPU::BaseO3CPU(BaseCPUParams *params) 655529Snate@binkert.org : BaseCPU(params), cpu_id(0) 665712Shsul@eecs.umich.edu{ 671060SN/A} 681060SN/A 691060SN/Avoid 702292SN/ABaseO3CPU::regStats() 712733Sktlim@umich.edu{ 722292SN/A BaseCPU::regStats(); 732292SN/A} 742292SN/A 752292SN/Atemplate <class Impl> 761060SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 771755SN/A : Event(CPU_Tick_Pri), cpu(c) 785606Snate@binkert.org{ 791060SN/A} 801060SN/A 811060SN/Atemplate <class Impl> 821060SN/Avoid 831060SN/AFullO3CPU<Impl>::TickEvent::process() 841755SN/A{ 851060SN/A cpu->tick(); 861060SN/A} 871060SN/A 881060SN/Atemplate <class Impl> 891060SN/Aconst char * 901060SN/AFullO3CPU<Impl>::TickEvent::description() const 915336Shines@cs.fsu.edu{ 921060SN/A return "FullO3CPU tick"; 934873Sstever@eecs.umich.edu} 941060SN/A 951060SN/Atemplate <class Impl> 961060SN/AFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 972829Sksewell@umich.edu : Event(CPU_Switch_Pri) 985606Snate@binkert.org{ 992829Sksewell@umich.edu} 1002829Sksewell@umich.edu 1012829Sksewell@umich.edutemplate <class Impl> 1022829Sksewell@umich.eduvoid 1032829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 1042829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1052829Sksewell@umich.edu{ 1062829Sksewell@umich.edu tid = thread_num; 1072829Sksewell@umich.edu cpu = thread_cpu; 1082829Sksewell@umich.edu} 1092829Sksewell@umich.edu 1102829Sksewell@umich.edutemplate <class Impl> 1112829Sksewell@umich.eduvoid 1122829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1132829Sksewell@umich.edu{ 1142829Sksewell@umich.edu cpu->activateThread(tid); 1152829Sksewell@umich.edu} 1162829Sksewell@umich.edu 1172829Sksewell@umich.edutemplate <class Impl> 1182829Sksewell@umich.educonst char * 1192829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1205336Shines@cs.fsu.edu{ 1212829Sksewell@umich.edu return "FullO3CPU \"Activate Thread\""; 1224873Sstever@eecs.umich.edu} 1232829Sksewell@umich.edu 1242829Sksewell@umich.edutemplate <class Impl> 1252829Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1262875Sksewell@umich.edu : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1275606Snate@binkert.org{ 1282875Sksewell@umich.edu} 1292875Sksewell@umich.edu 1302875Sksewell@umich.edutemplate <class Impl> 1312875Sksewell@umich.eduvoid 1322875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1332875Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1343859Sbinkertn@umich.edu{ 1352875Sksewell@umich.edu tid = thread_num; 1362875Sksewell@umich.edu cpu = thread_cpu; 1372875Sksewell@umich.edu remove = false; 1383859Sbinkertn@umich.edu} 1392875Sksewell@umich.edu 1402875Sksewell@umich.edutemplate <class Impl> 1412875Sksewell@umich.eduvoid 1422875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1432875Sksewell@umich.edu{ 1442875Sksewell@umich.edu cpu->deactivateThread(tid); 1452875Sksewell@umich.edu if (remove) 1463221Sktlim@umich.edu cpu->removeThread(tid); 1473221Sktlim@umich.edu} 1482875Sksewell@umich.edu 1492875Sksewell@umich.edutemplate <class Impl> 1502875Sksewell@umich.educonst char * 1512875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 1525336Shines@cs.fsu.edu{ 1532875Sksewell@umich.edu return "FullO3CPU \"Deallocate Context\""; 1544873Sstever@eecs.umich.edu} 1552875Sksewell@umich.edu 1562875Sksewell@umich.edutemplate <class Impl> 1572875Sksewell@umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 1585595Sgblack@eecs.umich.edu : BaseO3CPU(params), 1592733Sktlim@umich.edu itb(params->itb), 1603781Sgblack@eecs.umich.edu dtb(params->dtb), 1613781Sgblack@eecs.umich.edu tickEvent(this), 1621060SN/A removeInstsThisCycle(false), 1635737Scws3k@cs.virginia.edu fetch(this, params), 1645737Scws3k@cs.virginia.edu decode(this, params), 1655737Scws3k@cs.virginia.edu rename(this, params), 1662292SN/A iew(this, params), 1675595Sgblack@eecs.umich.edu commit(this, params), 1685595Sgblack@eecs.umich.edu 1695595Sgblack@eecs.umich.edu regFile(this, params->numPhysIntRegs, 1705595Sgblack@eecs.umich.edu params->numPhysFloatRegs), 1715595Sgblack@eecs.umich.edu 1721060SN/A freeList(params->numThreads, 1735595Sgblack@eecs.umich.edu TheISA::NumIntRegs, params->numPhysIntRegs, 1744329Sktlim@umich.edu TheISA::NumFloatRegs, params->numPhysFloatRegs), 1751060SN/A 1765529Snate@binkert.org rob(this, 1772292SN/A params->numROBEntries, params->squashWidth, 1782292SN/A params->smtROBPolicy, params->smtROBThreshold, 1791060SN/A params->numThreads), 1805595Sgblack@eecs.umich.edu 1814329Sktlim@umich.edu scoreboard(params->numThreads, 1822292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1835529Snate@binkert.org TheISA::NumFloatRegs, params->numPhysFloatRegs, 1841060SN/A TheISA::NumMiscRegs * number_of_threads, 1855529Snate@binkert.org TheISA::ZeroReg), 1862292SN/A 1872292SN/A timeBuffer(params->backComSize, params->forwardComSize), 1886221Snate@binkert.org fetchQueue(params->backComSize, params->forwardComSize), 1892292SN/A decodeQueue(params->backComSize, params->forwardComSize), 1901060SN/A renameQueue(params->backComSize, params->forwardComSize), 1912873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1922873Sktlim@umich.edu activityRec(NumStages, 1932873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1942873Sktlim@umich.edu params->activity), 1952873Sktlim@umich.edu 1965804Snate@binkert.org globalSeqNum(1), 1972873Sktlim@umich.edu#if FULL_SYSTEM 1982873Sktlim@umich.edu system(params->system), 1991060SN/A physmem(system->physmem), 2001060SN/A#endif // FULL_SYSTEM 2011858SN/A drainCount(0), 2022292SN/A deferRegistration(params->defer_registration), 2031060SN/A numThreads(number_of_threads) 2042843Sktlim@umich.edu{ 2056221Snate@binkert.org if (!deferRegistration) { 2061060SN/A _status = Running; 2073221Sktlim@umich.edu } else { 2083221Sktlim@umich.edu _status = Idle; 2093221Sktlim@umich.edu } 2103221Sktlim@umich.edu 2113221Sktlim@umich.edu#if USE_CHECKER 2121681SN/A if (params->checker) { 2134598Sbinkertn@umich.edu BaseCPU *temp_checker = params->checker; 2142794Sktlim@umich.edu checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2152316SN/A#if FULL_SYSTEM 2162316SN/A checker->setSystem(params->system); 2172316SN/A#endif 2182316SN/A } else { 2192316SN/A checker = NULL; 2204598Sbinkertn@umich.edu } 2214598Sbinkertn@umich.edu#endif // USE_CHECKER 2224598Sbinkertn@umich.edu 2232794Sktlim@umich.edu#if !FULL_SYSTEM 2242316SN/A thread.resize(number_of_threads); 2251858SN/A tids.resize(number_of_threads); 2266221Snate@binkert.org#endif 2276221Snate@binkert.org 2281681SN/A // The stages also need their CPU pointer setup. However this 2291681SN/A // must be done at the upper level CPU because they have pointers 2302325SN/A // to the upper level CPU, and not this FullO3CPU. 2312325SN/A 2322325SN/A // Set up Pointers to the activeThreads list for each stage 2331060SN/A fetch.setActiveThreads(&activeThreads); 2342292SN/A decode.setActiveThreads(&activeThreads); 2352292SN/A rename.setActiveThreads(&activeThreads); 2362292SN/A iew.setActiveThreads(&activeThreads); 2372292SN/A commit.setActiveThreads(&activeThreads); 2382292SN/A 2392292SN/A // Give each of the stages the time buffer they will use. 2401060SN/A fetch.setTimeBuffer(&timeBuffer); 2411060SN/A decode.setTimeBuffer(&timeBuffer); 2421060SN/A rename.setTimeBuffer(&timeBuffer); 2431060SN/A iew.setTimeBuffer(&timeBuffer); 2441060SN/A commit.setTimeBuffer(&timeBuffer); 2451060SN/A 2461060SN/A // Also setup each of the stages' queues. 2471060SN/A fetch.setFetchQueue(&fetchQueue); 2481060SN/A decode.setFetchQueue(&fetchQueue); 2491060SN/A commit.setFetchQueue(&fetchQueue); 2501060SN/A decode.setDecodeQueue(&decodeQueue); 2512292SN/A rename.setDecodeQueue(&decodeQueue); 2521060SN/A rename.setRenameQueue(&renameQueue); 2531060SN/A iew.setRenameQueue(&renameQueue); 2541060SN/A iew.setIEWQueue(&iewQueue); 2551060SN/A commit.setIEWQueue(&iewQueue); 2561060SN/A commit.setRenameQueue(&renameQueue); 2571060SN/A 2581060SN/A commit.setIEWStage(&iew); 2591060SN/A rename.setIEWStage(&iew); 2602292SN/A rename.setCommitStage(&commit); 2612292SN/A 2622292SN/A#if !FULL_SYSTEM 2632292SN/A int active_threads = params->workload.size(); 2642292SN/A 2656221Snate@binkert.org if (active_threads > Impl::MaxThreads) { 2662831Sksewell@umich.edu panic("Workload Size too large. Increase the 'MaxThreads'" 2672831Sksewell@umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2682831Sksewell@umich.edu "edit your workload size."); 2692831Sksewell@umich.edu } 2702831Sksewell@umich.edu#else 2712831Sksewell@umich.edu int active_threads = 1; 2722292SN/A#endif 2736221Snate@binkert.org 2742292SN/A //Make Sure That this a Valid Architeture 2752292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2762316SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2772292SN/A 2782292SN/A rename.setScoreboard(&scoreboard); 2792292SN/A iew.setScoreboard(&scoreboard); 2802292SN/A 2812292SN/A // Setup the rename map for whichever stages need it. 2822292SN/A PhysRegIndex lreg_idx = 0; 2831060SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2842292SN/A 2852292SN/A for (int tid=0; tid < numThreads; tid++) { 2861060SN/A bool bindRegs = (tid <= active_threads - 1); 2876221Snate@binkert.org 2882307SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2892292SN/A params->numPhysIntRegs, 2902292SN/A lreg_idx, //Index for Logical. Regs 2912292SN/A 2922325SN/A TheISA::NumFloatRegs, 2932292SN/A params->numPhysFloatRegs, 2942292SN/A freg_idx, //Index for Float Regs 2952292SN/A 2962325SN/A TheISA::NumMiscRegs, 2972292SN/A 2982292SN/A TheISA::ZeroReg, 2992292SN/A TheISA::ZeroReg, 3002292SN/A 3012292SN/A tid, 3022292SN/A false); 3032292SN/A 3042292SN/A renameMap[tid].init(TheISA::NumIntRegs, 3052292SN/A params->numPhysIntRegs, 3062292SN/A lreg_idx, //Index for Logical. Regs 3072292SN/A 3082325SN/A TheISA::NumFloatRegs, 3092292SN/A params->numPhysFloatRegs, 3102292SN/A freg_idx, //Index for Float Regs 3112292SN/A 3122325SN/A TheISA::NumMiscRegs, 3132292SN/A 3142292SN/A TheISA::ZeroReg, 3152292SN/A TheISA::ZeroReg, 3162292SN/A 3172292SN/A tid, 3182292SN/A bindRegs); 3192292SN/A 3202292SN/A activateThreadEvent[tid].init(tid, this); 3213221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3223221Sktlim@umich.edu } 3233221Sktlim@umich.edu 3242292SN/A rename.setRenameMap(renameMap); 3252292SN/A commit.setRenameMap(commitRenameMap); 3262292SN/A 3272292SN/A // Give renameMap & rename stage access to the freeList; 3282292SN/A for (int i=0; i < numThreads; i++) { 3292292SN/A renameMap[i].setFreeList(&freeList); 3306221Snate@binkert.org } 3316221Snate@binkert.org rename.setFreeList(&freeList); 3321060SN/A 3332292SN/A // Setup the ROB for whichever stages need it. 3341060SN/A commit.setROB(&rob); 3351060SN/A 3362292SN/A lastRunningCycle = curTick; 3377823Ssteve.reinhardt@amd.com 3382292SN/A lastActivatedCycle = -1; 3392829Sksewell@umich.edu 3406221Snate@binkert.org // Give renameMap & rename stage access to the freeList; 3413093Sksewell@umich.edu //for (int i=0; i < numThreads; i++) { 3426221Snate@binkert.org //globalSeqNum[i] = 1; 3436221Snate@binkert.org //} 3446221Snate@binkert.org 3453093Sksewell@umich.edu contextSwitch = false; 3462292SN/A DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3475595Sgblack@eecs.umich.edu 3485595Sgblack@eecs.umich.edu // Setup any thread state. 3495595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 3505595Sgblack@eecs.umich.edu 3515595Sgblack@eecs.umich.edu for (int i = 0; i < this->numThreads; ++i) { 3526221Snate@binkert.org#if FULL_SYSTEM 3535595Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 3545595Sgblack@eecs.umich.edu assert(this->numThreads == 1); 3555595Sgblack@eecs.umich.edu this->thread[i] = new Thread(this, 0); 3566221Snate@binkert.org this->thread[i]->setStatus(ThreadContext::Suspended); 3575595Sgblack@eecs.umich.edu#else 3586221Snate@binkert.org if (i < params->workload.size()) { 3595595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 3606221Snate@binkert.org i, this->thread[i]); 3616221Snate@binkert.org this->thread[i] = new typename FullO3CPU<Impl>::Thread( 3625595Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3636331Sgblack@eecs.umich.edu i, params->workload[i], i); 3645595Sgblack@eecs.umich.edu 3656221Snate@binkert.org this->thread[i]->setStatus(ThreadContext::Suspended); 3666221Snate@binkert.org 3675595Sgblack@eecs.umich.edu //usedTids[i] = true; 3685595Sgblack@eecs.umich.edu //threadMap[i] = i; 3695595Sgblack@eecs.umich.edu } else { 3705595Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 3715595Sgblack@eecs.umich.edu //when scheduling threads to CPU 3726221Snate@binkert.org Process* dummy_proc = NULL; 3735595Sgblack@eecs.umich.edu 3746331Sgblack@eecs.umich.edu this->thread[i] = new typename FullO3CPU<Impl>::Thread( 3756221Snate@binkert.org (typename Impl::O3CPU *)(this), 3765595Sgblack@eecs.umich.edu i, dummy_proc, i); 3775595Sgblack@eecs.umich.edu //usedTids[i] = false; 3785595Sgblack@eecs.umich.edu } 3795595Sgblack@eecs.umich.edu#endif // !FULL_SYSTEM 3805595Sgblack@eecs.umich.edu 3815595Sgblack@eecs.umich.edu ThreadContext *tc; 3825595Sgblack@eecs.umich.edu 3835595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 3845595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 3855595Sgblack@eecs.umich.edu 3865595Sgblack@eecs.umich.edu tc = o3_tc; 3875595Sgblack@eecs.umich.edu 3885595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 3895595Sgblack@eecs.umich.edu // CheckerThreadContext. 3905595Sgblack@eecs.umich.edu#if USE_CHECKER 3915595Sgblack@eecs.umich.edu if (params->checker) { 3925595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 3935595Sgblack@eecs.umich.edu o3_tc, this->checker); 3945595Sgblack@eecs.umich.edu } 3955595Sgblack@eecs.umich.edu#endif 3965595Sgblack@eecs.umich.edu 3976221Snate@binkert.org o3_tc->cpu = (typename Impl::O3CPU *)(this); 3985595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 3995595Sgblack@eecs.umich.edu o3_tc->thread = this->thread[i]; 4005595Sgblack@eecs.umich.edu 4016221Snate@binkert.org#if FULL_SYSTEM 4025595Sgblack@eecs.umich.edu // Setup quiesce event. 4035595Sgblack@eecs.umich.edu this->thread[i]->quiesceEvent = new EndQuiesceEvent(tc); 4046221Snate@binkert.org#endif 4055595Sgblack@eecs.umich.edu // Give the thread the TC. 4065595Sgblack@eecs.umich.edu this->thread[i]->tc = tc; 4075595Sgblack@eecs.umich.edu this->thread[i]->setCpuId(params->cpu_id); 4085595Sgblack@eecs.umich.edu 4095595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4106221Snate@binkert.org this->threadContexts.push_back(tc); 4116221Snate@binkert.org } 4125595Sgblack@eecs.umich.edu 4135595Sgblack@eecs.umich.edu for (int i=0; i < this->numThreads; i++) { 4145595Sgblack@eecs.umich.edu this->thread[i]->setFuncExeInst(0); 4151060SN/A } 4161060SN/A 4171060SN/A lockAddr = 0; 4181755SN/A lockFlag = false; 4191060SN/A} 4201060SN/A 4211060SN/A#if !FULL_SYSTEM 4221060SN/A 4231060SN/Atemplate <class Impl> 4245595Sgblack@eecs.umich.eduTheISA::IntReg 4251062SN/AFullO3CPU<Impl>::getSyscallArg(int i, int tid) 4262733Sktlim@umich.edu{ 4272292SN/A assert(i < TheISA::NumArgumentRegs); 4282733Sktlim@umich.edu TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), 4292292SN/A TheISA::ArgumentReg[i]); 4302292SN/A TheISA::IntReg val = this->readArchIntReg(idx, tid); 4312292SN/A#if THE_ISA == SPARC_ISA 4322292SN/A if (bits(this->readMiscRegNoEffect(SparcISA::MISCREG_PSTATE, tid), 3, 3)) 4332292SN/A val = bits(val, 31, 0); 4342292SN/A#endif 4352292SN/A return val; 4362292SN/A} 4372292SN/A 4382292SN/Atemplate <class Impl> 4392292SN/Avoid 4402292SN/AFullO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid) 4412292SN/A{ 4422292SN/A assert(i < TheISA::NumArgumentRegs); 4432292SN/A TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid), 4442292SN/A TheISA::ArgumentReg[i]); 4452292SN/A this->setArchIntReg(idx, val, tid); 4462292SN/A} 4472292SN/A#endif 4482292SN/A 4492292SN/Atemplate <class Impl> 4502292SN/AFullO3CPU<Impl>::~FullO3CPU() 4512292SN/A{ 4522292SN/A} 4532292SN/A 4542292SN/Atemplate <class Impl> 4552292SN/Avoid 4562292SN/AFullO3CPU<Impl>::regStats() 4572292SN/A{ 4584392Sktlim@umich.edu BaseO3CPU::regStats(); 4592292SN/A 4602292SN/A // Register any of the O3CPU's stats here. 4612292SN/A timesIdled 4622292SN/A .name(name() + ".timesIdled") 4632292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4644392Sktlim@umich.edu " unscheduled itself") 4652292SN/A .prereq(timesIdled); 4662292SN/A 4672292SN/A idleCycles 4682292SN/A .name(name() + ".idleCycles") 4692292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4704392Sktlim@umich.edu "to idling") 4712292SN/A .prereq(idleCycles); 4722292SN/A 4732292SN/A // Number of Instructions simulated 4742292SN/A // -------------------------------- 4752292SN/A // Should probably be in Base CPU but need templated 4764392Sktlim@umich.edu // MaxThreads so put in here instead 4772292SN/A committedInsts 4785595Sgblack@eecs.umich.edu .init(numThreads) 4795595Sgblack@eecs.umich.edu .name(name() + ".committedInsts") 4805595Sgblack@eecs.umich.edu .desc("Number of Instructions Simulated"); 4815595Sgblack@eecs.umich.edu 4825595Sgblack@eecs.umich.edu totalCommittedInsts 4831062SN/A .name(name() + ".committedInsts_total") 4841062SN/A .desc("Number of Instructions Simulated"); 4851062SN/A 4862871Sktlim@umich.edu cpi 4872871Sktlim@umich.edu .name(name() + ".cpi") 4882871Sktlim@umich.edu .desc("CPI: Cycles Per Instruction") 4892871Sktlim@umich.edu .precision(6); 4902871Sktlim@umich.edu cpi = numCycles / committedInsts; 4912871Sktlim@umich.edu 4922871Sktlim@umich.edu totalCpi 4932871Sktlim@umich.edu .name(name() + ".cpi_total") 4942871Sktlim@umich.edu .desc("CPI: Total CPI of All Threads") 4952871Sktlim@umich.edu .precision(6); 4962871Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 4972871Sktlim@umich.edu 4981062SN/A ipc 4991755SN/A .name(name() + ".ipc") 5001060SN/A .desc("IPC: Instructions Per Cycle") 5012733Sktlim@umich.edu .precision(6); 5021060SN/A ipc = committedInsts / numCycles; 5032292SN/A 5042292SN/A totalIpc 5052325SN/A .name(name() + ".ipc_total") 5062292SN/A .desc("IPC: Total IPC of All Threads") 5072292SN/A .precision(6); 5081060SN/A totalIpc = totalCommittedInsts / numCycles; 5091060SN/A 5101060SN/A this->fetch.regStats(); 5111060SN/A this->decode.regStats(); 5121060SN/A this->rename.regStats(); 5131060SN/A this->iew.regStats(); 5141060SN/A this->commit.regStats(); 5151060SN/A} 5161060SN/A 5171060SN/Atemplate <class Impl> 5182292SN/APort * 5192292SN/AFullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 5202292SN/A{ 5212292SN/A if (if_name == "dcache_port") 5222292SN/A return iew.getDcachePort(); 5231060SN/A else if (if_name == "icache_port") 5241060SN/A return fetch.getIcachePort(); 5251060SN/A else 5261060SN/A panic("No Such Port\n"); 5271060SN/A} 5281060SN/A 5291060SN/Atemplate <class Impl> 5302325SN/Avoid 5312292SN/AFullO3CPU<Impl>::tick() 5322292SN/A{ 5332292SN/A DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5342292SN/A 5352292SN/A ++numCycles; 5362325SN/A 5372867Sktlim@umich.edu// activity = false; 5382905Sktlim@umich.edu 5393226Sktlim@umich.edu //Tick each of the stages 5402325SN/A fetch.tick(); 5417823Ssteve.reinhardt@amd.com 5423221Sktlim@umich.edu decode.tick(); 5433226Sktlim@umich.edu 5447823Ssteve.reinhardt@amd.com rename.tick(); 5452325SN/A 5462325SN/A iew.tick(); 5477823Ssteve.reinhardt@amd.com 5483226Sktlim@umich.edu commit.tick(); 5492325SN/A 5502292SN/A#if !FULL_SYSTEM 5512292SN/A doContextSwitch(); 5522292SN/A#endif 5532292SN/A 5542292SN/A // Now advance the time buffers 5551060SN/A timeBuffer.advance(); 5561060SN/A 5571060SN/A fetchQueue.advance(); 5581060SN/A decodeQueue.advance(); 5591755SN/A renameQueue.advance(); 5601060SN/A iewQueue.advance(); 5615714Shsul@eecs.umich.edu 5621060SN/A activityRec.advance(); 5632292SN/A 5642292SN/A if (removeInstsThisCycle) { 5656221Snate@binkert.org cleanUpRemovedInsts(); 5666221Snate@binkert.org } 5672292SN/A 5686034Ssteve.reinhardt@amd.com if (!tickEvent.scheduled()) { 5696221Snate@binkert.org if (_status == SwitchedOut || 5702680Sktlim@umich.edu getState() == SimObject::Drained) { 5716034Ssteve.reinhardt@amd.com DPRINTF(O3CPU, "Switched out!\n"); 5726034Ssteve.reinhardt@amd.com // increment stat 5731681SN/A lastRunningCycle = curTick; 5742292SN/A } else if (!activityRec.active() || _status == Idle) { 5752292SN/A DPRINTF(O3CPU, "Idle!\n"); 5766221Snate@binkert.org lastRunningCycle = curTick; 5776221Snate@binkert.org timesIdled++; 5782292SN/A } else { 5792316SN/A schedule(tickEvent, nextCycle(curTick + ticks(1))); 5802292SN/A DPRINTF(O3CPU, "Scheduling next tick!\n"); 5812292SN/A } 5822292SN/A } 5832292SN/A 5842292SN/A#if !FULL_SYSTEM 5852292SN/A updateThreadPriority(); 5862292SN/A#endif 5872292SN/A} 5882292SN/A 5892292SN/Atemplate <class Impl> 5906221Snate@binkert.orgvoid 5912875Sksewell@umich.eduFullO3CPU<Impl>::init() 5926221Snate@binkert.org{ 5935314Sstever@gmail.com if (!deferRegistration) { 5942875Sksewell@umich.edu registerThreadContexts(); 5953226Sktlim@umich.edu } 5963226Sktlim@umich.edu 5972875Sksewell@umich.edu // Set inSyscall so that the CPU doesn't squash when initially 5982875Sksewell@umich.edu // setting up registers. 5992875Sksewell@umich.edu for (int i = 0; i < number_of_threads; ++i) 6002875Sksewell@umich.edu thread[i]->inSyscall = true; 6012875Sksewell@umich.edu 6022875Sksewell@umich.edu for (int tid=0; tid < number_of_threads; tid++) { 6032875Sksewell@umich.edu#if FULL_SYSTEM 6042875Sksewell@umich.edu ThreadContext *src_tc = threadContexts[tid]; 6052875Sksewell@umich.edu#else 6062875Sksewell@umich.edu ThreadContext *src_tc = thread[tid]->getTC(); 6076221Snate@binkert.org#endif 6082875Sksewell@umich.edu // Threads start in the Suspended State 6092875Sksewell@umich.edu if (src_tc->status() != ThreadContext::Suspended) { 6106221Snate@binkert.org continue; 6115314Sstever@gmail.com } 6122875Sksewell@umich.edu 6133226Sktlim@umich.edu#if FULL_SYSTEM 6143226Sktlim@umich.edu TheISA::initCPU(src_tc, src_tc->readCpuId()); 6152875Sksewell@umich.edu#endif 6162875Sksewell@umich.edu } 6172875Sksewell@umich.edu 6182875Sksewell@umich.edu // Clear inSyscall. 6192875Sksewell@umich.edu for (int i = 0; i < number_of_threads; ++i) 6202875Sksewell@umich.edu thread[i]->inSyscall = false; 6212875Sksewell@umich.edu 6222875Sksewell@umich.edu // Initialize stages. 6236221Snate@binkert.org fetch.initStage(); 6246221Snate@binkert.org iew.initStage(); 6256221Snate@binkert.org rename.initStage(); 6266221Snate@binkert.org commit.initStage(); 6276221Snate@binkert.org 6286221Snate@binkert.org commit.setThreads(thread); 6296221Snate@binkert.org} 6306221Snate@binkert.org 6316221Snate@binkert.orgtemplate <class Impl> 6326221Snate@binkert.orgvoid 6336221Snate@binkert.orgFullO3CPU<Impl>::activateThread(unsigned tid) 6346221Snate@binkert.org{ 6356221Snate@binkert.org std::list<unsigned>::iterator isActive = 6362875Sksewell@umich.edu std::find(activeThreads.begin(), activeThreads.end(), tid); 6376221Snate@binkert.org 6382875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6392875Sksewell@umich.edu 6402875Sksewell@umich.edu if (isActive == activeThreads.end()) { 6412875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6427823Ssteve.reinhardt@amd.com tid); 6432875Sksewell@umich.edu 6442875Sksewell@umich.edu activeThreads.push_back(tid); 6452875Sksewell@umich.edu } 6462875Sksewell@umich.edu} 6472875Sksewell@umich.edu 6487823Ssteve.reinhardt@amd.comtemplate <class Impl> 6492875Sksewell@umich.eduvoid 6502875Sksewell@umich.eduFullO3CPU<Impl>::deactivateThread(unsigned tid) 6512875Sksewell@umich.edu{ 6522875Sksewell@umich.edu //Remove From Active List, if Active 6532875Sksewell@umich.edu std::list<unsigned>::iterator thread_it = 6542875Sksewell@umich.edu std::find(activeThreads.begin(), activeThreads.end(), tid); 6552875Sksewell@umich.edu 6567823Ssteve.reinhardt@amd.com DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 6572875Sksewell@umich.edu 6582875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 6592875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6602875Sksewell@umich.edu tid); 6612875Sksewell@umich.edu activeThreads.erase(thread_it); 6622875Sksewell@umich.edu } 6633221Sktlim@umich.edu} 6646221Snate@binkert.org 6652875Sksewell@umich.edutemplate <class Impl> 6662875Sksewell@umich.eduvoid 6672875Sksewell@umich.eduFullO3CPU<Impl>::activateContext(int tid, int delay) 6682875Sksewell@umich.edu{ 6697823Ssteve.reinhardt@amd.com // Needs to set each stage to running as well. 6703221Sktlim@umich.edu if (delay){ 6713221Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 6722875Sksewell@umich.edu "on cycle %d\n", tid, curTick + ticks(delay)); 6732875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 6743221Sktlim@umich.edu } else { 6753221Sktlim@umich.edu activateThread(tid); 6763221Sktlim@umich.edu } 6772875Sksewell@umich.edu 6782875Sksewell@umich.edu if (lastActivatedCycle < curTick) { 6792875Sksewell@umich.edu scheduleTickEvent(delay); 6802875Sksewell@umich.edu 6812875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 6826221Snate@binkert.org // deschedule itself. 6832875Sksewell@umich.edu activityRec.activity(); 6842875Sksewell@umich.edu fetch.wakeFromQuiesce(); 6853221Sktlim@umich.edu 6863221Sktlim@umich.edu lastActivatedCycle = curTick; 6875570Snate@binkert.org 6883859Sbinkertn@umich.edu _status = Running; 6892910Sksewell@umich.edu } 6902875Sksewell@umich.edu} 6912875Sksewell@umich.edu 6922875Sksewell@umich.edutemplate <class Impl> 6932875Sksewell@umich.edubool 6942875Sksewell@umich.eduFullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay) 6956221Snate@binkert.org{ 6962875Sksewell@umich.edu // Schedule removal of thread data from CPU 6972910Sksewell@umich.edu if (delay){ 6982910Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 6993221Sktlim@umich.edu "on cycle %d\n", tid, curTick + ticks(delay)); 7002875Sksewell@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 7012875Sksewell@umich.edu return false; 7022875Sksewell@umich.edu } else { 7032875Sksewell@umich.edu deactivateThread(tid); 7046221Snate@binkert.org if (remove) 7052292SN/A removeThread(tid); 7062847Sksewell@umich.edu return true; 7072292SN/A } 7082683Sktlim@umich.edu} 7092292SN/A 7102680Sktlim@umich.edutemplate <class Impl> 7112292SN/Avoid 7122847Sksewell@umich.eduFullO3CPU<Impl>::suspendContext(int tid) 7132292SN/A{ 7142292SN/A DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 7152292SN/A bool deallocated = deallocateContext(tid, false, 1); 7162292SN/A // If this was the last thread then unschedule the tick event. 7172292SN/A if ((activeThreads.size() == 1 && !deallocated) || 7182292SN/A activeThreads.size() == 0) 7192292SN/A unscheduleTickEvent(); 7202292SN/A _status = Idle; 7212292SN/A} 7222292SN/A 7232292SN/Atemplate <class Impl> 7242292SN/Avoid 7252292SN/AFullO3CPU<Impl>::haltContext(int tid) 7262292SN/A{ 7272292SN/A //For now, this is the same as deallocate 7282292SN/A DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 7292292SN/A deallocateContext(tid, true, 1); 7302292SN/A} 7312292SN/A 7322847Sksewell@umich.edutemplate <class Impl> 7332292SN/Avoid 7342847Sksewell@umich.eduFullO3CPU<Impl>::insertThread(unsigned tid) 7357720Sgblack@eecs.umich.edu{ 7362292SN/A DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 7372680Sktlim@umich.edu // Will change now that the PC and thread state is internal to the CPU 7382292SN/A // and not in the ThreadContext. 7392292SN/A#if FULL_SYSTEM 7402292SN/A ThreadContext *src_tc = system->threadContexts[tid]; 7412292SN/A#else 7422292SN/A ThreadContext *src_tc = tcBase(tid); 7432292SN/A#endif 7442292SN/A 7452292SN/A //Bind Int Regs to Rename Map 7462292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7472292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 7486221Snate@binkert.org 7492292SN/A renameMap[tid].setEntry(ireg,phys_reg); 7502877Sksewell@umich.edu scoreboard.setReg(phys_reg); 7512847Sksewell@umich.edu } 7522847Sksewell@umich.edu 7532847Sksewell@umich.edu //Bind Float Regs to Rename Map 7545364Sksewell@umich.edu for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 7555364Sksewell@umich.edu PhysRegIndex phys_reg = freeList.getFloatReg(); 7565364Sksewell@umich.edu 7575364Sksewell@umich.edu renameMap[tid].setEntry(freg,phys_reg); 7585364Sksewell@umich.edu scoreboard.setReg(phys_reg); 7595364Sksewell@umich.edu } 7602847Sksewell@umich.edu 7612847Sksewell@umich.edu //Copy Thread Data Into RegFile 7622292SN/A //this->copyFromTC(tid); 7632292SN/A 7642292SN/A //Set PC/NPC/NNPC 7652292SN/A setPC(src_tc->readPC(), tid); 7662292SN/A setNextPC(src_tc->readNextPC(), tid); 7672292SN/A setNextNPC(src_tc->readNextNPC(), tid); 7682292SN/A 7692847Sksewell@umich.edu src_tc->setStatus(ThreadContext::Active); 7705362Sksewell@umich.edu 7712292SN/A activateContext(tid,1); 7722292SN/A 7732292SN/A //Reset ROB/IQ/LSQ Entries 7742292SN/A commit.rob->resetEntries(); 7752292SN/A iew.resetEntries(); 7762292SN/A} 7772847Sksewell@umich.edu 7782935Sksewell@umich.edutemplate <class Impl> 7797720Sgblack@eecs.umich.eduvoid 7802292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 7812935Sksewell@umich.edu{ 7822875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 7835363Sksewell@umich.edu 7842935Sksewell@umich.edu // Copy Thread Data From RegFile 7852292SN/A // If thread is suspended, it might be re-allocated 7865362Sksewell@umich.edu // this->copyToTC(tid); 7875362Sksewell@umich.edu 7882292SN/A 7892292SN/A // @todo: 2-27-2008: Fix how we free up rename mappings 7902847Sksewell@umich.edu // here to alleviate the case for double-freeing registers 7913229Sktlim@umich.edu // in SMT workloads. 7923229Sktlim@umich.edu 7933229Sktlim@umich.edu // Unbind Int Regs from Rename Map 7943229Sktlim@umich.edu for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7953229Sktlim@umich.edu PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 7963229Sktlim@umich.edu 7972292SN/A scoreboard.unsetReg(phys_reg); 7982292SN/A freeList.addReg(phys_reg); 7992292SN/A } 8002292SN/A 8013229Sktlim@umich.edu // Unbind Float Regs from Rename Map 8022292SN/A for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 8032292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 8042292SN/A 8052292SN/A scoreboard.unsetReg(phys_reg); 8062292SN/A freeList.addReg(phys_reg); 8076221Snate@binkert.org } 8082292SN/A 8092733Sktlim@umich.edu // Squash Throughout Pipeline 8102292SN/A InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; 8112292SN/A fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid); 8122292SN/A decode.squash(tid); 8132292SN/A rename.squash(squash_seq_num, tid); 8142292SN/A iew.squash(tid); 8152292SN/A iew.ldstQueue.squash(squash_seq_num, tid); 8162733Sktlim@umich.edu commit.rob->squash(squash_seq_num, tid); 8172292SN/A 8182292SN/A 8192292SN/A assert(iew.instQueue.getCount(tid) == 0); 8202292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 8212733Sktlim@umich.edu 8222292SN/A // Reset ROB/IQ/LSQ Entries 8232292SN/A 8242292SN/A // Commented out for now. This should be possible to do by 8252292SN/A // telling all the pipeline stages to drain first, and then 8262292SN/A // checking until the drain completes. Once the pipeline is 8272733Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 8282292SN/A/* 8292292SN/A if (activeThreads.size() >= 1) { 8302292SN/A commit.rob->resetEntries(); 8312292SN/A iew.resetEntries(); 8322292SN/A } 8332733Sktlim@umich.edu*/ 8342292SN/A} 8352292SN/A 8362292SN/A 8372292SN/Atemplate <class Impl> 8382292SN/Avoid 8392733Sktlim@umich.eduFullO3CPU<Impl>::activateWhenReady(int tid) 8402292SN/A{ 8412292SN/A DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 8422292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 8432292SN/A tid); 8442292SN/A 8452292SN/A bool ready = true; 8462292SN/A 8472292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 8482292SN/A DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8492292SN/A "Phys. Int. Regs.\n", 8502292SN/A tid); 8512292SN/A ready = false; 8522292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 8532292SN/A DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8542292SN/A "Phys. Float. Regs.\n", 8552292SN/A tid); 8562292SN/A ready = false; 8572875Sksewell@umich.edu } else if (commit.rob->numFreeEntries() >= 8582292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 8592292SN/A DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8601060SN/A "ROB entries.\n", 8611060SN/A tid); 8621060SN/A ready = false; 8634192Sktlim@umich.edu } else if (iew.instQueue.numFreeEntries() >= 8644192Sktlim@umich.edu iew.instQueue.entryAmount(activeThreads.size() + 1)) { 8655595Sgblack@eecs.umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8666221Snate@binkert.org "IQ entries.\n", 8675702Ssaidi@eecs.umich.edu tid); 8685702Ssaidi@eecs.umich.edu ready = false; 8695702Ssaidi@eecs.umich.edu } else if (iew.ldstQueue.numFreeEntries() >= 8705702Ssaidi@eecs.umich.edu iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 8715702Ssaidi@eecs.umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 8725702Ssaidi@eecs.umich.edu "LSQ entries.\n", 8735702Ssaidi@eecs.umich.edu tid); 8745702Ssaidi@eecs.umich.edu ready = false; 8755702Ssaidi@eecs.umich.edu } 8765702Ssaidi@eecs.umich.edu 8775702Ssaidi@eecs.umich.edu if (ready) { 8785702Ssaidi@eecs.umich.edu insertThread(tid); 8795702Ssaidi@eecs.umich.edu 8805702Ssaidi@eecs.umich.edu contextSwitch = false; 8816221Snate@binkert.org 8825702Ssaidi@eecs.umich.edu cpuWaitList.remove(tid); 8835702Ssaidi@eecs.umich.edu } else { 8845702Ssaidi@eecs.umich.edu suspendContext(tid); 8855702Ssaidi@eecs.umich.edu 8865702Ssaidi@eecs.umich.edu //blocks fetch 8875702Ssaidi@eecs.umich.edu contextSwitch = true; 8885702Ssaidi@eecs.umich.edu 8895702Ssaidi@eecs.umich.edu //@todo: dont always add to waitlist 8905702Ssaidi@eecs.umich.edu //do waitlist 8915702Ssaidi@eecs.umich.edu cpuWaitList.push_back(tid); 8925702Ssaidi@eecs.umich.edu } 8935702Ssaidi@eecs.umich.edu} 8945702Ssaidi@eecs.umich.edu 8955702Ssaidi@eecs.umich.edu#if FULL_SYSTEM 8965702Ssaidi@eecs.umich.edutemplate <class Impl> 8975702Ssaidi@eecs.umich.eduvoid 8985702Ssaidi@eecs.umich.eduFullO3CPU<Impl>::post_interrupt(int int_num, int index) 8995702Ssaidi@eecs.umich.edu{ 9005702Ssaidi@eecs.umich.edu BaseCPU::post_interrupt(int_num, index); 9015702Ssaidi@eecs.umich.edu 9025702Ssaidi@eecs.umich.edu if (this->thread[0]->status() == ThreadContext::Suspended) { 9035702Ssaidi@eecs.umich.edu DPRINTF(IPI,"Suspended Processor awoke\n"); 9045702Ssaidi@eecs.umich.edu this->threadContexts[0]->activate(); 9055702Ssaidi@eecs.umich.edu } 9065702Ssaidi@eecs.umich.edu} 9075595Sgblack@eecs.umich.edu 9085595Sgblack@eecs.umich.edutemplate <class Impl> 9095595Sgblack@eecs.umich.eduFault 9105647Sgblack@eecs.umich.eduFullO3CPU<Impl>::hwrei(unsigned tid) 9115595Sgblack@eecs.umich.edu{ 9125595Sgblack@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9135595Sgblack@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 9145595Sgblack@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 9155595Sgblack@eecs.umich.edu 9165595Sgblack@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 9175595Sgblack@eecs.umich.edu 9185595Sgblack@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 9195595Sgblack@eecs.umich.edu#endif 9205595Sgblack@eecs.umich.edu return NoFault; 9215595Sgblack@eecs.umich.edu} 9225595Sgblack@eecs.umich.edu 9235595Sgblack@eecs.umich.edutemplate <class Impl> 9245647Sgblack@eecs.umich.edubool 9255595Sgblack@eecs.umich.eduFullO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid) 9265595Sgblack@eecs.umich.edu{ 9277684Sgblack@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9285595Sgblack@eecs.umich.edu if (this->thread[tid]->kernelStats) 9295595Sgblack@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 9305595Sgblack@eecs.umich.edu this->threadContexts[tid]); 9315595Sgblack@eecs.umich.edu 9324192Sktlim@umich.edu switch (palFunc) { 9334192Sktlim@umich.edu case PAL::halt: 9344192Sktlim@umich.edu halt(); 9354192Sktlim@umich.edu if (--System::numSystemsRunning == 0) 9366221Snate@binkert.org exitSimLoop("all cpus halted"); 9376221Snate@binkert.org break; 9385497Ssaidi@eecs.umich.edu 9394192Sktlim@umich.edu case PAL::bpt: 9404192Sktlim@umich.edu case PAL::bugchk: 9414192Sktlim@umich.edu if (this->system->breakpoint()) 9421060SN/A return false; 9432852Sktlim@umich.edu break; 9447684Sgblack@eecs.umich.edu } 9455595Sgblack@eecs.umich.edu#endif 9465595Sgblack@eecs.umich.edu return true; 9477684Sgblack@eecs.umich.edu} 9485595Sgblack@eecs.umich.edu 9495595Sgblack@eecs.umich.edutemplate <class Impl> 9505595Sgblack@eecs.umich.eduFault 9515595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 9525595Sgblack@eecs.umich.edu{ 9535595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 9546221Snate@binkert.org return this->interrupts->getInterrupt(this->threadContexts[0]); 9555595Sgblack@eecs.umich.edu} 9565595Sgblack@eecs.umich.edu 9575595Sgblack@eecs.umich.edutemplate <class Impl> 9585595Sgblack@eecs.umich.eduvoid 9595595Sgblack@eecs.umich.eduFullO3CPU<Impl>::processInterrupts(Fault interrupt) 9605595Sgblack@eecs.umich.edu{ 9615595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 9625595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 9635595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 9645595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 9655595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 9665595Sgblack@eecs.umich.edu 9675595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 9685595Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 9695595Sgblack@eecs.umich.edu 9705595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 9715595Sgblack@eecs.umich.edu this->trap(interrupt, 0); 9725595Sgblack@eecs.umich.edu} 9735595Sgblack@eecs.umich.edu 9745595Sgblack@eecs.umich.edutemplate <class Impl> 9755595Sgblack@eecs.umich.eduvoid 9762864Sktlim@umich.eduFullO3CPU<Impl>::updateMemPorts() 9772864Sktlim@umich.edu{ 9782918Sktlim@umich.edu // Update all ThreadContext's memory ports (Functional/Virtual 9792918Sktlim@umich.edu // Ports) 9802864Sktlim@umich.edu for (int i = 0; i < thread.size(); ++i) 9812864Sktlim@umich.edu thread[i]->connectMemPorts(thread[i]->getTC()); 9822864Sktlim@umich.edu} 9832864Sktlim@umich.edu#endif 9842864Sktlim@umich.edu 9852864Sktlim@umich.edutemplate <class Impl> 9862864Sktlim@umich.eduvoid 9872864Sktlim@umich.eduFullO3CPU<Impl>::trap(Fault fault, unsigned tid) 9882864Sktlim@umich.edu{ 9896221Snate@binkert.org // Pass the thread's TC into the invoke method. 9906221Snate@binkert.org fault->invoke(this->threadContexts[tid]); 9912864Sktlim@umich.edu} 9922864Sktlim@umich.edu 9932864Sktlim@umich.edu#if !FULL_SYSTEM 9942864Sktlim@umich.edu 9952864Sktlim@umich.edutemplate <class Impl> 9962864Sktlim@umich.eduvoid 9972864Sktlim@umich.eduFullO3CPU<Impl>::syscall(int64_t callnum, int tid) 9982864Sktlim@umich.edu{ 9992864Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 10002864Sktlim@umich.edu 10012918Sktlim@umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 10022918Sktlim@umich.edu 10032864Sktlim@umich.edu // Temporarily increase this by one to account for the syscall 10042864Sktlim@umich.edu // instruction. 10052864Sktlim@umich.edu ++(this->thread[tid]->funcExeInst); 10062864Sktlim@umich.edu 10072864Sktlim@umich.edu // Execute the actual syscall. 10082864Sktlim@umich.edu this->thread[tid]->syscall(callnum); 10092864Sktlim@umich.edu 10102864Sktlim@umich.edu // Decrease funcExeInst by one as the normal commit will handle 10116221Snate@binkert.org // incrementing it. 10126221Snate@binkert.org --(this->thread[tid]->funcExeInst); 10132864Sktlim@umich.edu} 10142864Sktlim@umich.edu 10152864Sktlim@umich.edutemplate <class Impl> 10162864Sktlim@umich.eduvoid 10172864Sktlim@umich.eduFullO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid) 10182864Sktlim@umich.edu{ 10192864Sktlim@umich.edu TheISA::setSyscallReturn(return_value, this->tcBase(tid)); 10202905Sktlim@umich.edu} 10212843Sktlim@umich.edu 10221060SN/A#endif 10233125Sktlim@umich.edu 10243512Sktlim@umich.edutemplate <class Impl> 10253512Sktlim@umich.eduvoid 10263512Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 10273512Sktlim@umich.edu{ 10283512Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 10293512Sktlim@umich.edu SERIALIZE_ENUM(so_state); 10302843Sktlim@umich.edu BaseCPU::serialize(os); 10312843Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 10322843Sktlim@umich.edu tickEvent.serialize(os); 10332843Sktlim@umich.edu 10342843Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 10352843Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 10362325SN/A // get instantiated multiple times (causes a panic in statistics). 10372325SN/A static SimpleThread temp; 10382863Sktlim@umich.edu 10392905Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 10402864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 10412864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10422864Sktlim@umich.edu temp.serialize(os); 10432864Sktlim@umich.edu } 10442864Sktlim@umich.edu} 10452843Sktlim@umich.edu 10462863Sktlim@umich.edutemplate <class Impl> 10472863Sktlim@umich.eduvoid 10482852Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 10492905Sktlim@umich.edu{ 10502863Sktlim@umich.edu SimObject::State so_state; 10512905Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 10522863Sktlim@umich.edu BaseCPU::unserialize(cp, section); 10532316SN/A tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 10542310SN/A 10552316SN/A // Use SimpleThread's ability to checkpoint to make it easier to 10562316SN/A // read in the registers. Also make this static so it doesn't 10572843Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 10582316SN/A static SimpleThread temp; 10592843Sktlim@umich.edu 10602843Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 10612843Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 10622843Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 10632843Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 10642316SN/A } 10652905Sktlim@umich.edu} 10662905Sktlim@umich.edu 10672864Sktlim@umich.edutemplate <class Impl> 10682864Sktlim@umich.eduunsigned int 10692864Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 10703319Shsul@eecs.umich.edu{ 10714762Snate@binkert.org DPRINTF(O3CPU, "Switching out\n"); 10723319Shsul@eecs.umich.edu 10733319Shsul@eecs.umich.edu // If the CPU isn't doing anything, then return immediately. 10742843Sktlim@umich.edu if (_status == Idle || _status == SwitchedOut) { 10755606Snate@binkert.org return 0; 10762843Sktlim@umich.edu } 10772843Sktlim@umich.edu 10782316SN/A drainCount = 0; 10792843Sktlim@umich.edu fetch.drain(); 10802843Sktlim@umich.edu decode.drain(); 10812843Sktlim@umich.edu rename.drain(); 10822843Sktlim@umich.edu iew.drain(); 10832843Sktlim@umich.edu commit.drain(); 10842316SN/A 10852316SN/A // Wake the CPU and record activity so everything can drain out if 10862863Sktlim@umich.edu // the CPU was not able to immediately drain. 10872905Sktlim@umich.edu if (getState() != SimObject::Drained) { 10882863Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 10893126Sktlim@umich.edu // calls have been made, that way if all of the stages drain 10903126Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 10912863Sktlim@umich.edu // process on the drain event. 10922863Sktlim@umich.edu drainEvent = drain_event; 10932863Sktlim@umich.edu 10942863Sktlim@umich.edu wakeCPU(); 10952310SN/A activityRec.activity(); 10962843Sktlim@umich.edu 10972843Sktlim@umich.edu return 1; 10982843Sktlim@umich.edu } else { 10992843Sktlim@umich.edu return 0; 11002843Sktlim@umich.edu } 11012843Sktlim@umich.edu} 11022843Sktlim@umich.edu 11032843Sktlim@umich.edutemplate <class Impl> 11042843Sktlim@umich.eduvoid 11052325SN/AFullO3CPU<Impl>::resume() 11062843Sktlim@umich.edu{ 11072843Sktlim@umich.edu fetch.resume(); 11082843Sktlim@umich.edu decode.resume(); 11092843Sktlim@umich.edu rename.resume(); 11102843Sktlim@umich.edu iew.resume(); 11112843Sktlim@umich.edu commit.resume(); 11122843Sktlim@umich.edu 11132843Sktlim@umich.edu changeState(SimObject::Running); 11142843Sktlim@umich.edu 11152843Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 11162843Sktlim@umich.edu return; 11173126Sktlim@umich.edu 11183126Sktlim@umich.edu#if FULL_SYSTEM 11191060SN/A assert(system->getMemoryMode() == Enums::timing); 11201060SN/A#endif 11211060SN/A 11221060SN/A if (!tickEvent.scheduled()) 11231755SN/A schedule(tickEvent, nextCycle()); 11241060SN/A _status = Running; 11252325SN/A} 11262873Sktlim@umich.edu 11272307SN/Atemplate <class Impl> 11282307SN/Avoid 11292307SN/AFullO3CPU<Impl>::signalDrained() 11302307SN/A{ 11312307SN/A if (++drainCount == NumStages) { 11322307SN/A if (tickEvent.scheduled()) 11332307SN/A tickEvent.squash(); 11342325SN/A 11352307SN/A changeState(SimObject::Drained); 11364192Sktlim@umich.edu 11371060SN/A BaseCPU::switchOut(); 11382307SN/A 11392307SN/A if (drainEvent) { 11402307SN/A drainEvent->process(); 11412307SN/A drainEvent = NULL; 11422307SN/A } 11432307SN/A } 11447507Stjones1@inf.ed.ac.uk assert(drainCount <= 5); 11451060SN/A} 11462325SN/A 11472325SN/Atemplate <class Impl> 11486221Snate@binkert.orgvoid 11492307SN/AFullO3CPU<Impl>::switchOut() 11506221Snate@binkert.org{ 11515314Sstever@gmail.com fetch.switchOut(); 11522307SN/A rename.switchOut(); 11532307SN/A iew.switchOut(); 11542325SN/A commit.switchOut(); 11552325SN/A instList.clear(); 11562733Sktlim@umich.edu while (!removeList.empty()) { 11572307SN/A removeList.pop(); 11582307SN/A } 11592307SN/A 11602307SN/A _status = SwitchedOut; 11612307SN/A#if USE_CHECKER 11622325SN/A if (checker) 11632307SN/A checker->switchOut(); 11646221Snate@binkert.org#endif 11656221Snate@binkert.org if (tickEvent.scheduled()) 11662680Sktlim@umich.edu tickEvent.squash(); 11672680Sktlim@umich.edu} 11681681SN/A 11697507Stjones1@inf.ed.ac.uktemplate <class Impl> 11701681SN/Avoid 11711060SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 11722307SN/A{ 11735606Snate@binkert.org // Flush out any old data from the time buffers. 11741060SN/A for (int i = 0; i < timeBuffer.getSize(); ++i) { 11751060SN/A timeBuffer.advance(); 11761060SN/A fetchQueue.advance(); 11775595Sgblack@eecs.umich.edu decodeQueue.advance(); 11786221Snate@binkert.org renameQueue.advance(); 11795595Sgblack@eecs.umich.edu iewQueue.advance(); 11806313Sgblack@eecs.umich.edu } 11815595Sgblack@eecs.umich.edu 11825595Sgblack@eecs.umich.edu activityRec.reset(); 11835595Sgblack@eecs.umich.edu 11845595Sgblack@eecs.umich.edu BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort()); 11856221Snate@binkert.org 11865595Sgblack@eecs.umich.edu fetch.takeOverFrom(); 11876313Sgblack@eecs.umich.edu decode.takeOverFrom(); 11885595Sgblack@eecs.umich.edu rename.takeOverFrom(); 11895595Sgblack@eecs.umich.edu iew.takeOverFrom(); 11905595Sgblack@eecs.umich.edu commit.takeOverFrom(); 11915595Sgblack@eecs.umich.edu 11925595Sgblack@eecs.umich.edu assert(!tickEvent.scheduled()); 11936221Snate@binkert.org 11945595Sgblack@eecs.umich.edu // @todo: Figure out how to properly select the tid to put onto 11956313Sgblack@eecs.umich.edu // the active threads list. 11965595Sgblack@eecs.umich.edu int tid = 0; 11975595Sgblack@eecs.umich.edu 11985595Sgblack@eecs.umich.edu std::list<unsigned>::iterator isActive = 11995595Sgblack@eecs.umich.edu std::find(activeThreads.begin(), activeThreads.end(), tid); 12005595Sgblack@eecs.umich.edu 12016221Snate@binkert.org if (isActive == activeThreads.end()) { 12025595Sgblack@eecs.umich.edu //May Need to Re-code this if the delay variable is the delay 12036313Sgblack@eecs.umich.edu //needed for thread to activate 12045595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 12055595Sgblack@eecs.umich.edu tid); 12065595Sgblack@eecs.umich.edu 12071060SN/A activeThreads.push_back(tid); 12081755SN/A } 12091060SN/A 12101060SN/A // Set all statuses to active, schedule the CPU's tick event. 12111060SN/A // @todo: Fix up statuses so this is handled properly 12121060SN/A for (int i = 0; i < threadContexts.size(); ++i) { 12131060SN/A ThreadContext *tc = threadContexts[i]; 12142455SN/A if (tc->status() == ThreadContext::Active && _status != Running) { 12152455SN/A _status = Running; 12161060SN/A schedule(tickEvent, nextCycle()); 12172455SN/A } 12181060SN/A } 12191060SN/A if (!tickEvent.scheduled()) 12201060SN/A schedule(tickEvent, nextCycle()); 12212455SN/A} 12222455SN/A 12232455SN/Atemplate <class Impl> 12242455SN/ATheISA::MiscReg 12251060SN/AFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid) 12261060SN/A{ 12271060SN/A return this->regFile.readMiscRegNoEffect(misc_reg, tid); 12281060SN/A} 12291755SN/A 12301060SN/Atemplate <class Impl> 12311060SN/ATheISA::MiscReg 12321060SN/AFullO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid) 12331060SN/A{ 12341060SN/A return this->regFile.readMiscReg(misc_reg, tid); 12351060SN/A} 12362455SN/A 12371060SN/Atemplate <class Impl> 12382455SN/Avoid 12391060SN/AFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 12401060SN/A const TheISA::MiscReg &val, unsigned tid) 12411060SN/A{ 12421060SN/A this->regFile.setMiscRegNoEffect(misc_reg, val, tid); 12432455SN/A} 12442455SN/A 12452455SN/Atemplate <class Impl> 12461060SN/Avoid 12471060SN/AFullO3CPU<Impl>::setMiscReg(int misc_reg, 12481060SN/A const TheISA::MiscReg &val, unsigned tid) 12491060SN/A{ 12506221Snate@binkert.org this->regFile.setMiscReg(misc_reg, val, tid); 12511060SN/A} 12522292SN/A 12532292SN/Atemplate <class Impl> 12542292SN/Auint64_t 12552292SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 12562292SN/A{ 12572292SN/A return regFile.readIntReg(reg_idx); 12582292SN/A} 12596314Sgblack@eecs.umich.edu 12602292SN/Atemplate <class Impl> 12616032Ssteve.reinhardt@amd.comFloatReg 12622307SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 12632292SN/A{ 12642669Sktlim@umich.edu return regFile.readFloatReg(reg_idx, width); 12652292SN/A} 12662292SN/A 12672292SN/Atemplate <class Impl> 12682292SN/AFloatReg 12696221Snate@binkert.orgFullO3CPU<Impl>::readFloatReg(int reg_idx) 12702292SN/A{ 12716032Ssteve.reinhardt@amd.com return regFile.readFloatReg(reg_idx); 12722307SN/A} 12732292SN/A 12742669Sktlim@umich.edutemplate <class Impl> 12751060SN/AFloatRegBits 12761060SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 12771060SN/A{ 12781060SN/A return regFile.readFloatRegBits(reg_idx, width); 12796221Snate@binkert.org} 12801060SN/A 12812292SN/Atemplate <class Impl> 12822292SN/AFloatRegBits 12832292SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 12841060SN/A{ 12851060SN/A return regFile.readFloatRegBits(reg_idx); 12861060SN/A} 12871060SN/A 12886314Sgblack@eecs.umich.edutemplate <class Impl> 12891060SN/Avoid 12906032Ssteve.reinhardt@amd.comFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 12912918Sktlim@umich.edu{ 12922292SN/A regFile.setIntReg(reg_idx, val); 12932669Sktlim@umich.edu} 12941060SN/A 12951060SN/Atemplate <class Impl> 12961060SN/Avoid 12971060SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 12986221Snate@binkert.org{ 12991060SN/A regFile.setFloatReg(reg_idx, val, width); 13006032Ssteve.reinhardt@amd.com} 13012918Sktlim@umich.edu 13021060SN/Atemplate <class Impl> 13032669Sktlim@umich.eduvoid 13042292SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 13052292SN/A{ 13062292SN/A regFile.setFloatReg(reg_idx, val); 13077720Sgblack@eecs.umich.edu} 13087720Sgblack@eecs.umich.edu 13092292SN/Atemplate <class Impl> 13107720Sgblack@eecs.umich.eduvoid 13111060SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 13121060SN/A{ 13131060SN/A regFile.setFloatRegBits(reg_idx, val, width); 13141060SN/A} 13157720Sgblack@eecs.umich.edu 13161060SN/Atemplate <class Impl> 13177720Sgblack@eecs.umich.eduvoid 13182292SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 13191060SN/A{ 13202292SN/A regFile.setFloatRegBits(reg_idx, val); 13217720Sgblack@eecs.umich.edu} 13227720Sgblack@eecs.umich.edu 13234636Sgblack@eecs.umich.edutemplate <class Impl> 13247720Sgblack@eecs.umich.eduuint64_t 13254636Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 13264636Sgblack@eecs.umich.edu{ 13274636Sgblack@eecs.umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13287720Sgblack@eecs.umich.edu 13297720Sgblack@eecs.umich.edu return regFile.readIntReg(phys_reg); 13304636Sgblack@eecs.umich.edu} 13317720Sgblack@eecs.umich.edu 13324636Sgblack@eecs.umich.edutemplate <class Impl> 13334636Sgblack@eecs.umich.edufloat 13344636Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 13357720Sgblack@eecs.umich.edu{ 13367720Sgblack@eecs.umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 13372292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13387720Sgblack@eecs.umich.edu 13394636Sgblack@eecs.umich.edu return regFile.readFloatReg(phys_reg); 13404636Sgblack@eecs.umich.edu} 13414636Sgblack@eecs.umich.edu 13425595Sgblack@eecs.umich.edutemplate <class Impl> 13436221Snate@binkert.orgdouble 13445595Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 13455595Sgblack@eecs.umich.edu{ 13465595Sgblack@eecs.umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 13475595Sgblack@eecs.umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13485595Sgblack@eecs.umich.edu 13495595Sgblack@eecs.umich.edu return regFile.readFloatReg(phys_reg, 64); 13502292SN/A} 13512292SN/A 13522292SN/Atemplate <class Impl> 13532292SN/Auint64_t 13541060SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 13552292SN/A{ 13562292SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 13571060SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13582292SN/A 13592292SN/A return regFile.readFloatRegBits(phys_reg); 13606221Snate@binkert.org} 13612292SN/A 13622292SN/Atemplate <class Impl> 13632292SN/Avoid 13642292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 13652292SN/A{ 13662292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 13672292SN/A 13682292SN/A regFile.setIntReg(phys_reg, val); 13692292SN/A} 13702292SN/A 13712292SN/Atemplate <class Impl> 13722292SN/Avoid 13732292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 13742292SN/A{ 13752292SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 13762292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13772292SN/A 13782292SN/A regFile.setFloatReg(phys_reg, val); 13791060SN/A} 13801060SN/A 13811060SN/Atemplate <class Impl> 13821060SN/Avoid 13831755SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 13841060SN/A{ 13857720Sgblack@eecs.umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 13862292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13877720Sgblack@eecs.umich.edu 13881060SN/A regFile.setFloatReg(phys_reg, val, 64); 13892292SN/A} 13901060SN/A 13911060SN/Atemplate <class Impl> 13922292SN/Avoid 13931060SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 13941060SN/A{ 13951060SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 13961060SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 13976221Snate@binkert.org 13981060SN/A regFile.setFloatRegBits(phys_reg, val); 13992733Sktlim@umich.edu} 14002292SN/A 14011060SN/Atemplate <class Impl> 14022292SN/Auint64_t 14031060SN/AFullO3CPU<Impl>::readPC(unsigned tid) 14042292SN/A{ 14052292SN/A return commit.readPC(tid); 14062292SN/A} 14072292SN/A 14082292SN/Atemplate <class Impl> 14092733Sktlim@umich.eduvoid 14102292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 14112292SN/A{ 14122292SN/A commit.setPC(new_PC, tid); 14132292SN/A} 14142733Sktlim@umich.edu 14152292SN/Atemplate <class Impl> 14162292SN/Auint64_t 14172292SN/AFullO3CPU<Impl>::readMicroPC(unsigned tid) 14182292SN/A{ 14192292SN/A return commit.readMicroPC(tid); 14202292SN/A} 14212292SN/A 14222292SN/Atemplate <class Impl> 14232292SN/Avoid 14242292SN/AFullO3CPU<Impl>::setMicroPC(Addr new_PC,unsigned tid) 14252292SN/A{ 14262292SN/A commit.setMicroPC(new_PC, tid); 14272292SN/A} 14282292SN/A 14292292SN/Atemplate <class Impl> 14302292SN/Auint64_t 14312292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 14322292SN/A{ 14332292SN/A return commit.readNextPC(tid); 14342292SN/A} 14352292SN/A 14362292SN/Atemplate <class Impl> 14372292SN/Avoid 14381060SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 14391060SN/A{ 14401060SN/A commit.setNextPC(val, tid); 14411060SN/A} 14426221Snate@binkert.org 14431062SN/Atemplate <class Impl> 14442292SN/Auint64_t 14452292SN/AFullO3CPU<Impl>::readNextNPC(unsigned tid) 14462292SN/A{ 14472292SN/A return commit.readNextNPC(tid); 14482292SN/A} 14492292SN/A 14502292SN/Atemplate <class Impl> 14512292SN/Avoid 14522733Sktlim@umich.eduFullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid) 14532292SN/A{ 14542292SN/A commit.setNextNPC(val, tid); 14551062SN/A} 14562292SN/A 14571062SN/Atemplate <class Impl> 14582292SN/Auint64_t 14591062SN/AFullO3CPU<Impl>::readNextMicroPC(unsigned tid) 14602292SN/A{ 14611062SN/A return commit.readNextMicroPC(tid); 14622292SN/A} 14631062SN/A 14642292SN/Atemplate <class Impl> 14652292SN/Avoid 14662292SN/AFullO3CPU<Impl>::setNextMicroPC(Addr new_PC,unsigned tid) 14672292SN/A{ 14682292SN/A commit.setNextMicroPC(new_PC, tid); 14692292SN/A} 14702292SN/A 14716221Snate@binkert.orgtemplate <class Impl> 14722292SN/Avoid 14732292SN/AFullO3CPU<Impl>::squashFromTC(unsigned tid) 14742733Sktlim@umich.edu{ 14757720Sgblack@eecs.umich.edu this->thread[tid]->inSyscall = true; 14762292SN/A this->commit.generateTCEvent(tid); 14772292SN/A} 14787720Sgblack@eecs.umich.edu 14791062SN/Atemplate <class Impl> 14801062SN/Atypename FullO3CPU<Impl>::ListIt 14812292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 14822292SN/A{ 14832325SN/A instList.push_back(inst); 14842325SN/A 14852292SN/A return --(instList.end()); 14862292SN/A} 14872292SN/A 14882292SN/Atemplate <class Impl> 14892292SN/Avoid 14902292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 14912292SN/A{ 14922292SN/A // Keep an instruction count. 14932292SN/A thread[tid]->numInst++; 14942292SN/A thread[tid]->numInsts++; 14952733Sktlim@umich.edu committedInsts[tid]++; 14967720Sgblack@eecs.umich.edu totalCommittedInsts++; 14972292SN/A 14982292SN/A // Check for instruction-count-based events. 14997720Sgblack@eecs.umich.edu comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 15002292SN/A} 15012292SN/A 15022292SN/Atemplate <class Impl> 15032292SN/Avoid 15041062SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 15051062SN/A{ 15062292SN/A removeInstsThisCycle = true; 15071062SN/A 15082325SN/A removeList.push(inst->getInstListIt()); 15091062SN/A} 15101062SN/A 15111755SN/Atemplate <class Impl> 15121060SN/Avoid 15131060SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 15141060SN/A{ 15152325SN/A DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 15161060SN/A "[sn:%lli]\n", 15171060SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 15181755SN/A 15191060SN/A removeInstsThisCycle = true; 15201060SN/A 15211060SN/A // Remove the front instruction. 15222292SN/A removeList.push(inst->getInstListIt()); 15232292SN/A} 15242292SN/A 15252292SN/Atemplate <class Impl> 15262292SN/Avoid 15272292SN/AFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 15282292SN/A{ 15297720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 15302292SN/A " list.\n", tid); 15312292SN/A 15321060SN/A ListIt end_it; 15331060SN/A 15341060SN/A bool rob_empty = false; 15351060SN/A 15362325SN/A if (instList.empty()) { 15371060SN/A return; 15381060SN/A } else if (rob.isEmpty(/*tid*/)) { 15391755SN/A DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 15401060SN/A end_it = instList.begin(); 15411060SN/A rob_empty = true; 15421060SN/A } else { 15432325SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 15442292SN/A DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 15452292SN/A } 15462292SN/A 15472292SN/A removeInstsThisCycle = true; 15482325SN/A 15492325SN/A ListIt inst_it = instList.end(); 15502292SN/A 15512292SN/A inst_it--; 15522292SN/A 15532325SN/A // Walk through the instruction list, removing any instructions 15542325SN/A // that were inserted after the given instruction iterator, end_it. 15557823Ssteve.reinhardt@amd.com while (inst_it != end_it) { 15567823Ssteve.reinhardt@amd.com assert(!instList.empty()); 15572292SN/A 15585606Snate@binkert.org squashInstIt(inst_it, tid); 15592292SN/A 15602292SN/A inst_it--; 15615807Snate@binkert.org } 15625807Snate@binkert.org 15635807Snate@binkert.org // If the ROB was empty, then we actually need to remove the first 15645807Snate@binkert.org // instruction as well. 15655807Snate@binkert.org if (rob_empty) { 15665807Snate@binkert.org squashInstIt(inst_it, tid); 15675807Snate@binkert.org } 15685807Snate@binkert.org} 15695807Snate@binkert.org 15705807Snate@binkert.orgtemplate <class Impl> 15715807Snate@binkert.orgvoid 15725807Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 15735807Snate@binkert.org unsigned tid) 15745807Snate@binkert.org{ 15755807Snate@binkert.org assert(!instList.empty()); 15762292SN/A 15776221Snate@binkert.org removeInstsThisCycle = true; 15782292SN/A 15792292SN/A ListIt inst_iter = instList.end(); 15806221Snate@binkert.org 15816221Snate@binkert.org inst_iter--; 15826221Snate@binkert.org 15836221Snate@binkert.org DPRINTF(O3CPU, "Deleting instructions from instruction " 15842292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 15852292SN/A tid, seq_num, (*inst_iter)->seqNum); 15862292SN/A 15876221Snate@binkert.org while ((*inst_iter)->seqNum > seq_num) { 15882292SN/A 15892292SN/A bool break_loop = (inst_iter == instList.begin()); 15902292SN/A 15912292SN/A squashInstIt(inst_iter, tid); 15922292SN/A 15932292SN/A inst_iter--; 15942292SN/A 15952292SN/A if (break_loop) 15962292SN/A break; 15972292SN/A } 15986221Snate@binkert.org} 15996221Snate@binkert.org 16002292SN/Atemplate <class Impl> 16012292SN/Ainline void 16022292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 16032292SN/A{ 16042292SN/A if ((*instIt)->threadNumber == tid) { 16052292SN/A DPRINTF(O3CPU, "Squashing instruction, " 16062292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 16072292SN/A (*instIt)->threadNumber, 16082292SN/A (*instIt)->seqNum, 16092292SN/A (*instIt)->readPC()); 16102292SN/A 16112292SN/A // Mark it as squashed. 16126221Snate@binkert.org (*instIt)->setSquashed(); 16132292SN/A 16142292SN/A // @todo: Formulate a consistent method for deleting 16156221Snate@binkert.org // instructions from the instruction list 16166221Snate@binkert.org // Remove the instruction from the list. 16172292SN/A removeList.push(instIt); 16182292SN/A } 16192292SN/A} 16202292SN/A 16212292SN/Atemplate <class Impl> 16222292SN/Avoid 16232292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 16242292SN/A{ 16251060SN/A while (!removeList.empty()) { 16261755SN/A DPRINTF(O3CPU, "Removing instruction, " 16272818Sksewell@umich.edu "[tid:%i] [sn:%lli] PC %#x\n", 1628 (*removeList.front())->threadNumber, 1629 (*removeList.front())->seqNum, 1630 (*removeList.front())->readPC()); 1631 1632 instList.erase(removeList.front()); 1633 1634 removeList.pop(); 1635 } 1636 1637 removeInstsThisCycle = false; 1638} 1639/* 1640template <class Impl> 1641void 1642FullO3CPU<Impl>::removeAllInsts() 1643{ 1644 instList.clear(); 1645} 1646*/ 1647template <class Impl> 1648void 1649FullO3CPU<Impl>::dumpInsts() 1650{ 1651 int num = 0; 1652 1653 ListIt inst_list_it = instList.begin(); 1654 1655 cprintf("Dumping Instruction List\n"); 1656 1657 while (inst_list_it != instList.end()) { 1658 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 1659 "Squashed:%i\n\n", 1660 num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 1661 (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 1662 (*inst_list_it)->isSquashed()); 1663 inst_list_it++; 1664 ++num; 1665 } 1666} 1667/* 1668template <class Impl> 1669void 1670FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 1671{ 1672 iew.wakeDependents(inst); 1673} 1674*/ 1675template <class Impl> 1676void 1677FullO3CPU<Impl>::wakeCPU() 1678{ 1679 if (activityRec.active() || tickEvent.scheduled()) { 1680 DPRINTF(Activity, "CPU already running.\n"); 1681 return; 1682 } 1683 1684 DPRINTF(Activity, "Waking up CPU\n"); 1685 1686 idleCycles += tickToCycles((curTick - 1) - lastRunningCycle); 1687 numCycles += tickToCycles((curTick - 1) - lastRunningCycle); 1688 1689 schedule(tickEvent, nextCycle()); 1690} 1691 1692template <class Impl> 1693int 1694FullO3CPU<Impl>::getFreeTid() 1695{ 1696 for (int i=0; i < numThreads; i++) { 1697 if (!tids[i]) { 1698 tids[i] = true; 1699 return i; 1700 } 1701 } 1702 1703 return -1; 1704} 1705 1706template <class Impl> 1707void 1708FullO3CPU<Impl>::doContextSwitch() 1709{ 1710 if (contextSwitch) { 1711 1712 //ADD CODE TO DEACTIVE THREAD HERE (???) 1713 1714 for (int tid=0; tid < cpuWaitList.size(); tid++) { 1715 activateWhenReady(tid); 1716 } 1717 1718 if (cpuWaitList.size() == 0) 1719 contextSwitch = true; 1720 } 1721} 1722 1723template <class Impl> 1724void 1725FullO3CPU<Impl>::updateThreadPriority() 1726{ 1727 if (activeThreads.size() > 1) 1728 { 1729 //DEFAULT TO ROUND ROBIN SCHEME 1730 //e.g. Move highest priority to end of thread list 1731 std::list<unsigned>::iterator list_begin = activeThreads.begin(); 1732 std::list<unsigned>::iterator list_end = activeThreads.end(); 1733 1734 unsigned high_thread = *list_begin; 1735 1736 activeThreads.erase(list_begin); 1737 1738 activeThreads.push_back(high_thread); 1739 } 1740} 1741 1742// Forward declaration of FullO3CPU. 1743template class FullO3CPU<O3CPUImpl>; 1744