cpu.cc revision 5570
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 341858SN/A 354762Snate@binkert.org#include "cpu/activity.hh" 364762Snate@binkert.org#include "cpu/simple_thread.hh" 374762Snate@binkert.org#include "cpu/thread_context.hh" 384762Snate@binkert.org#include "cpu/o3/isa_specific.hh" 394762Snate@binkert.org#include "cpu/o3/cpu.hh" 404762Snate@binkert.org#include "enums/MemoryMode.hh" 414762Snate@binkert.org#include "sim/core.hh" 424762Snate@binkert.org#include "sim/stat_control.hh" 434762Snate@binkert.org 441858SN/A#if FULL_SYSTEM 452356SN/A#include "cpu/quiesce_event.hh" 461060SN/A#include "sim/system.hh" 471060SN/A#else 481060SN/A#include "sim/process.hh" 491060SN/A#endif 501060SN/A 512794Sktlim@umich.edu#if USE_CHECKER 522794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 532794Sktlim@umich.edu#endif 542794Sktlim@umich.edu 555529Snate@binkert.orgclass BaseCPUParams; 565529Snate@binkert.org 572669Sktlim@umich.eduusing namespace TheISA; 581060SN/A 595529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 602292SN/A : BaseCPU(params), cpu_id(0) 611060SN/A{ 621060SN/A} 631060SN/A 642292SN/Avoid 652733Sktlim@umich.eduBaseO3CPU::regStats() 662292SN/A{ 672292SN/A BaseCPU::regStats(); 682292SN/A} 692292SN/A 701060SN/Atemplate <class Impl> 711755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 721060SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 731060SN/A{ 741060SN/A} 751060SN/A 761060SN/Atemplate <class Impl> 771060SN/Avoid 781755SN/AFullO3CPU<Impl>::TickEvent::process() 791060SN/A{ 801060SN/A cpu->tick(); 811060SN/A} 821060SN/A 831060SN/Atemplate <class Impl> 841060SN/Aconst char * 855336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 861060SN/A{ 874873Sstever@eecs.umich.edu return "FullO3CPU tick"; 881060SN/A} 891060SN/A 901060SN/Atemplate <class Impl> 912829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 923221Sktlim@umich.edu : Event(&mainEventQueue, CPU_Switch_Pri) 932829Sksewell@umich.edu{ 942829Sksewell@umich.edu} 952829Sksewell@umich.edu 962829Sksewell@umich.edutemplate <class Impl> 972829Sksewell@umich.eduvoid 982829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 992829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1002829Sksewell@umich.edu{ 1012829Sksewell@umich.edu tid = thread_num; 1022829Sksewell@umich.edu cpu = thread_cpu; 1032829Sksewell@umich.edu} 1042829Sksewell@umich.edu 1052829Sksewell@umich.edutemplate <class Impl> 1062829Sksewell@umich.eduvoid 1072829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1082829Sksewell@umich.edu{ 1092829Sksewell@umich.edu cpu->activateThread(tid); 1102829Sksewell@umich.edu} 1112829Sksewell@umich.edu 1122829Sksewell@umich.edutemplate <class Impl> 1132829Sksewell@umich.educonst char * 1145336Shines@cs.fsu.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1152829Sksewell@umich.edu{ 1164873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1172829Sksewell@umich.edu} 1182829Sksewell@umich.edu 1192829Sksewell@umich.edutemplate <class Impl> 1202875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1213859Sbinkertn@umich.edu : Event(&mainEventQueue, CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1222875Sksewell@umich.edu{ 1232875Sksewell@umich.edu} 1242875Sksewell@umich.edu 1252875Sksewell@umich.edutemplate <class Impl> 1262875Sksewell@umich.eduvoid 1272875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1283859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1292875Sksewell@umich.edu{ 1302875Sksewell@umich.edu tid = thread_num; 1312875Sksewell@umich.edu cpu = thread_cpu; 1323859Sbinkertn@umich.edu remove = false; 1332875Sksewell@umich.edu} 1342875Sksewell@umich.edu 1352875Sksewell@umich.edutemplate <class Impl> 1362875Sksewell@umich.eduvoid 1372875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1382875Sksewell@umich.edu{ 1392875Sksewell@umich.edu cpu->deactivateThread(tid); 1403221Sktlim@umich.edu if (remove) 1413221Sktlim@umich.edu cpu->removeThread(tid); 1422875Sksewell@umich.edu} 1432875Sksewell@umich.edu 1442875Sksewell@umich.edutemplate <class Impl> 1452875Sksewell@umich.educonst char * 1465336Shines@cs.fsu.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 1472875Sksewell@umich.edu{ 1484873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 1492875Sksewell@umich.edu} 1502875Sksewell@umich.edu 1512875Sksewell@umich.edutemplate <class Impl> 1525529Snate@binkert.orgFullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, DerivO3CPUParams *params) 1532733Sktlim@umich.edu : BaseO3CPU(params), 1543781Sgblack@eecs.umich.edu itb(params->itb), 1553781Sgblack@eecs.umich.edu dtb(params->dtb), 1561060SN/A tickEvent(this), 1572292SN/A removeInstsThisCycle(false), 1584329Sktlim@umich.edu fetch(o3_cpu, params), 1594329Sktlim@umich.edu decode(o3_cpu, params), 1604329Sktlim@umich.edu rename(o3_cpu, params), 1614329Sktlim@umich.edu iew(o3_cpu, params), 1624329Sktlim@umich.edu commit(o3_cpu, params), 1631060SN/A 1644329Sktlim@umich.edu regFile(o3_cpu, params->numPhysIntRegs, 1654329Sktlim@umich.edu params->numPhysFloatRegs), 1661060SN/A 1675529Snate@binkert.org freeList(params->numThreads, 1682292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1692292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1701060SN/A 1714329Sktlim@umich.edu rob(o3_cpu, 1724329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 1732292SN/A params->smtROBPolicy, params->smtROBThreshold, 1745529Snate@binkert.org params->numThreads), 1751060SN/A 1765529Snate@binkert.org scoreboard(params->numThreads, 1772292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1782292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1792292SN/A TheISA::NumMiscRegs * number_of_threads, 1802292SN/A TheISA::ZeroReg), 1811060SN/A 1822873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1832873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1842873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1852873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1862873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1872873Sktlim@umich.edu activityRec(NumStages, 1882873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1892873Sktlim@umich.edu params->activity), 1901060SN/A 1911060SN/A globalSeqNum(1), 1921858SN/A#if FULL_SYSTEM 1932292SN/A system(params->system), 1941060SN/A physmem(system->physmem), 1951060SN/A#endif // FULL_SYSTEM 1962843Sktlim@umich.edu drainCount(0), 1975529Snate@binkert.org deferRegistration(params->defer_registration), 1982316SN/A numThreads(number_of_threads) 1991060SN/A{ 2003221Sktlim@umich.edu if (!deferRegistration) { 2013221Sktlim@umich.edu _status = Running; 2023221Sktlim@umich.edu } else { 2033221Sktlim@umich.edu _status = Idle; 2043221Sktlim@umich.edu } 2051681SN/A 2064598Sbinkertn@umich.edu#if USE_CHECKER 2072794Sktlim@umich.edu if (params->checker) { 2082316SN/A BaseCPU *temp_checker = params->checker; 2092316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2102316SN/A#if FULL_SYSTEM 2112316SN/A checker->setSystem(params->system); 2122316SN/A#endif 2134598Sbinkertn@umich.edu } else { 2144598Sbinkertn@umich.edu checker = NULL; 2154598Sbinkertn@umich.edu } 2162794Sktlim@umich.edu#endif // USE_CHECKER 2172316SN/A 2181858SN/A#if !FULL_SYSTEM 2192292SN/A thread.resize(number_of_threads); 2202292SN/A tids.resize(number_of_threads); 2211681SN/A#endif 2221681SN/A 2232325SN/A // The stages also need their CPU pointer setup. However this 2242325SN/A // must be done at the upper level CPU because they have pointers 2252325SN/A // to the upper level CPU, and not this FullO3CPU. 2261060SN/A 2272292SN/A // Set up Pointers to the activeThreads list for each stage 2282292SN/A fetch.setActiveThreads(&activeThreads); 2292292SN/A decode.setActiveThreads(&activeThreads); 2302292SN/A rename.setActiveThreads(&activeThreads); 2312292SN/A iew.setActiveThreads(&activeThreads); 2322292SN/A commit.setActiveThreads(&activeThreads); 2331060SN/A 2341060SN/A // Give each of the stages the time buffer they will use. 2351060SN/A fetch.setTimeBuffer(&timeBuffer); 2361060SN/A decode.setTimeBuffer(&timeBuffer); 2371060SN/A rename.setTimeBuffer(&timeBuffer); 2381060SN/A iew.setTimeBuffer(&timeBuffer); 2391060SN/A commit.setTimeBuffer(&timeBuffer); 2401060SN/A 2411060SN/A // Also setup each of the stages' queues. 2421060SN/A fetch.setFetchQueue(&fetchQueue); 2431060SN/A decode.setFetchQueue(&fetchQueue); 2442292SN/A commit.setFetchQueue(&fetchQueue); 2451060SN/A decode.setDecodeQueue(&decodeQueue); 2461060SN/A rename.setDecodeQueue(&decodeQueue); 2471060SN/A rename.setRenameQueue(&renameQueue); 2481060SN/A iew.setRenameQueue(&renameQueue); 2491060SN/A iew.setIEWQueue(&iewQueue); 2501060SN/A commit.setIEWQueue(&iewQueue); 2511060SN/A commit.setRenameQueue(&renameQueue); 2521060SN/A 2532292SN/A commit.setIEWStage(&iew); 2542292SN/A rename.setIEWStage(&iew); 2552292SN/A rename.setCommitStage(&commit); 2562292SN/A 2572292SN/A#if !FULL_SYSTEM 2582307SN/A int active_threads = params->workload.size(); 2592831Sksewell@umich.edu 2602831Sksewell@umich.edu if (active_threads > Impl::MaxThreads) { 2612831Sksewell@umich.edu panic("Workload Size too large. Increase the 'MaxThreads'" 2622831Sksewell@umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2632831Sksewell@umich.edu "edit your workload size."); 2642831Sksewell@umich.edu } 2652292SN/A#else 2662307SN/A int active_threads = 1; 2672292SN/A#endif 2682292SN/A 2692316SN/A //Make Sure That this a Valid Architeture 2702292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2712292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2722292SN/A 2732292SN/A rename.setScoreboard(&scoreboard); 2742292SN/A iew.setScoreboard(&scoreboard); 2752292SN/A 2761060SN/A // Setup the rename map for whichever stages need it. 2772292SN/A PhysRegIndex lreg_idx = 0; 2782292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2791060SN/A 2802292SN/A for (int tid=0; tid < numThreads; tid++) { 2812307SN/A bool bindRegs = (tid <= active_threads - 1); 2822292SN/A 2832292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2842292SN/A params->numPhysIntRegs, 2852325SN/A lreg_idx, //Index for Logical. Regs 2862292SN/A 2872292SN/A TheISA::NumFloatRegs, 2882292SN/A params->numPhysFloatRegs, 2892325SN/A freg_idx, //Index for Float Regs 2902292SN/A 2912292SN/A TheISA::NumMiscRegs, 2922292SN/A 2932292SN/A TheISA::ZeroReg, 2942292SN/A TheISA::ZeroReg, 2952292SN/A 2962292SN/A tid, 2972292SN/A false); 2982292SN/A 2992292SN/A renameMap[tid].init(TheISA::NumIntRegs, 3002292SN/A params->numPhysIntRegs, 3012325SN/A lreg_idx, //Index for Logical. Regs 3022292SN/A 3032292SN/A TheISA::NumFloatRegs, 3042292SN/A params->numPhysFloatRegs, 3052325SN/A freg_idx, //Index for Float Regs 3062292SN/A 3072292SN/A TheISA::NumMiscRegs, 3082292SN/A 3092292SN/A TheISA::ZeroReg, 3102292SN/A TheISA::ZeroReg, 3112292SN/A 3122292SN/A tid, 3132292SN/A bindRegs); 3143221Sktlim@umich.edu 3153221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3163221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3172292SN/A } 3182292SN/A 3192292SN/A rename.setRenameMap(renameMap); 3202292SN/A commit.setRenameMap(commitRenameMap); 3212292SN/A 3222292SN/A // Give renameMap & rename stage access to the freeList; 3232292SN/A for (int i=0; i < numThreads; i++) { 3242292SN/A renameMap[i].setFreeList(&freeList); 3252292SN/A } 3261060SN/A rename.setFreeList(&freeList); 3272292SN/A 3281060SN/A // Setup the ROB for whichever stages need it. 3291060SN/A commit.setROB(&rob); 3302292SN/A 3312292SN/A lastRunningCycle = curTick; 3322292SN/A 3332829Sksewell@umich.edu lastActivatedCycle = -1; 3342829Sksewell@umich.edu 3353093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3363093Sksewell@umich.edu //for (int i=0; i < numThreads; i++) { 3373093Sksewell@umich.edu //globalSeqNum[i] = 1; 3383093Sksewell@umich.edu //} 3393093Sksewell@umich.edu 3402292SN/A contextSwitch = false; 3411060SN/A} 3421060SN/A 3431060SN/Atemplate <class Impl> 3441755SN/AFullO3CPU<Impl>::~FullO3CPU() 3451060SN/A{ 3461060SN/A} 3471060SN/A 3481060SN/Atemplate <class Impl> 3491060SN/Avoid 3501755SN/AFullO3CPU<Impl>::fullCPURegStats() 3511062SN/A{ 3522733Sktlim@umich.edu BaseO3CPU::regStats(); 3532292SN/A 3542733Sktlim@umich.edu // Register any of the O3CPU's stats here. 3552292SN/A timesIdled 3562292SN/A .name(name() + ".timesIdled") 3572292SN/A .desc("Number of times that the entire CPU went into an idle state and" 3582292SN/A " unscheduled itself") 3592292SN/A .prereq(timesIdled); 3602292SN/A 3612292SN/A idleCycles 3622292SN/A .name(name() + ".idleCycles") 3632292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 3642292SN/A "to idling") 3652292SN/A .prereq(idleCycles); 3662292SN/A 3672292SN/A // Number of Instructions simulated 3682292SN/A // -------------------------------- 3692292SN/A // Should probably be in Base CPU but need templated 3702292SN/A // MaxThreads so put in here instead 3712292SN/A committedInsts 3722292SN/A .init(numThreads) 3732292SN/A .name(name() + ".committedInsts") 3742292SN/A .desc("Number of Instructions Simulated"); 3752292SN/A 3762292SN/A totalCommittedInsts 3772292SN/A .name(name() + ".committedInsts_total") 3782292SN/A .desc("Number of Instructions Simulated"); 3792292SN/A 3802292SN/A cpi 3812292SN/A .name(name() + ".cpi") 3822292SN/A .desc("CPI: Cycles Per Instruction") 3832292SN/A .precision(6); 3844392Sktlim@umich.edu cpi = numCycles / committedInsts; 3852292SN/A 3862292SN/A totalCpi 3872292SN/A .name(name() + ".cpi_total") 3882292SN/A .desc("CPI: Total CPI of All Threads") 3892292SN/A .precision(6); 3904392Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 3912292SN/A 3922292SN/A ipc 3932292SN/A .name(name() + ".ipc") 3942292SN/A .desc("IPC: Instructions Per Cycle") 3952292SN/A .precision(6); 3964392Sktlim@umich.edu ipc = committedInsts / numCycles; 3972292SN/A 3982292SN/A totalIpc 3992292SN/A .name(name() + ".ipc_total") 4002292SN/A .desc("IPC: Total IPC of All Threads") 4012292SN/A .precision(6); 4024392Sktlim@umich.edu totalIpc = totalCommittedInsts / numCycles; 4032292SN/A 4041062SN/A} 4051062SN/A 4061062SN/Atemplate <class Impl> 4072871Sktlim@umich.eduPort * 4082871Sktlim@umich.eduFullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 4092871Sktlim@umich.edu{ 4102871Sktlim@umich.edu if (if_name == "dcache_port") 4112871Sktlim@umich.edu return iew.getDcachePort(); 4122871Sktlim@umich.edu else if (if_name == "icache_port") 4132871Sktlim@umich.edu return fetch.getIcachePort(); 4142871Sktlim@umich.edu else 4152871Sktlim@umich.edu panic("No Such Port\n"); 4162871Sktlim@umich.edu} 4172871Sktlim@umich.edu 4182871Sktlim@umich.edutemplate <class Impl> 4191062SN/Avoid 4201755SN/AFullO3CPU<Impl>::tick() 4211060SN/A{ 4222733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 4231060SN/A 4242292SN/A ++numCycles; 4252292SN/A 4262325SN/A// activity = false; 4272292SN/A 4282292SN/A //Tick each of the stages 4291060SN/A fetch.tick(); 4301060SN/A 4311060SN/A decode.tick(); 4321060SN/A 4331060SN/A rename.tick(); 4341060SN/A 4351060SN/A iew.tick(); 4361060SN/A 4371060SN/A commit.tick(); 4381060SN/A 4392292SN/A#if !FULL_SYSTEM 4402292SN/A doContextSwitch(); 4412292SN/A#endif 4422292SN/A 4432292SN/A // Now advance the time buffers 4441060SN/A timeBuffer.advance(); 4451060SN/A 4461060SN/A fetchQueue.advance(); 4471060SN/A decodeQueue.advance(); 4481060SN/A renameQueue.advance(); 4491060SN/A iewQueue.advance(); 4501060SN/A 4512325SN/A activityRec.advance(); 4522292SN/A 4532292SN/A if (removeInstsThisCycle) { 4542292SN/A cleanUpRemovedInsts(); 4552292SN/A } 4562292SN/A 4572325SN/A if (!tickEvent.scheduled()) { 4582867Sktlim@umich.edu if (_status == SwitchedOut || 4592905Sktlim@umich.edu getState() == SimObject::Drained) { 4603226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 4612325SN/A // increment stat 4622325SN/A lastRunningCycle = curTick; 4633221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 4643226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 4652325SN/A lastRunningCycle = curTick; 4662325SN/A timesIdled++; 4672325SN/A } else { 4685100Ssaidi@eecs.umich.edu tickEvent.schedule(nextCycle(curTick + ticks(1))); 4693226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 4702325SN/A } 4712292SN/A } 4722292SN/A 4732292SN/A#if !FULL_SYSTEM 4742292SN/A updateThreadPriority(); 4752292SN/A#endif 4762292SN/A 4771060SN/A} 4781060SN/A 4791060SN/Atemplate <class Impl> 4801060SN/Avoid 4811755SN/AFullO3CPU<Impl>::init() 4821060SN/A{ 4832307SN/A if (!deferRegistration) { 4842680Sktlim@umich.edu registerThreadContexts(); 4852292SN/A } 4861060SN/A 4872292SN/A // Set inSyscall so that the CPU doesn't squash when initially 4882292SN/A // setting up registers. 4892292SN/A for (int i = 0; i < number_of_threads; ++i) 4902292SN/A thread[i]->inSyscall = true; 4912292SN/A 4922292SN/A for (int tid=0; tid < number_of_threads; tid++) { 4931858SN/A#if FULL_SYSTEM 4942680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 4951681SN/A#else 4962680Sktlim@umich.edu ThreadContext *src_tc = thread[tid]->getTC(); 4971681SN/A#endif 4982292SN/A // Threads start in the Suspended State 4992680Sktlim@umich.edu if (src_tc->status() != ThreadContext::Suspended) { 5002292SN/A continue; 5011060SN/A } 5021060SN/A 5032292SN/A#if FULL_SYSTEM 5042680Sktlim@umich.edu TheISA::initCPU(src_tc, src_tc->readCpuId()); 5052292SN/A#endif 5062292SN/A } 5072292SN/A 5082292SN/A // Clear inSyscall. 5092292SN/A for (int i = 0; i < number_of_threads; ++i) 5102292SN/A thread[i]->inSyscall = false; 5112292SN/A 5122316SN/A // Initialize stages. 5132292SN/A fetch.initStage(); 5142292SN/A iew.initStage(); 5152292SN/A rename.initStage(); 5162292SN/A commit.initStage(); 5172292SN/A 5182292SN/A commit.setThreads(thread); 5192292SN/A} 5202292SN/A 5212292SN/Atemplate <class Impl> 5222292SN/Avoid 5232875Sksewell@umich.eduFullO3CPU<Impl>::activateThread(unsigned tid) 5242875Sksewell@umich.edu{ 5255314Sstever@gmail.com std::list<unsigned>::iterator isActive = 5265314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 5272875Sksewell@umich.edu 5283226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 5293226Sktlim@umich.edu 5302875Sksewell@umich.edu if (isActive == activeThreads.end()) { 5312875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 5322875Sksewell@umich.edu tid); 5332875Sksewell@umich.edu 5342875Sksewell@umich.edu activeThreads.push_back(tid); 5352875Sksewell@umich.edu } 5362875Sksewell@umich.edu} 5372875Sksewell@umich.edu 5382875Sksewell@umich.edutemplate <class Impl> 5392875Sksewell@umich.eduvoid 5402875Sksewell@umich.eduFullO3CPU<Impl>::deactivateThread(unsigned tid) 5412875Sksewell@umich.edu{ 5422875Sksewell@umich.edu //Remove From Active List, if Active 5435314Sstever@gmail.com std::list<unsigned>::iterator thread_it = 5445314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 5452875Sksewell@umich.edu 5463226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 5473226Sktlim@umich.edu 5482875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 5492875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 5502875Sksewell@umich.edu tid); 5512875Sksewell@umich.edu activeThreads.erase(thread_it); 5522875Sksewell@umich.edu } 5532875Sksewell@umich.edu} 5542875Sksewell@umich.edu 5552875Sksewell@umich.edutemplate <class Impl> 5562875Sksewell@umich.eduvoid 5572875Sksewell@umich.eduFullO3CPU<Impl>::activateContext(int tid, int delay) 5582875Sksewell@umich.edu{ 5592875Sksewell@umich.edu // Needs to set each stage to running as well. 5602875Sksewell@umich.edu if (delay){ 5612875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 5625100Ssaidi@eecs.umich.edu "on cycle %d\n", tid, curTick + ticks(delay)); 5632875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 5642875Sksewell@umich.edu } else { 5652875Sksewell@umich.edu activateThread(tid); 5662875Sksewell@umich.edu } 5672875Sksewell@umich.edu 5683221Sktlim@umich.edu if (lastActivatedCycle < curTick) { 5692875Sksewell@umich.edu scheduleTickEvent(delay); 5702875Sksewell@umich.edu 5712875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 5722875Sksewell@umich.edu // deschedule itself. 5732875Sksewell@umich.edu activityRec.activity(); 5742875Sksewell@umich.edu fetch.wakeFromQuiesce(); 5752875Sksewell@umich.edu 5762875Sksewell@umich.edu lastActivatedCycle = curTick; 5772875Sksewell@umich.edu 5782875Sksewell@umich.edu _status = Running; 5792875Sksewell@umich.edu } 5802875Sksewell@umich.edu} 5812875Sksewell@umich.edu 5822875Sksewell@umich.edutemplate <class Impl> 5833221Sktlim@umich.edubool 5843221Sktlim@umich.eduFullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay) 5852875Sksewell@umich.edu{ 5862875Sksewell@umich.edu // Schedule removal of thread data from CPU 5872875Sksewell@umich.edu if (delay){ 5882875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 5895100Ssaidi@eecs.umich.edu "on cycle %d\n", tid, curTick + ticks(delay)); 5903221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 5913221Sktlim@umich.edu return false; 5922875Sksewell@umich.edu } else { 5932875Sksewell@umich.edu deactivateThread(tid); 5943221Sktlim@umich.edu if (remove) 5953221Sktlim@umich.edu removeThread(tid); 5963221Sktlim@umich.edu return true; 5972875Sksewell@umich.edu } 5982875Sksewell@umich.edu} 5992875Sksewell@umich.edu 6002875Sksewell@umich.edutemplate <class Impl> 6012875Sksewell@umich.eduvoid 6022875Sksewell@umich.eduFullO3CPU<Impl>::suspendContext(int tid) 6032875Sksewell@umich.edu{ 6042875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 6053221Sktlim@umich.edu bool deallocated = deallocateContext(tid, false, 1); 6063221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 6075570Snate@binkert.org if ((activeThreads.size() == 1 && !deallocated) || 6083859Sbinkertn@umich.edu activeThreads.size() == 0) 6092910Sksewell@umich.edu unscheduleTickEvent(); 6102875Sksewell@umich.edu _status = Idle; 6112875Sksewell@umich.edu} 6122875Sksewell@umich.edu 6132875Sksewell@umich.edutemplate <class Impl> 6142875Sksewell@umich.eduvoid 6152875Sksewell@umich.eduFullO3CPU<Impl>::haltContext(int tid) 6162875Sksewell@umich.edu{ 6172910Sksewell@umich.edu //For now, this is the same as deallocate 6182910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 6193221Sktlim@umich.edu deallocateContext(tid, true, 1); 6202875Sksewell@umich.edu} 6212875Sksewell@umich.edu 6222875Sksewell@umich.edutemplate <class Impl> 6232875Sksewell@umich.eduvoid 6242292SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 6252292SN/A{ 6262847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 6272292SN/A // Will change now that the PC and thread state is internal to the CPU 6282683Sktlim@umich.edu // and not in the ThreadContext. 6292292SN/A#if FULL_SYSTEM 6302680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 6312292SN/A#else 6322847Sksewell@umich.edu ThreadContext *src_tc = tcBase(tid); 6332292SN/A#endif 6342292SN/A 6352292SN/A //Bind Int Regs to Rename Map 6362292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 6372292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 6382292SN/A 6392292SN/A renameMap[tid].setEntry(ireg,phys_reg); 6402292SN/A scoreboard.setReg(phys_reg); 6412292SN/A } 6422292SN/A 6432292SN/A //Bind Float Regs to Rename Map 6442292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 6452292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 6462292SN/A 6472292SN/A renameMap[tid].setEntry(freg,phys_reg); 6482292SN/A scoreboard.setReg(phys_reg); 6492292SN/A } 6502292SN/A 6512292SN/A //Copy Thread Data Into RegFile 6522847Sksewell@umich.edu //this->copyFromTC(tid); 6532292SN/A 6542847Sksewell@umich.edu //Set PC/NPC/NNPC 6552847Sksewell@umich.edu setPC(src_tc->readPC(), tid); 6562847Sksewell@umich.edu setNextPC(src_tc->readNextPC(), tid); 6572847Sksewell@umich.edu setNextNPC(src_tc->readNextNPC(), tid); 6582292SN/A 6592680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 6602292SN/A 6612292SN/A activateContext(tid,1); 6622292SN/A 6632292SN/A //Reset ROB/IQ/LSQ Entries 6642292SN/A commit.rob->resetEntries(); 6652292SN/A iew.resetEntries(); 6662292SN/A} 6672292SN/A 6682292SN/Atemplate <class Impl> 6692292SN/Avoid 6702292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 6712292SN/A{ 6722877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 6732847Sksewell@umich.edu 6742847Sksewell@umich.edu // Copy Thread Data From RegFile 6752847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 6765364Sksewell@umich.edu // this->copyToTC(tid); 6775364Sksewell@umich.edu 6785364Sksewell@umich.edu 6795364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 6805364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 6815364Sksewell@umich.edu // in SMT workloads. 6822847Sksewell@umich.edu 6832847Sksewell@umich.edu // Unbind Int Regs from Rename Map 6842292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 6852292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 6862292SN/A 6872292SN/A scoreboard.unsetReg(phys_reg); 6882292SN/A freeList.addReg(phys_reg); 6892292SN/A } 6902292SN/A 6912847Sksewell@umich.edu // Unbind Float Regs from Rename Map 6925362Sksewell@umich.edu for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 6932292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 6942292SN/A 6952292SN/A scoreboard.unsetReg(phys_reg); 6962292SN/A freeList.addReg(phys_reg); 6972292SN/A } 6982292SN/A 6992847Sksewell@umich.edu // Squash Throughout Pipeline 7002935Sksewell@umich.edu InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; 7014636Sgblack@eecs.umich.edu fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid); 7022292SN/A decode.squash(tid); 7032935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 7042875Sksewell@umich.edu iew.squash(tid); 7055363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 7062935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 7072292SN/A 7085362Sksewell@umich.edu 7095362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 7102292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 7112292SN/A 7122847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 7133229Sktlim@umich.edu 7143229Sktlim@umich.edu // Commented out for now. This should be possible to do by 7153229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 7163229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 7173229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 7183229Sktlim@umich.edu/* 7192292SN/A if (activeThreads.size() >= 1) { 7202292SN/A commit.rob->resetEntries(); 7212292SN/A iew.resetEntries(); 7222292SN/A } 7233229Sktlim@umich.edu*/ 7242292SN/A} 7252292SN/A 7262292SN/A 7272292SN/Atemplate <class Impl> 7282292SN/Avoid 7292292SN/AFullO3CPU<Impl>::activateWhenReady(int tid) 7302292SN/A{ 7312733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 7322292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 7332292SN/A tid); 7342292SN/A 7352292SN/A bool ready = true; 7362292SN/A 7372292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 7382733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7392292SN/A "Phys. Int. Regs.\n", 7402292SN/A tid); 7412292SN/A ready = false; 7422292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 7432733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7442292SN/A "Phys. Float. Regs.\n", 7452292SN/A tid); 7462292SN/A ready = false; 7472292SN/A } else if (commit.rob->numFreeEntries() >= 7482292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 7492733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7502292SN/A "ROB entries.\n", 7512292SN/A tid); 7522292SN/A ready = false; 7532292SN/A } else if (iew.instQueue.numFreeEntries() >= 7542292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 7552733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7562292SN/A "IQ entries.\n", 7572292SN/A tid); 7582292SN/A ready = false; 7592292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 7602292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 7612733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7622292SN/A "LSQ entries.\n", 7632292SN/A tid); 7642292SN/A ready = false; 7652292SN/A } 7662292SN/A 7672292SN/A if (ready) { 7682292SN/A insertThread(tid); 7692292SN/A 7702292SN/A contextSwitch = false; 7712292SN/A 7722292SN/A cpuWaitList.remove(tid); 7732292SN/A } else { 7742292SN/A suspendContext(tid); 7752292SN/A 7762292SN/A //blocks fetch 7772292SN/A contextSwitch = true; 7782292SN/A 7792875Sksewell@umich.edu //@todo: dont always add to waitlist 7802292SN/A //do waitlist 7812292SN/A cpuWaitList.push_back(tid); 7821060SN/A } 7831060SN/A} 7841060SN/A 7854192Sktlim@umich.edu#if FULL_SYSTEM 7864192Sktlim@umich.edutemplate <class Impl> 7874192Sktlim@umich.eduvoid 7884192Sktlim@umich.eduFullO3CPU<Impl>::updateMemPorts() 7894192Sktlim@umich.edu{ 7904192Sktlim@umich.edu // Update all ThreadContext's memory ports (Functional/Virtual 7914192Sktlim@umich.edu // Ports) 7924192Sktlim@umich.edu for (int i = 0; i < thread.size(); ++i) 7935497Ssaidi@eecs.umich.edu thread[i]->connectMemPorts(thread[i]->getTC()); 7944192Sktlim@umich.edu} 7954192Sktlim@umich.edu#endif 7964192Sktlim@umich.edu 7971060SN/Atemplate <class Impl> 7982852Sktlim@umich.eduvoid 7992864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 8002864Sktlim@umich.edu{ 8012918Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 8022918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 8032864Sktlim@umich.edu BaseCPU::serialize(os); 8042864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 8052864Sktlim@umich.edu tickEvent.serialize(os); 8062864Sktlim@umich.edu 8072864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 8082864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 8092864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 8102864Sktlim@umich.edu static SimpleThread temp; 8112864Sktlim@umich.edu 8122864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 8132864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 8142864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 8152864Sktlim@umich.edu temp.serialize(os); 8162864Sktlim@umich.edu } 8172864Sktlim@umich.edu} 8182864Sktlim@umich.edu 8192864Sktlim@umich.edutemplate <class Impl> 8202864Sktlim@umich.eduvoid 8212864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 8222864Sktlim@umich.edu{ 8232918Sktlim@umich.edu SimObject::State so_state; 8242918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 8252864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 8262864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 8272864Sktlim@umich.edu 8282864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 8292864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 8302864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 8312864Sktlim@umich.edu static SimpleThread temp; 8322864Sktlim@umich.edu 8332864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 8342864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 8352864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 8362864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 8372864Sktlim@umich.edu } 8382864Sktlim@umich.edu} 8392864Sktlim@umich.edu 8402864Sktlim@umich.edutemplate <class Impl> 8412905Sktlim@umich.eduunsigned int 8422843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 8431060SN/A{ 8443125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 8453512Sktlim@umich.edu 8463512Sktlim@umich.edu // If the CPU isn't doing anything, then return immediately. 8473512Sktlim@umich.edu if (_status == Idle || _status == SwitchedOut) { 8483512Sktlim@umich.edu return 0; 8493512Sktlim@umich.edu } 8503512Sktlim@umich.edu 8512843Sktlim@umich.edu drainCount = 0; 8522843Sktlim@umich.edu fetch.drain(); 8532843Sktlim@umich.edu decode.drain(); 8542843Sktlim@umich.edu rename.drain(); 8552843Sktlim@umich.edu iew.drain(); 8562843Sktlim@umich.edu commit.drain(); 8572325SN/A 8582325SN/A // Wake the CPU and record activity so everything can drain out if 8592863Sktlim@umich.edu // the CPU was not able to immediately drain. 8602905Sktlim@umich.edu if (getState() != SimObject::Drained) { 8612864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 8622864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 8632864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 8642864Sktlim@umich.edu // process on the drain event. 8652864Sktlim@umich.edu drainEvent = drain_event; 8662843Sktlim@umich.edu 8672863Sktlim@umich.edu wakeCPU(); 8682863Sktlim@umich.edu activityRec.activity(); 8692852Sktlim@umich.edu 8702905Sktlim@umich.edu return 1; 8712863Sktlim@umich.edu } else { 8722905Sktlim@umich.edu return 0; 8732863Sktlim@umich.edu } 8742316SN/A} 8752310SN/A 8762316SN/Atemplate <class Impl> 8772316SN/Avoid 8782843Sktlim@umich.eduFullO3CPU<Impl>::resume() 8792316SN/A{ 8802843Sktlim@umich.edu fetch.resume(); 8812843Sktlim@umich.edu decode.resume(); 8822843Sktlim@umich.edu rename.resume(); 8832843Sktlim@umich.edu iew.resume(); 8842843Sktlim@umich.edu commit.resume(); 8852316SN/A 8862905Sktlim@umich.edu changeState(SimObject::Running); 8872905Sktlim@umich.edu 8882864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 8892864Sktlim@umich.edu return; 8902864Sktlim@umich.edu 8913319Shsul@eecs.umich.edu#if FULL_SYSTEM 8924762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 8933319Shsul@eecs.umich.edu#endif 8943319Shsul@eecs.umich.edu 8952843Sktlim@umich.edu if (!tickEvent.scheduled()) 8964030Sktlim@umich.edu tickEvent.schedule(nextCycle()); 8972843Sktlim@umich.edu _status = Running; 8982843Sktlim@umich.edu} 8992316SN/A 9002843Sktlim@umich.edutemplate <class Impl> 9012843Sktlim@umich.eduvoid 9022843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 9032843Sktlim@umich.edu{ 9042843Sktlim@umich.edu if (++drainCount == NumStages) { 9052316SN/A if (tickEvent.scheduled()) 9062316SN/A tickEvent.squash(); 9072863Sktlim@umich.edu 9082905Sktlim@umich.edu changeState(SimObject::Drained); 9092863Sktlim@umich.edu 9103126Sktlim@umich.edu BaseCPU::switchOut(); 9113126Sktlim@umich.edu 9122863Sktlim@umich.edu if (drainEvent) { 9132863Sktlim@umich.edu drainEvent->process(); 9142863Sktlim@umich.edu drainEvent = NULL; 9152863Sktlim@umich.edu } 9162310SN/A } 9172843Sktlim@umich.edu assert(drainCount <= 5); 9182843Sktlim@umich.edu} 9192843Sktlim@umich.edu 9202843Sktlim@umich.edutemplate <class Impl> 9212843Sktlim@umich.eduvoid 9222843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 9232843Sktlim@umich.edu{ 9242843Sktlim@umich.edu fetch.switchOut(); 9252843Sktlim@umich.edu rename.switchOut(); 9262325SN/A iew.switchOut(); 9272843Sktlim@umich.edu commit.switchOut(); 9282843Sktlim@umich.edu instList.clear(); 9292843Sktlim@umich.edu while (!removeList.empty()) { 9302843Sktlim@umich.edu removeList.pop(); 9312843Sktlim@umich.edu } 9322843Sktlim@umich.edu 9332843Sktlim@umich.edu _status = SwitchedOut; 9342843Sktlim@umich.edu#if USE_CHECKER 9352843Sktlim@umich.edu if (checker) 9362843Sktlim@umich.edu checker->switchOut(); 9372843Sktlim@umich.edu#endif 9383126Sktlim@umich.edu if (tickEvent.scheduled()) 9393126Sktlim@umich.edu tickEvent.squash(); 9401060SN/A} 9411060SN/A 9421060SN/Atemplate <class Impl> 9431060SN/Avoid 9441755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 9451060SN/A{ 9462325SN/A // Flush out any old data from the time buffers. 9472873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 9482307SN/A timeBuffer.advance(); 9492307SN/A fetchQueue.advance(); 9502307SN/A decodeQueue.advance(); 9512307SN/A renameQueue.advance(); 9522307SN/A iewQueue.advance(); 9532307SN/A } 9542307SN/A 9552325SN/A activityRec.reset(); 9562307SN/A 9574192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort()); 9581060SN/A 9592307SN/A fetch.takeOverFrom(); 9602307SN/A decode.takeOverFrom(); 9612307SN/A rename.takeOverFrom(); 9622307SN/A iew.takeOverFrom(); 9632307SN/A commit.takeOverFrom(); 9642307SN/A 9651060SN/A assert(!tickEvent.scheduled()); 9661060SN/A 9672325SN/A // @todo: Figure out how to properly select the tid to put onto 9682325SN/A // the active threads list. 9692307SN/A int tid = 0; 9702307SN/A 9715314Sstever@gmail.com std::list<unsigned>::iterator isActive = 9725314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 9732307SN/A 9742307SN/A if (isActive == activeThreads.end()) { 9752325SN/A //May Need to Re-code this if the delay variable is the delay 9762325SN/A //needed for thread to activate 9772733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 9782307SN/A tid); 9792307SN/A 9802307SN/A activeThreads.push_back(tid); 9812307SN/A } 9822307SN/A 9832325SN/A // Set all statuses to active, schedule the CPU's tick event. 9842307SN/A // @todo: Fix up statuses so this is handled properly 9852680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 9862680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 9872680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 9881681SN/A _status = Running; 9894030Sktlim@umich.edu tickEvent.schedule(nextCycle()); 9901681SN/A } 9911060SN/A } 9922307SN/A if (!tickEvent.scheduled()) 9934030Sktlim@umich.edu tickEvent.schedule(nextCycle()); 9941060SN/A} 9951060SN/A 9961060SN/Atemplate <class Impl> 9971060SN/Auint64_t 9981755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 9991060SN/A{ 10001060SN/A return regFile.readIntReg(reg_idx); 10011060SN/A} 10021060SN/A 10031060SN/Atemplate <class Impl> 10042455SN/AFloatReg 10052455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 10061060SN/A{ 10072455SN/A return regFile.readFloatReg(reg_idx, width); 10081060SN/A} 10091060SN/A 10101060SN/Atemplate <class Impl> 10112455SN/AFloatReg 10122455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 10131060SN/A{ 10142455SN/A return regFile.readFloatReg(reg_idx); 10151060SN/A} 10161060SN/A 10171060SN/Atemplate <class Impl> 10182455SN/AFloatRegBits 10192455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 10201060SN/A{ 10212455SN/A return regFile.readFloatRegBits(reg_idx, width); 10222455SN/A} 10232455SN/A 10242455SN/Atemplate <class Impl> 10252455SN/AFloatRegBits 10262455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 10272455SN/A{ 10282455SN/A return regFile.readFloatRegBits(reg_idx); 10291060SN/A} 10301060SN/A 10311060SN/Atemplate <class Impl> 10321060SN/Avoid 10331755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 10341060SN/A{ 10351060SN/A regFile.setIntReg(reg_idx, val); 10361060SN/A} 10371060SN/A 10381060SN/Atemplate <class Impl> 10391060SN/Avoid 10402455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 10411060SN/A{ 10422455SN/A regFile.setFloatReg(reg_idx, val, width); 10431060SN/A} 10441060SN/A 10451060SN/Atemplate <class Impl> 10461060SN/Avoid 10472455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 10481060SN/A{ 10492455SN/A regFile.setFloatReg(reg_idx, val); 10501060SN/A} 10511060SN/A 10521060SN/Atemplate <class Impl> 10531060SN/Avoid 10542455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 10551060SN/A{ 10562455SN/A regFile.setFloatRegBits(reg_idx, val, width); 10572455SN/A} 10582455SN/A 10592455SN/Atemplate <class Impl> 10602455SN/Avoid 10612455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 10622455SN/A{ 10632455SN/A regFile.setFloatRegBits(reg_idx, val); 10641060SN/A} 10651060SN/A 10661060SN/Atemplate <class Impl> 10671060SN/Auint64_t 10682292SN/AFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 10691060SN/A{ 10702292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10712292SN/A 10722292SN/A return regFile.readIntReg(phys_reg); 10732292SN/A} 10742292SN/A 10752292SN/Atemplate <class Impl> 10762292SN/Afloat 10772292SN/AFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 10782292SN/A{ 10792307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 10802307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10812292SN/A 10822669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 10832292SN/A} 10842292SN/A 10852292SN/Atemplate <class Impl> 10862292SN/Adouble 10872292SN/AFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 10882292SN/A{ 10892307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 10902307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10912292SN/A 10922669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 10932292SN/A} 10942292SN/A 10952292SN/Atemplate <class Impl> 10962292SN/Auint64_t 10972292SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 10982292SN/A{ 10992307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 11002307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 11012292SN/A 11022669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 11031060SN/A} 11041060SN/A 11051060SN/Atemplate <class Impl> 11061060SN/Avoid 11072292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 11081060SN/A{ 11092292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 11102292SN/A 11112292SN/A regFile.setIntReg(phys_reg, val); 11121060SN/A} 11131060SN/A 11141060SN/Atemplate <class Impl> 11151060SN/Avoid 11162292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 11171060SN/A{ 11182918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 11192918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 11202292SN/A 11212669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 11221060SN/A} 11231060SN/A 11241060SN/Atemplate <class Impl> 11251060SN/Avoid 11262292SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 11271060SN/A{ 11282918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 11292918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 11302292SN/A 11312669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 11321060SN/A} 11331060SN/A 11341060SN/Atemplate <class Impl> 11351060SN/Avoid 11362292SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 11371060SN/A{ 11382918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 11392918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 11401060SN/A 11412669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 11422292SN/A} 11432292SN/A 11442292SN/Atemplate <class Impl> 11452292SN/Auint64_t 11462292SN/AFullO3CPU<Impl>::readPC(unsigned tid) 11472292SN/A{ 11482292SN/A return commit.readPC(tid); 11491060SN/A} 11501060SN/A 11511060SN/Atemplate <class Impl> 11521060SN/Avoid 11532292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 11541060SN/A{ 11552292SN/A commit.setPC(new_PC, tid); 11562292SN/A} 11571060SN/A 11582292SN/Atemplate <class Impl> 11592292SN/Auint64_t 11604636Sgblack@eecs.umich.eduFullO3CPU<Impl>::readMicroPC(unsigned tid) 11614636Sgblack@eecs.umich.edu{ 11624636Sgblack@eecs.umich.edu return commit.readMicroPC(tid); 11634636Sgblack@eecs.umich.edu} 11644636Sgblack@eecs.umich.edu 11654636Sgblack@eecs.umich.edutemplate <class Impl> 11664636Sgblack@eecs.umich.eduvoid 11674636Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMicroPC(Addr new_PC,unsigned tid) 11684636Sgblack@eecs.umich.edu{ 11694636Sgblack@eecs.umich.edu commit.setMicroPC(new_PC, tid); 11704636Sgblack@eecs.umich.edu} 11714636Sgblack@eecs.umich.edu 11724636Sgblack@eecs.umich.edutemplate <class Impl> 11734636Sgblack@eecs.umich.eduuint64_t 11742292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 11752292SN/A{ 11762292SN/A return commit.readNextPC(tid); 11772292SN/A} 11781060SN/A 11792292SN/Atemplate <class Impl> 11802292SN/Avoid 11812292SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 11822292SN/A{ 11832292SN/A commit.setNextPC(val, tid); 11842292SN/A} 11851060SN/A 11862756Sksewell@umich.edutemplate <class Impl> 11872756Sksewell@umich.eduuint64_t 11882756Sksewell@umich.eduFullO3CPU<Impl>::readNextNPC(unsigned tid) 11892756Sksewell@umich.edu{ 11902756Sksewell@umich.edu return commit.readNextNPC(tid); 11912756Sksewell@umich.edu} 11922756Sksewell@umich.edu 11932756Sksewell@umich.edutemplate <class Impl> 11942756Sksewell@umich.eduvoid 11952935Sksewell@umich.eduFullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid) 11962756Sksewell@umich.edu{ 11972756Sksewell@umich.edu commit.setNextNPC(val, tid); 11982756Sksewell@umich.edu} 11992756Sksewell@umich.edu 12002292SN/Atemplate <class Impl> 12014636Sgblack@eecs.umich.eduuint64_t 12024636Sgblack@eecs.umich.eduFullO3CPU<Impl>::readNextMicroPC(unsigned tid) 12034636Sgblack@eecs.umich.edu{ 12044636Sgblack@eecs.umich.edu return commit.readNextMicroPC(tid); 12054636Sgblack@eecs.umich.edu} 12064636Sgblack@eecs.umich.edu 12074636Sgblack@eecs.umich.edutemplate <class Impl> 12084636Sgblack@eecs.umich.eduvoid 12094636Sgblack@eecs.umich.eduFullO3CPU<Impl>::setNextMicroPC(Addr new_PC,unsigned tid) 12104636Sgblack@eecs.umich.edu{ 12114636Sgblack@eecs.umich.edu commit.setNextMicroPC(new_PC, tid); 12124636Sgblack@eecs.umich.edu} 12134636Sgblack@eecs.umich.edu 12144636Sgblack@eecs.umich.edutemplate <class Impl> 12152292SN/Atypename FullO3CPU<Impl>::ListIt 12162292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 12172292SN/A{ 12182292SN/A instList.push_back(inst); 12191060SN/A 12202292SN/A return --(instList.end()); 12212292SN/A} 12221060SN/A 12232292SN/Atemplate <class Impl> 12242292SN/Avoid 12252292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 12262292SN/A{ 12272292SN/A // Keep an instruction count. 12282292SN/A thread[tid]->numInst++; 12292292SN/A thread[tid]->numInsts++; 12302292SN/A committedInsts[tid]++; 12312292SN/A totalCommittedInsts++; 12322292SN/A 12332292SN/A // Check for instruction-count-based events. 12342292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 12352292SN/A} 12362292SN/A 12372292SN/Atemplate <class Impl> 12382292SN/Avoid 12392292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 12402292SN/A{ 12412292SN/A removeInstsThisCycle = true; 12422292SN/A 12432292SN/A removeList.push(inst->getInstListIt()); 12441060SN/A} 12451060SN/A 12461060SN/Atemplate <class Impl> 12471060SN/Avoid 12481755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 12491060SN/A{ 12502733Sktlim@umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 12512292SN/A "[sn:%lli]\n", 12522303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 12531060SN/A 12542292SN/A removeInstsThisCycle = true; 12551060SN/A 12561060SN/A // Remove the front instruction. 12572292SN/A removeList.push(inst->getInstListIt()); 12581060SN/A} 12591060SN/A 12601060SN/Atemplate <class Impl> 12611060SN/Avoid 12624632Sgblack@eecs.umich.eduFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 12631060SN/A{ 12642733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 12652292SN/A " list.\n", tid); 12661060SN/A 12672292SN/A ListIt end_it; 12681060SN/A 12692292SN/A bool rob_empty = false; 12702292SN/A 12712292SN/A if (instList.empty()) { 12722292SN/A return; 12732292SN/A } else if (rob.isEmpty(/*tid*/)) { 12742733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 12752292SN/A end_it = instList.begin(); 12762292SN/A rob_empty = true; 12772292SN/A } else { 12782292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 12792733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 12802292SN/A } 12812292SN/A 12822292SN/A removeInstsThisCycle = true; 12832292SN/A 12842292SN/A ListIt inst_it = instList.end(); 12852292SN/A 12862292SN/A inst_it--; 12872292SN/A 12882292SN/A // Walk through the instruction list, removing any instructions 12892292SN/A // that were inserted after the given instruction iterator, end_it. 12902292SN/A while (inst_it != end_it) { 12912292SN/A assert(!instList.empty()); 12922292SN/A 12932292SN/A squashInstIt(inst_it, tid); 12942292SN/A 12952292SN/A inst_it--; 12962292SN/A } 12972292SN/A 12982292SN/A // If the ROB was empty, then we actually need to remove the first 12992292SN/A // instruction as well. 13002292SN/A if (rob_empty) { 13012292SN/A squashInstIt(inst_it, tid); 13022292SN/A } 13031060SN/A} 13041060SN/A 13051060SN/Atemplate <class Impl> 13061060SN/Avoid 13072292SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 13082292SN/A unsigned tid) 13091062SN/A{ 13102292SN/A assert(!instList.empty()); 13112292SN/A 13122292SN/A removeInstsThisCycle = true; 13132292SN/A 13142292SN/A ListIt inst_iter = instList.end(); 13152292SN/A 13162292SN/A inst_iter--; 13172292SN/A 13182733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 13192292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 13202292SN/A tid, seq_num, (*inst_iter)->seqNum); 13211062SN/A 13222292SN/A while ((*inst_iter)->seqNum > seq_num) { 13231062SN/A 13242292SN/A bool break_loop = (inst_iter == instList.begin()); 13251062SN/A 13262292SN/A squashInstIt(inst_iter, tid); 13271062SN/A 13282292SN/A inst_iter--; 13291062SN/A 13302292SN/A if (break_loop) 13312292SN/A break; 13322292SN/A } 13332292SN/A} 13342292SN/A 13352292SN/Atemplate <class Impl> 13362292SN/Ainline void 13372292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 13382292SN/A{ 13392292SN/A if ((*instIt)->threadNumber == tid) { 13402733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 13412292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 13422292SN/A (*instIt)->threadNumber, 13432292SN/A (*instIt)->seqNum, 13442292SN/A (*instIt)->readPC()); 13451062SN/A 13461062SN/A // Mark it as squashed. 13472292SN/A (*instIt)->setSquashed(); 13482292SN/A 13492325SN/A // @todo: Formulate a consistent method for deleting 13502325SN/A // instructions from the instruction list 13512292SN/A // Remove the instruction from the list. 13522292SN/A removeList.push(instIt); 13532292SN/A } 13542292SN/A} 13552292SN/A 13562292SN/Atemplate <class Impl> 13572292SN/Avoid 13582292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 13592292SN/A{ 13602292SN/A while (!removeList.empty()) { 13612733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 13622292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 13632292SN/A (*removeList.front())->threadNumber, 13642292SN/A (*removeList.front())->seqNum, 13652292SN/A (*removeList.front())->readPC()); 13662292SN/A 13672292SN/A instList.erase(removeList.front()); 13682292SN/A 13692292SN/A removeList.pop(); 13701062SN/A } 13711062SN/A 13722292SN/A removeInstsThisCycle = false; 13731062SN/A} 13742325SN/A/* 13751062SN/Atemplate <class Impl> 13761062SN/Avoid 13771755SN/AFullO3CPU<Impl>::removeAllInsts() 13781060SN/A{ 13791060SN/A instList.clear(); 13801060SN/A} 13812325SN/A*/ 13821060SN/Atemplate <class Impl> 13831060SN/Avoid 13841755SN/AFullO3CPU<Impl>::dumpInsts() 13851060SN/A{ 13861060SN/A int num = 0; 13871060SN/A 13882292SN/A ListIt inst_list_it = instList.begin(); 13892292SN/A 13902292SN/A cprintf("Dumping Instruction List\n"); 13912292SN/A 13922292SN/A while (inst_list_it != instList.end()) { 13932292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 13942292SN/A "Squashed:%i\n\n", 13952292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 13962292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 13972292SN/A (*inst_list_it)->isSquashed()); 13981060SN/A inst_list_it++; 13991060SN/A ++num; 14001060SN/A } 14011060SN/A} 14022325SN/A/* 14031060SN/Atemplate <class Impl> 14041060SN/Avoid 14051755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 14061060SN/A{ 14071060SN/A iew.wakeDependents(inst); 14081060SN/A} 14092325SN/A*/ 14102292SN/Atemplate <class Impl> 14112292SN/Avoid 14122292SN/AFullO3CPU<Impl>::wakeCPU() 14132292SN/A{ 14142325SN/A if (activityRec.active() || tickEvent.scheduled()) { 14152325SN/A DPRINTF(Activity, "CPU already running.\n"); 14162292SN/A return; 14172292SN/A } 14182292SN/A 14192325SN/A DPRINTF(Activity, "Waking up CPU\n"); 14202325SN/A 14215099Ssaidi@eecs.umich.edu idleCycles += tickToCycles((curTick - 1) - lastRunningCycle); 14225099Ssaidi@eecs.umich.edu numCycles += tickToCycles((curTick - 1) - lastRunningCycle); 14232292SN/A 14244030Sktlim@umich.edu tickEvent.schedule(nextCycle()); 14252292SN/A} 14262292SN/A 14272292SN/Atemplate <class Impl> 14282292SN/Aint 14292292SN/AFullO3CPU<Impl>::getFreeTid() 14302292SN/A{ 14312292SN/A for (int i=0; i < numThreads; i++) { 14322292SN/A if (!tids[i]) { 14332292SN/A tids[i] = true; 14342292SN/A return i; 14352292SN/A } 14362292SN/A } 14372292SN/A 14382292SN/A return -1; 14392292SN/A} 14402292SN/A 14412292SN/Atemplate <class Impl> 14422292SN/Avoid 14432292SN/AFullO3CPU<Impl>::doContextSwitch() 14442292SN/A{ 14452292SN/A if (contextSwitch) { 14462292SN/A 14472292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 14482292SN/A 14492292SN/A for (int tid=0; tid < cpuWaitList.size(); tid++) { 14502292SN/A activateWhenReady(tid); 14512292SN/A } 14522292SN/A 14532292SN/A if (cpuWaitList.size() == 0) 14542292SN/A contextSwitch = true; 14552292SN/A } 14562292SN/A} 14572292SN/A 14582292SN/Atemplate <class Impl> 14592292SN/Avoid 14602292SN/AFullO3CPU<Impl>::updateThreadPriority() 14612292SN/A{ 14622292SN/A if (activeThreads.size() > 1) 14632292SN/A { 14642292SN/A //DEFAULT TO ROUND ROBIN SCHEME 14652292SN/A //e.g. Move highest priority to end of thread list 14665314Sstever@gmail.com std::list<unsigned>::iterator list_begin = activeThreads.begin(); 14675314Sstever@gmail.com std::list<unsigned>::iterator list_end = activeThreads.end(); 14682292SN/A 14692292SN/A unsigned high_thread = *list_begin; 14702292SN/A 14712292SN/A activeThreads.erase(list_begin); 14722292SN/A 14732292SN/A activeThreads.push_back(high_thread); 14742292SN/A } 14752292SN/A} 14761060SN/A 14771755SN/A// Forward declaration of FullO3CPU. 14782818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1479