cpu.cc revision 5497
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 341858SN/A 354762Snate@binkert.org#include "cpu/activity.hh" 364762Snate@binkert.org#include "cpu/simple_thread.hh" 374762Snate@binkert.org#include "cpu/thread_context.hh" 384762Snate@binkert.org#include "cpu/o3/isa_specific.hh" 394762Snate@binkert.org#include "cpu/o3/cpu.hh" 404762Snate@binkert.org#include "enums/MemoryMode.hh" 414762Snate@binkert.org#include "sim/core.hh" 424762Snate@binkert.org#include "sim/stat_control.hh" 434762Snate@binkert.org 441858SN/A#if FULL_SYSTEM 452356SN/A#include "cpu/quiesce_event.hh" 461060SN/A#include "sim/system.hh" 471060SN/A#else 481060SN/A#include "sim/process.hh" 491060SN/A#endif 501060SN/A 512794Sktlim@umich.edu#if USE_CHECKER 522794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 532794Sktlim@umich.edu#endif 542794Sktlim@umich.edu 552669Sktlim@umich.eduusing namespace TheISA; 561060SN/A 572733Sktlim@umich.eduBaseO3CPU::BaseO3CPU(Params *params) 582292SN/A : BaseCPU(params), cpu_id(0) 591060SN/A{ 601060SN/A} 611060SN/A 622292SN/Avoid 632733Sktlim@umich.eduBaseO3CPU::regStats() 642292SN/A{ 652292SN/A BaseCPU::regStats(); 662292SN/A} 672292SN/A 681060SN/Atemplate <class Impl> 691755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 701060SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 711060SN/A{ 721060SN/A} 731060SN/A 741060SN/Atemplate <class Impl> 751060SN/Avoid 761755SN/AFullO3CPU<Impl>::TickEvent::process() 771060SN/A{ 781060SN/A cpu->tick(); 791060SN/A} 801060SN/A 811060SN/Atemplate <class Impl> 821060SN/Aconst char * 835336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 841060SN/A{ 854873Sstever@eecs.umich.edu return "FullO3CPU tick"; 861060SN/A} 871060SN/A 881060SN/Atemplate <class Impl> 892829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 903221Sktlim@umich.edu : Event(&mainEventQueue, CPU_Switch_Pri) 912829Sksewell@umich.edu{ 922829Sksewell@umich.edu} 932829Sksewell@umich.edu 942829Sksewell@umich.edutemplate <class Impl> 952829Sksewell@umich.eduvoid 962829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 972829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 982829Sksewell@umich.edu{ 992829Sksewell@umich.edu tid = thread_num; 1002829Sksewell@umich.edu cpu = thread_cpu; 1012829Sksewell@umich.edu} 1022829Sksewell@umich.edu 1032829Sksewell@umich.edutemplate <class Impl> 1042829Sksewell@umich.eduvoid 1052829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1062829Sksewell@umich.edu{ 1072829Sksewell@umich.edu cpu->activateThread(tid); 1082829Sksewell@umich.edu} 1092829Sksewell@umich.edu 1102829Sksewell@umich.edutemplate <class Impl> 1112829Sksewell@umich.educonst char * 1125336Shines@cs.fsu.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1132829Sksewell@umich.edu{ 1144873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1152829Sksewell@umich.edu} 1162829Sksewell@umich.edu 1172829Sksewell@umich.edutemplate <class Impl> 1182875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1193859Sbinkertn@umich.edu : Event(&mainEventQueue, CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1202875Sksewell@umich.edu{ 1212875Sksewell@umich.edu} 1222875Sksewell@umich.edu 1232875Sksewell@umich.edutemplate <class Impl> 1242875Sksewell@umich.eduvoid 1252875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1263859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1272875Sksewell@umich.edu{ 1282875Sksewell@umich.edu tid = thread_num; 1292875Sksewell@umich.edu cpu = thread_cpu; 1303859Sbinkertn@umich.edu remove = false; 1312875Sksewell@umich.edu} 1322875Sksewell@umich.edu 1332875Sksewell@umich.edutemplate <class Impl> 1342875Sksewell@umich.eduvoid 1352875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1362875Sksewell@umich.edu{ 1372875Sksewell@umich.edu cpu->deactivateThread(tid); 1383221Sktlim@umich.edu if (remove) 1393221Sktlim@umich.edu cpu->removeThread(tid); 1402875Sksewell@umich.edu} 1412875Sksewell@umich.edu 1422875Sksewell@umich.edutemplate <class Impl> 1432875Sksewell@umich.educonst char * 1445336Shines@cs.fsu.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 1452875Sksewell@umich.edu{ 1464873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 1472875Sksewell@umich.edu} 1482875Sksewell@umich.edu 1492875Sksewell@umich.edutemplate <class Impl> 1504329Sktlim@umich.eduFullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, Params *params) 1512733Sktlim@umich.edu : BaseO3CPU(params), 1523781Sgblack@eecs.umich.edu itb(params->itb), 1533781Sgblack@eecs.umich.edu dtb(params->dtb), 1541060SN/A tickEvent(this), 1552292SN/A removeInstsThisCycle(false), 1564329Sktlim@umich.edu fetch(o3_cpu, params), 1574329Sktlim@umich.edu decode(o3_cpu, params), 1584329Sktlim@umich.edu rename(o3_cpu, params), 1594329Sktlim@umich.edu iew(o3_cpu, params), 1604329Sktlim@umich.edu commit(o3_cpu, params), 1611060SN/A 1624329Sktlim@umich.edu regFile(o3_cpu, params->numPhysIntRegs, 1634329Sktlim@umich.edu params->numPhysFloatRegs), 1641060SN/A 1652831Sksewell@umich.edu freeList(params->numberOfThreads, 1662292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1672292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1681060SN/A 1694329Sktlim@umich.edu rob(o3_cpu, 1704329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 1712292SN/A params->smtROBPolicy, params->smtROBThreshold, 1722292SN/A params->numberOfThreads), 1731060SN/A 1742831Sksewell@umich.edu scoreboard(params->numberOfThreads, 1752292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1762292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1772292SN/A TheISA::NumMiscRegs * number_of_threads, 1782292SN/A TheISA::ZeroReg), 1791060SN/A 1802873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1812873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1822873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1832873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1842873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1852873Sktlim@umich.edu activityRec(NumStages, 1862873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1872873Sktlim@umich.edu params->activity), 1881060SN/A 1891060SN/A globalSeqNum(1), 1901858SN/A#if FULL_SYSTEM 1912292SN/A system(params->system), 1921060SN/A physmem(system->physmem), 1931060SN/A#endif // FULL_SYSTEM 1942843Sktlim@umich.edu drainCount(0), 1952316SN/A deferRegistration(params->deferRegistration), 1962316SN/A numThreads(number_of_threads) 1971060SN/A{ 1983221Sktlim@umich.edu if (!deferRegistration) { 1993221Sktlim@umich.edu _status = Running; 2003221Sktlim@umich.edu } else { 2013221Sktlim@umich.edu _status = Idle; 2023221Sktlim@umich.edu } 2031681SN/A 2044598Sbinkertn@umich.edu#if USE_CHECKER 2052794Sktlim@umich.edu if (params->checker) { 2062316SN/A BaseCPU *temp_checker = params->checker; 2072316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2082316SN/A#if FULL_SYSTEM 2092316SN/A checker->setSystem(params->system); 2102316SN/A#endif 2114598Sbinkertn@umich.edu } else { 2124598Sbinkertn@umich.edu checker = NULL; 2134598Sbinkertn@umich.edu } 2142794Sktlim@umich.edu#endif // USE_CHECKER 2152316SN/A 2161858SN/A#if !FULL_SYSTEM 2172292SN/A thread.resize(number_of_threads); 2182292SN/A tids.resize(number_of_threads); 2191681SN/A#endif 2201681SN/A 2212325SN/A // The stages also need their CPU pointer setup. However this 2222325SN/A // must be done at the upper level CPU because they have pointers 2232325SN/A // to the upper level CPU, and not this FullO3CPU. 2241060SN/A 2252292SN/A // Set up Pointers to the activeThreads list for each stage 2262292SN/A fetch.setActiveThreads(&activeThreads); 2272292SN/A decode.setActiveThreads(&activeThreads); 2282292SN/A rename.setActiveThreads(&activeThreads); 2292292SN/A iew.setActiveThreads(&activeThreads); 2302292SN/A commit.setActiveThreads(&activeThreads); 2311060SN/A 2321060SN/A // Give each of the stages the time buffer they will use. 2331060SN/A fetch.setTimeBuffer(&timeBuffer); 2341060SN/A decode.setTimeBuffer(&timeBuffer); 2351060SN/A rename.setTimeBuffer(&timeBuffer); 2361060SN/A iew.setTimeBuffer(&timeBuffer); 2371060SN/A commit.setTimeBuffer(&timeBuffer); 2381060SN/A 2391060SN/A // Also setup each of the stages' queues. 2401060SN/A fetch.setFetchQueue(&fetchQueue); 2411060SN/A decode.setFetchQueue(&fetchQueue); 2422292SN/A commit.setFetchQueue(&fetchQueue); 2431060SN/A decode.setDecodeQueue(&decodeQueue); 2441060SN/A rename.setDecodeQueue(&decodeQueue); 2451060SN/A rename.setRenameQueue(&renameQueue); 2461060SN/A iew.setRenameQueue(&renameQueue); 2471060SN/A iew.setIEWQueue(&iewQueue); 2481060SN/A commit.setIEWQueue(&iewQueue); 2491060SN/A commit.setRenameQueue(&renameQueue); 2501060SN/A 2512292SN/A commit.setIEWStage(&iew); 2522292SN/A rename.setIEWStage(&iew); 2532292SN/A rename.setCommitStage(&commit); 2542292SN/A 2552292SN/A#if !FULL_SYSTEM 2562307SN/A int active_threads = params->workload.size(); 2572831Sksewell@umich.edu 2582831Sksewell@umich.edu if (active_threads > Impl::MaxThreads) { 2592831Sksewell@umich.edu panic("Workload Size too large. Increase the 'MaxThreads'" 2602831Sksewell@umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2612831Sksewell@umich.edu "edit your workload size."); 2622831Sksewell@umich.edu } 2632292SN/A#else 2642307SN/A int active_threads = 1; 2652292SN/A#endif 2662292SN/A 2672316SN/A //Make Sure That this a Valid Architeture 2682292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2692292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2702292SN/A 2712292SN/A rename.setScoreboard(&scoreboard); 2722292SN/A iew.setScoreboard(&scoreboard); 2732292SN/A 2741060SN/A // Setup the rename map for whichever stages need it. 2752292SN/A PhysRegIndex lreg_idx = 0; 2762292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2771060SN/A 2782292SN/A for (int tid=0; tid < numThreads; tid++) { 2792307SN/A bool bindRegs = (tid <= active_threads - 1); 2802292SN/A 2812292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2822292SN/A params->numPhysIntRegs, 2832325SN/A lreg_idx, //Index for Logical. Regs 2842292SN/A 2852292SN/A TheISA::NumFloatRegs, 2862292SN/A params->numPhysFloatRegs, 2872325SN/A freg_idx, //Index for Float Regs 2882292SN/A 2892292SN/A TheISA::NumMiscRegs, 2902292SN/A 2912292SN/A TheISA::ZeroReg, 2922292SN/A TheISA::ZeroReg, 2932292SN/A 2942292SN/A tid, 2952292SN/A false); 2962292SN/A 2972292SN/A renameMap[tid].init(TheISA::NumIntRegs, 2982292SN/A params->numPhysIntRegs, 2992325SN/A lreg_idx, //Index for Logical. Regs 3002292SN/A 3012292SN/A TheISA::NumFloatRegs, 3022292SN/A params->numPhysFloatRegs, 3032325SN/A freg_idx, //Index for Float Regs 3042292SN/A 3052292SN/A TheISA::NumMiscRegs, 3062292SN/A 3072292SN/A TheISA::ZeroReg, 3082292SN/A TheISA::ZeroReg, 3092292SN/A 3102292SN/A tid, 3112292SN/A bindRegs); 3123221Sktlim@umich.edu 3133221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3143221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3152292SN/A } 3162292SN/A 3172292SN/A rename.setRenameMap(renameMap); 3182292SN/A commit.setRenameMap(commitRenameMap); 3192292SN/A 3202292SN/A // Give renameMap & rename stage access to the freeList; 3212292SN/A for (int i=0; i < numThreads; i++) { 3222292SN/A renameMap[i].setFreeList(&freeList); 3232292SN/A } 3241060SN/A rename.setFreeList(&freeList); 3252292SN/A 3261060SN/A // Setup the ROB for whichever stages need it. 3271060SN/A commit.setROB(&rob); 3282292SN/A 3292292SN/A lastRunningCycle = curTick; 3302292SN/A 3312829Sksewell@umich.edu lastActivatedCycle = -1; 3322829Sksewell@umich.edu 3333093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3343093Sksewell@umich.edu //for (int i=0; i < numThreads; i++) { 3353093Sksewell@umich.edu //globalSeqNum[i] = 1; 3363093Sksewell@umich.edu //} 3373093Sksewell@umich.edu 3382292SN/A contextSwitch = false; 3391060SN/A} 3401060SN/A 3411060SN/Atemplate <class Impl> 3421755SN/AFullO3CPU<Impl>::~FullO3CPU() 3431060SN/A{ 3441060SN/A} 3451060SN/A 3461060SN/Atemplate <class Impl> 3471060SN/Avoid 3481755SN/AFullO3CPU<Impl>::fullCPURegStats() 3491062SN/A{ 3502733Sktlim@umich.edu BaseO3CPU::regStats(); 3512292SN/A 3522733Sktlim@umich.edu // Register any of the O3CPU's stats here. 3532292SN/A timesIdled 3542292SN/A .name(name() + ".timesIdled") 3552292SN/A .desc("Number of times that the entire CPU went into an idle state and" 3562292SN/A " unscheduled itself") 3572292SN/A .prereq(timesIdled); 3582292SN/A 3592292SN/A idleCycles 3602292SN/A .name(name() + ".idleCycles") 3612292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 3622292SN/A "to idling") 3632292SN/A .prereq(idleCycles); 3642292SN/A 3652292SN/A // Number of Instructions simulated 3662292SN/A // -------------------------------- 3672292SN/A // Should probably be in Base CPU but need templated 3682292SN/A // MaxThreads so put in here instead 3692292SN/A committedInsts 3702292SN/A .init(numThreads) 3712292SN/A .name(name() + ".committedInsts") 3722292SN/A .desc("Number of Instructions Simulated"); 3732292SN/A 3742292SN/A totalCommittedInsts 3752292SN/A .name(name() + ".committedInsts_total") 3762292SN/A .desc("Number of Instructions Simulated"); 3772292SN/A 3782292SN/A cpi 3792292SN/A .name(name() + ".cpi") 3802292SN/A .desc("CPI: Cycles Per Instruction") 3812292SN/A .precision(6); 3824392Sktlim@umich.edu cpi = numCycles / committedInsts; 3832292SN/A 3842292SN/A totalCpi 3852292SN/A .name(name() + ".cpi_total") 3862292SN/A .desc("CPI: Total CPI of All Threads") 3872292SN/A .precision(6); 3884392Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 3892292SN/A 3902292SN/A ipc 3912292SN/A .name(name() + ".ipc") 3922292SN/A .desc("IPC: Instructions Per Cycle") 3932292SN/A .precision(6); 3944392Sktlim@umich.edu ipc = committedInsts / numCycles; 3952292SN/A 3962292SN/A totalIpc 3972292SN/A .name(name() + ".ipc_total") 3982292SN/A .desc("IPC: Total IPC of All Threads") 3992292SN/A .precision(6); 4004392Sktlim@umich.edu totalIpc = totalCommittedInsts / numCycles; 4012292SN/A 4021062SN/A} 4031062SN/A 4041062SN/Atemplate <class Impl> 4052871Sktlim@umich.eduPort * 4062871Sktlim@umich.eduFullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 4072871Sktlim@umich.edu{ 4082871Sktlim@umich.edu if (if_name == "dcache_port") 4092871Sktlim@umich.edu return iew.getDcachePort(); 4102871Sktlim@umich.edu else if (if_name == "icache_port") 4112871Sktlim@umich.edu return fetch.getIcachePort(); 4122871Sktlim@umich.edu else 4132871Sktlim@umich.edu panic("No Such Port\n"); 4142871Sktlim@umich.edu} 4152871Sktlim@umich.edu 4162871Sktlim@umich.edutemplate <class Impl> 4171062SN/Avoid 4181755SN/AFullO3CPU<Impl>::tick() 4191060SN/A{ 4202733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 4211060SN/A 4222292SN/A ++numCycles; 4232292SN/A 4242325SN/A// activity = false; 4252292SN/A 4262292SN/A //Tick each of the stages 4271060SN/A fetch.tick(); 4281060SN/A 4291060SN/A decode.tick(); 4301060SN/A 4311060SN/A rename.tick(); 4321060SN/A 4331060SN/A iew.tick(); 4341060SN/A 4351060SN/A commit.tick(); 4361060SN/A 4372292SN/A#if !FULL_SYSTEM 4382292SN/A doContextSwitch(); 4392292SN/A#endif 4402292SN/A 4412292SN/A // Now advance the time buffers 4421060SN/A timeBuffer.advance(); 4431060SN/A 4441060SN/A fetchQueue.advance(); 4451060SN/A decodeQueue.advance(); 4461060SN/A renameQueue.advance(); 4471060SN/A iewQueue.advance(); 4481060SN/A 4492325SN/A activityRec.advance(); 4502292SN/A 4512292SN/A if (removeInstsThisCycle) { 4522292SN/A cleanUpRemovedInsts(); 4532292SN/A } 4542292SN/A 4552325SN/A if (!tickEvent.scheduled()) { 4562867Sktlim@umich.edu if (_status == SwitchedOut || 4572905Sktlim@umich.edu getState() == SimObject::Drained) { 4583226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 4592325SN/A // increment stat 4602325SN/A lastRunningCycle = curTick; 4613221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 4623226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 4632325SN/A lastRunningCycle = curTick; 4642325SN/A timesIdled++; 4652325SN/A } else { 4665100Ssaidi@eecs.umich.edu tickEvent.schedule(nextCycle(curTick + ticks(1))); 4673226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 4682325SN/A } 4692292SN/A } 4702292SN/A 4712292SN/A#if !FULL_SYSTEM 4722292SN/A updateThreadPriority(); 4732292SN/A#endif 4742292SN/A 4751060SN/A} 4761060SN/A 4771060SN/Atemplate <class Impl> 4781060SN/Avoid 4791755SN/AFullO3CPU<Impl>::init() 4801060SN/A{ 4812307SN/A if (!deferRegistration) { 4822680Sktlim@umich.edu registerThreadContexts(); 4832292SN/A } 4841060SN/A 4852292SN/A // Set inSyscall so that the CPU doesn't squash when initially 4862292SN/A // setting up registers. 4872292SN/A for (int i = 0; i < number_of_threads; ++i) 4882292SN/A thread[i]->inSyscall = true; 4892292SN/A 4902292SN/A for (int tid=0; tid < number_of_threads; tid++) { 4911858SN/A#if FULL_SYSTEM 4922680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 4931681SN/A#else 4942680Sktlim@umich.edu ThreadContext *src_tc = thread[tid]->getTC(); 4951681SN/A#endif 4962292SN/A // Threads start in the Suspended State 4972680Sktlim@umich.edu if (src_tc->status() != ThreadContext::Suspended) { 4982292SN/A continue; 4991060SN/A } 5001060SN/A 5012292SN/A#if FULL_SYSTEM 5022680Sktlim@umich.edu TheISA::initCPU(src_tc, src_tc->readCpuId()); 5032292SN/A#endif 5042292SN/A } 5052292SN/A 5062292SN/A // Clear inSyscall. 5072292SN/A for (int i = 0; i < number_of_threads; ++i) 5082292SN/A thread[i]->inSyscall = false; 5092292SN/A 5102316SN/A // Initialize stages. 5112292SN/A fetch.initStage(); 5122292SN/A iew.initStage(); 5132292SN/A rename.initStage(); 5142292SN/A commit.initStage(); 5152292SN/A 5162292SN/A commit.setThreads(thread); 5172292SN/A} 5182292SN/A 5192292SN/Atemplate <class Impl> 5202292SN/Avoid 5212875Sksewell@umich.eduFullO3CPU<Impl>::activateThread(unsigned tid) 5222875Sksewell@umich.edu{ 5235314Sstever@gmail.com std::list<unsigned>::iterator isActive = 5245314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 5252875Sksewell@umich.edu 5263226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 5273226Sktlim@umich.edu 5282875Sksewell@umich.edu if (isActive == activeThreads.end()) { 5292875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 5302875Sksewell@umich.edu tid); 5312875Sksewell@umich.edu 5322875Sksewell@umich.edu activeThreads.push_back(tid); 5332875Sksewell@umich.edu } 5342875Sksewell@umich.edu} 5352875Sksewell@umich.edu 5362875Sksewell@umich.edutemplate <class Impl> 5372875Sksewell@umich.eduvoid 5382875Sksewell@umich.eduFullO3CPU<Impl>::deactivateThread(unsigned tid) 5392875Sksewell@umich.edu{ 5402875Sksewell@umich.edu //Remove From Active List, if Active 5415314Sstever@gmail.com std::list<unsigned>::iterator thread_it = 5425314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 5432875Sksewell@umich.edu 5443226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 5453226Sktlim@umich.edu 5462875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 5472875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 5482875Sksewell@umich.edu tid); 5492875Sksewell@umich.edu activeThreads.erase(thread_it); 5502875Sksewell@umich.edu } 5512875Sksewell@umich.edu} 5522875Sksewell@umich.edu 5532875Sksewell@umich.edutemplate <class Impl> 5542875Sksewell@umich.eduvoid 5552875Sksewell@umich.eduFullO3CPU<Impl>::activateContext(int tid, int delay) 5562875Sksewell@umich.edu{ 5572875Sksewell@umich.edu // Needs to set each stage to running as well. 5582875Sksewell@umich.edu if (delay){ 5592875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 5605100Ssaidi@eecs.umich.edu "on cycle %d\n", tid, curTick + ticks(delay)); 5612875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 5622875Sksewell@umich.edu } else { 5632875Sksewell@umich.edu activateThread(tid); 5642875Sksewell@umich.edu } 5652875Sksewell@umich.edu 5663221Sktlim@umich.edu if (lastActivatedCycle < curTick) { 5672875Sksewell@umich.edu scheduleTickEvent(delay); 5682875Sksewell@umich.edu 5692875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 5702875Sksewell@umich.edu // deschedule itself. 5712875Sksewell@umich.edu activityRec.activity(); 5722875Sksewell@umich.edu fetch.wakeFromQuiesce(); 5732875Sksewell@umich.edu 5742875Sksewell@umich.edu lastActivatedCycle = curTick; 5752875Sksewell@umich.edu 5762875Sksewell@umich.edu _status = Running; 5772875Sksewell@umich.edu } 5782875Sksewell@umich.edu} 5792875Sksewell@umich.edu 5802875Sksewell@umich.edutemplate <class Impl> 5813221Sktlim@umich.edubool 5823221Sktlim@umich.eduFullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay) 5832875Sksewell@umich.edu{ 5842875Sksewell@umich.edu // Schedule removal of thread data from CPU 5852875Sksewell@umich.edu if (delay){ 5862875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 5875100Ssaidi@eecs.umich.edu "on cycle %d\n", tid, curTick + ticks(delay)); 5883221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 5893221Sktlim@umich.edu return false; 5902875Sksewell@umich.edu } else { 5912875Sksewell@umich.edu deactivateThread(tid); 5923221Sktlim@umich.edu if (remove) 5933221Sktlim@umich.edu removeThread(tid); 5943221Sktlim@umich.edu return true; 5952875Sksewell@umich.edu } 5962875Sksewell@umich.edu} 5972875Sksewell@umich.edu 5982875Sksewell@umich.edutemplate <class Impl> 5992875Sksewell@umich.eduvoid 6002875Sksewell@umich.eduFullO3CPU<Impl>::suspendContext(int tid) 6012875Sksewell@umich.edu{ 6022875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 6033221Sktlim@umich.edu bool deallocated = deallocateContext(tid, false, 1); 6043221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 6053859Sbinkertn@umich.edu if (activeThreads.size() == 1 && !deallocated || 6063859Sbinkertn@umich.edu activeThreads.size() == 0) 6072910Sksewell@umich.edu unscheduleTickEvent(); 6082875Sksewell@umich.edu _status = Idle; 6092875Sksewell@umich.edu} 6102875Sksewell@umich.edu 6112875Sksewell@umich.edutemplate <class Impl> 6122875Sksewell@umich.eduvoid 6132875Sksewell@umich.eduFullO3CPU<Impl>::haltContext(int tid) 6142875Sksewell@umich.edu{ 6152910Sksewell@umich.edu //For now, this is the same as deallocate 6162910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 6173221Sktlim@umich.edu deallocateContext(tid, true, 1); 6182875Sksewell@umich.edu} 6192875Sksewell@umich.edu 6202875Sksewell@umich.edutemplate <class Impl> 6212875Sksewell@umich.eduvoid 6222292SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 6232292SN/A{ 6242847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 6252292SN/A // Will change now that the PC and thread state is internal to the CPU 6262683Sktlim@umich.edu // and not in the ThreadContext. 6272292SN/A#if FULL_SYSTEM 6282680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 6292292SN/A#else 6302847Sksewell@umich.edu ThreadContext *src_tc = tcBase(tid); 6312292SN/A#endif 6322292SN/A 6332292SN/A //Bind Int Regs to Rename Map 6342292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 6352292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 6362292SN/A 6372292SN/A renameMap[tid].setEntry(ireg,phys_reg); 6382292SN/A scoreboard.setReg(phys_reg); 6392292SN/A } 6402292SN/A 6412292SN/A //Bind Float Regs to Rename Map 6422292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 6432292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 6442292SN/A 6452292SN/A renameMap[tid].setEntry(freg,phys_reg); 6462292SN/A scoreboard.setReg(phys_reg); 6472292SN/A } 6482292SN/A 6492292SN/A //Copy Thread Data Into RegFile 6502847Sksewell@umich.edu //this->copyFromTC(tid); 6512292SN/A 6522847Sksewell@umich.edu //Set PC/NPC/NNPC 6532847Sksewell@umich.edu setPC(src_tc->readPC(), tid); 6542847Sksewell@umich.edu setNextPC(src_tc->readNextPC(), tid); 6552847Sksewell@umich.edu setNextNPC(src_tc->readNextNPC(), tid); 6562292SN/A 6572680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 6582292SN/A 6592292SN/A activateContext(tid,1); 6602292SN/A 6612292SN/A //Reset ROB/IQ/LSQ Entries 6622292SN/A commit.rob->resetEntries(); 6632292SN/A iew.resetEntries(); 6642292SN/A} 6652292SN/A 6662292SN/Atemplate <class Impl> 6672292SN/Avoid 6682292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 6692292SN/A{ 6702877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 6712847Sksewell@umich.edu 6722847Sksewell@umich.edu // Copy Thread Data From RegFile 6732847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 6745364Sksewell@umich.edu // this->copyToTC(tid); 6755364Sksewell@umich.edu 6765364Sksewell@umich.edu 6775364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 6785364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 6795364Sksewell@umich.edu // in SMT workloads. 6802847Sksewell@umich.edu 6812847Sksewell@umich.edu // Unbind Int Regs from Rename Map 6822292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 6832292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 6842292SN/A 6852292SN/A scoreboard.unsetReg(phys_reg); 6862292SN/A freeList.addReg(phys_reg); 6872292SN/A } 6882292SN/A 6892847Sksewell@umich.edu // Unbind Float Regs from Rename Map 6905362Sksewell@umich.edu for (int freg = TheISA::NumIntRegs; freg < TheISA::NumFloatRegs; freg++) { 6912292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 6922292SN/A 6932292SN/A scoreboard.unsetReg(phys_reg); 6942292SN/A freeList.addReg(phys_reg); 6952292SN/A } 6962292SN/A 6972847Sksewell@umich.edu // Squash Throughout Pipeline 6982935Sksewell@umich.edu InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; 6994636Sgblack@eecs.umich.edu fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid); 7002292SN/A decode.squash(tid); 7012935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 7022875Sksewell@umich.edu iew.squash(tid); 7035363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 7042935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 7052292SN/A 7065362Sksewell@umich.edu 7075362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 7082292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 7092292SN/A 7102847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 7113229Sktlim@umich.edu 7123229Sktlim@umich.edu // Commented out for now. This should be possible to do by 7133229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 7143229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 7153229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 7163229Sktlim@umich.edu/* 7172292SN/A if (activeThreads.size() >= 1) { 7182292SN/A commit.rob->resetEntries(); 7192292SN/A iew.resetEntries(); 7202292SN/A } 7213229Sktlim@umich.edu*/ 7222292SN/A} 7232292SN/A 7242292SN/A 7252292SN/Atemplate <class Impl> 7262292SN/Avoid 7272292SN/AFullO3CPU<Impl>::activateWhenReady(int tid) 7282292SN/A{ 7292733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 7302292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 7312292SN/A tid); 7322292SN/A 7332292SN/A bool ready = true; 7342292SN/A 7352292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 7362733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7372292SN/A "Phys. Int. Regs.\n", 7382292SN/A tid); 7392292SN/A ready = false; 7402292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 7412733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7422292SN/A "Phys. Float. Regs.\n", 7432292SN/A tid); 7442292SN/A ready = false; 7452292SN/A } else if (commit.rob->numFreeEntries() >= 7462292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 7472733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7482292SN/A "ROB entries.\n", 7492292SN/A tid); 7502292SN/A ready = false; 7512292SN/A } else if (iew.instQueue.numFreeEntries() >= 7522292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 7532733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7542292SN/A "IQ entries.\n", 7552292SN/A tid); 7562292SN/A ready = false; 7572292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 7582292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 7592733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7602292SN/A "LSQ entries.\n", 7612292SN/A tid); 7622292SN/A ready = false; 7632292SN/A } 7642292SN/A 7652292SN/A if (ready) { 7662292SN/A insertThread(tid); 7672292SN/A 7682292SN/A contextSwitch = false; 7692292SN/A 7702292SN/A cpuWaitList.remove(tid); 7712292SN/A } else { 7722292SN/A suspendContext(tid); 7732292SN/A 7742292SN/A //blocks fetch 7752292SN/A contextSwitch = true; 7762292SN/A 7772875Sksewell@umich.edu //@todo: dont always add to waitlist 7782292SN/A //do waitlist 7792292SN/A cpuWaitList.push_back(tid); 7801060SN/A } 7811060SN/A} 7821060SN/A 7834192Sktlim@umich.edu#if FULL_SYSTEM 7844192Sktlim@umich.edutemplate <class Impl> 7854192Sktlim@umich.eduvoid 7864192Sktlim@umich.eduFullO3CPU<Impl>::updateMemPorts() 7874192Sktlim@umich.edu{ 7884192Sktlim@umich.edu // Update all ThreadContext's memory ports (Functional/Virtual 7894192Sktlim@umich.edu // Ports) 7904192Sktlim@umich.edu for (int i = 0; i < thread.size(); ++i) 7915497Ssaidi@eecs.umich.edu thread[i]->connectMemPorts(thread[i]->getTC()); 7924192Sktlim@umich.edu} 7934192Sktlim@umich.edu#endif 7944192Sktlim@umich.edu 7951060SN/Atemplate <class Impl> 7962852Sktlim@umich.eduvoid 7972864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 7982864Sktlim@umich.edu{ 7992918Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 8002918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 8012864Sktlim@umich.edu BaseCPU::serialize(os); 8022864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 8032864Sktlim@umich.edu tickEvent.serialize(os); 8042864Sktlim@umich.edu 8052864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 8062864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 8072864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 8082864Sktlim@umich.edu static SimpleThread temp; 8092864Sktlim@umich.edu 8102864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 8112864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 8122864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 8132864Sktlim@umich.edu temp.serialize(os); 8142864Sktlim@umich.edu } 8152864Sktlim@umich.edu} 8162864Sktlim@umich.edu 8172864Sktlim@umich.edutemplate <class Impl> 8182864Sktlim@umich.eduvoid 8192864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 8202864Sktlim@umich.edu{ 8212918Sktlim@umich.edu SimObject::State so_state; 8222918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 8232864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 8242864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 8252864Sktlim@umich.edu 8262864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 8272864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 8282864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 8292864Sktlim@umich.edu static SimpleThread temp; 8302864Sktlim@umich.edu 8312864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 8322864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 8332864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 8342864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 8352864Sktlim@umich.edu } 8362864Sktlim@umich.edu} 8372864Sktlim@umich.edu 8382864Sktlim@umich.edutemplate <class Impl> 8392905Sktlim@umich.eduunsigned int 8402843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 8411060SN/A{ 8423125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 8433512Sktlim@umich.edu 8443512Sktlim@umich.edu // If the CPU isn't doing anything, then return immediately. 8453512Sktlim@umich.edu if (_status == Idle || _status == SwitchedOut) { 8463512Sktlim@umich.edu return 0; 8473512Sktlim@umich.edu } 8483512Sktlim@umich.edu 8492843Sktlim@umich.edu drainCount = 0; 8502843Sktlim@umich.edu fetch.drain(); 8512843Sktlim@umich.edu decode.drain(); 8522843Sktlim@umich.edu rename.drain(); 8532843Sktlim@umich.edu iew.drain(); 8542843Sktlim@umich.edu commit.drain(); 8552325SN/A 8562325SN/A // Wake the CPU and record activity so everything can drain out if 8572863Sktlim@umich.edu // the CPU was not able to immediately drain. 8582905Sktlim@umich.edu if (getState() != SimObject::Drained) { 8592864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 8602864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 8612864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 8622864Sktlim@umich.edu // process on the drain event. 8632864Sktlim@umich.edu drainEvent = drain_event; 8642843Sktlim@umich.edu 8652863Sktlim@umich.edu wakeCPU(); 8662863Sktlim@umich.edu activityRec.activity(); 8672852Sktlim@umich.edu 8682905Sktlim@umich.edu return 1; 8692863Sktlim@umich.edu } else { 8702905Sktlim@umich.edu return 0; 8712863Sktlim@umich.edu } 8722316SN/A} 8732310SN/A 8742316SN/Atemplate <class Impl> 8752316SN/Avoid 8762843Sktlim@umich.eduFullO3CPU<Impl>::resume() 8772316SN/A{ 8782843Sktlim@umich.edu fetch.resume(); 8792843Sktlim@umich.edu decode.resume(); 8802843Sktlim@umich.edu rename.resume(); 8812843Sktlim@umich.edu iew.resume(); 8822843Sktlim@umich.edu commit.resume(); 8832316SN/A 8842905Sktlim@umich.edu changeState(SimObject::Running); 8852905Sktlim@umich.edu 8862864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 8872864Sktlim@umich.edu return; 8882864Sktlim@umich.edu 8893319Shsul@eecs.umich.edu#if FULL_SYSTEM 8904762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 8913319Shsul@eecs.umich.edu#endif 8923319Shsul@eecs.umich.edu 8932843Sktlim@umich.edu if (!tickEvent.scheduled()) 8944030Sktlim@umich.edu tickEvent.schedule(nextCycle()); 8952843Sktlim@umich.edu _status = Running; 8962843Sktlim@umich.edu} 8972316SN/A 8982843Sktlim@umich.edutemplate <class Impl> 8992843Sktlim@umich.eduvoid 9002843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 9012843Sktlim@umich.edu{ 9022843Sktlim@umich.edu if (++drainCount == NumStages) { 9032316SN/A if (tickEvent.scheduled()) 9042316SN/A tickEvent.squash(); 9052863Sktlim@umich.edu 9062905Sktlim@umich.edu changeState(SimObject::Drained); 9072863Sktlim@umich.edu 9083126Sktlim@umich.edu BaseCPU::switchOut(); 9093126Sktlim@umich.edu 9102863Sktlim@umich.edu if (drainEvent) { 9112863Sktlim@umich.edu drainEvent->process(); 9122863Sktlim@umich.edu drainEvent = NULL; 9132863Sktlim@umich.edu } 9142310SN/A } 9152843Sktlim@umich.edu assert(drainCount <= 5); 9162843Sktlim@umich.edu} 9172843Sktlim@umich.edu 9182843Sktlim@umich.edutemplate <class Impl> 9192843Sktlim@umich.eduvoid 9202843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 9212843Sktlim@umich.edu{ 9222843Sktlim@umich.edu fetch.switchOut(); 9232843Sktlim@umich.edu rename.switchOut(); 9242325SN/A iew.switchOut(); 9252843Sktlim@umich.edu commit.switchOut(); 9262843Sktlim@umich.edu instList.clear(); 9272843Sktlim@umich.edu while (!removeList.empty()) { 9282843Sktlim@umich.edu removeList.pop(); 9292843Sktlim@umich.edu } 9302843Sktlim@umich.edu 9312843Sktlim@umich.edu _status = SwitchedOut; 9322843Sktlim@umich.edu#if USE_CHECKER 9332843Sktlim@umich.edu if (checker) 9342843Sktlim@umich.edu checker->switchOut(); 9352843Sktlim@umich.edu#endif 9363126Sktlim@umich.edu if (tickEvent.scheduled()) 9373126Sktlim@umich.edu tickEvent.squash(); 9381060SN/A} 9391060SN/A 9401060SN/Atemplate <class Impl> 9411060SN/Avoid 9421755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 9431060SN/A{ 9442325SN/A // Flush out any old data from the time buffers. 9452873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 9462307SN/A timeBuffer.advance(); 9472307SN/A fetchQueue.advance(); 9482307SN/A decodeQueue.advance(); 9492307SN/A renameQueue.advance(); 9502307SN/A iewQueue.advance(); 9512307SN/A } 9522307SN/A 9532325SN/A activityRec.reset(); 9542307SN/A 9554192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort()); 9561060SN/A 9572307SN/A fetch.takeOverFrom(); 9582307SN/A decode.takeOverFrom(); 9592307SN/A rename.takeOverFrom(); 9602307SN/A iew.takeOverFrom(); 9612307SN/A commit.takeOverFrom(); 9622307SN/A 9631060SN/A assert(!tickEvent.scheduled()); 9641060SN/A 9652325SN/A // @todo: Figure out how to properly select the tid to put onto 9662325SN/A // the active threads list. 9672307SN/A int tid = 0; 9682307SN/A 9695314Sstever@gmail.com std::list<unsigned>::iterator isActive = 9705314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 9712307SN/A 9722307SN/A if (isActive == activeThreads.end()) { 9732325SN/A //May Need to Re-code this if the delay variable is the delay 9742325SN/A //needed for thread to activate 9752733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 9762307SN/A tid); 9772307SN/A 9782307SN/A activeThreads.push_back(tid); 9792307SN/A } 9802307SN/A 9812325SN/A // Set all statuses to active, schedule the CPU's tick event. 9822307SN/A // @todo: Fix up statuses so this is handled properly 9832680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 9842680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 9852680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 9861681SN/A _status = Running; 9874030Sktlim@umich.edu tickEvent.schedule(nextCycle()); 9881681SN/A } 9891060SN/A } 9902307SN/A if (!tickEvent.scheduled()) 9914030Sktlim@umich.edu tickEvent.schedule(nextCycle()); 9921060SN/A} 9931060SN/A 9941060SN/Atemplate <class Impl> 9951060SN/Auint64_t 9961755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 9971060SN/A{ 9981060SN/A return regFile.readIntReg(reg_idx); 9991060SN/A} 10001060SN/A 10011060SN/Atemplate <class Impl> 10022455SN/AFloatReg 10032455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 10041060SN/A{ 10052455SN/A return regFile.readFloatReg(reg_idx, width); 10061060SN/A} 10071060SN/A 10081060SN/Atemplate <class Impl> 10092455SN/AFloatReg 10102455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 10111060SN/A{ 10122455SN/A return regFile.readFloatReg(reg_idx); 10131060SN/A} 10141060SN/A 10151060SN/Atemplate <class Impl> 10162455SN/AFloatRegBits 10172455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 10181060SN/A{ 10192455SN/A return regFile.readFloatRegBits(reg_idx, width); 10202455SN/A} 10212455SN/A 10222455SN/Atemplate <class Impl> 10232455SN/AFloatRegBits 10242455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 10252455SN/A{ 10262455SN/A return regFile.readFloatRegBits(reg_idx); 10271060SN/A} 10281060SN/A 10291060SN/Atemplate <class Impl> 10301060SN/Avoid 10311755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 10321060SN/A{ 10331060SN/A regFile.setIntReg(reg_idx, val); 10341060SN/A} 10351060SN/A 10361060SN/Atemplate <class Impl> 10371060SN/Avoid 10382455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 10391060SN/A{ 10402455SN/A regFile.setFloatReg(reg_idx, val, width); 10411060SN/A} 10421060SN/A 10431060SN/Atemplate <class Impl> 10441060SN/Avoid 10452455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 10461060SN/A{ 10472455SN/A regFile.setFloatReg(reg_idx, val); 10481060SN/A} 10491060SN/A 10501060SN/Atemplate <class Impl> 10511060SN/Avoid 10522455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 10531060SN/A{ 10542455SN/A regFile.setFloatRegBits(reg_idx, val, width); 10552455SN/A} 10562455SN/A 10572455SN/Atemplate <class Impl> 10582455SN/Avoid 10592455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 10602455SN/A{ 10612455SN/A regFile.setFloatRegBits(reg_idx, val); 10621060SN/A} 10631060SN/A 10641060SN/Atemplate <class Impl> 10651060SN/Auint64_t 10662292SN/AFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 10671060SN/A{ 10682292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10692292SN/A 10702292SN/A return regFile.readIntReg(phys_reg); 10712292SN/A} 10722292SN/A 10732292SN/Atemplate <class Impl> 10742292SN/Afloat 10752292SN/AFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 10762292SN/A{ 10772307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 10782307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10792292SN/A 10802669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 10812292SN/A} 10822292SN/A 10832292SN/Atemplate <class Impl> 10842292SN/Adouble 10852292SN/AFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 10862292SN/A{ 10872307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 10882307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10892292SN/A 10902669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 10912292SN/A} 10922292SN/A 10932292SN/Atemplate <class Impl> 10942292SN/Auint64_t 10952292SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 10962292SN/A{ 10972307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 10982307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10992292SN/A 11002669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 11011060SN/A} 11021060SN/A 11031060SN/Atemplate <class Impl> 11041060SN/Avoid 11052292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 11061060SN/A{ 11072292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 11082292SN/A 11092292SN/A regFile.setIntReg(phys_reg, val); 11101060SN/A} 11111060SN/A 11121060SN/Atemplate <class Impl> 11131060SN/Avoid 11142292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 11151060SN/A{ 11162918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 11172918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 11182292SN/A 11192669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 11201060SN/A} 11211060SN/A 11221060SN/Atemplate <class Impl> 11231060SN/Avoid 11242292SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 11251060SN/A{ 11262918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 11272918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 11282292SN/A 11292669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 11301060SN/A} 11311060SN/A 11321060SN/Atemplate <class Impl> 11331060SN/Avoid 11342292SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 11351060SN/A{ 11362918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 11372918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 11381060SN/A 11392669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 11402292SN/A} 11412292SN/A 11422292SN/Atemplate <class Impl> 11432292SN/Auint64_t 11442292SN/AFullO3CPU<Impl>::readPC(unsigned tid) 11452292SN/A{ 11462292SN/A return commit.readPC(tid); 11471060SN/A} 11481060SN/A 11491060SN/Atemplate <class Impl> 11501060SN/Avoid 11512292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 11521060SN/A{ 11532292SN/A commit.setPC(new_PC, tid); 11542292SN/A} 11551060SN/A 11562292SN/Atemplate <class Impl> 11572292SN/Auint64_t 11584636Sgblack@eecs.umich.eduFullO3CPU<Impl>::readMicroPC(unsigned tid) 11594636Sgblack@eecs.umich.edu{ 11604636Sgblack@eecs.umich.edu return commit.readMicroPC(tid); 11614636Sgblack@eecs.umich.edu} 11624636Sgblack@eecs.umich.edu 11634636Sgblack@eecs.umich.edutemplate <class Impl> 11644636Sgblack@eecs.umich.eduvoid 11654636Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMicroPC(Addr new_PC,unsigned tid) 11664636Sgblack@eecs.umich.edu{ 11674636Sgblack@eecs.umich.edu commit.setMicroPC(new_PC, tid); 11684636Sgblack@eecs.umich.edu} 11694636Sgblack@eecs.umich.edu 11704636Sgblack@eecs.umich.edutemplate <class Impl> 11714636Sgblack@eecs.umich.eduuint64_t 11722292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 11732292SN/A{ 11742292SN/A return commit.readNextPC(tid); 11752292SN/A} 11761060SN/A 11772292SN/Atemplate <class Impl> 11782292SN/Avoid 11792292SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 11802292SN/A{ 11812292SN/A commit.setNextPC(val, tid); 11822292SN/A} 11831060SN/A 11842756Sksewell@umich.edutemplate <class Impl> 11852756Sksewell@umich.eduuint64_t 11862756Sksewell@umich.eduFullO3CPU<Impl>::readNextNPC(unsigned tid) 11872756Sksewell@umich.edu{ 11882756Sksewell@umich.edu return commit.readNextNPC(tid); 11892756Sksewell@umich.edu} 11902756Sksewell@umich.edu 11912756Sksewell@umich.edutemplate <class Impl> 11922756Sksewell@umich.eduvoid 11932935Sksewell@umich.eduFullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid) 11942756Sksewell@umich.edu{ 11952756Sksewell@umich.edu commit.setNextNPC(val, tid); 11962756Sksewell@umich.edu} 11972756Sksewell@umich.edu 11982292SN/Atemplate <class Impl> 11994636Sgblack@eecs.umich.eduuint64_t 12004636Sgblack@eecs.umich.eduFullO3CPU<Impl>::readNextMicroPC(unsigned tid) 12014636Sgblack@eecs.umich.edu{ 12024636Sgblack@eecs.umich.edu return commit.readNextMicroPC(tid); 12034636Sgblack@eecs.umich.edu} 12044636Sgblack@eecs.umich.edu 12054636Sgblack@eecs.umich.edutemplate <class Impl> 12064636Sgblack@eecs.umich.eduvoid 12074636Sgblack@eecs.umich.eduFullO3CPU<Impl>::setNextMicroPC(Addr new_PC,unsigned tid) 12084636Sgblack@eecs.umich.edu{ 12094636Sgblack@eecs.umich.edu commit.setNextMicroPC(new_PC, tid); 12104636Sgblack@eecs.umich.edu} 12114636Sgblack@eecs.umich.edu 12124636Sgblack@eecs.umich.edutemplate <class Impl> 12132292SN/Atypename FullO3CPU<Impl>::ListIt 12142292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 12152292SN/A{ 12162292SN/A instList.push_back(inst); 12171060SN/A 12182292SN/A return --(instList.end()); 12192292SN/A} 12201060SN/A 12212292SN/Atemplate <class Impl> 12222292SN/Avoid 12232292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 12242292SN/A{ 12252292SN/A // Keep an instruction count. 12262292SN/A thread[tid]->numInst++; 12272292SN/A thread[tid]->numInsts++; 12282292SN/A committedInsts[tid]++; 12292292SN/A totalCommittedInsts++; 12302292SN/A 12312292SN/A // Check for instruction-count-based events. 12322292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 12332292SN/A} 12342292SN/A 12352292SN/Atemplate <class Impl> 12362292SN/Avoid 12372292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 12382292SN/A{ 12392292SN/A removeInstsThisCycle = true; 12402292SN/A 12412292SN/A removeList.push(inst->getInstListIt()); 12421060SN/A} 12431060SN/A 12441060SN/Atemplate <class Impl> 12451060SN/Avoid 12461755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 12471060SN/A{ 12482733Sktlim@umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 12492292SN/A "[sn:%lli]\n", 12502303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 12511060SN/A 12522292SN/A removeInstsThisCycle = true; 12531060SN/A 12541060SN/A // Remove the front instruction. 12552292SN/A removeList.push(inst->getInstListIt()); 12561060SN/A} 12571060SN/A 12581060SN/Atemplate <class Impl> 12591060SN/Avoid 12604632Sgblack@eecs.umich.eduFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 12611060SN/A{ 12622733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 12632292SN/A " list.\n", tid); 12641060SN/A 12652292SN/A ListIt end_it; 12661060SN/A 12672292SN/A bool rob_empty = false; 12682292SN/A 12692292SN/A if (instList.empty()) { 12702292SN/A return; 12712292SN/A } else if (rob.isEmpty(/*tid*/)) { 12722733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 12732292SN/A end_it = instList.begin(); 12742292SN/A rob_empty = true; 12752292SN/A } else { 12762292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 12772733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 12782292SN/A } 12792292SN/A 12802292SN/A removeInstsThisCycle = true; 12812292SN/A 12822292SN/A ListIt inst_it = instList.end(); 12832292SN/A 12842292SN/A inst_it--; 12852292SN/A 12862292SN/A // Walk through the instruction list, removing any instructions 12872292SN/A // that were inserted after the given instruction iterator, end_it. 12882292SN/A while (inst_it != end_it) { 12892292SN/A assert(!instList.empty()); 12902292SN/A 12912292SN/A squashInstIt(inst_it, tid); 12922292SN/A 12932292SN/A inst_it--; 12942292SN/A } 12952292SN/A 12962292SN/A // If the ROB was empty, then we actually need to remove the first 12972292SN/A // instruction as well. 12982292SN/A if (rob_empty) { 12992292SN/A squashInstIt(inst_it, tid); 13002292SN/A } 13011060SN/A} 13021060SN/A 13031060SN/Atemplate <class Impl> 13041060SN/Avoid 13052292SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 13062292SN/A unsigned tid) 13071062SN/A{ 13082292SN/A assert(!instList.empty()); 13092292SN/A 13102292SN/A removeInstsThisCycle = true; 13112292SN/A 13122292SN/A ListIt inst_iter = instList.end(); 13132292SN/A 13142292SN/A inst_iter--; 13152292SN/A 13162733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 13172292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 13182292SN/A tid, seq_num, (*inst_iter)->seqNum); 13191062SN/A 13202292SN/A while ((*inst_iter)->seqNum > seq_num) { 13211062SN/A 13222292SN/A bool break_loop = (inst_iter == instList.begin()); 13231062SN/A 13242292SN/A squashInstIt(inst_iter, tid); 13251062SN/A 13262292SN/A inst_iter--; 13271062SN/A 13282292SN/A if (break_loop) 13292292SN/A break; 13302292SN/A } 13312292SN/A} 13322292SN/A 13332292SN/Atemplate <class Impl> 13342292SN/Ainline void 13352292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 13362292SN/A{ 13372292SN/A if ((*instIt)->threadNumber == tid) { 13382733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 13392292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 13402292SN/A (*instIt)->threadNumber, 13412292SN/A (*instIt)->seqNum, 13422292SN/A (*instIt)->readPC()); 13431062SN/A 13441062SN/A // Mark it as squashed. 13452292SN/A (*instIt)->setSquashed(); 13462292SN/A 13472325SN/A // @todo: Formulate a consistent method for deleting 13482325SN/A // instructions from the instruction list 13492292SN/A // Remove the instruction from the list. 13502292SN/A removeList.push(instIt); 13512292SN/A } 13522292SN/A} 13532292SN/A 13542292SN/Atemplate <class Impl> 13552292SN/Avoid 13562292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 13572292SN/A{ 13582292SN/A while (!removeList.empty()) { 13592733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 13602292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 13612292SN/A (*removeList.front())->threadNumber, 13622292SN/A (*removeList.front())->seqNum, 13632292SN/A (*removeList.front())->readPC()); 13642292SN/A 13652292SN/A instList.erase(removeList.front()); 13662292SN/A 13672292SN/A removeList.pop(); 13681062SN/A } 13691062SN/A 13702292SN/A removeInstsThisCycle = false; 13711062SN/A} 13722325SN/A/* 13731062SN/Atemplate <class Impl> 13741062SN/Avoid 13751755SN/AFullO3CPU<Impl>::removeAllInsts() 13761060SN/A{ 13771060SN/A instList.clear(); 13781060SN/A} 13792325SN/A*/ 13801060SN/Atemplate <class Impl> 13811060SN/Avoid 13821755SN/AFullO3CPU<Impl>::dumpInsts() 13831060SN/A{ 13841060SN/A int num = 0; 13851060SN/A 13862292SN/A ListIt inst_list_it = instList.begin(); 13872292SN/A 13882292SN/A cprintf("Dumping Instruction List\n"); 13892292SN/A 13902292SN/A while (inst_list_it != instList.end()) { 13912292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 13922292SN/A "Squashed:%i\n\n", 13932292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 13942292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 13952292SN/A (*inst_list_it)->isSquashed()); 13961060SN/A inst_list_it++; 13971060SN/A ++num; 13981060SN/A } 13991060SN/A} 14002325SN/A/* 14011060SN/Atemplate <class Impl> 14021060SN/Avoid 14031755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 14041060SN/A{ 14051060SN/A iew.wakeDependents(inst); 14061060SN/A} 14072325SN/A*/ 14082292SN/Atemplate <class Impl> 14092292SN/Avoid 14102292SN/AFullO3CPU<Impl>::wakeCPU() 14112292SN/A{ 14122325SN/A if (activityRec.active() || tickEvent.scheduled()) { 14132325SN/A DPRINTF(Activity, "CPU already running.\n"); 14142292SN/A return; 14152292SN/A } 14162292SN/A 14172325SN/A DPRINTF(Activity, "Waking up CPU\n"); 14182325SN/A 14195099Ssaidi@eecs.umich.edu idleCycles += tickToCycles((curTick - 1) - lastRunningCycle); 14205099Ssaidi@eecs.umich.edu numCycles += tickToCycles((curTick - 1) - lastRunningCycle); 14212292SN/A 14224030Sktlim@umich.edu tickEvent.schedule(nextCycle()); 14232292SN/A} 14242292SN/A 14252292SN/Atemplate <class Impl> 14262292SN/Aint 14272292SN/AFullO3CPU<Impl>::getFreeTid() 14282292SN/A{ 14292292SN/A for (int i=0; i < numThreads; i++) { 14302292SN/A if (!tids[i]) { 14312292SN/A tids[i] = true; 14322292SN/A return i; 14332292SN/A } 14342292SN/A } 14352292SN/A 14362292SN/A return -1; 14372292SN/A} 14382292SN/A 14392292SN/Atemplate <class Impl> 14402292SN/Avoid 14412292SN/AFullO3CPU<Impl>::doContextSwitch() 14422292SN/A{ 14432292SN/A if (contextSwitch) { 14442292SN/A 14452292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 14462292SN/A 14472292SN/A for (int tid=0; tid < cpuWaitList.size(); tid++) { 14482292SN/A activateWhenReady(tid); 14492292SN/A } 14502292SN/A 14512292SN/A if (cpuWaitList.size() == 0) 14522292SN/A contextSwitch = true; 14532292SN/A } 14542292SN/A} 14552292SN/A 14562292SN/Atemplate <class Impl> 14572292SN/Avoid 14582292SN/AFullO3CPU<Impl>::updateThreadPriority() 14592292SN/A{ 14602292SN/A if (activeThreads.size() > 1) 14612292SN/A { 14622292SN/A //DEFAULT TO ROUND ROBIN SCHEME 14632292SN/A //e.g. Move highest priority to end of thread list 14645314Sstever@gmail.com std::list<unsigned>::iterator list_begin = activeThreads.begin(); 14655314Sstever@gmail.com std::list<unsigned>::iterator list_end = activeThreads.end(); 14662292SN/A 14672292SN/A unsigned high_thread = *list_begin; 14682292SN/A 14692292SN/A activeThreads.erase(list_begin); 14702292SN/A 14712292SN/A activeThreads.push_back(high_thread); 14722292SN/A } 14732292SN/A} 14741060SN/A 14751755SN/A// Forward declaration of FullO3CPU. 14762818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1477