cpu.cc revision 5100
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 341858SN/A 354762Snate@binkert.org#include "cpu/activity.hh" 364762Snate@binkert.org#include "cpu/simple_thread.hh" 374762Snate@binkert.org#include "cpu/thread_context.hh" 384762Snate@binkert.org#include "cpu/o3/isa_specific.hh" 394762Snate@binkert.org#include "cpu/o3/cpu.hh" 404762Snate@binkert.org#include "enums/MemoryMode.hh" 414762Snate@binkert.org#include "sim/core.hh" 424762Snate@binkert.org#include "sim/stat_control.hh" 434762Snate@binkert.org 441858SN/A#if FULL_SYSTEM 452356SN/A#include "cpu/quiesce_event.hh" 461060SN/A#include "sim/system.hh" 471060SN/A#else 481060SN/A#include "sim/process.hh" 491060SN/A#endif 501060SN/A 512794Sktlim@umich.edu#if USE_CHECKER 522794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 532794Sktlim@umich.edu#endif 542794Sktlim@umich.edu 551060SN/Ausing namespace std; 562669Sktlim@umich.eduusing namespace TheISA; 571060SN/A 582733Sktlim@umich.eduBaseO3CPU::BaseO3CPU(Params *params) 592292SN/A : BaseCPU(params), cpu_id(0) 601060SN/A{ 611060SN/A} 621060SN/A 632292SN/Avoid 642733Sktlim@umich.eduBaseO3CPU::regStats() 652292SN/A{ 662292SN/A BaseCPU::regStats(); 672292SN/A} 682292SN/A 691060SN/Atemplate <class Impl> 701755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 711060SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 721060SN/A{ 731060SN/A} 741060SN/A 751060SN/Atemplate <class Impl> 761060SN/Avoid 771755SN/AFullO3CPU<Impl>::TickEvent::process() 781060SN/A{ 791060SN/A cpu->tick(); 801060SN/A} 811060SN/A 821060SN/Atemplate <class Impl> 831060SN/Aconst char * 841755SN/AFullO3CPU<Impl>::TickEvent::description() 851060SN/A{ 864873Sstever@eecs.umich.edu return "FullO3CPU tick"; 871060SN/A} 881060SN/A 891060SN/Atemplate <class Impl> 902829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 913221Sktlim@umich.edu : Event(&mainEventQueue, CPU_Switch_Pri) 922829Sksewell@umich.edu{ 932829Sksewell@umich.edu} 942829Sksewell@umich.edu 952829Sksewell@umich.edutemplate <class Impl> 962829Sksewell@umich.eduvoid 972829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 982829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 992829Sksewell@umich.edu{ 1002829Sksewell@umich.edu tid = thread_num; 1012829Sksewell@umich.edu cpu = thread_cpu; 1022829Sksewell@umich.edu} 1032829Sksewell@umich.edu 1042829Sksewell@umich.edutemplate <class Impl> 1052829Sksewell@umich.eduvoid 1062829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1072829Sksewell@umich.edu{ 1082829Sksewell@umich.edu cpu->activateThread(tid); 1092829Sksewell@umich.edu} 1102829Sksewell@umich.edu 1112829Sksewell@umich.edutemplate <class Impl> 1122829Sksewell@umich.educonst char * 1132829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::description() 1142829Sksewell@umich.edu{ 1154873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1162829Sksewell@umich.edu} 1172829Sksewell@umich.edu 1182829Sksewell@umich.edutemplate <class Impl> 1192875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1203859Sbinkertn@umich.edu : Event(&mainEventQueue, CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1212875Sksewell@umich.edu{ 1222875Sksewell@umich.edu} 1232875Sksewell@umich.edu 1242875Sksewell@umich.edutemplate <class Impl> 1252875Sksewell@umich.eduvoid 1262875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1273859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1282875Sksewell@umich.edu{ 1292875Sksewell@umich.edu tid = thread_num; 1302875Sksewell@umich.edu cpu = thread_cpu; 1313859Sbinkertn@umich.edu remove = false; 1322875Sksewell@umich.edu} 1332875Sksewell@umich.edu 1342875Sksewell@umich.edutemplate <class Impl> 1352875Sksewell@umich.eduvoid 1362875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1372875Sksewell@umich.edu{ 1382875Sksewell@umich.edu cpu->deactivateThread(tid); 1393221Sktlim@umich.edu if (remove) 1403221Sktlim@umich.edu cpu->removeThread(tid); 1412875Sksewell@umich.edu} 1422875Sksewell@umich.edu 1432875Sksewell@umich.edutemplate <class Impl> 1442875Sksewell@umich.educonst char * 1452875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::description() 1462875Sksewell@umich.edu{ 1474873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 1482875Sksewell@umich.edu} 1492875Sksewell@umich.edu 1502875Sksewell@umich.edutemplate <class Impl> 1514329Sktlim@umich.eduFullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, Params *params) 1522733Sktlim@umich.edu : BaseO3CPU(params), 1533781Sgblack@eecs.umich.edu itb(params->itb), 1543781Sgblack@eecs.umich.edu dtb(params->dtb), 1551060SN/A tickEvent(this), 1562292SN/A removeInstsThisCycle(false), 1574329Sktlim@umich.edu fetch(o3_cpu, params), 1584329Sktlim@umich.edu decode(o3_cpu, params), 1594329Sktlim@umich.edu rename(o3_cpu, params), 1604329Sktlim@umich.edu iew(o3_cpu, params), 1614329Sktlim@umich.edu commit(o3_cpu, params), 1621060SN/A 1634329Sktlim@umich.edu regFile(o3_cpu, params->numPhysIntRegs, 1644329Sktlim@umich.edu params->numPhysFloatRegs), 1651060SN/A 1662831Sksewell@umich.edu freeList(params->numberOfThreads, 1672292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1682292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1691060SN/A 1704329Sktlim@umich.edu rob(o3_cpu, 1714329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 1722292SN/A params->smtROBPolicy, params->smtROBThreshold, 1732292SN/A params->numberOfThreads), 1741060SN/A 1752831Sksewell@umich.edu scoreboard(params->numberOfThreads, 1762292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1772292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1782292SN/A TheISA::NumMiscRegs * number_of_threads, 1792292SN/A TheISA::ZeroReg), 1801060SN/A 1812873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1822873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1832873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1842873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1852873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1862873Sktlim@umich.edu activityRec(NumStages, 1872873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1882873Sktlim@umich.edu params->activity), 1891060SN/A 1901060SN/A globalSeqNum(1), 1911858SN/A#if FULL_SYSTEM 1922292SN/A system(params->system), 1931060SN/A physmem(system->physmem), 1941060SN/A#endif // FULL_SYSTEM 1952843Sktlim@umich.edu drainCount(0), 1962316SN/A deferRegistration(params->deferRegistration), 1972316SN/A numThreads(number_of_threads) 1981060SN/A{ 1993221Sktlim@umich.edu if (!deferRegistration) { 2003221Sktlim@umich.edu _status = Running; 2013221Sktlim@umich.edu } else { 2023221Sktlim@umich.edu _status = Idle; 2033221Sktlim@umich.edu } 2041681SN/A 2054598Sbinkertn@umich.edu#if USE_CHECKER 2062794Sktlim@umich.edu if (params->checker) { 2072316SN/A BaseCPU *temp_checker = params->checker; 2082316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2092316SN/A#if FULL_SYSTEM 2102316SN/A checker->setSystem(params->system); 2112316SN/A#endif 2124598Sbinkertn@umich.edu } else { 2134598Sbinkertn@umich.edu checker = NULL; 2144598Sbinkertn@umich.edu } 2152794Sktlim@umich.edu#endif // USE_CHECKER 2162316SN/A 2171858SN/A#if !FULL_SYSTEM 2182292SN/A thread.resize(number_of_threads); 2192292SN/A tids.resize(number_of_threads); 2201681SN/A#endif 2211681SN/A 2222325SN/A // The stages also need their CPU pointer setup. However this 2232325SN/A // must be done at the upper level CPU because they have pointers 2242325SN/A // to the upper level CPU, and not this FullO3CPU. 2251060SN/A 2262292SN/A // Set up Pointers to the activeThreads list for each stage 2272292SN/A fetch.setActiveThreads(&activeThreads); 2282292SN/A decode.setActiveThreads(&activeThreads); 2292292SN/A rename.setActiveThreads(&activeThreads); 2302292SN/A iew.setActiveThreads(&activeThreads); 2312292SN/A commit.setActiveThreads(&activeThreads); 2321060SN/A 2331060SN/A // Give each of the stages the time buffer they will use. 2341060SN/A fetch.setTimeBuffer(&timeBuffer); 2351060SN/A decode.setTimeBuffer(&timeBuffer); 2361060SN/A rename.setTimeBuffer(&timeBuffer); 2371060SN/A iew.setTimeBuffer(&timeBuffer); 2381060SN/A commit.setTimeBuffer(&timeBuffer); 2391060SN/A 2401060SN/A // Also setup each of the stages' queues. 2411060SN/A fetch.setFetchQueue(&fetchQueue); 2421060SN/A decode.setFetchQueue(&fetchQueue); 2432292SN/A commit.setFetchQueue(&fetchQueue); 2441060SN/A decode.setDecodeQueue(&decodeQueue); 2451060SN/A rename.setDecodeQueue(&decodeQueue); 2461060SN/A rename.setRenameQueue(&renameQueue); 2471060SN/A iew.setRenameQueue(&renameQueue); 2481060SN/A iew.setIEWQueue(&iewQueue); 2491060SN/A commit.setIEWQueue(&iewQueue); 2501060SN/A commit.setRenameQueue(&renameQueue); 2511060SN/A 2522292SN/A commit.setIEWStage(&iew); 2532292SN/A rename.setIEWStage(&iew); 2542292SN/A rename.setCommitStage(&commit); 2552292SN/A 2562292SN/A#if !FULL_SYSTEM 2572307SN/A int active_threads = params->workload.size(); 2582831Sksewell@umich.edu 2592831Sksewell@umich.edu if (active_threads > Impl::MaxThreads) { 2602831Sksewell@umich.edu panic("Workload Size too large. Increase the 'MaxThreads'" 2612831Sksewell@umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2622831Sksewell@umich.edu "edit your workload size."); 2632831Sksewell@umich.edu } 2642292SN/A#else 2652307SN/A int active_threads = 1; 2662292SN/A#endif 2672292SN/A 2682316SN/A //Make Sure That this a Valid Architeture 2692292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2702292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2712292SN/A 2722292SN/A rename.setScoreboard(&scoreboard); 2732292SN/A iew.setScoreboard(&scoreboard); 2742292SN/A 2751060SN/A // Setup the rename map for whichever stages need it. 2762292SN/A PhysRegIndex lreg_idx = 0; 2772292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2781060SN/A 2792292SN/A for (int tid=0; tid < numThreads; tid++) { 2802307SN/A bool bindRegs = (tid <= active_threads - 1); 2812292SN/A 2822292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2832292SN/A params->numPhysIntRegs, 2842325SN/A lreg_idx, //Index for Logical. Regs 2852292SN/A 2862292SN/A TheISA::NumFloatRegs, 2872292SN/A params->numPhysFloatRegs, 2882325SN/A freg_idx, //Index for Float Regs 2892292SN/A 2902292SN/A TheISA::NumMiscRegs, 2912292SN/A 2922292SN/A TheISA::ZeroReg, 2932292SN/A TheISA::ZeroReg, 2942292SN/A 2952292SN/A tid, 2962292SN/A false); 2972292SN/A 2982292SN/A renameMap[tid].init(TheISA::NumIntRegs, 2992292SN/A params->numPhysIntRegs, 3002325SN/A lreg_idx, //Index for Logical. Regs 3012292SN/A 3022292SN/A TheISA::NumFloatRegs, 3032292SN/A params->numPhysFloatRegs, 3042325SN/A freg_idx, //Index for Float Regs 3052292SN/A 3062292SN/A TheISA::NumMiscRegs, 3072292SN/A 3082292SN/A TheISA::ZeroReg, 3092292SN/A TheISA::ZeroReg, 3102292SN/A 3112292SN/A tid, 3122292SN/A bindRegs); 3133221Sktlim@umich.edu 3143221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3153221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3162292SN/A } 3172292SN/A 3182292SN/A rename.setRenameMap(renameMap); 3192292SN/A commit.setRenameMap(commitRenameMap); 3202292SN/A 3212292SN/A // Give renameMap & rename stage access to the freeList; 3222292SN/A for (int i=0; i < numThreads; i++) { 3232292SN/A renameMap[i].setFreeList(&freeList); 3242292SN/A } 3251060SN/A rename.setFreeList(&freeList); 3262292SN/A 3271060SN/A // Setup the ROB for whichever stages need it. 3281060SN/A commit.setROB(&rob); 3292292SN/A 3302292SN/A lastRunningCycle = curTick; 3312292SN/A 3322829Sksewell@umich.edu lastActivatedCycle = -1; 3332829Sksewell@umich.edu 3343093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3353093Sksewell@umich.edu //for (int i=0; i < numThreads; i++) { 3363093Sksewell@umich.edu //globalSeqNum[i] = 1; 3373093Sksewell@umich.edu //} 3383093Sksewell@umich.edu 3392292SN/A contextSwitch = false; 3401060SN/A} 3411060SN/A 3421060SN/Atemplate <class Impl> 3431755SN/AFullO3CPU<Impl>::~FullO3CPU() 3441060SN/A{ 3451060SN/A} 3461060SN/A 3471060SN/Atemplate <class Impl> 3481060SN/Avoid 3491755SN/AFullO3CPU<Impl>::fullCPURegStats() 3501062SN/A{ 3512733Sktlim@umich.edu BaseO3CPU::regStats(); 3522292SN/A 3532733Sktlim@umich.edu // Register any of the O3CPU's stats here. 3542292SN/A timesIdled 3552292SN/A .name(name() + ".timesIdled") 3562292SN/A .desc("Number of times that the entire CPU went into an idle state and" 3572292SN/A " unscheduled itself") 3582292SN/A .prereq(timesIdled); 3592292SN/A 3602292SN/A idleCycles 3612292SN/A .name(name() + ".idleCycles") 3622292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 3632292SN/A "to idling") 3642292SN/A .prereq(idleCycles); 3652292SN/A 3662292SN/A // Number of Instructions simulated 3672292SN/A // -------------------------------- 3682292SN/A // Should probably be in Base CPU but need templated 3692292SN/A // MaxThreads so put in here instead 3702292SN/A committedInsts 3712292SN/A .init(numThreads) 3722292SN/A .name(name() + ".committedInsts") 3732292SN/A .desc("Number of Instructions Simulated"); 3742292SN/A 3752292SN/A totalCommittedInsts 3762292SN/A .name(name() + ".committedInsts_total") 3772292SN/A .desc("Number of Instructions Simulated"); 3782292SN/A 3792292SN/A cpi 3802292SN/A .name(name() + ".cpi") 3812292SN/A .desc("CPI: Cycles Per Instruction") 3822292SN/A .precision(6); 3834392Sktlim@umich.edu cpi = numCycles / committedInsts; 3842292SN/A 3852292SN/A totalCpi 3862292SN/A .name(name() + ".cpi_total") 3872292SN/A .desc("CPI: Total CPI of All Threads") 3882292SN/A .precision(6); 3894392Sktlim@umich.edu totalCpi = numCycles / totalCommittedInsts; 3902292SN/A 3912292SN/A ipc 3922292SN/A .name(name() + ".ipc") 3932292SN/A .desc("IPC: Instructions Per Cycle") 3942292SN/A .precision(6); 3954392Sktlim@umich.edu ipc = committedInsts / numCycles; 3962292SN/A 3972292SN/A totalIpc 3982292SN/A .name(name() + ".ipc_total") 3992292SN/A .desc("IPC: Total IPC of All Threads") 4002292SN/A .precision(6); 4014392Sktlim@umich.edu totalIpc = totalCommittedInsts / numCycles; 4022292SN/A 4031062SN/A} 4041062SN/A 4051062SN/Atemplate <class Impl> 4062871Sktlim@umich.eduPort * 4072871Sktlim@umich.eduFullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 4082871Sktlim@umich.edu{ 4092871Sktlim@umich.edu if (if_name == "dcache_port") 4102871Sktlim@umich.edu return iew.getDcachePort(); 4112871Sktlim@umich.edu else if (if_name == "icache_port") 4122871Sktlim@umich.edu return fetch.getIcachePort(); 4132871Sktlim@umich.edu else 4142871Sktlim@umich.edu panic("No Such Port\n"); 4152871Sktlim@umich.edu} 4162871Sktlim@umich.edu 4172871Sktlim@umich.edutemplate <class Impl> 4181062SN/Avoid 4191755SN/AFullO3CPU<Impl>::tick() 4201060SN/A{ 4212733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 4221060SN/A 4232292SN/A ++numCycles; 4242292SN/A 4252325SN/A// activity = false; 4262292SN/A 4272292SN/A //Tick each of the stages 4281060SN/A fetch.tick(); 4291060SN/A 4301060SN/A decode.tick(); 4311060SN/A 4321060SN/A rename.tick(); 4331060SN/A 4341060SN/A iew.tick(); 4351060SN/A 4361060SN/A commit.tick(); 4371060SN/A 4382292SN/A#if !FULL_SYSTEM 4392292SN/A doContextSwitch(); 4402292SN/A#endif 4412292SN/A 4422292SN/A // Now advance the time buffers 4431060SN/A timeBuffer.advance(); 4441060SN/A 4451060SN/A fetchQueue.advance(); 4461060SN/A decodeQueue.advance(); 4471060SN/A renameQueue.advance(); 4481060SN/A iewQueue.advance(); 4491060SN/A 4502325SN/A activityRec.advance(); 4512292SN/A 4522292SN/A if (removeInstsThisCycle) { 4532292SN/A cleanUpRemovedInsts(); 4542292SN/A } 4552292SN/A 4562325SN/A if (!tickEvent.scheduled()) { 4572867Sktlim@umich.edu if (_status == SwitchedOut || 4582905Sktlim@umich.edu getState() == SimObject::Drained) { 4593226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 4602325SN/A // increment stat 4612325SN/A lastRunningCycle = curTick; 4623221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 4633226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 4642325SN/A lastRunningCycle = curTick; 4652325SN/A timesIdled++; 4662325SN/A } else { 4675100Ssaidi@eecs.umich.edu tickEvent.schedule(nextCycle(curTick + ticks(1))); 4683226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 4692325SN/A } 4702292SN/A } 4712292SN/A 4722292SN/A#if !FULL_SYSTEM 4732292SN/A updateThreadPriority(); 4742292SN/A#endif 4752292SN/A 4761060SN/A} 4771060SN/A 4781060SN/Atemplate <class Impl> 4791060SN/Avoid 4801755SN/AFullO3CPU<Impl>::init() 4811060SN/A{ 4822307SN/A if (!deferRegistration) { 4832680Sktlim@umich.edu registerThreadContexts(); 4842292SN/A } 4851060SN/A 4862292SN/A // Set inSyscall so that the CPU doesn't squash when initially 4872292SN/A // setting up registers. 4882292SN/A for (int i = 0; i < number_of_threads; ++i) 4892292SN/A thread[i]->inSyscall = true; 4902292SN/A 4912292SN/A for (int tid=0; tid < number_of_threads; tid++) { 4921858SN/A#if FULL_SYSTEM 4932680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 4941681SN/A#else 4952680Sktlim@umich.edu ThreadContext *src_tc = thread[tid]->getTC(); 4961681SN/A#endif 4972292SN/A // Threads start in the Suspended State 4982680Sktlim@umich.edu if (src_tc->status() != ThreadContext::Suspended) { 4992292SN/A continue; 5001060SN/A } 5011060SN/A 5022292SN/A#if FULL_SYSTEM 5032680Sktlim@umich.edu TheISA::initCPU(src_tc, src_tc->readCpuId()); 5042292SN/A#endif 5052292SN/A } 5062292SN/A 5072292SN/A // Clear inSyscall. 5082292SN/A for (int i = 0; i < number_of_threads; ++i) 5092292SN/A thread[i]->inSyscall = false; 5102292SN/A 5112316SN/A // Initialize stages. 5122292SN/A fetch.initStage(); 5132292SN/A iew.initStage(); 5142292SN/A rename.initStage(); 5152292SN/A commit.initStage(); 5162292SN/A 5172292SN/A commit.setThreads(thread); 5182292SN/A} 5192292SN/A 5202292SN/Atemplate <class Impl> 5212292SN/Avoid 5222875Sksewell@umich.eduFullO3CPU<Impl>::activateThread(unsigned tid) 5232875Sksewell@umich.edu{ 5242875Sksewell@umich.edu list<unsigned>::iterator isActive = find( 5252875Sksewell@umich.edu activeThreads.begin(), activeThreads.end(), tid); 5262875Sksewell@umich.edu 5273226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 5283226Sktlim@umich.edu 5292875Sksewell@umich.edu if (isActive == activeThreads.end()) { 5302875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 5312875Sksewell@umich.edu tid); 5322875Sksewell@umich.edu 5332875Sksewell@umich.edu activeThreads.push_back(tid); 5342875Sksewell@umich.edu } 5352875Sksewell@umich.edu} 5362875Sksewell@umich.edu 5372875Sksewell@umich.edutemplate <class Impl> 5382875Sksewell@umich.eduvoid 5392875Sksewell@umich.eduFullO3CPU<Impl>::deactivateThread(unsigned tid) 5402875Sksewell@umich.edu{ 5412875Sksewell@umich.edu //Remove From Active List, if Active 5422875Sksewell@umich.edu list<unsigned>::iterator thread_it = 5432875Sksewell@umich.edu find(activeThreads.begin(), activeThreads.end(), tid); 5442875Sksewell@umich.edu 5453226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 5463226Sktlim@umich.edu 5472875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 5482875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 5492875Sksewell@umich.edu tid); 5502875Sksewell@umich.edu activeThreads.erase(thread_it); 5512875Sksewell@umich.edu } 5522875Sksewell@umich.edu} 5532875Sksewell@umich.edu 5542875Sksewell@umich.edutemplate <class Impl> 5552875Sksewell@umich.eduvoid 5562875Sksewell@umich.eduFullO3CPU<Impl>::activateContext(int tid, int delay) 5572875Sksewell@umich.edu{ 5582875Sksewell@umich.edu // Needs to set each stage to running as well. 5592875Sksewell@umich.edu if (delay){ 5602875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 5615100Ssaidi@eecs.umich.edu "on cycle %d\n", tid, curTick + ticks(delay)); 5622875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 5632875Sksewell@umich.edu } else { 5642875Sksewell@umich.edu activateThread(tid); 5652875Sksewell@umich.edu } 5662875Sksewell@umich.edu 5673221Sktlim@umich.edu if (lastActivatedCycle < curTick) { 5682875Sksewell@umich.edu scheduleTickEvent(delay); 5692875Sksewell@umich.edu 5702875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 5712875Sksewell@umich.edu // deschedule itself. 5722875Sksewell@umich.edu activityRec.activity(); 5732875Sksewell@umich.edu fetch.wakeFromQuiesce(); 5742875Sksewell@umich.edu 5752875Sksewell@umich.edu lastActivatedCycle = curTick; 5762875Sksewell@umich.edu 5772875Sksewell@umich.edu _status = Running; 5782875Sksewell@umich.edu } 5792875Sksewell@umich.edu} 5802875Sksewell@umich.edu 5812875Sksewell@umich.edutemplate <class Impl> 5823221Sktlim@umich.edubool 5833221Sktlim@umich.eduFullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay) 5842875Sksewell@umich.edu{ 5852875Sksewell@umich.edu // Schedule removal of thread data from CPU 5862875Sksewell@umich.edu if (delay){ 5872875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 5885100Ssaidi@eecs.umich.edu "on cycle %d\n", tid, curTick + ticks(delay)); 5893221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 5903221Sktlim@umich.edu return false; 5912875Sksewell@umich.edu } else { 5922875Sksewell@umich.edu deactivateThread(tid); 5933221Sktlim@umich.edu if (remove) 5943221Sktlim@umich.edu removeThread(tid); 5953221Sktlim@umich.edu return true; 5962875Sksewell@umich.edu } 5972875Sksewell@umich.edu} 5982875Sksewell@umich.edu 5992875Sksewell@umich.edutemplate <class Impl> 6002875Sksewell@umich.eduvoid 6012875Sksewell@umich.eduFullO3CPU<Impl>::suspendContext(int tid) 6022875Sksewell@umich.edu{ 6032875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 6043221Sktlim@umich.edu bool deallocated = deallocateContext(tid, false, 1); 6053221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 6063859Sbinkertn@umich.edu if (activeThreads.size() == 1 && !deallocated || 6073859Sbinkertn@umich.edu activeThreads.size() == 0) 6082910Sksewell@umich.edu unscheduleTickEvent(); 6092875Sksewell@umich.edu _status = Idle; 6102875Sksewell@umich.edu} 6112875Sksewell@umich.edu 6122875Sksewell@umich.edutemplate <class Impl> 6132875Sksewell@umich.eduvoid 6142875Sksewell@umich.eduFullO3CPU<Impl>::haltContext(int tid) 6152875Sksewell@umich.edu{ 6162910Sksewell@umich.edu //For now, this is the same as deallocate 6172910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 6183221Sktlim@umich.edu deallocateContext(tid, true, 1); 6192875Sksewell@umich.edu} 6202875Sksewell@umich.edu 6212875Sksewell@umich.edutemplate <class Impl> 6222875Sksewell@umich.eduvoid 6232292SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 6242292SN/A{ 6252847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 6262292SN/A // Will change now that the PC and thread state is internal to the CPU 6272683Sktlim@umich.edu // and not in the ThreadContext. 6282292SN/A#if FULL_SYSTEM 6292680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 6302292SN/A#else 6312847Sksewell@umich.edu ThreadContext *src_tc = tcBase(tid); 6322292SN/A#endif 6332292SN/A 6342292SN/A //Bind Int Regs to Rename Map 6352292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 6362292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 6372292SN/A 6382292SN/A renameMap[tid].setEntry(ireg,phys_reg); 6392292SN/A scoreboard.setReg(phys_reg); 6402292SN/A } 6412292SN/A 6422292SN/A //Bind Float Regs to Rename Map 6432292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 6442292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 6452292SN/A 6462292SN/A renameMap[tid].setEntry(freg,phys_reg); 6472292SN/A scoreboard.setReg(phys_reg); 6482292SN/A } 6492292SN/A 6502292SN/A //Copy Thread Data Into RegFile 6512847Sksewell@umich.edu //this->copyFromTC(tid); 6522292SN/A 6532847Sksewell@umich.edu //Set PC/NPC/NNPC 6542847Sksewell@umich.edu setPC(src_tc->readPC(), tid); 6552847Sksewell@umich.edu setNextPC(src_tc->readNextPC(), tid); 6562847Sksewell@umich.edu setNextNPC(src_tc->readNextNPC(), tid); 6572292SN/A 6582680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 6592292SN/A 6602292SN/A activateContext(tid,1); 6612292SN/A 6622292SN/A //Reset ROB/IQ/LSQ Entries 6632292SN/A commit.rob->resetEntries(); 6642292SN/A iew.resetEntries(); 6652292SN/A} 6662292SN/A 6672292SN/Atemplate <class Impl> 6682292SN/Avoid 6692292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 6702292SN/A{ 6712877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 6722847Sksewell@umich.edu 6732847Sksewell@umich.edu // Copy Thread Data From RegFile 6742847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 6752847Sksewell@umich.edu //this->copyToTC(tid); 6762847Sksewell@umich.edu 6772847Sksewell@umich.edu // Unbind Int Regs from Rename Map 6782292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 6792292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 6802292SN/A 6812292SN/A scoreboard.unsetReg(phys_reg); 6822292SN/A freeList.addReg(phys_reg); 6832292SN/A } 6842292SN/A 6852847Sksewell@umich.edu // Unbind Float Regs from Rename Map 6862292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 6872292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 6882292SN/A 6892292SN/A scoreboard.unsetReg(phys_reg); 6902292SN/A freeList.addReg(phys_reg); 6912292SN/A } 6922292SN/A 6932847Sksewell@umich.edu // Squash Throughout Pipeline 6942935Sksewell@umich.edu InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; 6954636Sgblack@eecs.umich.edu fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid); 6962292SN/A decode.squash(tid); 6972935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 6982875Sksewell@umich.edu iew.squash(tid); 6992935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 7002292SN/A 7012292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 7022292SN/A 7032847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 7043229Sktlim@umich.edu 7053229Sktlim@umich.edu // Commented out for now. This should be possible to do by 7063229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 7073229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 7083229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 7093229Sktlim@umich.edu/* 7102292SN/A if (activeThreads.size() >= 1) { 7112292SN/A commit.rob->resetEntries(); 7122292SN/A iew.resetEntries(); 7132292SN/A } 7143229Sktlim@umich.edu*/ 7152292SN/A} 7162292SN/A 7172292SN/A 7182292SN/Atemplate <class Impl> 7192292SN/Avoid 7202292SN/AFullO3CPU<Impl>::activateWhenReady(int tid) 7212292SN/A{ 7222733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 7232292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 7242292SN/A tid); 7252292SN/A 7262292SN/A bool ready = true; 7272292SN/A 7282292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 7292733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7302292SN/A "Phys. Int. Regs.\n", 7312292SN/A tid); 7322292SN/A ready = false; 7332292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 7342733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7352292SN/A "Phys. Float. Regs.\n", 7362292SN/A tid); 7372292SN/A ready = false; 7382292SN/A } else if (commit.rob->numFreeEntries() >= 7392292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 7402733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7412292SN/A "ROB entries.\n", 7422292SN/A tid); 7432292SN/A ready = false; 7442292SN/A } else if (iew.instQueue.numFreeEntries() >= 7452292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 7462733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7472292SN/A "IQ entries.\n", 7482292SN/A tid); 7492292SN/A ready = false; 7502292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 7512292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 7522733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7532292SN/A "LSQ entries.\n", 7542292SN/A tid); 7552292SN/A ready = false; 7562292SN/A } 7572292SN/A 7582292SN/A if (ready) { 7592292SN/A insertThread(tid); 7602292SN/A 7612292SN/A contextSwitch = false; 7622292SN/A 7632292SN/A cpuWaitList.remove(tid); 7642292SN/A } else { 7652292SN/A suspendContext(tid); 7662292SN/A 7672292SN/A //blocks fetch 7682292SN/A contextSwitch = true; 7692292SN/A 7702875Sksewell@umich.edu //@todo: dont always add to waitlist 7712292SN/A //do waitlist 7722292SN/A cpuWaitList.push_back(tid); 7731060SN/A } 7741060SN/A} 7751060SN/A 7764192Sktlim@umich.edu#if FULL_SYSTEM 7774192Sktlim@umich.edutemplate <class Impl> 7784192Sktlim@umich.eduvoid 7794192Sktlim@umich.eduFullO3CPU<Impl>::updateMemPorts() 7804192Sktlim@umich.edu{ 7814192Sktlim@umich.edu // Update all ThreadContext's memory ports (Functional/Virtual 7824192Sktlim@umich.edu // Ports) 7834192Sktlim@umich.edu for (int i = 0; i < thread.size(); ++i) 7844192Sktlim@umich.edu thread[i]->connectMemPorts(); 7854192Sktlim@umich.edu} 7864192Sktlim@umich.edu#endif 7874192Sktlim@umich.edu 7881060SN/Atemplate <class Impl> 7892852Sktlim@umich.eduvoid 7902864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 7912864Sktlim@umich.edu{ 7922918Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 7932918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 7942864Sktlim@umich.edu BaseCPU::serialize(os); 7952864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 7962864Sktlim@umich.edu tickEvent.serialize(os); 7972864Sktlim@umich.edu 7982864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 7992864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 8002864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 8012864Sktlim@umich.edu static SimpleThread temp; 8022864Sktlim@umich.edu 8032864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 8042864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 8052864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 8062864Sktlim@umich.edu temp.serialize(os); 8072864Sktlim@umich.edu } 8082864Sktlim@umich.edu} 8092864Sktlim@umich.edu 8102864Sktlim@umich.edutemplate <class Impl> 8112864Sktlim@umich.eduvoid 8122864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 8132864Sktlim@umich.edu{ 8142918Sktlim@umich.edu SimObject::State so_state; 8152918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 8162864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 8172864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 8182864Sktlim@umich.edu 8192864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 8202864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 8212864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 8222864Sktlim@umich.edu static SimpleThread temp; 8232864Sktlim@umich.edu 8242864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 8252864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 8262864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 8272864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 8282864Sktlim@umich.edu } 8292864Sktlim@umich.edu} 8302864Sktlim@umich.edu 8312864Sktlim@umich.edutemplate <class Impl> 8322905Sktlim@umich.eduunsigned int 8332843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 8341060SN/A{ 8353125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 8363512Sktlim@umich.edu 8373512Sktlim@umich.edu // If the CPU isn't doing anything, then return immediately. 8383512Sktlim@umich.edu if (_status == Idle || _status == SwitchedOut) { 8393512Sktlim@umich.edu return 0; 8403512Sktlim@umich.edu } 8413512Sktlim@umich.edu 8422843Sktlim@umich.edu drainCount = 0; 8432843Sktlim@umich.edu fetch.drain(); 8442843Sktlim@umich.edu decode.drain(); 8452843Sktlim@umich.edu rename.drain(); 8462843Sktlim@umich.edu iew.drain(); 8472843Sktlim@umich.edu commit.drain(); 8482325SN/A 8492325SN/A // Wake the CPU and record activity so everything can drain out if 8502863Sktlim@umich.edu // the CPU was not able to immediately drain. 8512905Sktlim@umich.edu if (getState() != SimObject::Drained) { 8522864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 8532864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 8542864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 8552864Sktlim@umich.edu // process on the drain event. 8562864Sktlim@umich.edu drainEvent = drain_event; 8572843Sktlim@umich.edu 8582863Sktlim@umich.edu wakeCPU(); 8592863Sktlim@umich.edu activityRec.activity(); 8602852Sktlim@umich.edu 8612905Sktlim@umich.edu return 1; 8622863Sktlim@umich.edu } else { 8632905Sktlim@umich.edu return 0; 8642863Sktlim@umich.edu } 8652316SN/A} 8662310SN/A 8672316SN/Atemplate <class Impl> 8682316SN/Avoid 8692843Sktlim@umich.eduFullO3CPU<Impl>::resume() 8702316SN/A{ 8712843Sktlim@umich.edu fetch.resume(); 8722843Sktlim@umich.edu decode.resume(); 8732843Sktlim@umich.edu rename.resume(); 8742843Sktlim@umich.edu iew.resume(); 8752843Sktlim@umich.edu commit.resume(); 8762316SN/A 8772905Sktlim@umich.edu changeState(SimObject::Running); 8782905Sktlim@umich.edu 8792864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 8802864Sktlim@umich.edu return; 8812864Sktlim@umich.edu 8823319Shsul@eecs.umich.edu#if FULL_SYSTEM 8834762Snate@binkert.org assert(system->getMemoryMode() == Enums::timing); 8843319Shsul@eecs.umich.edu#endif 8853319Shsul@eecs.umich.edu 8862843Sktlim@umich.edu if (!tickEvent.scheduled()) 8874030Sktlim@umich.edu tickEvent.schedule(nextCycle()); 8882843Sktlim@umich.edu _status = Running; 8892843Sktlim@umich.edu} 8902316SN/A 8912843Sktlim@umich.edutemplate <class Impl> 8922843Sktlim@umich.eduvoid 8932843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 8942843Sktlim@umich.edu{ 8952843Sktlim@umich.edu if (++drainCount == NumStages) { 8962316SN/A if (tickEvent.scheduled()) 8972316SN/A tickEvent.squash(); 8982863Sktlim@umich.edu 8992905Sktlim@umich.edu changeState(SimObject::Drained); 9002863Sktlim@umich.edu 9013126Sktlim@umich.edu BaseCPU::switchOut(); 9023126Sktlim@umich.edu 9032863Sktlim@umich.edu if (drainEvent) { 9042863Sktlim@umich.edu drainEvent->process(); 9052863Sktlim@umich.edu drainEvent = NULL; 9062863Sktlim@umich.edu } 9072310SN/A } 9082843Sktlim@umich.edu assert(drainCount <= 5); 9092843Sktlim@umich.edu} 9102843Sktlim@umich.edu 9112843Sktlim@umich.edutemplate <class Impl> 9122843Sktlim@umich.eduvoid 9132843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 9142843Sktlim@umich.edu{ 9152843Sktlim@umich.edu fetch.switchOut(); 9162843Sktlim@umich.edu rename.switchOut(); 9172325SN/A iew.switchOut(); 9182843Sktlim@umich.edu commit.switchOut(); 9192843Sktlim@umich.edu instList.clear(); 9202843Sktlim@umich.edu while (!removeList.empty()) { 9212843Sktlim@umich.edu removeList.pop(); 9222843Sktlim@umich.edu } 9232843Sktlim@umich.edu 9242843Sktlim@umich.edu _status = SwitchedOut; 9252843Sktlim@umich.edu#if USE_CHECKER 9262843Sktlim@umich.edu if (checker) 9272843Sktlim@umich.edu checker->switchOut(); 9282843Sktlim@umich.edu#endif 9293126Sktlim@umich.edu if (tickEvent.scheduled()) 9303126Sktlim@umich.edu tickEvent.squash(); 9311060SN/A} 9321060SN/A 9331060SN/Atemplate <class Impl> 9341060SN/Avoid 9351755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 9361060SN/A{ 9372325SN/A // Flush out any old data from the time buffers. 9382873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 9392307SN/A timeBuffer.advance(); 9402307SN/A fetchQueue.advance(); 9412307SN/A decodeQueue.advance(); 9422307SN/A renameQueue.advance(); 9432307SN/A iewQueue.advance(); 9442307SN/A } 9452307SN/A 9462325SN/A activityRec.reset(); 9472307SN/A 9484192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort()); 9491060SN/A 9502307SN/A fetch.takeOverFrom(); 9512307SN/A decode.takeOverFrom(); 9522307SN/A rename.takeOverFrom(); 9532307SN/A iew.takeOverFrom(); 9542307SN/A commit.takeOverFrom(); 9552307SN/A 9561060SN/A assert(!tickEvent.scheduled()); 9571060SN/A 9582325SN/A // @todo: Figure out how to properly select the tid to put onto 9592325SN/A // the active threads list. 9602307SN/A int tid = 0; 9612307SN/A 9622307SN/A list<unsigned>::iterator isActive = find( 9632307SN/A activeThreads.begin(), activeThreads.end(), tid); 9642307SN/A 9652307SN/A if (isActive == activeThreads.end()) { 9662325SN/A //May Need to Re-code this if the delay variable is the delay 9672325SN/A //needed for thread to activate 9682733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 9692307SN/A tid); 9702307SN/A 9712307SN/A activeThreads.push_back(tid); 9722307SN/A } 9732307SN/A 9742325SN/A // Set all statuses to active, schedule the CPU's tick event. 9752307SN/A // @todo: Fix up statuses so this is handled properly 9762680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 9772680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 9782680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 9791681SN/A _status = Running; 9804030Sktlim@umich.edu tickEvent.schedule(nextCycle()); 9811681SN/A } 9821060SN/A } 9832307SN/A if (!tickEvent.scheduled()) 9844030Sktlim@umich.edu tickEvent.schedule(nextCycle()); 9851060SN/A} 9861060SN/A 9871060SN/Atemplate <class Impl> 9881060SN/Auint64_t 9891755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 9901060SN/A{ 9911060SN/A return regFile.readIntReg(reg_idx); 9921060SN/A} 9931060SN/A 9941060SN/Atemplate <class Impl> 9952455SN/AFloatReg 9962455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 9971060SN/A{ 9982455SN/A return regFile.readFloatReg(reg_idx, width); 9991060SN/A} 10001060SN/A 10011060SN/Atemplate <class Impl> 10022455SN/AFloatReg 10032455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 10041060SN/A{ 10052455SN/A return regFile.readFloatReg(reg_idx); 10061060SN/A} 10071060SN/A 10081060SN/Atemplate <class Impl> 10092455SN/AFloatRegBits 10102455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 10111060SN/A{ 10122455SN/A return regFile.readFloatRegBits(reg_idx, width); 10132455SN/A} 10142455SN/A 10152455SN/Atemplate <class Impl> 10162455SN/AFloatRegBits 10172455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 10182455SN/A{ 10192455SN/A return regFile.readFloatRegBits(reg_idx); 10201060SN/A} 10211060SN/A 10221060SN/Atemplate <class Impl> 10231060SN/Avoid 10241755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 10251060SN/A{ 10261060SN/A regFile.setIntReg(reg_idx, val); 10271060SN/A} 10281060SN/A 10291060SN/Atemplate <class Impl> 10301060SN/Avoid 10312455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 10321060SN/A{ 10332455SN/A regFile.setFloatReg(reg_idx, val, width); 10341060SN/A} 10351060SN/A 10361060SN/Atemplate <class Impl> 10371060SN/Avoid 10382455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 10391060SN/A{ 10402455SN/A regFile.setFloatReg(reg_idx, val); 10411060SN/A} 10421060SN/A 10431060SN/Atemplate <class Impl> 10441060SN/Avoid 10452455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 10461060SN/A{ 10472455SN/A regFile.setFloatRegBits(reg_idx, val, width); 10482455SN/A} 10492455SN/A 10502455SN/Atemplate <class Impl> 10512455SN/Avoid 10522455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 10532455SN/A{ 10542455SN/A regFile.setFloatRegBits(reg_idx, val); 10551060SN/A} 10561060SN/A 10571060SN/Atemplate <class Impl> 10581060SN/Auint64_t 10592292SN/AFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 10601060SN/A{ 10612292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10622292SN/A 10632292SN/A return regFile.readIntReg(phys_reg); 10642292SN/A} 10652292SN/A 10662292SN/Atemplate <class Impl> 10672292SN/Afloat 10682292SN/AFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 10692292SN/A{ 10702307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 10712307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10722292SN/A 10732669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 10742292SN/A} 10752292SN/A 10762292SN/Atemplate <class Impl> 10772292SN/Adouble 10782292SN/AFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 10792292SN/A{ 10802307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 10812307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10822292SN/A 10832669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 10842292SN/A} 10852292SN/A 10862292SN/Atemplate <class Impl> 10872292SN/Auint64_t 10882292SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 10892292SN/A{ 10902307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 10912307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10922292SN/A 10932669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 10941060SN/A} 10951060SN/A 10961060SN/Atemplate <class Impl> 10971060SN/Avoid 10982292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 10991060SN/A{ 11002292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 11012292SN/A 11022292SN/A regFile.setIntReg(phys_reg, val); 11031060SN/A} 11041060SN/A 11051060SN/Atemplate <class Impl> 11061060SN/Avoid 11072292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 11081060SN/A{ 11092918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 11102918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 11112292SN/A 11122669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 11131060SN/A} 11141060SN/A 11151060SN/Atemplate <class Impl> 11161060SN/Avoid 11172292SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 11181060SN/A{ 11192918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 11202918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 11212292SN/A 11222669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 11231060SN/A} 11241060SN/A 11251060SN/Atemplate <class Impl> 11261060SN/Avoid 11272292SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 11281060SN/A{ 11292918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 11302918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 11311060SN/A 11322669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 11332292SN/A} 11342292SN/A 11352292SN/Atemplate <class Impl> 11362292SN/Auint64_t 11372292SN/AFullO3CPU<Impl>::readPC(unsigned tid) 11382292SN/A{ 11392292SN/A return commit.readPC(tid); 11401060SN/A} 11411060SN/A 11421060SN/Atemplate <class Impl> 11431060SN/Avoid 11442292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 11451060SN/A{ 11462292SN/A commit.setPC(new_PC, tid); 11472292SN/A} 11481060SN/A 11492292SN/Atemplate <class Impl> 11502292SN/Auint64_t 11514636Sgblack@eecs.umich.eduFullO3CPU<Impl>::readMicroPC(unsigned tid) 11524636Sgblack@eecs.umich.edu{ 11534636Sgblack@eecs.umich.edu return commit.readMicroPC(tid); 11544636Sgblack@eecs.umich.edu} 11554636Sgblack@eecs.umich.edu 11564636Sgblack@eecs.umich.edutemplate <class Impl> 11574636Sgblack@eecs.umich.eduvoid 11584636Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMicroPC(Addr new_PC,unsigned tid) 11594636Sgblack@eecs.umich.edu{ 11604636Sgblack@eecs.umich.edu commit.setMicroPC(new_PC, tid); 11614636Sgblack@eecs.umich.edu} 11624636Sgblack@eecs.umich.edu 11634636Sgblack@eecs.umich.edutemplate <class Impl> 11644636Sgblack@eecs.umich.eduuint64_t 11652292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 11662292SN/A{ 11672292SN/A return commit.readNextPC(tid); 11682292SN/A} 11691060SN/A 11702292SN/Atemplate <class Impl> 11712292SN/Avoid 11722292SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 11732292SN/A{ 11742292SN/A commit.setNextPC(val, tid); 11752292SN/A} 11761060SN/A 11772756Sksewell@umich.edutemplate <class Impl> 11782756Sksewell@umich.eduuint64_t 11792756Sksewell@umich.eduFullO3CPU<Impl>::readNextNPC(unsigned tid) 11802756Sksewell@umich.edu{ 11812756Sksewell@umich.edu return commit.readNextNPC(tid); 11822756Sksewell@umich.edu} 11832756Sksewell@umich.edu 11842756Sksewell@umich.edutemplate <class Impl> 11852756Sksewell@umich.eduvoid 11862935Sksewell@umich.eduFullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid) 11872756Sksewell@umich.edu{ 11882756Sksewell@umich.edu commit.setNextNPC(val, tid); 11892756Sksewell@umich.edu} 11902756Sksewell@umich.edu 11912292SN/Atemplate <class Impl> 11924636Sgblack@eecs.umich.eduuint64_t 11934636Sgblack@eecs.umich.eduFullO3CPU<Impl>::readNextMicroPC(unsigned tid) 11944636Sgblack@eecs.umich.edu{ 11954636Sgblack@eecs.umich.edu return commit.readNextMicroPC(tid); 11964636Sgblack@eecs.umich.edu} 11974636Sgblack@eecs.umich.edu 11984636Sgblack@eecs.umich.edutemplate <class Impl> 11994636Sgblack@eecs.umich.eduvoid 12004636Sgblack@eecs.umich.eduFullO3CPU<Impl>::setNextMicroPC(Addr new_PC,unsigned tid) 12014636Sgblack@eecs.umich.edu{ 12024636Sgblack@eecs.umich.edu commit.setNextMicroPC(new_PC, tid); 12034636Sgblack@eecs.umich.edu} 12044636Sgblack@eecs.umich.edu 12054636Sgblack@eecs.umich.edutemplate <class Impl> 12062292SN/Atypename FullO3CPU<Impl>::ListIt 12072292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 12082292SN/A{ 12092292SN/A instList.push_back(inst); 12101060SN/A 12112292SN/A return --(instList.end()); 12122292SN/A} 12131060SN/A 12142292SN/Atemplate <class Impl> 12152292SN/Avoid 12162292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 12172292SN/A{ 12182292SN/A // Keep an instruction count. 12192292SN/A thread[tid]->numInst++; 12202292SN/A thread[tid]->numInsts++; 12212292SN/A committedInsts[tid]++; 12222292SN/A totalCommittedInsts++; 12232292SN/A 12242292SN/A // Check for instruction-count-based events. 12252292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 12262292SN/A} 12272292SN/A 12282292SN/Atemplate <class Impl> 12292292SN/Avoid 12302292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 12312292SN/A{ 12322292SN/A removeInstsThisCycle = true; 12332292SN/A 12342292SN/A removeList.push(inst->getInstListIt()); 12351060SN/A} 12361060SN/A 12371060SN/Atemplate <class Impl> 12381060SN/Avoid 12391755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 12401060SN/A{ 12412733Sktlim@umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 12422292SN/A "[sn:%lli]\n", 12432303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 12441060SN/A 12452292SN/A removeInstsThisCycle = true; 12461060SN/A 12471060SN/A // Remove the front instruction. 12482292SN/A removeList.push(inst->getInstListIt()); 12491060SN/A} 12501060SN/A 12511060SN/Atemplate <class Impl> 12521060SN/Avoid 12534632Sgblack@eecs.umich.eduFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 12541060SN/A{ 12552733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 12562292SN/A " list.\n", tid); 12571060SN/A 12582292SN/A ListIt end_it; 12591060SN/A 12602292SN/A bool rob_empty = false; 12612292SN/A 12622292SN/A if (instList.empty()) { 12632292SN/A return; 12642292SN/A } else if (rob.isEmpty(/*tid*/)) { 12652733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 12662292SN/A end_it = instList.begin(); 12672292SN/A rob_empty = true; 12682292SN/A } else { 12692292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 12702733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 12712292SN/A } 12722292SN/A 12732292SN/A removeInstsThisCycle = true; 12742292SN/A 12752292SN/A ListIt inst_it = instList.end(); 12762292SN/A 12772292SN/A inst_it--; 12782292SN/A 12792292SN/A // Walk through the instruction list, removing any instructions 12802292SN/A // that were inserted after the given instruction iterator, end_it. 12812292SN/A while (inst_it != end_it) { 12822292SN/A assert(!instList.empty()); 12832292SN/A 12842292SN/A squashInstIt(inst_it, tid); 12852292SN/A 12862292SN/A inst_it--; 12872292SN/A } 12882292SN/A 12892292SN/A // If the ROB was empty, then we actually need to remove the first 12902292SN/A // instruction as well. 12912292SN/A if (rob_empty) { 12922292SN/A squashInstIt(inst_it, tid); 12932292SN/A } 12941060SN/A} 12951060SN/A 12961060SN/Atemplate <class Impl> 12971060SN/Avoid 12982292SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 12992292SN/A unsigned tid) 13001062SN/A{ 13012292SN/A assert(!instList.empty()); 13022292SN/A 13032292SN/A removeInstsThisCycle = true; 13042292SN/A 13052292SN/A ListIt inst_iter = instList.end(); 13062292SN/A 13072292SN/A inst_iter--; 13082292SN/A 13092733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 13102292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 13112292SN/A tid, seq_num, (*inst_iter)->seqNum); 13121062SN/A 13132292SN/A while ((*inst_iter)->seqNum > seq_num) { 13141062SN/A 13152292SN/A bool break_loop = (inst_iter == instList.begin()); 13161062SN/A 13172292SN/A squashInstIt(inst_iter, tid); 13181062SN/A 13192292SN/A inst_iter--; 13201062SN/A 13212292SN/A if (break_loop) 13222292SN/A break; 13232292SN/A } 13242292SN/A} 13252292SN/A 13262292SN/Atemplate <class Impl> 13272292SN/Ainline void 13282292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 13292292SN/A{ 13302292SN/A if ((*instIt)->threadNumber == tid) { 13312733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 13322292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 13332292SN/A (*instIt)->threadNumber, 13342292SN/A (*instIt)->seqNum, 13352292SN/A (*instIt)->readPC()); 13361062SN/A 13371062SN/A // Mark it as squashed. 13382292SN/A (*instIt)->setSquashed(); 13392292SN/A 13402325SN/A // @todo: Formulate a consistent method for deleting 13412325SN/A // instructions from the instruction list 13422292SN/A // Remove the instruction from the list. 13432292SN/A removeList.push(instIt); 13442292SN/A } 13452292SN/A} 13462292SN/A 13472292SN/Atemplate <class Impl> 13482292SN/Avoid 13492292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 13502292SN/A{ 13512292SN/A while (!removeList.empty()) { 13522733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 13532292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 13542292SN/A (*removeList.front())->threadNumber, 13552292SN/A (*removeList.front())->seqNum, 13562292SN/A (*removeList.front())->readPC()); 13572292SN/A 13582292SN/A instList.erase(removeList.front()); 13592292SN/A 13602292SN/A removeList.pop(); 13611062SN/A } 13621062SN/A 13632292SN/A removeInstsThisCycle = false; 13641062SN/A} 13652325SN/A/* 13661062SN/Atemplate <class Impl> 13671062SN/Avoid 13681755SN/AFullO3CPU<Impl>::removeAllInsts() 13691060SN/A{ 13701060SN/A instList.clear(); 13711060SN/A} 13722325SN/A*/ 13731060SN/Atemplate <class Impl> 13741060SN/Avoid 13751755SN/AFullO3CPU<Impl>::dumpInsts() 13761060SN/A{ 13771060SN/A int num = 0; 13781060SN/A 13792292SN/A ListIt inst_list_it = instList.begin(); 13802292SN/A 13812292SN/A cprintf("Dumping Instruction List\n"); 13822292SN/A 13832292SN/A while (inst_list_it != instList.end()) { 13842292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 13852292SN/A "Squashed:%i\n\n", 13862292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 13872292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 13882292SN/A (*inst_list_it)->isSquashed()); 13891060SN/A inst_list_it++; 13901060SN/A ++num; 13911060SN/A } 13921060SN/A} 13932325SN/A/* 13941060SN/Atemplate <class Impl> 13951060SN/Avoid 13961755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 13971060SN/A{ 13981060SN/A iew.wakeDependents(inst); 13991060SN/A} 14002325SN/A*/ 14012292SN/Atemplate <class Impl> 14022292SN/Avoid 14032292SN/AFullO3CPU<Impl>::wakeCPU() 14042292SN/A{ 14052325SN/A if (activityRec.active() || tickEvent.scheduled()) { 14062325SN/A DPRINTF(Activity, "CPU already running.\n"); 14072292SN/A return; 14082292SN/A } 14092292SN/A 14102325SN/A DPRINTF(Activity, "Waking up CPU\n"); 14112325SN/A 14125099Ssaidi@eecs.umich.edu idleCycles += tickToCycles((curTick - 1) - lastRunningCycle); 14135099Ssaidi@eecs.umich.edu numCycles += tickToCycles((curTick - 1) - lastRunningCycle); 14142292SN/A 14154030Sktlim@umich.edu tickEvent.schedule(nextCycle()); 14162292SN/A} 14172292SN/A 14182292SN/Atemplate <class Impl> 14192292SN/Aint 14202292SN/AFullO3CPU<Impl>::getFreeTid() 14212292SN/A{ 14222292SN/A for (int i=0; i < numThreads; i++) { 14232292SN/A if (!tids[i]) { 14242292SN/A tids[i] = true; 14252292SN/A return i; 14262292SN/A } 14272292SN/A } 14282292SN/A 14292292SN/A return -1; 14302292SN/A} 14312292SN/A 14322292SN/Atemplate <class Impl> 14332292SN/Avoid 14342292SN/AFullO3CPU<Impl>::doContextSwitch() 14352292SN/A{ 14362292SN/A if (contextSwitch) { 14372292SN/A 14382292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 14392292SN/A 14402292SN/A for (int tid=0; tid < cpuWaitList.size(); tid++) { 14412292SN/A activateWhenReady(tid); 14422292SN/A } 14432292SN/A 14442292SN/A if (cpuWaitList.size() == 0) 14452292SN/A contextSwitch = true; 14462292SN/A } 14472292SN/A} 14482292SN/A 14492292SN/Atemplate <class Impl> 14502292SN/Avoid 14512292SN/AFullO3CPU<Impl>::updateThreadPriority() 14522292SN/A{ 14532292SN/A if (activeThreads.size() > 1) 14542292SN/A { 14552292SN/A //DEFAULT TO ROUND ROBIN SCHEME 14562292SN/A //e.g. Move highest priority to end of thread list 14572292SN/A list<unsigned>::iterator list_begin = activeThreads.begin(); 14582292SN/A list<unsigned>::iterator list_end = activeThreads.end(); 14592292SN/A 14602292SN/A unsigned high_thread = *list_begin; 14612292SN/A 14622292SN/A activeThreads.erase(list_begin); 14632292SN/A 14642292SN/A activeThreads.push_back(high_thread); 14652292SN/A } 14662292SN/A} 14671060SN/A 14681755SN/A// Forward declaration of FullO3CPU. 14692818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1470