cpu.cc revision 4636
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 341858SN/A 351858SN/A#if FULL_SYSTEM 362356SN/A#include "cpu/quiesce_event.hh" 371060SN/A#include "sim/system.hh" 381060SN/A#else 391060SN/A#include "sim/process.hh" 401060SN/A#endif 411060SN/A 422325SN/A#include "cpu/activity.hh" 432683Sktlim@umich.edu#include "cpu/simple_thread.hh" 442680Sktlim@umich.edu#include "cpu/thread_context.hh" 452817Sksewell@umich.edu#include "cpu/o3/isa_specific.hh" 461717SN/A#include "cpu/o3/cpu.hh" 471060SN/A 484167Sbinkertn@umich.edu#include "sim/core.hh" 492292SN/A#include "sim/stat_control.hh" 502292SN/A 512794Sktlim@umich.edu#if USE_CHECKER 522794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 532794Sktlim@umich.edu#endif 542794Sktlim@umich.edu 551060SN/Ausing namespace std; 562669Sktlim@umich.eduusing namespace TheISA; 571060SN/A 582733Sktlim@umich.eduBaseO3CPU::BaseO3CPU(Params *params) 592292SN/A : BaseCPU(params), cpu_id(0) 601060SN/A{ 611060SN/A} 621060SN/A 632292SN/Avoid 642733Sktlim@umich.eduBaseO3CPU::regStats() 652292SN/A{ 662292SN/A BaseCPU::regStats(); 672292SN/A} 682292SN/A 691060SN/Atemplate <class Impl> 701755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 711060SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 721060SN/A{ 731060SN/A} 741060SN/A 751060SN/Atemplate <class Impl> 761060SN/Avoid 771755SN/AFullO3CPU<Impl>::TickEvent::process() 781060SN/A{ 791060SN/A cpu->tick(); 801060SN/A} 811060SN/A 821060SN/Atemplate <class Impl> 831060SN/Aconst char * 841755SN/AFullO3CPU<Impl>::TickEvent::description() 851060SN/A{ 861755SN/A return "FullO3CPU tick event"; 871060SN/A} 881060SN/A 891060SN/Atemplate <class Impl> 902829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 913221Sktlim@umich.edu : Event(&mainEventQueue, CPU_Switch_Pri) 922829Sksewell@umich.edu{ 932829Sksewell@umich.edu} 942829Sksewell@umich.edu 952829Sksewell@umich.edutemplate <class Impl> 962829Sksewell@umich.eduvoid 972829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 982829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 992829Sksewell@umich.edu{ 1002829Sksewell@umich.edu tid = thread_num; 1012829Sksewell@umich.edu cpu = thread_cpu; 1022829Sksewell@umich.edu} 1032829Sksewell@umich.edu 1042829Sksewell@umich.edutemplate <class Impl> 1052829Sksewell@umich.eduvoid 1062829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1072829Sksewell@umich.edu{ 1082829Sksewell@umich.edu cpu->activateThread(tid); 1092829Sksewell@umich.edu} 1102829Sksewell@umich.edu 1112829Sksewell@umich.edutemplate <class Impl> 1122829Sksewell@umich.educonst char * 1132829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::description() 1142829Sksewell@umich.edu{ 1152829Sksewell@umich.edu return "FullO3CPU \"Activate Thread\" event"; 1162829Sksewell@umich.edu} 1172829Sksewell@umich.edu 1182829Sksewell@umich.edutemplate <class Impl> 1192875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1203859Sbinkertn@umich.edu : Event(&mainEventQueue, CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1212875Sksewell@umich.edu{ 1222875Sksewell@umich.edu} 1232875Sksewell@umich.edu 1242875Sksewell@umich.edutemplate <class Impl> 1252875Sksewell@umich.eduvoid 1262875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1273859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1282875Sksewell@umich.edu{ 1292875Sksewell@umich.edu tid = thread_num; 1302875Sksewell@umich.edu cpu = thread_cpu; 1313859Sbinkertn@umich.edu remove = false; 1322875Sksewell@umich.edu} 1332875Sksewell@umich.edu 1342875Sksewell@umich.edutemplate <class Impl> 1352875Sksewell@umich.eduvoid 1362875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1372875Sksewell@umich.edu{ 1382875Sksewell@umich.edu cpu->deactivateThread(tid); 1393221Sktlim@umich.edu if (remove) 1403221Sktlim@umich.edu cpu->removeThread(tid); 1412875Sksewell@umich.edu} 1422875Sksewell@umich.edu 1432875Sksewell@umich.edutemplate <class Impl> 1442875Sksewell@umich.educonst char * 1452875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::description() 1462875Sksewell@umich.edu{ 1472875Sksewell@umich.edu return "FullO3CPU \"Deallocate Context\" event"; 1482875Sksewell@umich.edu} 1492875Sksewell@umich.edu 1502875Sksewell@umich.edutemplate <class Impl> 1514329Sktlim@umich.eduFullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, Params *params) 1522733Sktlim@umich.edu : BaseO3CPU(params), 1533781Sgblack@eecs.umich.edu#if FULL_SYSTEM 1543781Sgblack@eecs.umich.edu itb(params->itb), 1553781Sgblack@eecs.umich.edu dtb(params->dtb), 1563781Sgblack@eecs.umich.edu#endif 1571060SN/A tickEvent(this), 1582292SN/A removeInstsThisCycle(false), 1594329Sktlim@umich.edu fetch(o3_cpu, params), 1604329Sktlim@umich.edu decode(o3_cpu, params), 1614329Sktlim@umich.edu rename(o3_cpu, params), 1624329Sktlim@umich.edu iew(o3_cpu, params), 1634329Sktlim@umich.edu commit(o3_cpu, params), 1641060SN/A 1654329Sktlim@umich.edu regFile(o3_cpu, params->numPhysIntRegs, 1664329Sktlim@umich.edu params->numPhysFloatRegs), 1671060SN/A 1682831Sksewell@umich.edu freeList(params->numberOfThreads, 1692292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1702292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1711060SN/A 1724329Sktlim@umich.edu rob(o3_cpu, 1734329Sktlim@umich.edu params->numROBEntries, params->squashWidth, 1742292SN/A params->smtROBPolicy, params->smtROBThreshold, 1752292SN/A params->numberOfThreads), 1761060SN/A 1772831Sksewell@umich.edu scoreboard(params->numberOfThreads, 1782292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1792292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1802292SN/A TheISA::NumMiscRegs * number_of_threads, 1812292SN/A TheISA::ZeroReg), 1821060SN/A 1832873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1842873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1852873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1862873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1872873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1882873Sktlim@umich.edu activityRec(NumStages, 1892873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1902873Sktlim@umich.edu params->activity), 1911060SN/A 1921060SN/A globalSeqNum(1), 1931858SN/A#if FULL_SYSTEM 1942292SN/A system(params->system), 1951060SN/A physmem(system->physmem), 1961060SN/A#endif // FULL_SYSTEM 1972843Sktlim@umich.edu drainCount(0), 1982316SN/A deferRegistration(params->deferRegistration), 1992316SN/A numThreads(number_of_threads) 2001060SN/A{ 2013221Sktlim@umich.edu if (!deferRegistration) { 2023221Sktlim@umich.edu _status = Running; 2033221Sktlim@umich.edu } else { 2043221Sktlim@umich.edu _status = Idle; 2053221Sktlim@umich.edu } 2061681SN/A 2072733Sktlim@umich.edu checker = NULL; 2082733Sktlim@umich.edu 2092794Sktlim@umich.edu if (params->checker) { 2102733Sktlim@umich.edu#if USE_CHECKER 2112316SN/A BaseCPU *temp_checker = params->checker; 2122316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2132316SN/A#if FULL_SYSTEM 2142316SN/A checker->setSystem(params->system); 2152316SN/A#endif 2162794Sktlim@umich.edu#else 2172794Sktlim@umich.edu panic("Checker enabled but not compiled in!"); 2182794Sktlim@umich.edu#endif // USE_CHECKER 2192316SN/A } 2202316SN/A 2211858SN/A#if !FULL_SYSTEM 2222292SN/A thread.resize(number_of_threads); 2232292SN/A tids.resize(number_of_threads); 2241681SN/A#endif 2251681SN/A 2262325SN/A // The stages also need their CPU pointer setup. However this 2272325SN/A // must be done at the upper level CPU because they have pointers 2282325SN/A // to the upper level CPU, and not this FullO3CPU. 2291060SN/A 2302292SN/A // Set up Pointers to the activeThreads list for each stage 2312292SN/A fetch.setActiveThreads(&activeThreads); 2322292SN/A decode.setActiveThreads(&activeThreads); 2332292SN/A rename.setActiveThreads(&activeThreads); 2342292SN/A iew.setActiveThreads(&activeThreads); 2352292SN/A commit.setActiveThreads(&activeThreads); 2361060SN/A 2371060SN/A // Give each of the stages the time buffer they will use. 2381060SN/A fetch.setTimeBuffer(&timeBuffer); 2391060SN/A decode.setTimeBuffer(&timeBuffer); 2401060SN/A rename.setTimeBuffer(&timeBuffer); 2411060SN/A iew.setTimeBuffer(&timeBuffer); 2421060SN/A commit.setTimeBuffer(&timeBuffer); 2431060SN/A 2441060SN/A // Also setup each of the stages' queues. 2451060SN/A fetch.setFetchQueue(&fetchQueue); 2461060SN/A decode.setFetchQueue(&fetchQueue); 2472292SN/A commit.setFetchQueue(&fetchQueue); 2481060SN/A decode.setDecodeQueue(&decodeQueue); 2491060SN/A rename.setDecodeQueue(&decodeQueue); 2501060SN/A rename.setRenameQueue(&renameQueue); 2511060SN/A iew.setRenameQueue(&renameQueue); 2521060SN/A iew.setIEWQueue(&iewQueue); 2531060SN/A commit.setIEWQueue(&iewQueue); 2541060SN/A commit.setRenameQueue(&renameQueue); 2551060SN/A 2562292SN/A commit.setIEWStage(&iew); 2572292SN/A rename.setIEWStage(&iew); 2582292SN/A rename.setCommitStage(&commit); 2592292SN/A 2602292SN/A#if !FULL_SYSTEM 2612307SN/A int active_threads = params->workload.size(); 2622831Sksewell@umich.edu 2632831Sksewell@umich.edu if (active_threads > Impl::MaxThreads) { 2642831Sksewell@umich.edu panic("Workload Size too large. Increase the 'MaxThreads'" 2652831Sksewell@umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2662831Sksewell@umich.edu "edit your workload size."); 2672831Sksewell@umich.edu } 2682292SN/A#else 2692307SN/A int active_threads = 1; 2702292SN/A#endif 2712292SN/A 2722316SN/A //Make Sure That this a Valid Architeture 2732292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2742292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2752292SN/A 2762292SN/A rename.setScoreboard(&scoreboard); 2772292SN/A iew.setScoreboard(&scoreboard); 2782292SN/A 2791060SN/A // Setup the rename map for whichever stages need it. 2802292SN/A PhysRegIndex lreg_idx = 0; 2812292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2821060SN/A 2832292SN/A for (int tid=0; tid < numThreads; tid++) { 2842307SN/A bool bindRegs = (tid <= active_threads - 1); 2852292SN/A 2862292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2872292SN/A params->numPhysIntRegs, 2882325SN/A lreg_idx, //Index for Logical. Regs 2892292SN/A 2902292SN/A TheISA::NumFloatRegs, 2912292SN/A params->numPhysFloatRegs, 2922325SN/A freg_idx, //Index for Float Regs 2932292SN/A 2942292SN/A TheISA::NumMiscRegs, 2952292SN/A 2962292SN/A TheISA::ZeroReg, 2972292SN/A TheISA::ZeroReg, 2982292SN/A 2992292SN/A tid, 3002292SN/A false); 3012292SN/A 3022292SN/A renameMap[tid].init(TheISA::NumIntRegs, 3032292SN/A params->numPhysIntRegs, 3042325SN/A lreg_idx, //Index for Logical. Regs 3052292SN/A 3062292SN/A TheISA::NumFloatRegs, 3072292SN/A params->numPhysFloatRegs, 3082325SN/A freg_idx, //Index for Float Regs 3092292SN/A 3102292SN/A TheISA::NumMiscRegs, 3112292SN/A 3122292SN/A TheISA::ZeroReg, 3132292SN/A TheISA::ZeroReg, 3142292SN/A 3152292SN/A tid, 3162292SN/A bindRegs); 3173221Sktlim@umich.edu 3183221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3193221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3202292SN/A } 3212292SN/A 3222292SN/A rename.setRenameMap(renameMap); 3232292SN/A commit.setRenameMap(commitRenameMap); 3242292SN/A 3252292SN/A // Give renameMap & rename stage access to the freeList; 3262292SN/A for (int i=0; i < numThreads; i++) { 3272292SN/A renameMap[i].setFreeList(&freeList); 3282292SN/A } 3291060SN/A rename.setFreeList(&freeList); 3302292SN/A 3311060SN/A // Setup the ROB for whichever stages need it. 3321060SN/A commit.setROB(&rob); 3332292SN/A 3342292SN/A lastRunningCycle = curTick; 3352292SN/A 3362829Sksewell@umich.edu lastActivatedCycle = -1; 3372829Sksewell@umich.edu 3383093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3393093Sksewell@umich.edu //for (int i=0; i < numThreads; i++) { 3403093Sksewell@umich.edu //globalSeqNum[i] = 1; 3413093Sksewell@umich.edu //} 3423093Sksewell@umich.edu 3432292SN/A contextSwitch = false; 3441060SN/A} 3451060SN/A 3461060SN/Atemplate <class Impl> 3471755SN/AFullO3CPU<Impl>::~FullO3CPU() 3481060SN/A{ 3491060SN/A} 3501060SN/A 3511060SN/Atemplate <class Impl> 3521060SN/Avoid 3531755SN/AFullO3CPU<Impl>::fullCPURegStats() 3541062SN/A{ 3552733Sktlim@umich.edu BaseO3CPU::regStats(); 3562292SN/A 3572733Sktlim@umich.edu // Register any of the O3CPU's stats here. 3582292SN/A timesIdled 3592292SN/A .name(name() + ".timesIdled") 3602292SN/A .desc("Number of times that the entire CPU went into an idle state and" 3612292SN/A " unscheduled itself") 3622292SN/A .prereq(timesIdled); 3632292SN/A 3642292SN/A idleCycles 3652292SN/A .name(name() + ".idleCycles") 3662292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 3672292SN/A "to idling") 3682292SN/A .prereq(idleCycles); 3692292SN/A 3702292SN/A // Number of Instructions simulated 3712292SN/A // -------------------------------- 3722292SN/A // Should probably be in Base CPU but need templated 3732292SN/A // MaxThreads so put in here instead 3742292SN/A committedInsts 3752292SN/A .init(numThreads) 3762292SN/A .name(name() + ".committedInsts") 3772292SN/A .desc("Number of Instructions Simulated"); 3782292SN/A 3792292SN/A totalCommittedInsts 3802292SN/A .name(name() + ".committedInsts_total") 3812292SN/A .desc("Number of Instructions Simulated"); 3822292SN/A 3832292SN/A cpi 3842292SN/A .name(name() + ".cpi") 3852292SN/A .desc("CPI: Cycles Per Instruction") 3862292SN/A .precision(6); 3872292SN/A cpi = simTicks / committedInsts; 3882292SN/A 3892292SN/A totalCpi 3902292SN/A .name(name() + ".cpi_total") 3912292SN/A .desc("CPI: Total CPI of All Threads") 3922292SN/A .precision(6); 3932292SN/A totalCpi = simTicks / totalCommittedInsts; 3942292SN/A 3952292SN/A ipc 3962292SN/A .name(name() + ".ipc") 3972292SN/A .desc("IPC: Instructions Per Cycle") 3982292SN/A .precision(6); 3992292SN/A ipc = committedInsts / simTicks; 4002292SN/A 4012292SN/A totalIpc 4022292SN/A .name(name() + ".ipc_total") 4032292SN/A .desc("IPC: Total IPC of All Threads") 4042292SN/A .precision(6); 4052292SN/A totalIpc = totalCommittedInsts / simTicks; 4062292SN/A 4071062SN/A} 4081062SN/A 4091062SN/Atemplate <class Impl> 4102871Sktlim@umich.eduPort * 4112871Sktlim@umich.eduFullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 4122871Sktlim@umich.edu{ 4132871Sktlim@umich.edu if (if_name == "dcache_port") 4142871Sktlim@umich.edu return iew.getDcachePort(); 4152871Sktlim@umich.edu else if (if_name == "icache_port") 4162871Sktlim@umich.edu return fetch.getIcachePort(); 4172871Sktlim@umich.edu else 4182871Sktlim@umich.edu panic("No Such Port\n"); 4192871Sktlim@umich.edu} 4202871Sktlim@umich.edu 4212871Sktlim@umich.edutemplate <class Impl> 4221062SN/Avoid 4231755SN/AFullO3CPU<Impl>::tick() 4241060SN/A{ 4252733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 4261060SN/A 4272292SN/A ++numCycles; 4282292SN/A 4292325SN/A// activity = false; 4302292SN/A 4312292SN/A //Tick each of the stages 4321060SN/A fetch.tick(); 4331060SN/A 4341060SN/A decode.tick(); 4351060SN/A 4361060SN/A rename.tick(); 4371060SN/A 4381060SN/A iew.tick(); 4391060SN/A 4401060SN/A commit.tick(); 4411060SN/A 4422292SN/A#if !FULL_SYSTEM 4432292SN/A doContextSwitch(); 4442292SN/A#endif 4452292SN/A 4462292SN/A // Now advance the time buffers 4471060SN/A timeBuffer.advance(); 4481060SN/A 4491060SN/A fetchQueue.advance(); 4501060SN/A decodeQueue.advance(); 4511060SN/A renameQueue.advance(); 4521060SN/A iewQueue.advance(); 4531060SN/A 4542325SN/A activityRec.advance(); 4552292SN/A 4562292SN/A if (removeInstsThisCycle) { 4572292SN/A cleanUpRemovedInsts(); 4582292SN/A } 4592292SN/A 4602325SN/A if (!tickEvent.scheduled()) { 4612867Sktlim@umich.edu if (_status == SwitchedOut || 4622905Sktlim@umich.edu getState() == SimObject::Drained) { 4633226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 4642325SN/A // increment stat 4652325SN/A lastRunningCycle = curTick; 4663221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 4673226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 4682325SN/A lastRunningCycle = curTick; 4692325SN/A timesIdled++; 4702325SN/A } else { 4714030Sktlim@umich.edu tickEvent.schedule(nextCycle(curTick + cycles(1))); 4723226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 4732325SN/A } 4742292SN/A } 4752292SN/A 4762292SN/A#if !FULL_SYSTEM 4772292SN/A updateThreadPriority(); 4782292SN/A#endif 4792292SN/A 4801060SN/A} 4811060SN/A 4821060SN/Atemplate <class Impl> 4831060SN/Avoid 4841755SN/AFullO3CPU<Impl>::init() 4851060SN/A{ 4862307SN/A if (!deferRegistration) { 4872680Sktlim@umich.edu registerThreadContexts(); 4882292SN/A } 4891060SN/A 4902292SN/A // Set inSyscall so that the CPU doesn't squash when initially 4912292SN/A // setting up registers. 4922292SN/A for (int i = 0; i < number_of_threads; ++i) 4932292SN/A thread[i]->inSyscall = true; 4942292SN/A 4952292SN/A for (int tid=0; tid < number_of_threads; tid++) { 4961858SN/A#if FULL_SYSTEM 4972680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 4981681SN/A#else 4992680Sktlim@umich.edu ThreadContext *src_tc = thread[tid]->getTC(); 5001681SN/A#endif 5012292SN/A // Threads start in the Suspended State 5022680Sktlim@umich.edu if (src_tc->status() != ThreadContext::Suspended) { 5032292SN/A continue; 5041060SN/A } 5051060SN/A 5062292SN/A#if FULL_SYSTEM 5072680Sktlim@umich.edu TheISA::initCPU(src_tc, src_tc->readCpuId()); 5082292SN/A#endif 5092292SN/A } 5102292SN/A 5112292SN/A // Clear inSyscall. 5122292SN/A for (int i = 0; i < number_of_threads; ++i) 5132292SN/A thread[i]->inSyscall = false; 5142292SN/A 5152316SN/A // Initialize stages. 5162292SN/A fetch.initStage(); 5172292SN/A iew.initStage(); 5182292SN/A rename.initStage(); 5192292SN/A commit.initStage(); 5202292SN/A 5212292SN/A commit.setThreads(thread); 5222292SN/A} 5232292SN/A 5242292SN/Atemplate <class Impl> 5252292SN/Avoid 5262875Sksewell@umich.eduFullO3CPU<Impl>::activateThread(unsigned tid) 5272875Sksewell@umich.edu{ 5282875Sksewell@umich.edu list<unsigned>::iterator isActive = find( 5292875Sksewell@umich.edu activeThreads.begin(), activeThreads.end(), tid); 5302875Sksewell@umich.edu 5313226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 5323226Sktlim@umich.edu 5332875Sksewell@umich.edu if (isActive == activeThreads.end()) { 5342875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 5352875Sksewell@umich.edu tid); 5362875Sksewell@umich.edu 5372875Sksewell@umich.edu activeThreads.push_back(tid); 5382875Sksewell@umich.edu } 5392875Sksewell@umich.edu} 5402875Sksewell@umich.edu 5412875Sksewell@umich.edutemplate <class Impl> 5422875Sksewell@umich.eduvoid 5432875Sksewell@umich.eduFullO3CPU<Impl>::deactivateThread(unsigned tid) 5442875Sksewell@umich.edu{ 5452875Sksewell@umich.edu //Remove From Active List, if Active 5462875Sksewell@umich.edu list<unsigned>::iterator thread_it = 5472875Sksewell@umich.edu find(activeThreads.begin(), activeThreads.end(), tid); 5482875Sksewell@umich.edu 5493226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 5503226Sktlim@umich.edu 5512875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 5522875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 5532875Sksewell@umich.edu tid); 5542875Sksewell@umich.edu activeThreads.erase(thread_it); 5552875Sksewell@umich.edu } 5562875Sksewell@umich.edu} 5572875Sksewell@umich.edu 5582875Sksewell@umich.edutemplate <class Impl> 5592875Sksewell@umich.eduvoid 5602875Sksewell@umich.eduFullO3CPU<Impl>::activateContext(int tid, int delay) 5612875Sksewell@umich.edu{ 5622875Sksewell@umich.edu // Needs to set each stage to running as well. 5632875Sksewell@umich.edu if (delay){ 5642875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 5652875Sksewell@umich.edu "on cycle %d\n", tid, curTick + cycles(delay)); 5662875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 5672875Sksewell@umich.edu } else { 5682875Sksewell@umich.edu activateThread(tid); 5692875Sksewell@umich.edu } 5702875Sksewell@umich.edu 5713221Sktlim@umich.edu if (lastActivatedCycle < curTick) { 5722875Sksewell@umich.edu scheduleTickEvent(delay); 5732875Sksewell@umich.edu 5742875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 5752875Sksewell@umich.edu // deschedule itself. 5762875Sksewell@umich.edu activityRec.activity(); 5772875Sksewell@umich.edu fetch.wakeFromQuiesce(); 5782875Sksewell@umich.edu 5792875Sksewell@umich.edu lastActivatedCycle = curTick; 5802875Sksewell@umich.edu 5812875Sksewell@umich.edu _status = Running; 5822875Sksewell@umich.edu } 5832875Sksewell@umich.edu} 5842875Sksewell@umich.edu 5852875Sksewell@umich.edutemplate <class Impl> 5863221Sktlim@umich.edubool 5873221Sktlim@umich.eduFullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay) 5882875Sksewell@umich.edu{ 5892875Sksewell@umich.edu // Schedule removal of thread data from CPU 5902875Sksewell@umich.edu if (delay){ 5912875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 5922875Sksewell@umich.edu "on cycle %d\n", tid, curTick + cycles(delay)); 5933221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 5943221Sktlim@umich.edu return false; 5952875Sksewell@umich.edu } else { 5962875Sksewell@umich.edu deactivateThread(tid); 5973221Sktlim@umich.edu if (remove) 5983221Sktlim@umich.edu removeThread(tid); 5993221Sktlim@umich.edu return true; 6002875Sksewell@umich.edu } 6012875Sksewell@umich.edu} 6022875Sksewell@umich.edu 6032875Sksewell@umich.edutemplate <class Impl> 6042875Sksewell@umich.eduvoid 6052875Sksewell@umich.eduFullO3CPU<Impl>::suspendContext(int tid) 6062875Sksewell@umich.edu{ 6072875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 6083221Sktlim@umich.edu bool deallocated = deallocateContext(tid, false, 1); 6093221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 6103859Sbinkertn@umich.edu if (activeThreads.size() == 1 && !deallocated || 6113859Sbinkertn@umich.edu activeThreads.size() == 0) 6122910Sksewell@umich.edu unscheduleTickEvent(); 6132875Sksewell@umich.edu _status = Idle; 6142875Sksewell@umich.edu} 6152875Sksewell@umich.edu 6162875Sksewell@umich.edutemplate <class Impl> 6172875Sksewell@umich.eduvoid 6182875Sksewell@umich.eduFullO3CPU<Impl>::haltContext(int tid) 6192875Sksewell@umich.edu{ 6202910Sksewell@umich.edu //For now, this is the same as deallocate 6212910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 6223221Sktlim@umich.edu deallocateContext(tid, true, 1); 6232875Sksewell@umich.edu} 6242875Sksewell@umich.edu 6252875Sksewell@umich.edutemplate <class Impl> 6262875Sksewell@umich.eduvoid 6272292SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 6282292SN/A{ 6292847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 6302292SN/A // Will change now that the PC and thread state is internal to the CPU 6312683Sktlim@umich.edu // and not in the ThreadContext. 6322292SN/A#if FULL_SYSTEM 6332680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 6342292SN/A#else 6352847Sksewell@umich.edu ThreadContext *src_tc = tcBase(tid); 6362292SN/A#endif 6372292SN/A 6382292SN/A //Bind Int Regs to Rename Map 6392292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 6402292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 6412292SN/A 6422292SN/A renameMap[tid].setEntry(ireg,phys_reg); 6432292SN/A scoreboard.setReg(phys_reg); 6442292SN/A } 6452292SN/A 6462292SN/A //Bind Float Regs to Rename Map 6472292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 6482292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 6492292SN/A 6502292SN/A renameMap[tid].setEntry(freg,phys_reg); 6512292SN/A scoreboard.setReg(phys_reg); 6522292SN/A } 6532292SN/A 6542292SN/A //Copy Thread Data Into RegFile 6552847Sksewell@umich.edu //this->copyFromTC(tid); 6562292SN/A 6572847Sksewell@umich.edu //Set PC/NPC/NNPC 6582847Sksewell@umich.edu setPC(src_tc->readPC(), tid); 6592847Sksewell@umich.edu setNextPC(src_tc->readNextPC(), tid); 6602847Sksewell@umich.edu setNextNPC(src_tc->readNextNPC(), tid); 6612292SN/A 6622680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 6632292SN/A 6642292SN/A activateContext(tid,1); 6652292SN/A 6662292SN/A //Reset ROB/IQ/LSQ Entries 6672292SN/A commit.rob->resetEntries(); 6682292SN/A iew.resetEntries(); 6692292SN/A} 6702292SN/A 6712292SN/Atemplate <class Impl> 6722292SN/Avoid 6732292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 6742292SN/A{ 6752877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 6762847Sksewell@umich.edu 6772847Sksewell@umich.edu // Copy Thread Data From RegFile 6782847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 6792847Sksewell@umich.edu //this->copyToTC(tid); 6802847Sksewell@umich.edu 6812847Sksewell@umich.edu // Unbind Int Regs from Rename Map 6822292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 6832292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 6842292SN/A 6852292SN/A scoreboard.unsetReg(phys_reg); 6862292SN/A freeList.addReg(phys_reg); 6872292SN/A } 6882292SN/A 6892847Sksewell@umich.edu // Unbind Float Regs from Rename Map 6902292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 6912292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 6922292SN/A 6932292SN/A scoreboard.unsetReg(phys_reg); 6942292SN/A freeList.addReg(phys_reg); 6952292SN/A } 6962292SN/A 6972847Sksewell@umich.edu // Squash Throughout Pipeline 6982935Sksewell@umich.edu InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; 6994636Sgblack@eecs.umich.edu fetch.squash(0, sizeof(TheISA::MachInst), 0, squash_seq_num, tid); 7002292SN/A decode.squash(tid); 7012935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 7022875Sksewell@umich.edu iew.squash(tid); 7032935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 7042292SN/A 7052292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 7062292SN/A 7072847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 7083229Sktlim@umich.edu 7093229Sktlim@umich.edu // Commented out for now. This should be possible to do by 7103229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 7113229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 7123229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 7133229Sktlim@umich.edu/* 7142292SN/A if (activeThreads.size() >= 1) { 7152292SN/A commit.rob->resetEntries(); 7162292SN/A iew.resetEntries(); 7172292SN/A } 7183229Sktlim@umich.edu*/ 7192292SN/A} 7202292SN/A 7212292SN/A 7222292SN/Atemplate <class Impl> 7232292SN/Avoid 7242292SN/AFullO3CPU<Impl>::activateWhenReady(int tid) 7252292SN/A{ 7262733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 7272292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 7282292SN/A tid); 7292292SN/A 7302292SN/A bool ready = true; 7312292SN/A 7322292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 7332733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7342292SN/A "Phys. Int. Regs.\n", 7352292SN/A tid); 7362292SN/A ready = false; 7372292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 7382733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7392292SN/A "Phys. Float. Regs.\n", 7402292SN/A tid); 7412292SN/A ready = false; 7422292SN/A } else if (commit.rob->numFreeEntries() >= 7432292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 7442733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7452292SN/A "ROB entries.\n", 7462292SN/A tid); 7472292SN/A ready = false; 7482292SN/A } else if (iew.instQueue.numFreeEntries() >= 7492292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 7502733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7512292SN/A "IQ entries.\n", 7522292SN/A tid); 7532292SN/A ready = false; 7542292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 7552292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 7562733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7572292SN/A "LSQ entries.\n", 7582292SN/A tid); 7592292SN/A ready = false; 7602292SN/A } 7612292SN/A 7622292SN/A if (ready) { 7632292SN/A insertThread(tid); 7642292SN/A 7652292SN/A contextSwitch = false; 7662292SN/A 7672292SN/A cpuWaitList.remove(tid); 7682292SN/A } else { 7692292SN/A suspendContext(tid); 7702292SN/A 7712292SN/A //blocks fetch 7722292SN/A contextSwitch = true; 7732292SN/A 7742875Sksewell@umich.edu //@todo: dont always add to waitlist 7752292SN/A //do waitlist 7762292SN/A cpuWaitList.push_back(tid); 7771060SN/A } 7781060SN/A} 7791060SN/A 7804192Sktlim@umich.edu#if FULL_SYSTEM 7814192Sktlim@umich.edutemplate <class Impl> 7824192Sktlim@umich.eduvoid 7834192Sktlim@umich.eduFullO3CPU<Impl>::updateMemPorts() 7844192Sktlim@umich.edu{ 7854192Sktlim@umich.edu // Update all ThreadContext's memory ports (Functional/Virtual 7864192Sktlim@umich.edu // Ports) 7874192Sktlim@umich.edu for (int i = 0; i < thread.size(); ++i) 7884192Sktlim@umich.edu thread[i]->connectMemPorts(); 7894192Sktlim@umich.edu} 7904192Sktlim@umich.edu#endif 7914192Sktlim@umich.edu 7921060SN/Atemplate <class Impl> 7932852Sktlim@umich.eduvoid 7942864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 7952864Sktlim@umich.edu{ 7962918Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 7972918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 7982864Sktlim@umich.edu BaseCPU::serialize(os); 7992864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 8002864Sktlim@umich.edu tickEvent.serialize(os); 8012864Sktlim@umich.edu 8022864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 8032864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 8042864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 8052864Sktlim@umich.edu static SimpleThread temp; 8062864Sktlim@umich.edu 8072864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 8082864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 8092864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 8102864Sktlim@umich.edu temp.serialize(os); 8112864Sktlim@umich.edu } 8122864Sktlim@umich.edu} 8132864Sktlim@umich.edu 8142864Sktlim@umich.edutemplate <class Impl> 8152864Sktlim@umich.eduvoid 8162864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 8172864Sktlim@umich.edu{ 8182918Sktlim@umich.edu SimObject::State so_state; 8192918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 8202864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 8212864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 8222864Sktlim@umich.edu 8232864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 8242864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 8252864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 8262864Sktlim@umich.edu static SimpleThread temp; 8272864Sktlim@umich.edu 8282864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 8292864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 8302864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 8312864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 8322864Sktlim@umich.edu } 8332864Sktlim@umich.edu} 8342864Sktlim@umich.edu 8352864Sktlim@umich.edutemplate <class Impl> 8362905Sktlim@umich.eduunsigned int 8372843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 8381060SN/A{ 8393125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 8403512Sktlim@umich.edu 8413512Sktlim@umich.edu // If the CPU isn't doing anything, then return immediately. 8423512Sktlim@umich.edu if (_status == Idle || _status == SwitchedOut) { 8433512Sktlim@umich.edu return 0; 8443512Sktlim@umich.edu } 8453512Sktlim@umich.edu 8462843Sktlim@umich.edu drainCount = 0; 8472843Sktlim@umich.edu fetch.drain(); 8482843Sktlim@umich.edu decode.drain(); 8492843Sktlim@umich.edu rename.drain(); 8502843Sktlim@umich.edu iew.drain(); 8512843Sktlim@umich.edu commit.drain(); 8522325SN/A 8532325SN/A // Wake the CPU and record activity so everything can drain out if 8542863Sktlim@umich.edu // the CPU was not able to immediately drain. 8552905Sktlim@umich.edu if (getState() != SimObject::Drained) { 8562864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 8572864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 8582864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 8592864Sktlim@umich.edu // process on the drain event. 8602864Sktlim@umich.edu drainEvent = drain_event; 8612843Sktlim@umich.edu 8622863Sktlim@umich.edu wakeCPU(); 8632863Sktlim@umich.edu activityRec.activity(); 8642852Sktlim@umich.edu 8652905Sktlim@umich.edu return 1; 8662863Sktlim@umich.edu } else { 8672905Sktlim@umich.edu return 0; 8682863Sktlim@umich.edu } 8692316SN/A} 8702310SN/A 8712316SN/Atemplate <class Impl> 8722316SN/Avoid 8732843Sktlim@umich.eduFullO3CPU<Impl>::resume() 8742316SN/A{ 8752843Sktlim@umich.edu fetch.resume(); 8762843Sktlim@umich.edu decode.resume(); 8772843Sktlim@umich.edu rename.resume(); 8782843Sktlim@umich.edu iew.resume(); 8792843Sktlim@umich.edu commit.resume(); 8802316SN/A 8812905Sktlim@umich.edu changeState(SimObject::Running); 8822905Sktlim@umich.edu 8832864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 8842864Sktlim@umich.edu return; 8852864Sktlim@umich.edu 8863319Shsul@eecs.umich.edu#if FULL_SYSTEM 8873319Shsul@eecs.umich.edu assert(system->getMemoryMode() == System::Timing); 8883319Shsul@eecs.umich.edu#endif 8893319Shsul@eecs.umich.edu 8902843Sktlim@umich.edu if (!tickEvent.scheduled()) 8914030Sktlim@umich.edu tickEvent.schedule(nextCycle()); 8922843Sktlim@umich.edu _status = Running; 8932843Sktlim@umich.edu} 8942316SN/A 8952843Sktlim@umich.edutemplate <class Impl> 8962843Sktlim@umich.eduvoid 8972843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 8982843Sktlim@umich.edu{ 8992843Sktlim@umich.edu if (++drainCount == NumStages) { 9002316SN/A if (tickEvent.scheduled()) 9012316SN/A tickEvent.squash(); 9022863Sktlim@umich.edu 9032905Sktlim@umich.edu changeState(SimObject::Drained); 9042863Sktlim@umich.edu 9053126Sktlim@umich.edu BaseCPU::switchOut(); 9063126Sktlim@umich.edu 9072863Sktlim@umich.edu if (drainEvent) { 9082863Sktlim@umich.edu drainEvent->process(); 9092863Sktlim@umich.edu drainEvent = NULL; 9102863Sktlim@umich.edu } 9112310SN/A } 9122843Sktlim@umich.edu assert(drainCount <= 5); 9132843Sktlim@umich.edu} 9142843Sktlim@umich.edu 9152843Sktlim@umich.edutemplate <class Impl> 9162843Sktlim@umich.eduvoid 9172843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 9182843Sktlim@umich.edu{ 9192843Sktlim@umich.edu fetch.switchOut(); 9202843Sktlim@umich.edu rename.switchOut(); 9212325SN/A iew.switchOut(); 9222843Sktlim@umich.edu commit.switchOut(); 9232843Sktlim@umich.edu instList.clear(); 9242843Sktlim@umich.edu while (!removeList.empty()) { 9252843Sktlim@umich.edu removeList.pop(); 9262843Sktlim@umich.edu } 9272843Sktlim@umich.edu 9282843Sktlim@umich.edu _status = SwitchedOut; 9292843Sktlim@umich.edu#if USE_CHECKER 9302843Sktlim@umich.edu if (checker) 9312843Sktlim@umich.edu checker->switchOut(); 9322843Sktlim@umich.edu#endif 9333126Sktlim@umich.edu if (tickEvent.scheduled()) 9343126Sktlim@umich.edu tickEvent.squash(); 9351060SN/A} 9361060SN/A 9371060SN/Atemplate <class Impl> 9381060SN/Avoid 9391755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 9401060SN/A{ 9412325SN/A // Flush out any old data from the time buffers. 9422873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 9432307SN/A timeBuffer.advance(); 9442307SN/A fetchQueue.advance(); 9452307SN/A decodeQueue.advance(); 9462307SN/A renameQueue.advance(); 9472307SN/A iewQueue.advance(); 9482307SN/A } 9492307SN/A 9502325SN/A activityRec.reset(); 9512307SN/A 9524192Sktlim@umich.edu BaseCPU::takeOverFrom(oldCPU, fetch.getIcachePort(), iew.getDcachePort()); 9531060SN/A 9542307SN/A fetch.takeOverFrom(); 9552307SN/A decode.takeOverFrom(); 9562307SN/A rename.takeOverFrom(); 9572307SN/A iew.takeOverFrom(); 9582307SN/A commit.takeOverFrom(); 9592307SN/A 9601060SN/A assert(!tickEvent.scheduled()); 9611060SN/A 9622325SN/A // @todo: Figure out how to properly select the tid to put onto 9632325SN/A // the active threads list. 9642307SN/A int tid = 0; 9652307SN/A 9662307SN/A list<unsigned>::iterator isActive = find( 9672307SN/A activeThreads.begin(), activeThreads.end(), tid); 9682307SN/A 9692307SN/A if (isActive == activeThreads.end()) { 9702325SN/A //May Need to Re-code this if the delay variable is the delay 9712325SN/A //needed for thread to activate 9722733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 9732307SN/A tid); 9742307SN/A 9752307SN/A activeThreads.push_back(tid); 9762307SN/A } 9772307SN/A 9782325SN/A // Set all statuses to active, schedule the CPU's tick event. 9792307SN/A // @todo: Fix up statuses so this is handled properly 9802680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 9812680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 9822680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 9831681SN/A _status = Running; 9844030Sktlim@umich.edu tickEvent.schedule(nextCycle()); 9851681SN/A } 9861060SN/A } 9872307SN/A if (!tickEvent.scheduled()) 9884030Sktlim@umich.edu tickEvent.schedule(nextCycle()); 9891060SN/A} 9901060SN/A 9911060SN/Atemplate <class Impl> 9921060SN/Auint64_t 9931755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 9941060SN/A{ 9951060SN/A return regFile.readIntReg(reg_idx); 9961060SN/A} 9971060SN/A 9981060SN/Atemplate <class Impl> 9992455SN/AFloatReg 10002455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 10011060SN/A{ 10022455SN/A return regFile.readFloatReg(reg_idx, width); 10031060SN/A} 10041060SN/A 10051060SN/Atemplate <class Impl> 10062455SN/AFloatReg 10072455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 10081060SN/A{ 10092455SN/A return regFile.readFloatReg(reg_idx); 10101060SN/A} 10111060SN/A 10121060SN/Atemplate <class Impl> 10132455SN/AFloatRegBits 10142455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 10151060SN/A{ 10162455SN/A return regFile.readFloatRegBits(reg_idx, width); 10172455SN/A} 10182455SN/A 10192455SN/Atemplate <class Impl> 10202455SN/AFloatRegBits 10212455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 10222455SN/A{ 10232455SN/A return regFile.readFloatRegBits(reg_idx); 10241060SN/A} 10251060SN/A 10261060SN/Atemplate <class Impl> 10271060SN/Avoid 10281755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 10291060SN/A{ 10301060SN/A regFile.setIntReg(reg_idx, val); 10311060SN/A} 10321060SN/A 10331060SN/Atemplate <class Impl> 10341060SN/Avoid 10352455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 10361060SN/A{ 10372455SN/A regFile.setFloatReg(reg_idx, val, width); 10381060SN/A} 10391060SN/A 10401060SN/Atemplate <class Impl> 10411060SN/Avoid 10422455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 10431060SN/A{ 10442455SN/A regFile.setFloatReg(reg_idx, val); 10451060SN/A} 10461060SN/A 10471060SN/Atemplate <class Impl> 10481060SN/Avoid 10492455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 10501060SN/A{ 10512455SN/A regFile.setFloatRegBits(reg_idx, val, width); 10522455SN/A} 10532455SN/A 10542455SN/Atemplate <class Impl> 10552455SN/Avoid 10562455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 10572455SN/A{ 10582455SN/A regFile.setFloatRegBits(reg_idx, val); 10591060SN/A} 10601060SN/A 10611060SN/Atemplate <class Impl> 10621060SN/Auint64_t 10632292SN/AFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 10641060SN/A{ 10652292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10662292SN/A 10672292SN/A return regFile.readIntReg(phys_reg); 10682292SN/A} 10692292SN/A 10702292SN/Atemplate <class Impl> 10712292SN/Afloat 10722292SN/AFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 10732292SN/A{ 10742307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 10752307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10762292SN/A 10772669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 10782292SN/A} 10792292SN/A 10802292SN/Atemplate <class Impl> 10812292SN/Adouble 10822292SN/AFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 10832292SN/A{ 10842307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 10852307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10862292SN/A 10872669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 10882292SN/A} 10892292SN/A 10902292SN/Atemplate <class Impl> 10912292SN/Auint64_t 10922292SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 10932292SN/A{ 10942307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 10952307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10962292SN/A 10972669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 10981060SN/A} 10991060SN/A 11001060SN/Atemplate <class Impl> 11011060SN/Avoid 11022292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 11031060SN/A{ 11042292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 11052292SN/A 11062292SN/A regFile.setIntReg(phys_reg, val); 11071060SN/A} 11081060SN/A 11091060SN/Atemplate <class Impl> 11101060SN/Avoid 11112292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 11121060SN/A{ 11132918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 11142918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 11152292SN/A 11162669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 11171060SN/A} 11181060SN/A 11191060SN/Atemplate <class Impl> 11201060SN/Avoid 11212292SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 11221060SN/A{ 11232918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 11242918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 11252292SN/A 11262669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 11271060SN/A} 11281060SN/A 11291060SN/Atemplate <class Impl> 11301060SN/Avoid 11312292SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 11321060SN/A{ 11332918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 11342918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 11351060SN/A 11362669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 11372292SN/A} 11382292SN/A 11392292SN/Atemplate <class Impl> 11402292SN/Auint64_t 11412292SN/AFullO3CPU<Impl>::readPC(unsigned tid) 11422292SN/A{ 11432292SN/A return commit.readPC(tid); 11441060SN/A} 11451060SN/A 11461060SN/Atemplate <class Impl> 11471060SN/Avoid 11482292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 11491060SN/A{ 11502292SN/A commit.setPC(new_PC, tid); 11512292SN/A} 11521060SN/A 11532292SN/Atemplate <class Impl> 11542292SN/Auint64_t 11554636Sgblack@eecs.umich.eduFullO3CPU<Impl>::readMicroPC(unsigned tid) 11564636Sgblack@eecs.umich.edu{ 11574636Sgblack@eecs.umich.edu return commit.readMicroPC(tid); 11584636Sgblack@eecs.umich.edu} 11594636Sgblack@eecs.umich.edu 11604636Sgblack@eecs.umich.edutemplate <class Impl> 11614636Sgblack@eecs.umich.eduvoid 11624636Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMicroPC(Addr new_PC,unsigned tid) 11634636Sgblack@eecs.umich.edu{ 11644636Sgblack@eecs.umich.edu commit.setMicroPC(new_PC, tid); 11654636Sgblack@eecs.umich.edu} 11664636Sgblack@eecs.umich.edu 11674636Sgblack@eecs.umich.edutemplate <class Impl> 11684636Sgblack@eecs.umich.eduuint64_t 11692292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 11702292SN/A{ 11712292SN/A return commit.readNextPC(tid); 11722292SN/A} 11731060SN/A 11742292SN/Atemplate <class Impl> 11752292SN/Avoid 11762292SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 11772292SN/A{ 11782292SN/A commit.setNextPC(val, tid); 11792292SN/A} 11801060SN/A 11812756Sksewell@umich.edutemplate <class Impl> 11822756Sksewell@umich.eduuint64_t 11832756Sksewell@umich.eduFullO3CPU<Impl>::readNextNPC(unsigned tid) 11842756Sksewell@umich.edu{ 11852756Sksewell@umich.edu return commit.readNextNPC(tid); 11862756Sksewell@umich.edu} 11872756Sksewell@umich.edu 11882756Sksewell@umich.edutemplate <class Impl> 11892756Sksewell@umich.eduvoid 11902935Sksewell@umich.eduFullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid) 11912756Sksewell@umich.edu{ 11922756Sksewell@umich.edu commit.setNextNPC(val, tid); 11932756Sksewell@umich.edu} 11942756Sksewell@umich.edu 11952292SN/Atemplate <class Impl> 11964636Sgblack@eecs.umich.eduuint64_t 11974636Sgblack@eecs.umich.eduFullO3CPU<Impl>::readNextMicroPC(unsigned tid) 11984636Sgblack@eecs.umich.edu{ 11994636Sgblack@eecs.umich.edu return commit.readNextMicroPC(tid); 12004636Sgblack@eecs.umich.edu} 12014636Sgblack@eecs.umich.edu 12024636Sgblack@eecs.umich.edutemplate <class Impl> 12034636Sgblack@eecs.umich.eduvoid 12044636Sgblack@eecs.umich.eduFullO3CPU<Impl>::setNextMicroPC(Addr new_PC,unsigned tid) 12054636Sgblack@eecs.umich.edu{ 12064636Sgblack@eecs.umich.edu commit.setNextMicroPC(new_PC, tid); 12074636Sgblack@eecs.umich.edu} 12084636Sgblack@eecs.umich.edu 12094636Sgblack@eecs.umich.edutemplate <class Impl> 12102292SN/Atypename FullO3CPU<Impl>::ListIt 12112292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 12122292SN/A{ 12132292SN/A instList.push_back(inst); 12141060SN/A 12152292SN/A return --(instList.end()); 12162292SN/A} 12171060SN/A 12182292SN/Atemplate <class Impl> 12192292SN/Avoid 12202292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 12212292SN/A{ 12222292SN/A // Keep an instruction count. 12232292SN/A thread[tid]->numInst++; 12242292SN/A thread[tid]->numInsts++; 12252292SN/A committedInsts[tid]++; 12262292SN/A totalCommittedInsts++; 12272292SN/A 12282292SN/A // Check for instruction-count-based events. 12292292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 12302292SN/A} 12312292SN/A 12322292SN/Atemplate <class Impl> 12332292SN/Avoid 12342292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 12352292SN/A{ 12362292SN/A removeInstsThisCycle = true; 12372292SN/A 12382292SN/A removeList.push(inst->getInstListIt()); 12391060SN/A} 12401060SN/A 12411060SN/Atemplate <class Impl> 12421060SN/Avoid 12431755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 12441060SN/A{ 12452733Sktlim@umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 12462292SN/A "[sn:%lli]\n", 12472303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 12481060SN/A 12492292SN/A removeInstsThisCycle = true; 12501060SN/A 12511060SN/A // Remove the front instruction. 12522292SN/A removeList.push(inst->getInstListIt()); 12531060SN/A} 12541060SN/A 12551060SN/Atemplate <class Impl> 12561060SN/Avoid 12574632Sgblack@eecs.umich.eduFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 12581060SN/A{ 12592733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 12602292SN/A " list.\n", tid); 12611060SN/A 12622292SN/A ListIt end_it; 12631060SN/A 12642292SN/A bool rob_empty = false; 12652292SN/A 12662292SN/A if (instList.empty()) { 12672292SN/A return; 12682292SN/A } else if (rob.isEmpty(/*tid*/)) { 12692733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 12702292SN/A end_it = instList.begin(); 12712292SN/A rob_empty = true; 12722292SN/A } else { 12732292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 12742733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 12752292SN/A } 12762292SN/A 12772292SN/A removeInstsThisCycle = true; 12782292SN/A 12792292SN/A ListIt inst_it = instList.end(); 12802292SN/A 12812292SN/A inst_it--; 12822292SN/A 12832292SN/A // Walk through the instruction list, removing any instructions 12842292SN/A // that were inserted after the given instruction iterator, end_it. 12852292SN/A while (inst_it != end_it) { 12862292SN/A assert(!instList.empty()); 12872292SN/A 12882292SN/A squashInstIt(inst_it, tid); 12892292SN/A 12902292SN/A inst_it--; 12912292SN/A } 12922292SN/A 12932292SN/A // If the ROB was empty, then we actually need to remove the first 12942292SN/A // instruction as well. 12952292SN/A if (rob_empty) { 12962292SN/A squashInstIt(inst_it, tid); 12972292SN/A } 12981060SN/A} 12991060SN/A 13001060SN/Atemplate <class Impl> 13011060SN/Avoid 13022292SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 13032292SN/A unsigned tid) 13041062SN/A{ 13052292SN/A assert(!instList.empty()); 13062292SN/A 13072292SN/A removeInstsThisCycle = true; 13082292SN/A 13092292SN/A ListIt inst_iter = instList.end(); 13102292SN/A 13112292SN/A inst_iter--; 13122292SN/A 13132733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 13142292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 13152292SN/A tid, seq_num, (*inst_iter)->seqNum); 13161062SN/A 13172292SN/A while ((*inst_iter)->seqNum > seq_num) { 13181062SN/A 13192292SN/A bool break_loop = (inst_iter == instList.begin()); 13201062SN/A 13212292SN/A squashInstIt(inst_iter, tid); 13221062SN/A 13232292SN/A inst_iter--; 13241062SN/A 13252292SN/A if (break_loop) 13262292SN/A break; 13272292SN/A } 13282292SN/A} 13292292SN/A 13302292SN/Atemplate <class Impl> 13312292SN/Ainline void 13322292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 13332292SN/A{ 13342292SN/A if ((*instIt)->threadNumber == tid) { 13352733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 13362292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 13372292SN/A (*instIt)->threadNumber, 13382292SN/A (*instIt)->seqNum, 13392292SN/A (*instIt)->readPC()); 13401062SN/A 13411062SN/A // Mark it as squashed. 13422292SN/A (*instIt)->setSquashed(); 13432292SN/A 13442325SN/A // @todo: Formulate a consistent method for deleting 13452325SN/A // instructions from the instruction list 13462292SN/A // Remove the instruction from the list. 13472292SN/A removeList.push(instIt); 13482292SN/A } 13492292SN/A} 13502292SN/A 13512292SN/Atemplate <class Impl> 13522292SN/Avoid 13532292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 13542292SN/A{ 13552292SN/A while (!removeList.empty()) { 13562733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 13572292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 13582292SN/A (*removeList.front())->threadNumber, 13592292SN/A (*removeList.front())->seqNum, 13602292SN/A (*removeList.front())->readPC()); 13612292SN/A 13622292SN/A instList.erase(removeList.front()); 13632292SN/A 13642292SN/A removeList.pop(); 13651062SN/A } 13661062SN/A 13672292SN/A removeInstsThisCycle = false; 13681062SN/A} 13692325SN/A/* 13701062SN/Atemplate <class Impl> 13711062SN/Avoid 13721755SN/AFullO3CPU<Impl>::removeAllInsts() 13731060SN/A{ 13741060SN/A instList.clear(); 13751060SN/A} 13762325SN/A*/ 13771060SN/Atemplate <class Impl> 13781060SN/Avoid 13791755SN/AFullO3CPU<Impl>::dumpInsts() 13801060SN/A{ 13811060SN/A int num = 0; 13821060SN/A 13832292SN/A ListIt inst_list_it = instList.begin(); 13842292SN/A 13852292SN/A cprintf("Dumping Instruction List\n"); 13862292SN/A 13872292SN/A while (inst_list_it != instList.end()) { 13882292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 13892292SN/A "Squashed:%i\n\n", 13902292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 13912292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 13922292SN/A (*inst_list_it)->isSquashed()); 13931060SN/A inst_list_it++; 13941060SN/A ++num; 13951060SN/A } 13961060SN/A} 13972325SN/A/* 13981060SN/Atemplate <class Impl> 13991060SN/Avoid 14001755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 14011060SN/A{ 14021060SN/A iew.wakeDependents(inst); 14031060SN/A} 14042325SN/A*/ 14052292SN/Atemplate <class Impl> 14062292SN/Avoid 14072292SN/AFullO3CPU<Impl>::wakeCPU() 14082292SN/A{ 14092325SN/A if (activityRec.active() || tickEvent.scheduled()) { 14102325SN/A DPRINTF(Activity, "CPU already running.\n"); 14112292SN/A return; 14122292SN/A } 14132292SN/A 14142325SN/A DPRINTF(Activity, "Waking up CPU\n"); 14152325SN/A 14162325SN/A idleCycles += (curTick - 1) - lastRunningCycle; 14172292SN/A 14184030Sktlim@umich.edu tickEvent.schedule(nextCycle()); 14192292SN/A} 14202292SN/A 14212292SN/Atemplate <class Impl> 14222292SN/Aint 14232292SN/AFullO3CPU<Impl>::getFreeTid() 14242292SN/A{ 14252292SN/A for (int i=0; i < numThreads; i++) { 14262292SN/A if (!tids[i]) { 14272292SN/A tids[i] = true; 14282292SN/A return i; 14292292SN/A } 14302292SN/A } 14312292SN/A 14322292SN/A return -1; 14332292SN/A} 14342292SN/A 14352292SN/Atemplate <class Impl> 14362292SN/Avoid 14372292SN/AFullO3CPU<Impl>::doContextSwitch() 14382292SN/A{ 14392292SN/A if (contextSwitch) { 14402292SN/A 14412292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 14422292SN/A 14432292SN/A for (int tid=0; tid < cpuWaitList.size(); tid++) { 14442292SN/A activateWhenReady(tid); 14452292SN/A } 14462292SN/A 14472292SN/A if (cpuWaitList.size() == 0) 14482292SN/A contextSwitch = true; 14492292SN/A } 14502292SN/A} 14512292SN/A 14522292SN/Atemplate <class Impl> 14532292SN/Avoid 14542292SN/AFullO3CPU<Impl>::updateThreadPriority() 14552292SN/A{ 14562292SN/A if (activeThreads.size() > 1) 14572292SN/A { 14582292SN/A //DEFAULT TO ROUND ROBIN SCHEME 14592292SN/A //e.g. Move highest priority to end of thread list 14602292SN/A list<unsigned>::iterator list_begin = activeThreads.begin(); 14612292SN/A list<unsigned>::iterator list_end = activeThreads.end(); 14622292SN/A 14632292SN/A unsigned high_thread = *list_begin; 14642292SN/A 14652292SN/A activeThreads.erase(list_begin); 14662292SN/A 14672292SN/A activeThreads.push_back(high_thread); 14682292SN/A } 14692292SN/A} 14701060SN/A 14711755SN/A// Forward declaration of FullO3CPU. 14722818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1473