cpu.cc revision 3512
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 341858SN/A 351858SN/A#if FULL_SYSTEM 362356SN/A#include "cpu/quiesce_event.hh" 371060SN/A#include "sim/system.hh" 381060SN/A#else 391060SN/A#include "sim/process.hh" 401060SN/A#endif 411060SN/A 422325SN/A#include "cpu/activity.hh" 432683Sktlim@umich.edu#include "cpu/simple_thread.hh" 442680Sktlim@umich.edu#include "cpu/thread_context.hh" 452817Sksewell@umich.edu#include "cpu/o3/isa_specific.hh" 461717SN/A#include "cpu/o3/cpu.hh" 471060SN/A 482325SN/A#include "sim/root.hh" 492292SN/A#include "sim/stat_control.hh" 502292SN/A 512794Sktlim@umich.edu#if USE_CHECKER 522794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 532794Sktlim@umich.edu#endif 542794Sktlim@umich.edu 551060SN/Ausing namespace std; 562669Sktlim@umich.eduusing namespace TheISA; 571060SN/A 582733Sktlim@umich.eduBaseO3CPU::BaseO3CPU(Params *params) 592292SN/A : BaseCPU(params), cpu_id(0) 601060SN/A{ 611060SN/A} 621060SN/A 632292SN/Avoid 642733Sktlim@umich.eduBaseO3CPU::regStats() 652292SN/A{ 662292SN/A BaseCPU::regStats(); 672292SN/A} 682292SN/A 691060SN/Atemplate <class Impl> 701755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 711060SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 721060SN/A{ 731060SN/A} 741060SN/A 751060SN/Atemplate <class Impl> 761060SN/Avoid 771755SN/AFullO3CPU<Impl>::TickEvent::process() 781060SN/A{ 791060SN/A cpu->tick(); 801060SN/A} 811060SN/A 821060SN/Atemplate <class Impl> 831060SN/Aconst char * 841755SN/AFullO3CPU<Impl>::TickEvent::description() 851060SN/A{ 861755SN/A return "FullO3CPU tick event"; 871060SN/A} 881060SN/A 891060SN/Atemplate <class Impl> 902829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 913221Sktlim@umich.edu : Event(&mainEventQueue, CPU_Switch_Pri) 922829Sksewell@umich.edu{ 932829Sksewell@umich.edu} 942829Sksewell@umich.edu 952829Sksewell@umich.edutemplate <class Impl> 962829Sksewell@umich.eduvoid 972829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 982829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 992829Sksewell@umich.edu{ 1002829Sksewell@umich.edu tid = thread_num; 1012829Sksewell@umich.edu cpu = thread_cpu; 1022829Sksewell@umich.edu} 1032829Sksewell@umich.edu 1042829Sksewell@umich.edutemplate <class Impl> 1052829Sksewell@umich.eduvoid 1062829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1072829Sksewell@umich.edu{ 1082829Sksewell@umich.edu cpu->activateThread(tid); 1092829Sksewell@umich.edu} 1102829Sksewell@umich.edu 1112829Sksewell@umich.edutemplate <class Impl> 1122829Sksewell@umich.educonst char * 1132829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::description() 1142829Sksewell@umich.edu{ 1152829Sksewell@umich.edu return "FullO3CPU \"Activate Thread\" event"; 1162829Sksewell@umich.edu} 1172829Sksewell@umich.edu 1182829Sksewell@umich.edutemplate <class Impl> 1192875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1202875Sksewell@umich.edu : Event(&mainEventQueue, CPU_Tick_Pri) 1212875Sksewell@umich.edu{ 1222875Sksewell@umich.edu} 1232875Sksewell@umich.edu 1242875Sksewell@umich.edutemplate <class Impl> 1252875Sksewell@umich.eduvoid 1262875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1272875Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1282875Sksewell@umich.edu{ 1292875Sksewell@umich.edu tid = thread_num; 1302875Sksewell@umich.edu cpu = thread_cpu; 1312875Sksewell@umich.edu} 1322875Sksewell@umich.edu 1332875Sksewell@umich.edutemplate <class Impl> 1342875Sksewell@umich.eduvoid 1352875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1362875Sksewell@umich.edu{ 1372875Sksewell@umich.edu cpu->deactivateThread(tid); 1383221Sktlim@umich.edu if (remove) 1393221Sktlim@umich.edu cpu->removeThread(tid); 1402875Sksewell@umich.edu} 1412875Sksewell@umich.edu 1422875Sksewell@umich.edutemplate <class Impl> 1432875Sksewell@umich.educonst char * 1442875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::description() 1452875Sksewell@umich.edu{ 1462875Sksewell@umich.edu return "FullO3CPU \"Deallocate Context\" event"; 1472875Sksewell@umich.edu} 1482875Sksewell@umich.edu 1492875Sksewell@umich.edutemplate <class Impl> 1502292SN/AFullO3CPU<Impl>::FullO3CPU(Params *params) 1512733Sktlim@umich.edu : BaseO3CPU(params), 1521060SN/A tickEvent(this), 1532292SN/A removeInstsThisCycle(false), 1541060SN/A fetch(params), 1551060SN/A decode(params), 1561060SN/A rename(params), 1571060SN/A iew(params), 1581060SN/A commit(params), 1591060SN/A 1602292SN/A regFile(params->numPhysIntRegs, params->numPhysFloatRegs), 1611060SN/A 1622831Sksewell@umich.edu freeList(params->numberOfThreads, 1632292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1642292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1651060SN/A 1662292SN/A rob(params->numROBEntries, params->squashWidth, 1672292SN/A params->smtROBPolicy, params->smtROBThreshold, 1682292SN/A params->numberOfThreads), 1691060SN/A 1702831Sksewell@umich.edu scoreboard(params->numberOfThreads, 1712292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1722292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1732292SN/A TheISA::NumMiscRegs * number_of_threads, 1742292SN/A TheISA::ZeroReg), 1751060SN/A 1762873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1772873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1782873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1792873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1802873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1812873Sktlim@umich.edu activityRec(NumStages, 1822873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1832873Sktlim@umich.edu params->activity), 1841060SN/A 1851060SN/A globalSeqNum(1), 1861858SN/A#if FULL_SYSTEM 1872292SN/A system(params->system), 1881060SN/A physmem(system->physmem), 1891060SN/A#endif // FULL_SYSTEM 1902843Sktlim@umich.edu drainCount(0), 1912316SN/A deferRegistration(params->deferRegistration), 1922316SN/A numThreads(number_of_threads) 1931060SN/A{ 1943221Sktlim@umich.edu if (!deferRegistration) { 1953221Sktlim@umich.edu _status = Running; 1963221Sktlim@umich.edu } else { 1973221Sktlim@umich.edu _status = Idle; 1983221Sktlim@umich.edu } 1991681SN/A 2002733Sktlim@umich.edu checker = NULL; 2012733Sktlim@umich.edu 2022794Sktlim@umich.edu if (params->checker) { 2032733Sktlim@umich.edu#if USE_CHECKER 2042316SN/A BaseCPU *temp_checker = params->checker; 2052316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2062316SN/A#if FULL_SYSTEM 2072316SN/A checker->setSystem(params->system); 2082316SN/A#endif 2092794Sktlim@umich.edu#else 2102794Sktlim@umich.edu panic("Checker enabled but not compiled in!"); 2112794Sktlim@umich.edu#endif // USE_CHECKER 2122316SN/A } 2132316SN/A 2141858SN/A#if !FULL_SYSTEM 2152292SN/A thread.resize(number_of_threads); 2162292SN/A tids.resize(number_of_threads); 2171681SN/A#endif 2181681SN/A 2192325SN/A // The stages also need their CPU pointer setup. However this 2202325SN/A // must be done at the upper level CPU because they have pointers 2212325SN/A // to the upper level CPU, and not this FullO3CPU. 2221060SN/A 2232292SN/A // Set up Pointers to the activeThreads list for each stage 2242292SN/A fetch.setActiveThreads(&activeThreads); 2252292SN/A decode.setActiveThreads(&activeThreads); 2262292SN/A rename.setActiveThreads(&activeThreads); 2272292SN/A iew.setActiveThreads(&activeThreads); 2282292SN/A commit.setActiveThreads(&activeThreads); 2291060SN/A 2301060SN/A // Give each of the stages the time buffer they will use. 2311060SN/A fetch.setTimeBuffer(&timeBuffer); 2321060SN/A decode.setTimeBuffer(&timeBuffer); 2331060SN/A rename.setTimeBuffer(&timeBuffer); 2341060SN/A iew.setTimeBuffer(&timeBuffer); 2351060SN/A commit.setTimeBuffer(&timeBuffer); 2361060SN/A 2371060SN/A // Also setup each of the stages' queues. 2381060SN/A fetch.setFetchQueue(&fetchQueue); 2391060SN/A decode.setFetchQueue(&fetchQueue); 2402292SN/A commit.setFetchQueue(&fetchQueue); 2411060SN/A decode.setDecodeQueue(&decodeQueue); 2421060SN/A rename.setDecodeQueue(&decodeQueue); 2431060SN/A rename.setRenameQueue(&renameQueue); 2441060SN/A iew.setRenameQueue(&renameQueue); 2451060SN/A iew.setIEWQueue(&iewQueue); 2461060SN/A commit.setIEWQueue(&iewQueue); 2471060SN/A commit.setRenameQueue(&renameQueue); 2481060SN/A 2492292SN/A commit.setIEWStage(&iew); 2502292SN/A rename.setIEWStage(&iew); 2512292SN/A rename.setCommitStage(&commit); 2522292SN/A 2532292SN/A#if !FULL_SYSTEM 2542307SN/A int active_threads = params->workload.size(); 2552831Sksewell@umich.edu 2562831Sksewell@umich.edu if (active_threads > Impl::MaxThreads) { 2572831Sksewell@umich.edu panic("Workload Size too large. Increase the 'MaxThreads'" 2582831Sksewell@umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2592831Sksewell@umich.edu "edit your workload size."); 2602831Sksewell@umich.edu } 2612292SN/A#else 2622307SN/A int active_threads = 1; 2632292SN/A#endif 2642292SN/A 2652316SN/A //Make Sure That this a Valid Architeture 2662292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2672292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2682292SN/A 2692292SN/A rename.setScoreboard(&scoreboard); 2702292SN/A iew.setScoreboard(&scoreboard); 2712292SN/A 2721060SN/A // Setup the rename map for whichever stages need it. 2732292SN/A PhysRegIndex lreg_idx = 0; 2742292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2751060SN/A 2762292SN/A for (int tid=0; tid < numThreads; tid++) { 2772307SN/A bool bindRegs = (tid <= active_threads - 1); 2782292SN/A 2792292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2802292SN/A params->numPhysIntRegs, 2812325SN/A lreg_idx, //Index for Logical. Regs 2822292SN/A 2832292SN/A TheISA::NumFloatRegs, 2842292SN/A params->numPhysFloatRegs, 2852325SN/A freg_idx, //Index for Float Regs 2862292SN/A 2872292SN/A TheISA::NumMiscRegs, 2882292SN/A 2892292SN/A TheISA::ZeroReg, 2902292SN/A TheISA::ZeroReg, 2912292SN/A 2922292SN/A tid, 2932292SN/A false); 2942292SN/A 2952292SN/A renameMap[tid].init(TheISA::NumIntRegs, 2962292SN/A params->numPhysIntRegs, 2972325SN/A lreg_idx, //Index for Logical. Regs 2982292SN/A 2992292SN/A TheISA::NumFloatRegs, 3002292SN/A params->numPhysFloatRegs, 3012325SN/A freg_idx, //Index for Float Regs 3022292SN/A 3032292SN/A TheISA::NumMiscRegs, 3042292SN/A 3052292SN/A TheISA::ZeroReg, 3062292SN/A TheISA::ZeroReg, 3072292SN/A 3082292SN/A tid, 3092292SN/A bindRegs); 3103221Sktlim@umich.edu 3113221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3123221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3132292SN/A } 3142292SN/A 3152292SN/A rename.setRenameMap(renameMap); 3162292SN/A commit.setRenameMap(commitRenameMap); 3172292SN/A 3182292SN/A // Give renameMap & rename stage access to the freeList; 3192292SN/A for (int i=0; i < numThreads; i++) { 3202292SN/A renameMap[i].setFreeList(&freeList); 3212292SN/A } 3221060SN/A rename.setFreeList(&freeList); 3232292SN/A 3241060SN/A // Setup the ROB for whichever stages need it. 3251060SN/A commit.setROB(&rob); 3262292SN/A 3272292SN/A lastRunningCycle = curTick; 3282292SN/A 3292829Sksewell@umich.edu lastActivatedCycle = -1; 3302829Sksewell@umich.edu 3313093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3323093Sksewell@umich.edu //for (int i=0; i < numThreads; i++) { 3333093Sksewell@umich.edu //globalSeqNum[i] = 1; 3343093Sksewell@umich.edu //} 3353093Sksewell@umich.edu 3362292SN/A contextSwitch = false; 3371060SN/A} 3381060SN/A 3391060SN/Atemplate <class Impl> 3401755SN/AFullO3CPU<Impl>::~FullO3CPU() 3411060SN/A{ 3421060SN/A} 3431060SN/A 3441060SN/Atemplate <class Impl> 3451060SN/Avoid 3461755SN/AFullO3CPU<Impl>::fullCPURegStats() 3471062SN/A{ 3482733Sktlim@umich.edu BaseO3CPU::regStats(); 3492292SN/A 3502733Sktlim@umich.edu // Register any of the O3CPU's stats here. 3512292SN/A timesIdled 3522292SN/A .name(name() + ".timesIdled") 3532292SN/A .desc("Number of times that the entire CPU went into an idle state and" 3542292SN/A " unscheduled itself") 3552292SN/A .prereq(timesIdled); 3562292SN/A 3572292SN/A idleCycles 3582292SN/A .name(name() + ".idleCycles") 3592292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 3602292SN/A "to idling") 3612292SN/A .prereq(idleCycles); 3622292SN/A 3632292SN/A // Number of Instructions simulated 3642292SN/A // -------------------------------- 3652292SN/A // Should probably be in Base CPU but need templated 3662292SN/A // MaxThreads so put in here instead 3672292SN/A committedInsts 3682292SN/A .init(numThreads) 3692292SN/A .name(name() + ".committedInsts") 3702292SN/A .desc("Number of Instructions Simulated"); 3712292SN/A 3722292SN/A totalCommittedInsts 3732292SN/A .name(name() + ".committedInsts_total") 3742292SN/A .desc("Number of Instructions Simulated"); 3752292SN/A 3762292SN/A cpi 3772292SN/A .name(name() + ".cpi") 3782292SN/A .desc("CPI: Cycles Per Instruction") 3792292SN/A .precision(6); 3802292SN/A cpi = simTicks / committedInsts; 3812292SN/A 3822292SN/A totalCpi 3832292SN/A .name(name() + ".cpi_total") 3842292SN/A .desc("CPI: Total CPI of All Threads") 3852292SN/A .precision(6); 3862292SN/A totalCpi = simTicks / totalCommittedInsts; 3872292SN/A 3882292SN/A ipc 3892292SN/A .name(name() + ".ipc") 3902292SN/A .desc("IPC: Instructions Per Cycle") 3912292SN/A .precision(6); 3922292SN/A ipc = committedInsts / simTicks; 3932292SN/A 3942292SN/A totalIpc 3952292SN/A .name(name() + ".ipc_total") 3962292SN/A .desc("IPC: Total IPC of All Threads") 3972292SN/A .precision(6); 3982292SN/A totalIpc = totalCommittedInsts / simTicks; 3992292SN/A 4001062SN/A} 4011062SN/A 4021062SN/Atemplate <class Impl> 4032871Sktlim@umich.eduPort * 4042871Sktlim@umich.eduFullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 4052871Sktlim@umich.edu{ 4062871Sktlim@umich.edu if (if_name == "dcache_port") 4072871Sktlim@umich.edu return iew.getDcachePort(); 4082871Sktlim@umich.edu else if (if_name == "icache_port") 4092871Sktlim@umich.edu return fetch.getIcachePort(); 4102871Sktlim@umich.edu else 4112871Sktlim@umich.edu panic("No Such Port\n"); 4122871Sktlim@umich.edu} 4132871Sktlim@umich.edu 4142871Sktlim@umich.edutemplate <class Impl> 4151062SN/Avoid 4161755SN/AFullO3CPU<Impl>::tick() 4171060SN/A{ 4182733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 4191060SN/A 4202292SN/A ++numCycles; 4212292SN/A 4222325SN/A// activity = false; 4232292SN/A 4242292SN/A //Tick each of the stages 4251060SN/A fetch.tick(); 4261060SN/A 4271060SN/A decode.tick(); 4281060SN/A 4291060SN/A rename.tick(); 4301060SN/A 4311060SN/A iew.tick(); 4321060SN/A 4331060SN/A commit.tick(); 4341060SN/A 4352292SN/A#if !FULL_SYSTEM 4362292SN/A doContextSwitch(); 4372292SN/A#endif 4382292SN/A 4392292SN/A // Now advance the time buffers 4401060SN/A timeBuffer.advance(); 4411060SN/A 4421060SN/A fetchQueue.advance(); 4431060SN/A decodeQueue.advance(); 4441060SN/A renameQueue.advance(); 4451060SN/A iewQueue.advance(); 4461060SN/A 4472325SN/A activityRec.advance(); 4482292SN/A 4492292SN/A if (removeInstsThisCycle) { 4502292SN/A cleanUpRemovedInsts(); 4512292SN/A } 4522292SN/A 4532325SN/A if (!tickEvent.scheduled()) { 4542867Sktlim@umich.edu if (_status == SwitchedOut || 4552905Sktlim@umich.edu getState() == SimObject::Drained) { 4563226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 4572325SN/A // increment stat 4582325SN/A lastRunningCycle = curTick; 4593221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 4603226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 4612325SN/A lastRunningCycle = curTick; 4622325SN/A timesIdled++; 4632325SN/A } else { 4642325SN/A tickEvent.schedule(curTick + cycles(1)); 4653226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 4662325SN/A } 4672292SN/A } 4682292SN/A 4692292SN/A#if !FULL_SYSTEM 4702292SN/A updateThreadPriority(); 4712292SN/A#endif 4722292SN/A 4731060SN/A} 4741060SN/A 4751060SN/Atemplate <class Impl> 4761060SN/Avoid 4771755SN/AFullO3CPU<Impl>::init() 4781060SN/A{ 4792307SN/A if (!deferRegistration) { 4802680Sktlim@umich.edu registerThreadContexts(); 4812292SN/A } 4821060SN/A 4832292SN/A // Set inSyscall so that the CPU doesn't squash when initially 4842292SN/A // setting up registers. 4852292SN/A for (int i = 0; i < number_of_threads; ++i) 4862292SN/A thread[i]->inSyscall = true; 4872292SN/A 4882292SN/A for (int tid=0; tid < number_of_threads; tid++) { 4891858SN/A#if FULL_SYSTEM 4902680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 4911681SN/A#else 4922680Sktlim@umich.edu ThreadContext *src_tc = thread[tid]->getTC(); 4931681SN/A#endif 4942292SN/A // Threads start in the Suspended State 4952680Sktlim@umich.edu if (src_tc->status() != ThreadContext::Suspended) { 4962292SN/A continue; 4971060SN/A } 4981060SN/A 4992292SN/A#if FULL_SYSTEM 5002680Sktlim@umich.edu TheISA::initCPU(src_tc, src_tc->readCpuId()); 5012292SN/A#endif 5022292SN/A } 5032292SN/A 5042292SN/A // Clear inSyscall. 5052292SN/A for (int i = 0; i < number_of_threads; ++i) 5062292SN/A thread[i]->inSyscall = false; 5072292SN/A 5082316SN/A // Initialize stages. 5092292SN/A fetch.initStage(); 5102292SN/A iew.initStage(); 5112292SN/A rename.initStage(); 5122292SN/A commit.initStage(); 5132292SN/A 5142292SN/A commit.setThreads(thread); 5152292SN/A} 5162292SN/A 5172292SN/Atemplate <class Impl> 5182292SN/Avoid 5192875Sksewell@umich.eduFullO3CPU<Impl>::activateThread(unsigned tid) 5202875Sksewell@umich.edu{ 5212875Sksewell@umich.edu list<unsigned>::iterator isActive = find( 5222875Sksewell@umich.edu activeThreads.begin(), activeThreads.end(), tid); 5232875Sksewell@umich.edu 5243226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 5253226Sktlim@umich.edu 5262875Sksewell@umich.edu if (isActive == activeThreads.end()) { 5272875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 5282875Sksewell@umich.edu tid); 5292875Sksewell@umich.edu 5302875Sksewell@umich.edu activeThreads.push_back(tid); 5312875Sksewell@umich.edu } 5322875Sksewell@umich.edu} 5332875Sksewell@umich.edu 5342875Sksewell@umich.edutemplate <class Impl> 5352875Sksewell@umich.eduvoid 5362875Sksewell@umich.eduFullO3CPU<Impl>::deactivateThread(unsigned tid) 5372875Sksewell@umich.edu{ 5382875Sksewell@umich.edu //Remove From Active List, if Active 5392875Sksewell@umich.edu list<unsigned>::iterator thread_it = 5402875Sksewell@umich.edu find(activeThreads.begin(), activeThreads.end(), tid); 5412875Sksewell@umich.edu 5423226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 5433226Sktlim@umich.edu 5442875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 5452875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 5462875Sksewell@umich.edu tid); 5472875Sksewell@umich.edu activeThreads.erase(thread_it); 5482875Sksewell@umich.edu } 5492875Sksewell@umich.edu} 5502875Sksewell@umich.edu 5512875Sksewell@umich.edutemplate <class Impl> 5522875Sksewell@umich.eduvoid 5532875Sksewell@umich.eduFullO3CPU<Impl>::activateContext(int tid, int delay) 5542875Sksewell@umich.edu{ 5552875Sksewell@umich.edu // Needs to set each stage to running as well. 5562875Sksewell@umich.edu if (delay){ 5572875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 5582875Sksewell@umich.edu "on cycle %d\n", tid, curTick + cycles(delay)); 5592875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 5602875Sksewell@umich.edu } else { 5612875Sksewell@umich.edu activateThread(tid); 5622875Sksewell@umich.edu } 5632875Sksewell@umich.edu 5643221Sktlim@umich.edu if (lastActivatedCycle < curTick) { 5652875Sksewell@umich.edu scheduleTickEvent(delay); 5662875Sksewell@umich.edu 5672875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 5682875Sksewell@umich.edu // deschedule itself. 5692875Sksewell@umich.edu activityRec.activity(); 5702875Sksewell@umich.edu fetch.wakeFromQuiesce(); 5712875Sksewell@umich.edu 5722875Sksewell@umich.edu lastActivatedCycle = curTick; 5732875Sksewell@umich.edu 5742875Sksewell@umich.edu _status = Running; 5752875Sksewell@umich.edu } 5762875Sksewell@umich.edu} 5772875Sksewell@umich.edu 5782875Sksewell@umich.edutemplate <class Impl> 5793221Sktlim@umich.edubool 5803221Sktlim@umich.eduFullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay) 5812875Sksewell@umich.edu{ 5822875Sksewell@umich.edu // Schedule removal of thread data from CPU 5832875Sksewell@umich.edu if (delay){ 5842875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 5852875Sksewell@umich.edu "on cycle %d\n", tid, curTick + cycles(delay)); 5863221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 5873221Sktlim@umich.edu return false; 5882875Sksewell@umich.edu } else { 5892875Sksewell@umich.edu deactivateThread(tid); 5903221Sktlim@umich.edu if (remove) 5913221Sktlim@umich.edu removeThread(tid); 5923221Sktlim@umich.edu return true; 5932875Sksewell@umich.edu } 5942875Sksewell@umich.edu} 5952875Sksewell@umich.edu 5962875Sksewell@umich.edutemplate <class Impl> 5972875Sksewell@umich.eduvoid 5982875Sksewell@umich.eduFullO3CPU<Impl>::suspendContext(int tid) 5992875Sksewell@umich.edu{ 6002875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 6013221Sktlim@umich.edu bool deallocated = deallocateContext(tid, false, 1); 6023221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 6033221Sktlim@umich.edu if ((activeThreads.size() == 1 && !deallocated) || activeThreads.size() == 0) 6042910Sksewell@umich.edu unscheduleTickEvent(); 6052875Sksewell@umich.edu _status = Idle; 6062875Sksewell@umich.edu} 6072875Sksewell@umich.edu 6082875Sksewell@umich.edutemplate <class Impl> 6092875Sksewell@umich.eduvoid 6102875Sksewell@umich.eduFullO3CPU<Impl>::haltContext(int tid) 6112875Sksewell@umich.edu{ 6122910Sksewell@umich.edu //For now, this is the same as deallocate 6132910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 6143221Sktlim@umich.edu deallocateContext(tid, true, 1); 6152875Sksewell@umich.edu} 6162875Sksewell@umich.edu 6172875Sksewell@umich.edutemplate <class Impl> 6182875Sksewell@umich.eduvoid 6192292SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 6202292SN/A{ 6212847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 6222292SN/A // Will change now that the PC and thread state is internal to the CPU 6232683Sktlim@umich.edu // and not in the ThreadContext. 6242292SN/A#if FULL_SYSTEM 6252680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 6262292SN/A#else 6272847Sksewell@umich.edu ThreadContext *src_tc = tcBase(tid); 6282292SN/A#endif 6292292SN/A 6302292SN/A //Bind Int Regs to Rename Map 6312292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 6322292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 6332292SN/A 6342292SN/A renameMap[tid].setEntry(ireg,phys_reg); 6352292SN/A scoreboard.setReg(phys_reg); 6362292SN/A } 6372292SN/A 6382292SN/A //Bind Float Regs to Rename Map 6392292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 6402292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 6412292SN/A 6422292SN/A renameMap[tid].setEntry(freg,phys_reg); 6432292SN/A scoreboard.setReg(phys_reg); 6442292SN/A } 6452292SN/A 6462292SN/A //Copy Thread Data Into RegFile 6472847Sksewell@umich.edu //this->copyFromTC(tid); 6482292SN/A 6492847Sksewell@umich.edu //Set PC/NPC/NNPC 6502847Sksewell@umich.edu setPC(src_tc->readPC(), tid); 6512847Sksewell@umich.edu setNextPC(src_tc->readNextPC(), tid); 6523093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 6532847Sksewell@umich.edu setNextNPC(src_tc->readNextNPC(), tid); 6542847Sksewell@umich.edu#endif 6552292SN/A 6562680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 6572292SN/A 6582292SN/A activateContext(tid,1); 6592292SN/A 6602292SN/A //Reset ROB/IQ/LSQ Entries 6612292SN/A commit.rob->resetEntries(); 6622292SN/A iew.resetEntries(); 6632292SN/A} 6642292SN/A 6652292SN/Atemplate <class Impl> 6662292SN/Avoid 6672292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 6682292SN/A{ 6692877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 6702847Sksewell@umich.edu 6712847Sksewell@umich.edu // Copy Thread Data From RegFile 6722847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 6732847Sksewell@umich.edu //this->copyToTC(tid); 6742847Sksewell@umich.edu 6752847Sksewell@umich.edu // Unbind Int Regs from Rename Map 6762292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 6772292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 6782292SN/A 6792292SN/A scoreboard.unsetReg(phys_reg); 6802292SN/A freeList.addReg(phys_reg); 6812292SN/A } 6822292SN/A 6832847Sksewell@umich.edu // Unbind Float Regs from Rename Map 6842292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 6852292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 6862292SN/A 6872292SN/A scoreboard.unsetReg(phys_reg); 6882292SN/A freeList.addReg(phys_reg); 6892292SN/A } 6902292SN/A 6912847Sksewell@umich.edu // Squash Throughout Pipeline 6922935Sksewell@umich.edu InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; 6932935Sksewell@umich.edu fetch.squash(0, squash_seq_num, true, tid); 6942292SN/A decode.squash(tid); 6952935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 6962875Sksewell@umich.edu iew.squash(tid); 6972935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 6982292SN/A 6992292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 7002292SN/A 7012847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 7023229Sktlim@umich.edu 7033229Sktlim@umich.edu // Commented out for now. This should be possible to do by 7043229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 7053229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 7063229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 7073229Sktlim@umich.edu/* 7082292SN/A if (activeThreads.size() >= 1) { 7092292SN/A commit.rob->resetEntries(); 7102292SN/A iew.resetEntries(); 7112292SN/A } 7123229Sktlim@umich.edu*/ 7132292SN/A} 7142292SN/A 7152292SN/A 7162292SN/Atemplate <class Impl> 7172292SN/Avoid 7182292SN/AFullO3CPU<Impl>::activateWhenReady(int tid) 7192292SN/A{ 7202733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 7212292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 7222292SN/A tid); 7232292SN/A 7242292SN/A bool ready = true; 7252292SN/A 7262292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 7272733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7282292SN/A "Phys. Int. Regs.\n", 7292292SN/A tid); 7302292SN/A ready = false; 7312292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 7322733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7332292SN/A "Phys. Float. Regs.\n", 7342292SN/A tid); 7352292SN/A ready = false; 7362292SN/A } else if (commit.rob->numFreeEntries() >= 7372292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 7382733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7392292SN/A "ROB entries.\n", 7402292SN/A tid); 7412292SN/A ready = false; 7422292SN/A } else if (iew.instQueue.numFreeEntries() >= 7432292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 7442733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7452292SN/A "IQ entries.\n", 7462292SN/A tid); 7472292SN/A ready = false; 7482292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 7492292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 7502733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7512292SN/A "LSQ entries.\n", 7522292SN/A tid); 7532292SN/A ready = false; 7542292SN/A } 7552292SN/A 7562292SN/A if (ready) { 7572292SN/A insertThread(tid); 7582292SN/A 7592292SN/A contextSwitch = false; 7602292SN/A 7612292SN/A cpuWaitList.remove(tid); 7622292SN/A } else { 7632292SN/A suspendContext(tid); 7642292SN/A 7652292SN/A //blocks fetch 7662292SN/A contextSwitch = true; 7672292SN/A 7682875Sksewell@umich.edu //@todo: dont always add to waitlist 7692292SN/A //do waitlist 7702292SN/A cpuWaitList.push_back(tid); 7711060SN/A } 7721060SN/A} 7731060SN/A 7741060SN/Atemplate <class Impl> 7752852Sktlim@umich.eduvoid 7762864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 7772864Sktlim@umich.edu{ 7782918Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 7792918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 7802864Sktlim@umich.edu BaseCPU::serialize(os); 7812864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 7822864Sktlim@umich.edu tickEvent.serialize(os); 7832864Sktlim@umich.edu 7842864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 7852864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 7862864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 7872864Sktlim@umich.edu static SimpleThread temp; 7882864Sktlim@umich.edu 7892864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 7902864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 7912864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 7922864Sktlim@umich.edu temp.serialize(os); 7932864Sktlim@umich.edu } 7942864Sktlim@umich.edu} 7952864Sktlim@umich.edu 7962864Sktlim@umich.edutemplate <class Impl> 7972864Sktlim@umich.eduvoid 7982864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 7992864Sktlim@umich.edu{ 8002918Sktlim@umich.edu SimObject::State so_state; 8012918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 8022864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 8032864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 8042864Sktlim@umich.edu 8052864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 8062864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 8072864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 8082864Sktlim@umich.edu static SimpleThread temp; 8092864Sktlim@umich.edu 8102864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 8112864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 8122864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 8132864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 8142864Sktlim@umich.edu } 8152864Sktlim@umich.edu} 8162864Sktlim@umich.edu 8172864Sktlim@umich.edutemplate <class Impl> 8182905Sktlim@umich.eduunsigned int 8192843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 8201060SN/A{ 8213125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 8223512Sktlim@umich.edu 8233512Sktlim@umich.edu // If the CPU isn't doing anything, then return immediately. 8243512Sktlim@umich.edu if (_status == Idle || _status == SwitchedOut) { 8253512Sktlim@umich.edu return 0; 8263512Sktlim@umich.edu } 8273512Sktlim@umich.edu 8282843Sktlim@umich.edu drainCount = 0; 8292843Sktlim@umich.edu fetch.drain(); 8302843Sktlim@umich.edu decode.drain(); 8312843Sktlim@umich.edu rename.drain(); 8322843Sktlim@umich.edu iew.drain(); 8332843Sktlim@umich.edu commit.drain(); 8342325SN/A 8352325SN/A // Wake the CPU and record activity so everything can drain out if 8362863Sktlim@umich.edu // the CPU was not able to immediately drain. 8372905Sktlim@umich.edu if (getState() != SimObject::Drained) { 8382864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 8392864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 8402864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 8412864Sktlim@umich.edu // process on the drain event. 8422864Sktlim@umich.edu drainEvent = drain_event; 8432843Sktlim@umich.edu 8442863Sktlim@umich.edu wakeCPU(); 8452863Sktlim@umich.edu activityRec.activity(); 8462852Sktlim@umich.edu 8472905Sktlim@umich.edu return 1; 8482863Sktlim@umich.edu } else { 8492905Sktlim@umich.edu return 0; 8502863Sktlim@umich.edu } 8512316SN/A} 8522310SN/A 8532316SN/Atemplate <class Impl> 8542316SN/Avoid 8552843Sktlim@umich.eduFullO3CPU<Impl>::resume() 8562316SN/A{ 8572843Sktlim@umich.edu fetch.resume(); 8582843Sktlim@umich.edu decode.resume(); 8592843Sktlim@umich.edu rename.resume(); 8602843Sktlim@umich.edu iew.resume(); 8612843Sktlim@umich.edu commit.resume(); 8622316SN/A 8632905Sktlim@umich.edu changeState(SimObject::Running); 8642905Sktlim@umich.edu 8652864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 8662864Sktlim@umich.edu return; 8672864Sktlim@umich.edu 8683319Shsul@eecs.umich.edu#if FULL_SYSTEM 8693319Shsul@eecs.umich.edu assert(system->getMemoryMode() == System::Timing); 8703319Shsul@eecs.umich.edu#endif 8713319Shsul@eecs.umich.edu 8722843Sktlim@umich.edu if (!tickEvent.scheduled()) 8732843Sktlim@umich.edu tickEvent.schedule(curTick); 8742843Sktlim@umich.edu _status = Running; 8752843Sktlim@umich.edu} 8762316SN/A 8772843Sktlim@umich.edutemplate <class Impl> 8782843Sktlim@umich.eduvoid 8792843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 8802843Sktlim@umich.edu{ 8812843Sktlim@umich.edu if (++drainCount == NumStages) { 8822316SN/A if (tickEvent.scheduled()) 8832316SN/A tickEvent.squash(); 8842863Sktlim@umich.edu 8852905Sktlim@umich.edu changeState(SimObject::Drained); 8862863Sktlim@umich.edu 8873126Sktlim@umich.edu BaseCPU::switchOut(); 8883126Sktlim@umich.edu 8892863Sktlim@umich.edu if (drainEvent) { 8902863Sktlim@umich.edu drainEvent->process(); 8912863Sktlim@umich.edu drainEvent = NULL; 8922863Sktlim@umich.edu } 8932310SN/A } 8942843Sktlim@umich.edu assert(drainCount <= 5); 8952843Sktlim@umich.edu} 8962843Sktlim@umich.edu 8972843Sktlim@umich.edutemplate <class Impl> 8982843Sktlim@umich.eduvoid 8992843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 9002843Sktlim@umich.edu{ 9012843Sktlim@umich.edu fetch.switchOut(); 9022843Sktlim@umich.edu rename.switchOut(); 9032325SN/A iew.switchOut(); 9042843Sktlim@umich.edu commit.switchOut(); 9052843Sktlim@umich.edu instList.clear(); 9062843Sktlim@umich.edu while (!removeList.empty()) { 9072843Sktlim@umich.edu removeList.pop(); 9082843Sktlim@umich.edu } 9092843Sktlim@umich.edu 9102843Sktlim@umich.edu _status = SwitchedOut; 9112843Sktlim@umich.edu#if USE_CHECKER 9122843Sktlim@umich.edu if (checker) 9132843Sktlim@umich.edu checker->switchOut(); 9142843Sktlim@umich.edu#endif 9153126Sktlim@umich.edu if (tickEvent.scheduled()) 9163126Sktlim@umich.edu tickEvent.squash(); 9171060SN/A} 9181060SN/A 9191060SN/Atemplate <class Impl> 9201060SN/Avoid 9211755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 9221060SN/A{ 9232325SN/A // Flush out any old data from the time buffers. 9242873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 9252307SN/A timeBuffer.advance(); 9262307SN/A fetchQueue.advance(); 9272307SN/A decodeQueue.advance(); 9282307SN/A renameQueue.advance(); 9292307SN/A iewQueue.advance(); 9302307SN/A } 9312307SN/A 9322325SN/A activityRec.reset(); 9332307SN/A 9341060SN/A BaseCPU::takeOverFrom(oldCPU); 9351060SN/A 9362307SN/A fetch.takeOverFrom(); 9372307SN/A decode.takeOverFrom(); 9382307SN/A rename.takeOverFrom(); 9392307SN/A iew.takeOverFrom(); 9402307SN/A commit.takeOverFrom(); 9412307SN/A 9421060SN/A assert(!tickEvent.scheduled()); 9431060SN/A 9442325SN/A // @todo: Figure out how to properly select the tid to put onto 9452325SN/A // the active threads list. 9462307SN/A int tid = 0; 9472307SN/A 9482307SN/A list<unsigned>::iterator isActive = find( 9492307SN/A activeThreads.begin(), activeThreads.end(), tid); 9502307SN/A 9512307SN/A if (isActive == activeThreads.end()) { 9522325SN/A //May Need to Re-code this if the delay variable is the delay 9532325SN/A //needed for thread to activate 9542733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 9552307SN/A tid); 9562307SN/A 9572307SN/A activeThreads.push_back(tid); 9582307SN/A } 9592307SN/A 9602325SN/A // Set all statuses to active, schedule the CPU's tick event. 9612307SN/A // @todo: Fix up statuses so this is handled properly 9622680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 9632680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 9642680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 9651681SN/A _status = Running; 9661681SN/A tickEvent.schedule(curTick); 9671681SN/A } 9681060SN/A } 9692307SN/A if (!tickEvent.scheduled()) 9702307SN/A tickEvent.schedule(curTick); 9713221Sktlim@umich.edu 9723221Sktlim@umich.edu Port *peer; 9733221Sktlim@umich.edu Port *icachePort = fetch.getIcachePort(); 9743221Sktlim@umich.edu if (icachePort->getPeer() == NULL) { 9753227Sktlim@umich.edu peer = oldCPU->getPort("icache_port")->getPeer(); 9763221Sktlim@umich.edu icachePort->setPeer(peer); 9773221Sktlim@umich.edu } else { 9783221Sktlim@umich.edu peer = icachePort->getPeer(); 9793221Sktlim@umich.edu } 9803221Sktlim@umich.edu peer->setPeer(icachePort); 9813221Sktlim@umich.edu 9823221Sktlim@umich.edu Port *dcachePort = iew.getDcachePort(); 9833221Sktlim@umich.edu if (dcachePort->getPeer() == NULL) { 9843227Sktlim@umich.edu peer = oldCPU->getPort("dcache_port")->getPeer(); 9853221Sktlim@umich.edu dcachePort->setPeer(peer); 9863221Sktlim@umich.edu } else { 9873221Sktlim@umich.edu peer = dcachePort->getPeer(); 9883221Sktlim@umich.edu } 9893221Sktlim@umich.edu peer->setPeer(dcachePort); 9901060SN/A} 9911060SN/A 9921060SN/Atemplate <class Impl> 9931060SN/Auint64_t 9941755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 9951060SN/A{ 9961060SN/A return regFile.readIntReg(reg_idx); 9971060SN/A} 9981060SN/A 9991060SN/Atemplate <class Impl> 10002455SN/AFloatReg 10012455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 10021060SN/A{ 10032455SN/A return regFile.readFloatReg(reg_idx, width); 10041060SN/A} 10051060SN/A 10061060SN/Atemplate <class Impl> 10072455SN/AFloatReg 10082455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 10091060SN/A{ 10102455SN/A return regFile.readFloatReg(reg_idx); 10111060SN/A} 10121060SN/A 10131060SN/Atemplate <class Impl> 10142455SN/AFloatRegBits 10152455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 10161060SN/A{ 10172455SN/A return regFile.readFloatRegBits(reg_idx, width); 10182455SN/A} 10192455SN/A 10202455SN/Atemplate <class Impl> 10212455SN/AFloatRegBits 10222455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 10232455SN/A{ 10242455SN/A return regFile.readFloatRegBits(reg_idx); 10251060SN/A} 10261060SN/A 10271060SN/Atemplate <class Impl> 10281060SN/Avoid 10291755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 10301060SN/A{ 10311060SN/A regFile.setIntReg(reg_idx, val); 10321060SN/A} 10331060SN/A 10341060SN/Atemplate <class Impl> 10351060SN/Avoid 10362455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 10371060SN/A{ 10382455SN/A regFile.setFloatReg(reg_idx, val, width); 10391060SN/A} 10401060SN/A 10411060SN/Atemplate <class Impl> 10421060SN/Avoid 10432455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 10441060SN/A{ 10452455SN/A regFile.setFloatReg(reg_idx, val); 10461060SN/A} 10471060SN/A 10481060SN/Atemplate <class Impl> 10491060SN/Avoid 10502455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 10511060SN/A{ 10522455SN/A regFile.setFloatRegBits(reg_idx, val, width); 10532455SN/A} 10542455SN/A 10552455SN/Atemplate <class Impl> 10562455SN/Avoid 10572455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 10582455SN/A{ 10592455SN/A regFile.setFloatRegBits(reg_idx, val); 10601060SN/A} 10611060SN/A 10621060SN/Atemplate <class Impl> 10631060SN/Auint64_t 10642292SN/AFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 10651060SN/A{ 10662292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10672292SN/A 10682292SN/A return regFile.readIntReg(phys_reg); 10692292SN/A} 10702292SN/A 10712292SN/Atemplate <class Impl> 10722292SN/Afloat 10732292SN/AFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 10742292SN/A{ 10752307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 10762307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10772292SN/A 10782669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 10792292SN/A} 10802292SN/A 10812292SN/Atemplate <class Impl> 10822292SN/Adouble 10832292SN/AFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 10842292SN/A{ 10852307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 10862307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10872292SN/A 10882669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 10892292SN/A} 10902292SN/A 10912292SN/Atemplate <class Impl> 10922292SN/Auint64_t 10932292SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 10942292SN/A{ 10952307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 10962307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10972292SN/A 10982669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 10991060SN/A} 11001060SN/A 11011060SN/Atemplate <class Impl> 11021060SN/Avoid 11032292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 11041060SN/A{ 11052292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 11062292SN/A 11072292SN/A regFile.setIntReg(phys_reg, val); 11081060SN/A} 11091060SN/A 11101060SN/Atemplate <class Impl> 11111060SN/Avoid 11122292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 11131060SN/A{ 11142918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 11152918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 11162292SN/A 11172669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 11181060SN/A} 11191060SN/A 11201060SN/Atemplate <class Impl> 11211060SN/Avoid 11222292SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 11231060SN/A{ 11242918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 11252918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 11262292SN/A 11272669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 11281060SN/A} 11291060SN/A 11301060SN/Atemplate <class Impl> 11311060SN/Avoid 11322292SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 11331060SN/A{ 11342918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 11352918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 11361060SN/A 11372669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 11382292SN/A} 11392292SN/A 11402292SN/Atemplate <class Impl> 11412292SN/Auint64_t 11422292SN/AFullO3CPU<Impl>::readPC(unsigned tid) 11432292SN/A{ 11442292SN/A return commit.readPC(tid); 11451060SN/A} 11461060SN/A 11471060SN/Atemplate <class Impl> 11481060SN/Avoid 11492292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 11501060SN/A{ 11512292SN/A commit.setPC(new_PC, tid); 11522292SN/A} 11531060SN/A 11542292SN/Atemplate <class Impl> 11552292SN/Auint64_t 11562292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 11572292SN/A{ 11582292SN/A return commit.readNextPC(tid); 11592292SN/A} 11601060SN/A 11612292SN/Atemplate <class Impl> 11622292SN/Avoid 11632292SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 11642292SN/A{ 11652292SN/A commit.setNextPC(val, tid); 11662292SN/A} 11671060SN/A 11682756Sksewell@umich.edutemplate <class Impl> 11692756Sksewell@umich.eduuint64_t 11702756Sksewell@umich.eduFullO3CPU<Impl>::readNextNPC(unsigned tid) 11712756Sksewell@umich.edu{ 11722756Sksewell@umich.edu return commit.readNextNPC(tid); 11732756Sksewell@umich.edu} 11742756Sksewell@umich.edu 11752756Sksewell@umich.edutemplate <class Impl> 11762756Sksewell@umich.eduvoid 11772935Sksewell@umich.eduFullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid) 11782756Sksewell@umich.edu{ 11792756Sksewell@umich.edu commit.setNextNPC(val, tid); 11802756Sksewell@umich.edu} 11812756Sksewell@umich.edu 11822292SN/Atemplate <class Impl> 11832292SN/Atypename FullO3CPU<Impl>::ListIt 11842292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 11852292SN/A{ 11862292SN/A instList.push_back(inst); 11871060SN/A 11882292SN/A return --(instList.end()); 11892292SN/A} 11901060SN/A 11912292SN/Atemplate <class Impl> 11922292SN/Avoid 11932292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 11942292SN/A{ 11952292SN/A // Keep an instruction count. 11962292SN/A thread[tid]->numInst++; 11972292SN/A thread[tid]->numInsts++; 11982292SN/A committedInsts[tid]++; 11992292SN/A totalCommittedInsts++; 12002292SN/A 12012292SN/A // Check for instruction-count-based events. 12022292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 12032292SN/A} 12042292SN/A 12052292SN/Atemplate <class Impl> 12062292SN/Avoid 12072292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 12082292SN/A{ 12092292SN/A removeInstsThisCycle = true; 12102292SN/A 12112292SN/A removeList.push(inst->getInstListIt()); 12121060SN/A} 12131060SN/A 12141060SN/Atemplate <class Impl> 12151060SN/Avoid 12161755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 12171060SN/A{ 12182733Sktlim@umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 12192292SN/A "[sn:%lli]\n", 12202303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 12211060SN/A 12222292SN/A removeInstsThisCycle = true; 12231060SN/A 12241060SN/A // Remove the front instruction. 12252292SN/A removeList.push(inst->getInstListIt()); 12261060SN/A} 12271060SN/A 12281060SN/Atemplate <class Impl> 12291060SN/Avoid 12302935Sksewell@umich.eduFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid, 12312935Sksewell@umich.edu bool squash_delay_slot, 12322935Sksewell@umich.edu const InstSeqNum &delay_slot_seq_num) 12331060SN/A{ 12342733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 12352292SN/A " list.\n", tid); 12361060SN/A 12372292SN/A ListIt end_it; 12381060SN/A 12392292SN/A bool rob_empty = false; 12402292SN/A 12412292SN/A if (instList.empty()) { 12422292SN/A return; 12432292SN/A } else if (rob.isEmpty(/*tid*/)) { 12442733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 12452292SN/A end_it = instList.begin(); 12462292SN/A rob_empty = true; 12472292SN/A } else { 12482292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 12492733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 12502292SN/A } 12512292SN/A 12522292SN/A removeInstsThisCycle = true; 12532292SN/A 12542292SN/A ListIt inst_it = instList.end(); 12552292SN/A 12562292SN/A inst_it--; 12572292SN/A 12582292SN/A // Walk through the instruction list, removing any instructions 12592292SN/A // that were inserted after the given instruction iterator, end_it. 12602292SN/A while (inst_it != end_it) { 12612292SN/A assert(!instList.empty()); 12622292SN/A 12633093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 12642935Sksewell@umich.edu if(!squash_delay_slot && 12652935Sksewell@umich.edu delay_slot_seq_num >= (*inst_it)->seqNum) { 12662935Sksewell@umich.edu break; 12672935Sksewell@umich.edu } 12682935Sksewell@umich.edu#endif 12692292SN/A squashInstIt(inst_it, tid); 12702292SN/A 12712292SN/A inst_it--; 12722292SN/A } 12732292SN/A 12742292SN/A // If the ROB was empty, then we actually need to remove the first 12752292SN/A // instruction as well. 12762292SN/A if (rob_empty) { 12772292SN/A squashInstIt(inst_it, tid); 12782292SN/A } 12791060SN/A} 12801060SN/A 12811060SN/Atemplate <class Impl> 12821060SN/Avoid 12832292SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 12842292SN/A unsigned tid) 12851062SN/A{ 12862292SN/A assert(!instList.empty()); 12872292SN/A 12882292SN/A removeInstsThisCycle = true; 12892292SN/A 12902292SN/A ListIt inst_iter = instList.end(); 12912292SN/A 12922292SN/A inst_iter--; 12932292SN/A 12942733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 12952292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 12962292SN/A tid, seq_num, (*inst_iter)->seqNum); 12971062SN/A 12982292SN/A while ((*inst_iter)->seqNum > seq_num) { 12991062SN/A 13002292SN/A bool break_loop = (inst_iter == instList.begin()); 13011062SN/A 13022292SN/A squashInstIt(inst_iter, tid); 13031062SN/A 13042292SN/A inst_iter--; 13051062SN/A 13062292SN/A if (break_loop) 13072292SN/A break; 13082292SN/A } 13092292SN/A} 13102292SN/A 13112292SN/Atemplate <class Impl> 13122292SN/Ainline void 13132292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 13142292SN/A{ 13152292SN/A if ((*instIt)->threadNumber == tid) { 13162733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 13172292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 13182292SN/A (*instIt)->threadNumber, 13192292SN/A (*instIt)->seqNum, 13202292SN/A (*instIt)->readPC()); 13211062SN/A 13221062SN/A // Mark it as squashed. 13232292SN/A (*instIt)->setSquashed(); 13242292SN/A 13252325SN/A // @todo: Formulate a consistent method for deleting 13262325SN/A // instructions from the instruction list 13272292SN/A // Remove the instruction from the list. 13282292SN/A removeList.push(instIt); 13292292SN/A } 13302292SN/A} 13312292SN/A 13322292SN/Atemplate <class Impl> 13332292SN/Avoid 13342292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 13352292SN/A{ 13362292SN/A while (!removeList.empty()) { 13372733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 13382292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 13392292SN/A (*removeList.front())->threadNumber, 13402292SN/A (*removeList.front())->seqNum, 13412292SN/A (*removeList.front())->readPC()); 13422292SN/A 13432292SN/A instList.erase(removeList.front()); 13442292SN/A 13452292SN/A removeList.pop(); 13461062SN/A } 13471062SN/A 13482292SN/A removeInstsThisCycle = false; 13491062SN/A} 13502325SN/A/* 13511062SN/Atemplate <class Impl> 13521062SN/Avoid 13531755SN/AFullO3CPU<Impl>::removeAllInsts() 13541060SN/A{ 13551060SN/A instList.clear(); 13561060SN/A} 13572325SN/A*/ 13581060SN/Atemplate <class Impl> 13591060SN/Avoid 13601755SN/AFullO3CPU<Impl>::dumpInsts() 13611060SN/A{ 13621060SN/A int num = 0; 13631060SN/A 13642292SN/A ListIt inst_list_it = instList.begin(); 13652292SN/A 13662292SN/A cprintf("Dumping Instruction List\n"); 13672292SN/A 13682292SN/A while (inst_list_it != instList.end()) { 13692292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 13702292SN/A "Squashed:%i\n\n", 13712292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 13722292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 13732292SN/A (*inst_list_it)->isSquashed()); 13741060SN/A inst_list_it++; 13751060SN/A ++num; 13761060SN/A } 13771060SN/A} 13782325SN/A/* 13791060SN/Atemplate <class Impl> 13801060SN/Avoid 13811755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 13821060SN/A{ 13831060SN/A iew.wakeDependents(inst); 13841060SN/A} 13852325SN/A*/ 13862292SN/Atemplate <class Impl> 13872292SN/Avoid 13882292SN/AFullO3CPU<Impl>::wakeCPU() 13892292SN/A{ 13902325SN/A if (activityRec.active() || tickEvent.scheduled()) { 13912325SN/A DPRINTF(Activity, "CPU already running.\n"); 13922292SN/A return; 13932292SN/A } 13942292SN/A 13952325SN/A DPRINTF(Activity, "Waking up CPU\n"); 13962325SN/A 13972325SN/A idleCycles += (curTick - 1) - lastRunningCycle; 13982292SN/A 13992292SN/A tickEvent.schedule(curTick); 14002292SN/A} 14012292SN/A 14022292SN/Atemplate <class Impl> 14032292SN/Aint 14042292SN/AFullO3CPU<Impl>::getFreeTid() 14052292SN/A{ 14062292SN/A for (int i=0; i < numThreads; i++) { 14072292SN/A if (!tids[i]) { 14082292SN/A tids[i] = true; 14092292SN/A return i; 14102292SN/A } 14112292SN/A } 14122292SN/A 14132292SN/A return -1; 14142292SN/A} 14152292SN/A 14162292SN/Atemplate <class Impl> 14172292SN/Avoid 14182292SN/AFullO3CPU<Impl>::doContextSwitch() 14192292SN/A{ 14202292SN/A if (contextSwitch) { 14212292SN/A 14222292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 14232292SN/A 14242292SN/A for (int tid=0; tid < cpuWaitList.size(); tid++) { 14252292SN/A activateWhenReady(tid); 14262292SN/A } 14272292SN/A 14282292SN/A if (cpuWaitList.size() == 0) 14292292SN/A contextSwitch = true; 14302292SN/A } 14312292SN/A} 14322292SN/A 14332292SN/Atemplate <class Impl> 14342292SN/Avoid 14352292SN/AFullO3CPU<Impl>::updateThreadPriority() 14362292SN/A{ 14372292SN/A if (activeThreads.size() > 1) 14382292SN/A { 14392292SN/A //DEFAULT TO ROUND ROBIN SCHEME 14402292SN/A //e.g. Move highest priority to end of thread list 14412292SN/A list<unsigned>::iterator list_begin = activeThreads.begin(); 14422292SN/A list<unsigned>::iterator list_end = activeThreads.end(); 14432292SN/A 14442292SN/A unsigned high_thread = *list_begin; 14452292SN/A 14462292SN/A activeThreads.erase(list_begin); 14472292SN/A 14482292SN/A activeThreads.push_back(high_thread); 14492292SN/A } 14502292SN/A} 14511060SN/A 14521755SN/A// Forward declaration of FullO3CPU. 14532818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1454