cpu.cc revision 3125
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 341858SN/A 351858SN/A#if FULL_SYSTEM 362356SN/A#include "cpu/quiesce_event.hh" 371060SN/A#include "sim/system.hh" 381060SN/A#else 391060SN/A#include "sim/process.hh" 401060SN/A#endif 411060SN/A 422325SN/A#include "cpu/activity.hh" 432683Sktlim@umich.edu#include "cpu/simple_thread.hh" 442680Sktlim@umich.edu#include "cpu/thread_context.hh" 452817Sksewell@umich.edu#include "cpu/o3/isa_specific.hh" 461717SN/A#include "cpu/o3/cpu.hh" 471060SN/A 482325SN/A#include "sim/root.hh" 492292SN/A#include "sim/stat_control.hh" 502292SN/A 512794Sktlim@umich.edu#if USE_CHECKER 522794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 532794Sktlim@umich.edu#endif 542794Sktlim@umich.edu 551060SN/Ausing namespace std; 562669Sktlim@umich.eduusing namespace TheISA; 571060SN/A 582733Sktlim@umich.eduBaseO3CPU::BaseO3CPU(Params *params) 592292SN/A : BaseCPU(params), cpu_id(0) 601060SN/A{ 611060SN/A} 621060SN/A 632292SN/Avoid 642733Sktlim@umich.eduBaseO3CPU::regStats() 652292SN/A{ 662292SN/A BaseCPU::regStats(); 672292SN/A} 682292SN/A 691060SN/Atemplate <class Impl> 701755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 711060SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 721060SN/A{ 731060SN/A} 741060SN/A 751060SN/Atemplate <class Impl> 761060SN/Avoid 771755SN/AFullO3CPU<Impl>::TickEvent::process() 781060SN/A{ 791060SN/A cpu->tick(); 801060SN/A} 811060SN/A 821060SN/Atemplate <class Impl> 831060SN/Aconst char * 841755SN/AFullO3CPU<Impl>::TickEvent::description() 851060SN/A{ 861755SN/A return "FullO3CPU tick event"; 871060SN/A} 881060SN/A 891060SN/Atemplate <class Impl> 902829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 912829Sksewell@umich.edu : Event(&mainEventQueue, CPU_Tick_Pri) 922829Sksewell@umich.edu{ 932829Sksewell@umich.edu} 942829Sksewell@umich.edu 952829Sksewell@umich.edutemplate <class Impl> 962829Sksewell@umich.eduvoid 972829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 982829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 992829Sksewell@umich.edu{ 1002829Sksewell@umich.edu tid = thread_num; 1012829Sksewell@umich.edu cpu = thread_cpu; 1022829Sksewell@umich.edu} 1032829Sksewell@umich.edu 1042829Sksewell@umich.edutemplate <class Impl> 1052829Sksewell@umich.eduvoid 1062829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1072829Sksewell@umich.edu{ 1082829Sksewell@umich.edu cpu->activateThread(tid); 1092829Sksewell@umich.edu} 1102829Sksewell@umich.edu 1112829Sksewell@umich.edutemplate <class Impl> 1122829Sksewell@umich.educonst char * 1132829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::description() 1142829Sksewell@umich.edu{ 1152829Sksewell@umich.edu return "FullO3CPU \"Activate Thread\" event"; 1162829Sksewell@umich.edu} 1172829Sksewell@umich.edu 1182829Sksewell@umich.edutemplate <class Impl> 1192875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1202875Sksewell@umich.edu : Event(&mainEventQueue, CPU_Tick_Pri) 1212875Sksewell@umich.edu{ 1222875Sksewell@umich.edu} 1232875Sksewell@umich.edu 1242875Sksewell@umich.edutemplate <class Impl> 1252875Sksewell@umich.eduvoid 1262875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1272875Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1282875Sksewell@umich.edu{ 1292875Sksewell@umich.edu tid = thread_num; 1302875Sksewell@umich.edu cpu = thread_cpu; 1312875Sksewell@umich.edu} 1322875Sksewell@umich.edu 1332875Sksewell@umich.edutemplate <class Impl> 1342875Sksewell@umich.eduvoid 1352875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1362875Sksewell@umich.edu{ 1372875Sksewell@umich.edu cpu->deactivateThread(tid); 1382875Sksewell@umich.edu cpu->removeThread(tid); 1392875Sksewell@umich.edu} 1402875Sksewell@umich.edu 1412875Sksewell@umich.edutemplate <class Impl> 1422875Sksewell@umich.educonst char * 1432875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::description() 1442875Sksewell@umich.edu{ 1452875Sksewell@umich.edu return "FullO3CPU \"Deallocate Context\" event"; 1462875Sksewell@umich.edu} 1472875Sksewell@umich.edu 1482875Sksewell@umich.edutemplate <class Impl> 1492292SN/AFullO3CPU<Impl>::FullO3CPU(Params *params) 1502733Sktlim@umich.edu : BaseO3CPU(params), 1511060SN/A tickEvent(this), 1522292SN/A removeInstsThisCycle(false), 1531060SN/A fetch(params), 1541060SN/A decode(params), 1551060SN/A rename(params), 1561060SN/A iew(params), 1571060SN/A commit(params), 1581060SN/A 1592292SN/A regFile(params->numPhysIntRegs, params->numPhysFloatRegs), 1601060SN/A 1612831Sksewell@umich.edu freeList(params->numberOfThreads, 1622292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1632292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1641060SN/A 1652292SN/A rob(params->numROBEntries, params->squashWidth, 1662292SN/A params->smtROBPolicy, params->smtROBThreshold, 1672292SN/A params->numberOfThreads), 1681060SN/A 1692831Sksewell@umich.edu scoreboard(params->numberOfThreads, 1702292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1712292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1722292SN/A TheISA::NumMiscRegs * number_of_threads, 1732292SN/A TheISA::ZeroReg), 1741060SN/A 1752873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1762873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1772873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1782873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1792873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1802873Sktlim@umich.edu activityRec(NumStages, 1812873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1822873Sktlim@umich.edu params->activity), 1831060SN/A 1841060SN/A globalSeqNum(1), 1851858SN/A#if FULL_SYSTEM 1862292SN/A system(params->system), 1871060SN/A physmem(system->physmem), 1881060SN/A#endif // FULL_SYSTEM 1892292SN/A mem(params->mem), 1902843Sktlim@umich.edu drainCount(0), 1912316SN/A deferRegistration(params->deferRegistration), 1922316SN/A numThreads(number_of_threads) 1931060SN/A{ 1941060SN/A _status = Idle; 1951681SN/A 1962733Sktlim@umich.edu checker = NULL; 1972733Sktlim@umich.edu 1982794Sktlim@umich.edu if (params->checker) { 1992733Sktlim@umich.edu#if USE_CHECKER 2002316SN/A BaseCPU *temp_checker = params->checker; 2012316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2022316SN/A checker->setMemory(mem); 2032316SN/A#if FULL_SYSTEM 2042316SN/A checker->setSystem(params->system); 2052316SN/A#endif 2062794Sktlim@umich.edu#else 2072794Sktlim@umich.edu panic("Checker enabled but not compiled in!"); 2082794Sktlim@umich.edu#endif // USE_CHECKER 2092316SN/A } 2102316SN/A 2111858SN/A#if !FULL_SYSTEM 2122292SN/A thread.resize(number_of_threads); 2132292SN/A tids.resize(number_of_threads); 2141681SN/A#endif 2151681SN/A 2162325SN/A // The stages also need their CPU pointer setup. However this 2172325SN/A // must be done at the upper level CPU because they have pointers 2182325SN/A // to the upper level CPU, and not this FullO3CPU. 2191060SN/A 2202292SN/A // Set up Pointers to the activeThreads list for each stage 2212292SN/A fetch.setActiveThreads(&activeThreads); 2222292SN/A decode.setActiveThreads(&activeThreads); 2232292SN/A rename.setActiveThreads(&activeThreads); 2242292SN/A iew.setActiveThreads(&activeThreads); 2252292SN/A commit.setActiveThreads(&activeThreads); 2261060SN/A 2271060SN/A // Give each of the stages the time buffer they will use. 2281060SN/A fetch.setTimeBuffer(&timeBuffer); 2291060SN/A decode.setTimeBuffer(&timeBuffer); 2301060SN/A rename.setTimeBuffer(&timeBuffer); 2311060SN/A iew.setTimeBuffer(&timeBuffer); 2321060SN/A commit.setTimeBuffer(&timeBuffer); 2331060SN/A 2341060SN/A // Also setup each of the stages' queues. 2351060SN/A fetch.setFetchQueue(&fetchQueue); 2361060SN/A decode.setFetchQueue(&fetchQueue); 2372292SN/A commit.setFetchQueue(&fetchQueue); 2381060SN/A decode.setDecodeQueue(&decodeQueue); 2391060SN/A rename.setDecodeQueue(&decodeQueue); 2401060SN/A rename.setRenameQueue(&renameQueue); 2411060SN/A iew.setRenameQueue(&renameQueue); 2421060SN/A iew.setIEWQueue(&iewQueue); 2431060SN/A commit.setIEWQueue(&iewQueue); 2441060SN/A commit.setRenameQueue(&renameQueue); 2451060SN/A 2462292SN/A commit.setIEWStage(&iew); 2472292SN/A rename.setIEWStage(&iew); 2482292SN/A rename.setCommitStage(&commit); 2492292SN/A 2502292SN/A#if !FULL_SYSTEM 2512307SN/A int active_threads = params->workload.size(); 2522831Sksewell@umich.edu 2532831Sksewell@umich.edu if (active_threads > Impl::MaxThreads) { 2542831Sksewell@umich.edu panic("Workload Size too large. Increase the 'MaxThreads'" 2552831Sksewell@umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2562831Sksewell@umich.edu "edit your workload size."); 2572831Sksewell@umich.edu } 2582292SN/A#else 2592307SN/A int active_threads = 1; 2602292SN/A#endif 2612292SN/A 2622316SN/A //Make Sure That this a Valid Architeture 2632292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2642292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2652292SN/A 2662292SN/A rename.setScoreboard(&scoreboard); 2672292SN/A iew.setScoreboard(&scoreboard); 2682292SN/A 2691060SN/A // Setup the rename map for whichever stages need it. 2702292SN/A PhysRegIndex lreg_idx = 0; 2712292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2721060SN/A 2732292SN/A for (int tid=0; tid < numThreads; tid++) { 2742307SN/A bool bindRegs = (tid <= active_threads - 1); 2752292SN/A 2762292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2772292SN/A params->numPhysIntRegs, 2782325SN/A lreg_idx, //Index for Logical. Regs 2792292SN/A 2802292SN/A TheISA::NumFloatRegs, 2812292SN/A params->numPhysFloatRegs, 2822325SN/A freg_idx, //Index for Float Regs 2832292SN/A 2842292SN/A TheISA::NumMiscRegs, 2852292SN/A 2862292SN/A TheISA::ZeroReg, 2872292SN/A TheISA::ZeroReg, 2882292SN/A 2892292SN/A tid, 2902292SN/A false); 2912292SN/A 2922292SN/A renameMap[tid].init(TheISA::NumIntRegs, 2932292SN/A params->numPhysIntRegs, 2942325SN/A lreg_idx, //Index for Logical. Regs 2952292SN/A 2962292SN/A TheISA::NumFloatRegs, 2972292SN/A params->numPhysFloatRegs, 2982325SN/A freg_idx, //Index for Float Regs 2992292SN/A 3002292SN/A TheISA::NumMiscRegs, 3012292SN/A 3022292SN/A TheISA::ZeroReg, 3032292SN/A TheISA::ZeroReg, 3042292SN/A 3052292SN/A tid, 3062292SN/A bindRegs); 3072292SN/A } 3082292SN/A 3092292SN/A rename.setRenameMap(renameMap); 3102292SN/A commit.setRenameMap(commitRenameMap); 3112292SN/A 3122292SN/A // Give renameMap & rename stage access to the freeList; 3132292SN/A for (int i=0; i < numThreads; i++) { 3142292SN/A renameMap[i].setFreeList(&freeList); 3152292SN/A } 3161060SN/A rename.setFreeList(&freeList); 3172292SN/A 3181060SN/A // Setup the ROB for whichever stages need it. 3191060SN/A commit.setROB(&rob); 3202292SN/A 3212292SN/A lastRunningCycle = curTick; 3222292SN/A 3232829Sksewell@umich.edu lastActivatedCycle = -1; 3242829Sksewell@umich.edu 3253093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3263093Sksewell@umich.edu //for (int i=0; i < numThreads; i++) { 3273093Sksewell@umich.edu //globalSeqNum[i] = 1; 3283093Sksewell@umich.edu //} 3293093Sksewell@umich.edu 3302292SN/A contextSwitch = false; 3311060SN/A} 3321060SN/A 3331060SN/Atemplate <class Impl> 3341755SN/AFullO3CPU<Impl>::~FullO3CPU() 3351060SN/A{ 3361060SN/A} 3371060SN/A 3381060SN/Atemplate <class Impl> 3391060SN/Avoid 3401755SN/AFullO3CPU<Impl>::fullCPURegStats() 3411062SN/A{ 3422733Sktlim@umich.edu BaseO3CPU::regStats(); 3432292SN/A 3442733Sktlim@umich.edu // Register any of the O3CPU's stats here. 3452292SN/A timesIdled 3462292SN/A .name(name() + ".timesIdled") 3472292SN/A .desc("Number of times that the entire CPU went into an idle state and" 3482292SN/A " unscheduled itself") 3492292SN/A .prereq(timesIdled); 3502292SN/A 3512292SN/A idleCycles 3522292SN/A .name(name() + ".idleCycles") 3532292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 3542292SN/A "to idling") 3552292SN/A .prereq(idleCycles); 3562292SN/A 3572292SN/A // Number of Instructions simulated 3582292SN/A // -------------------------------- 3592292SN/A // Should probably be in Base CPU but need templated 3602292SN/A // MaxThreads so put in here instead 3612292SN/A committedInsts 3622292SN/A .init(numThreads) 3632292SN/A .name(name() + ".committedInsts") 3642292SN/A .desc("Number of Instructions Simulated"); 3652292SN/A 3662292SN/A totalCommittedInsts 3672292SN/A .name(name() + ".committedInsts_total") 3682292SN/A .desc("Number of Instructions Simulated"); 3692292SN/A 3702292SN/A cpi 3712292SN/A .name(name() + ".cpi") 3722292SN/A .desc("CPI: Cycles Per Instruction") 3732292SN/A .precision(6); 3742292SN/A cpi = simTicks / committedInsts; 3752292SN/A 3762292SN/A totalCpi 3772292SN/A .name(name() + ".cpi_total") 3782292SN/A .desc("CPI: Total CPI of All Threads") 3792292SN/A .precision(6); 3802292SN/A totalCpi = simTicks / totalCommittedInsts; 3812292SN/A 3822292SN/A ipc 3832292SN/A .name(name() + ".ipc") 3842292SN/A .desc("IPC: Instructions Per Cycle") 3852292SN/A .precision(6); 3862292SN/A ipc = committedInsts / simTicks; 3872292SN/A 3882292SN/A totalIpc 3892292SN/A .name(name() + ".ipc_total") 3902292SN/A .desc("IPC: Total IPC of All Threads") 3912292SN/A .precision(6); 3922292SN/A totalIpc = totalCommittedInsts / simTicks; 3932292SN/A 3941062SN/A} 3951062SN/A 3961062SN/Atemplate <class Impl> 3972871Sktlim@umich.eduPort * 3982871Sktlim@umich.eduFullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 3992871Sktlim@umich.edu{ 4002871Sktlim@umich.edu if (if_name == "dcache_port") 4012871Sktlim@umich.edu return iew.getDcachePort(); 4022871Sktlim@umich.edu else if (if_name == "icache_port") 4032871Sktlim@umich.edu return fetch.getIcachePort(); 4042871Sktlim@umich.edu else 4052871Sktlim@umich.edu panic("No Such Port\n"); 4062871Sktlim@umich.edu} 4072871Sktlim@umich.edu 4082871Sktlim@umich.edutemplate <class Impl> 4091062SN/Avoid 4101755SN/AFullO3CPU<Impl>::tick() 4111060SN/A{ 4122733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 4131060SN/A 4142292SN/A ++numCycles; 4152292SN/A 4162325SN/A// activity = false; 4172292SN/A 4182292SN/A //Tick each of the stages 4191060SN/A fetch.tick(); 4201060SN/A 4211060SN/A decode.tick(); 4221060SN/A 4231060SN/A rename.tick(); 4241060SN/A 4251060SN/A iew.tick(); 4261060SN/A 4271060SN/A commit.tick(); 4281060SN/A 4292292SN/A#if !FULL_SYSTEM 4302292SN/A doContextSwitch(); 4312292SN/A#endif 4322292SN/A 4332292SN/A // Now advance the time buffers 4341060SN/A timeBuffer.advance(); 4351060SN/A 4361060SN/A fetchQueue.advance(); 4371060SN/A decodeQueue.advance(); 4381060SN/A renameQueue.advance(); 4391060SN/A iewQueue.advance(); 4401060SN/A 4412325SN/A activityRec.advance(); 4422292SN/A 4432292SN/A if (removeInstsThisCycle) { 4442292SN/A cleanUpRemovedInsts(); 4452292SN/A } 4462292SN/A 4472325SN/A if (!tickEvent.scheduled()) { 4482867Sktlim@umich.edu if (_status == SwitchedOut || 4492905Sktlim@umich.edu getState() == SimObject::Drained) { 4502325SN/A // increment stat 4512325SN/A lastRunningCycle = curTick; 4522325SN/A } else if (!activityRec.active()) { 4532325SN/A lastRunningCycle = curTick; 4542325SN/A timesIdled++; 4552325SN/A } else { 4562325SN/A tickEvent.schedule(curTick + cycles(1)); 4572325SN/A } 4582292SN/A } 4592292SN/A 4602292SN/A#if !FULL_SYSTEM 4612292SN/A updateThreadPriority(); 4622292SN/A#endif 4632292SN/A 4641060SN/A} 4651060SN/A 4661060SN/Atemplate <class Impl> 4671060SN/Avoid 4681755SN/AFullO3CPU<Impl>::init() 4691060SN/A{ 4702307SN/A if (!deferRegistration) { 4712680Sktlim@umich.edu registerThreadContexts(); 4722292SN/A } 4731060SN/A 4742292SN/A // Set inSyscall so that the CPU doesn't squash when initially 4752292SN/A // setting up registers. 4762292SN/A for (int i = 0; i < number_of_threads; ++i) 4772292SN/A thread[i]->inSyscall = true; 4782292SN/A 4792292SN/A for (int tid=0; tid < number_of_threads; tid++) { 4801858SN/A#if FULL_SYSTEM 4812680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 4821681SN/A#else 4832680Sktlim@umich.edu ThreadContext *src_tc = thread[tid]->getTC(); 4841681SN/A#endif 4852292SN/A // Threads start in the Suspended State 4862680Sktlim@umich.edu if (src_tc->status() != ThreadContext::Suspended) { 4872292SN/A continue; 4881060SN/A } 4891060SN/A 4902292SN/A#if FULL_SYSTEM 4912680Sktlim@umich.edu TheISA::initCPU(src_tc, src_tc->readCpuId()); 4922292SN/A#endif 4932292SN/A } 4942292SN/A 4952292SN/A // Clear inSyscall. 4962292SN/A for (int i = 0; i < number_of_threads; ++i) 4972292SN/A thread[i]->inSyscall = false; 4982292SN/A 4992316SN/A // Initialize stages. 5002292SN/A fetch.initStage(); 5012292SN/A iew.initStage(); 5022292SN/A rename.initStage(); 5032292SN/A commit.initStage(); 5042292SN/A 5052292SN/A commit.setThreads(thread); 5062292SN/A} 5072292SN/A 5082292SN/Atemplate <class Impl> 5092292SN/Avoid 5102875Sksewell@umich.eduFullO3CPU<Impl>::activateThread(unsigned tid) 5112875Sksewell@umich.edu{ 5122875Sksewell@umich.edu list<unsigned>::iterator isActive = find( 5132875Sksewell@umich.edu activeThreads.begin(), activeThreads.end(), tid); 5142875Sksewell@umich.edu 5152875Sksewell@umich.edu if (isActive == activeThreads.end()) { 5162875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 5172875Sksewell@umich.edu tid); 5182875Sksewell@umich.edu 5192875Sksewell@umich.edu activeThreads.push_back(tid); 5202875Sksewell@umich.edu } 5212875Sksewell@umich.edu} 5222875Sksewell@umich.edu 5232875Sksewell@umich.edutemplate <class Impl> 5242875Sksewell@umich.eduvoid 5252875Sksewell@umich.eduFullO3CPU<Impl>::deactivateThread(unsigned tid) 5262875Sksewell@umich.edu{ 5272875Sksewell@umich.edu //Remove From Active List, if Active 5282875Sksewell@umich.edu list<unsigned>::iterator thread_it = 5292875Sksewell@umich.edu find(activeThreads.begin(), activeThreads.end(), tid); 5302875Sksewell@umich.edu 5312875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 5322875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 5332875Sksewell@umich.edu tid); 5342875Sksewell@umich.edu activeThreads.erase(thread_it); 5352875Sksewell@umich.edu } 5362875Sksewell@umich.edu} 5372875Sksewell@umich.edu 5382875Sksewell@umich.edutemplate <class Impl> 5392875Sksewell@umich.eduvoid 5402875Sksewell@umich.eduFullO3CPU<Impl>::activateContext(int tid, int delay) 5412875Sksewell@umich.edu{ 5422875Sksewell@umich.edu // Needs to set each stage to running as well. 5432875Sksewell@umich.edu if (delay){ 5442875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 5452875Sksewell@umich.edu "on cycle %d\n", tid, curTick + cycles(delay)); 5462875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 5472875Sksewell@umich.edu } else { 5482875Sksewell@umich.edu activateThread(tid); 5492875Sksewell@umich.edu } 5502875Sksewell@umich.edu 5512875Sksewell@umich.edu if(lastActivatedCycle < curTick) { 5522875Sksewell@umich.edu scheduleTickEvent(delay); 5532875Sksewell@umich.edu 5542875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 5552875Sksewell@umich.edu // deschedule itself. 5562875Sksewell@umich.edu activityRec.activity(); 5572875Sksewell@umich.edu fetch.wakeFromQuiesce(); 5582875Sksewell@umich.edu 5592875Sksewell@umich.edu lastActivatedCycle = curTick; 5602875Sksewell@umich.edu 5612875Sksewell@umich.edu _status = Running; 5622875Sksewell@umich.edu } 5632875Sksewell@umich.edu} 5642875Sksewell@umich.edu 5652875Sksewell@umich.edutemplate <class Impl> 5662875Sksewell@umich.eduvoid 5672875Sksewell@umich.eduFullO3CPU<Impl>::deallocateContext(int tid, int delay) 5682875Sksewell@umich.edu{ 5692875Sksewell@umich.edu // Schedule removal of thread data from CPU 5702875Sksewell@umich.edu if (delay){ 5712875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 5722875Sksewell@umich.edu "on cycle %d\n", tid, curTick + cycles(delay)); 5732875Sksewell@umich.edu scheduleDeallocateContextEvent(tid, delay); 5742875Sksewell@umich.edu } else { 5752875Sksewell@umich.edu deactivateThread(tid); 5762875Sksewell@umich.edu removeThread(tid); 5772875Sksewell@umich.edu } 5782875Sksewell@umich.edu} 5792875Sksewell@umich.edu 5802875Sksewell@umich.edutemplate <class Impl> 5812875Sksewell@umich.eduvoid 5822875Sksewell@umich.eduFullO3CPU<Impl>::suspendContext(int tid) 5832875Sksewell@umich.edu{ 5842875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 5852911Sksewell@umich.edu deactivateThread(tid); 5862910Sksewell@umich.edu if (activeThreads.size() == 0) 5872910Sksewell@umich.edu unscheduleTickEvent(); 5882875Sksewell@umich.edu _status = Idle; 5892875Sksewell@umich.edu} 5902875Sksewell@umich.edu 5912875Sksewell@umich.edutemplate <class Impl> 5922875Sksewell@umich.eduvoid 5932875Sksewell@umich.eduFullO3CPU<Impl>::haltContext(int tid) 5942875Sksewell@umich.edu{ 5952910Sksewell@umich.edu //For now, this is the same as deallocate 5962910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 5972910Sksewell@umich.edu deallocateContext(tid, 1); 5982875Sksewell@umich.edu} 5992875Sksewell@umich.edu 6002875Sksewell@umich.edutemplate <class Impl> 6012875Sksewell@umich.eduvoid 6022292SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 6032292SN/A{ 6042847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 6052292SN/A // Will change now that the PC and thread state is internal to the CPU 6062683Sktlim@umich.edu // and not in the ThreadContext. 6072292SN/A#if FULL_SYSTEM 6082680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 6092292SN/A#else 6102847Sksewell@umich.edu ThreadContext *src_tc = tcBase(tid); 6112292SN/A#endif 6122292SN/A 6132292SN/A //Bind Int Regs to Rename Map 6142292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 6152292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 6162292SN/A 6172292SN/A renameMap[tid].setEntry(ireg,phys_reg); 6182292SN/A scoreboard.setReg(phys_reg); 6192292SN/A } 6202292SN/A 6212292SN/A //Bind Float Regs to Rename Map 6222292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 6232292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 6242292SN/A 6252292SN/A renameMap[tid].setEntry(freg,phys_reg); 6262292SN/A scoreboard.setReg(phys_reg); 6272292SN/A } 6282292SN/A 6292292SN/A //Copy Thread Data Into RegFile 6302847Sksewell@umich.edu //this->copyFromTC(tid); 6312292SN/A 6322847Sksewell@umich.edu //Set PC/NPC/NNPC 6332847Sksewell@umich.edu setPC(src_tc->readPC(), tid); 6342847Sksewell@umich.edu setNextPC(src_tc->readNextPC(), tid); 6353093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 6362847Sksewell@umich.edu setNextNPC(src_tc->readNextNPC(), tid); 6372847Sksewell@umich.edu#endif 6382292SN/A 6392680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 6402292SN/A 6412292SN/A activateContext(tid,1); 6422292SN/A 6432292SN/A //Reset ROB/IQ/LSQ Entries 6442292SN/A commit.rob->resetEntries(); 6452292SN/A iew.resetEntries(); 6462292SN/A} 6472292SN/A 6482292SN/Atemplate <class Impl> 6492292SN/Avoid 6502292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 6512292SN/A{ 6522877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 6532847Sksewell@umich.edu 6542847Sksewell@umich.edu // Copy Thread Data From RegFile 6552847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 6562847Sksewell@umich.edu //this->copyToTC(tid); 6572847Sksewell@umich.edu 6582847Sksewell@umich.edu // Unbind Int Regs from Rename Map 6592292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 6602292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 6612292SN/A 6622292SN/A scoreboard.unsetReg(phys_reg); 6632292SN/A freeList.addReg(phys_reg); 6642292SN/A } 6652292SN/A 6662847Sksewell@umich.edu // Unbind Float Regs from Rename Map 6672292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 6682292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 6692292SN/A 6702292SN/A scoreboard.unsetReg(phys_reg); 6712292SN/A freeList.addReg(phys_reg); 6722292SN/A } 6732292SN/A 6742847Sksewell@umich.edu // Squash Throughout Pipeline 6752935Sksewell@umich.edu InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum; 6762935Sksewell@umich.edu fetch.squash(0, squash_seq_num, true, tid); 6772292SN/A decode.squash(tid); 6782935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 6792875Sksewell@umich.edu iew.squash(tid); 6802935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 6812292SN/A 6822292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 6832292SN/A 6842847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 6852292SN/A if (activeThreads.size() >= 1) { 6862292SN/A commit.rob->resetEntries(); 6872292SN/A iew.resetEntries(); 6882292SN/A } 6892292SN/A} 6902292SN/A 6912292SN/A 6922292SN/Atemplate <class Impl> 6932292SN/Avoid 6942292SN/AFullO3CPU<Impl>::activateWhenReady(int tid) 6952292SN/A{ 6962733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 6972292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 6982292SN/A tid); 6992292SN/A 7002292SN/A bool ready = true; 7012292SN/A 7022292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 7032733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7042292SN/A "Phys. Int. Regs.\n", 7052292SN/A tid); 7062292SN/A ready = false; 7072292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 7082733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7092292SN/A "Phys. Float. Regs.\n", 7102292SN/A tid); 7112292SN/A ready = false; 7122292SN/A } else if (commit.rob->numFreeEntries() >= 7132292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 7142733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7152292SN/A "ROB entries.\n", 7162292SN/A tid); 7172292SN/A ready = false; 7182292SN/A } else if (iew.instQueue.numFreeEntries() >= 7192292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 7202733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7212292SN/A "IQ entries.\n", 7222292SN/A tid); 7232292SN/A ready = false; 7242292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 7252292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 7262733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7272292SN/A "LSQ entries.\n", 7282292SN/A tid); 7292292SN/A ready = false; 7302292SN/A } 7312292SN/A 7322292SN/A if (ready) { 7332292SN/A insertThread(tid); 7342292SN/A 7352292SN/A contextSwitch = false; 7362292SN/A 7372292SN/A cpuWaitList.remove(tid); 7382292SN/A } else { 7392292SN/A suspendContext(tid); 7402292SN/A 7412292SN/A //blocks fetch 7422292SN/A contextSwitch = true; 7432292SN/A 7442875Sksewell@umich.edu //@todo: dont always add to waitlist 7452292SN/A //do waitlist 7462292SN/A cpuWaitList.push_back(tid); 7471060SN/A } 7481060SN/A} 7491060SN/A 7501060SN/Atemplate <class Impl> 7512852Sktlim@umich.eduvoid 7522864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 7532864Sktlim@umich.edu{ 7542918Sktlim@umich.edu SimObject::State so_state = SimObject::getState(); 7552918Sktlim@umich.edu SERIALIZE_ENUM(so_state); 7562864Sktlim@umich.edu BaseCPU::serialize(os); 7572864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 7582864Sktlim@umich.edu tickEvent.serialize(os); 7592864Sktlim@umich.edu 7602864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 7612864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 7622864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 7632864Sktlim@umich.edu static SimpleThread temp; 7642864Sktlim@umich.edu 7652864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 7662864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 7672864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 7682864Sktlim@umich.edu temp.serialize(os); 7692864Sktlim@umich.edu } 7702864Sktlim@umich.edu} 7712864Sktlim@umich.edu 7722864Sktlim@umich.edutemplate <class Impl> 7732864Sktlim@umich.eduvoid 7742864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 7752864Sktlim@umich.edu{ 7762918Sktlim@umich.edu SimObject::State so_state; 7772918Sktlim@umich.edu UNSERIALIZE_ENUM(so_state); 7782864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 7792864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 7802864Sktlim@umich.edu 7812864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 7822864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 7832864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 7842864Sktlim@umich.edu static SimpleThread temp; 7852864Sktlim@umich.edu 7862864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 7872864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 7882864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 7892864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 7902864Sktlim@umich.edu } 7912864Sktlim@umich.edu} 7922864Sktlim@umich.edu 7932864Sktlim@umich.edutemplate <class Impl> 7942905Sktlim@umich.eduunsigned int 7952843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 7961060SN/A{ 7973125Sktlim@umich.edu DPRINTF(O3CPU, "Switching out\n"); 7983125Sktlim@umich.edu BaseCPU::switchOut(_sampler); 7992843Sktlim@umich.edu drainCount = 0; 8002843Sktlim@umich.edu fetch.drain(); 8012843Sktlim@umich.edu decode.drain(); 8022843Sktlim@umich.edu rename.drain(); 8032843Sktlim@umich.edu iew.drain(); 8042843Sktlim@umich.edu commit.drain(); 8052325SN/A 8062325SN/A // Wake the CPU and record activity so everything can drain out if 8072863Sktlim@umich.edu // the CPU was not able to immediately drain. 8082905Sktlim@umich.edu if (getState() != SimObject::Drained) { 8092864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 8102864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 8112864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 8122864Sktlim@umich.edu // process on the drain event. 8132864Sktlim@umich.edu drainEvent = drain_event; 8142843Sktlim@umich.edu 8152863Sktlim@umich.edu wakeCPU(); 8162863Sktlim@umich.edu activityRec.activity(); 8172852Sktlim@umich.edu 8182905Sktlim@umich.edu return 1; 8192863Sktlim@umich.edu } else { 8202905Sktlim@umich.edu return 0; 8212863Sktlim@umich.edu } 8222316SN/A} 8232310SN/A 8242316SN/Atemplate <class Impl> 8252316SN/Avoid 8262843Sktlim@umich.eduFullO3CPU<Impl>::resume() 8272316SN/A{ 8282905Sktlim@umich.edu assert(system->getMemoryMode() == System::Timing); 8292843Sktlim@umich.edu fetch.resume(); 8302843Sktlim@umich.edu decode.resume(); 8312843Sktlim@umich.edu rename.resume(); 8322843Sktlim@umich.edu iew.resume(); 8332843Sktlim@umich.edu commit.resume(); 8342316SN/A 8352905Sktlim@umich.edu changeState(SimObject::Running); 8362905Sktlim@umich.edu 8372864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 8382864Sktlim@umich.edu return; 8392864Sktlim@umich.edu 8402843Sktlim@umich.edu if (!tickEvent.scheduled()) 8412843Sktlim@umich.edu tickEvent.schedule(curTick); 8422843Sktlim@umich.edu _status = Running; 8432843Sktlim@umich.edu} 8442316SN/A 8452843Sktlim@umich.edutemplate <class Impl> 8462843Sktlim@umich.eduvoid 8472843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 8482843Sktlim@umich.edu{ 8492843Sktlim@umich.edu if (++drainCount == NumStages) { 8502316SN/A if (tickEvent.scheduled()) 8512316SN/A tickEvent.squash(); 8522863Sktlim@umich.edu 8532905Sktlim@umich.edu changeState(SimObject::Drained); 8542863Sktlim@umich.edu 8552863Sktlim@umich.edu if (drainEvent) { 8562863Sktlim@umich.edu drainEvent->process(); 8572863Sktlim@umich.edu drainEvent = NULL; 8582863Sktlim@umich.edu } 8592310SN/A } 8602843Sktlim@umich.edu assert(drainCount <= 5); 8612843Sktlim@umich.edu} 8622843Sktlim@umich.edu 8632843Sktlim@umich.edutemplate <class Impl> 8642843Sktlim@umich.eduvoid 8652843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 8662843Sktlim@umich.edu{ 8672843Sktlim@umich.edu fetch.switchOut(); 8682843Sktlim@umich.edu rename.switchOut(); 8692325SN/A iew.switchOut(); 8702843Sktlim@umich.edu commit.switchOut(); 8712843Sktlim@umich.edu instList.clear(); 8722843Sktlim@umich.edu while (!removeList.empty()) { 8732843Sktlim@umich.edu removeList.pop(); 8742843Sktlim@umich.edu } 8752843Sktlim@umich.edu 8762843Sktlim@umich.edu _status = SwitchedOut; 8772843Sktlim@umich.edu#if USE_CHECKER 8782843Sktlim@umich.edu if (checker) 8792843Sktlim@umich.edu checker->switchOut(); 8802843Sktlim@umich.edu#endif 8811060SN/A} 8821060SN/A 8831060SN/Atemplate <class Impl> 8841060SN/Avoid 8851755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 8861060SN/A{ 8872325SN/A // Flush out any old data from the time buffers. 8882873Sktlim@umich.edu for (int i = 0; i < timeBuffer.getSize(); ++i) { 8892307SN/A timeBuffer.advance(); 8902307SN/A fetchQueue.advance(); 8912307SN/A decodeQueue.advance(); 8922307SN/A renameQueue.advance(); 8932307SN/A iewQueue.advance(); 8942307SN/A } 8952307SN/A 8962325SN/A activityRec.reset(); 8972307SN/A 8981060SN/A BaseCPU::takeOverFrom(oldCPU); 8991060SN/A 9002307SN/A fetch.takeOverFrom(); 9012307SN/A decode.takeOverFrom(); 9022307SN/A rename.takeOverFrom(); 9032307SN/A iew.takeOverFrom(); 9042307SN/A commit.takeOverFrom(); 9052307SN/A 9061060SN/A assert(!tickEvent.scheduled()); 9071060SN/A 9082325SN/A // @todo: Figure out how to properly select the tid to put onto 9092325SN/A // the active threads list. 9102307SN/A int tid = 0; 9112307SN/A 9122307SN/A list<unsigned>::iterator isActive = find( 9132307SN/A activeThreads.begin(), activeThreads.end(), tid); 9142307SN/A 9152307SN/A if (isActive == activeThreads.end()) { 9162325SN/A //May Need to Re-code this if the delay variable is the delay 9172325SN/A //needed for thread to activate 9182733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 9192307SN/A tid); 9202307SN/A 9212307SN/A activeThreads.push_back(tid); 9222307SN/A } 9232307SN/A 9242325SN/A // Set all statuses to active, schedule the CPU's tick event. 9252307SN/A // @todo: Fix up statuses so this is handled properly 9262680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 9272680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 9282680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 9291681SN/A _status = Running; 9301681SN/A tickEvent.schedule(curTick); 9311681SN/A } 9321060SN/A } 9332307SN/A if (!tickEvent.scheduled()) 9342307SN/A tickEvent.schedule(curTick); 9351060SN/A} 9361060SN/A 9371060SN/Atemplate <class Impl> 9382353SN/Avoid 9392353SN/AFullO3CPU<Impl>::serialize(std::ostream &os) 9402353SN/A{ 9412353SN/A BaseCPU::serialize(os); 9422353SN/A nameOut(os, csprintf("%s.tickEvent", name())); 9432353SN/A tickEvent.serialize(os); 9442353SN/A 9452353SN/A // Use SimpleThread's ability to checkpoint to make it easier to 9462353SN/A // write out the registers. Also make this static so it doesn't 9472353SN/A // get instantiated multiple times (causes a panic in statistics). 9482356SN/A static CPUExecContext temp; 9492353SN/A 9502353SN/A for (int i = 0; i < thread.size(); i++) { 9512353SN/A nameOut(os, csprintf("%s.xc.%i", name(), i)); 9522356SN/A temp.copyXC(thread[i]->getXCProxy()); 9532353SN/A temp.serialize(os); 9542353SN/A } 9552353SN/A} 9562353SN/A 9572353SN/Atemplate <class Impl> 9582353SN/Avoid 9592353SN/AFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 9602353SN/A{ 9612353SN/A BaseCPU::unserialize(cp, section); 9622353SN/A tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 9632353SN/A 9642353SN/A // Use SimpleThread's ability to checkpoint to make it easier to 9652353SN/A // read in the registers. Also make this static so it doesn't 9662353SN/A // get instantiated multiple times (causes a panic in statistics). 9672356SN/A static CPUExecContext temp; 9682353SN/A 9692353SN/A for (int i = 0; i < thread.size(); i++) { 9702356SN/A temp.copyXC(thread[i]->getXCProxy()); 9712353SN/A temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 9722356SN/A thread[i]->getXCProxy()->copyArchRegs(temp.getProxy()); 9732353SN/A } 9742353SN/A} 9752356SN/A 9762325SN/Atemplate <class Impl> 9771060SN/Auint64_t 9781755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 9791060SN/A{ 9801060SN/A return regFile.readIntReg(reg_idx); 9811060SN/A} 9821060SN/A 9831060SN/Atemplate <class Impl> 9842455SN/AFloatReg 9852455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 9861060SN/A{ 9872455SN/A return regFile.readFloatReg(reg_idx, width); 9881060SN/A} 9891060SN/A 9901060SN/Atemplate <class Impl> 9912455SN/AFloatReg 9922455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 9931060SN/A{ 9942455SN/A return regFile.readFloatReg(reg_idx); 9951060SN/A} 9961060SN/A 9971060SN/Atemplate <class Impl> 9982455SN/AFloatRegBits 9992455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 10001060SN/A{ 10012455SN/A return regFile.readFloatRegBits(reg_idx, width); 10022455SN/A} 10032455SN/A 10042455SN/Atemplate <class Impl> 10052455SN/AFloatRegBits 10062455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 10072455SN/A{ 10082455SN/A return regFile.readFloatRegBits(reg_idx); 10091060SN/A} 10101060SN/A 10111060SN/Atemplate <class Impl> 10121060SN/Avoid 10131755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 10141060SN/A{ 10151060SN/A regFile.setIntReg(reg_idx, val); 10161060SN/A} 10171060SN/A 10181060SN/Atemplate <class Impl> 10191060SN/Avoid 10202455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 10211060SN/A{ 10222455SN/A regFile.setFloatReg(reg_idx, val, width); 10231060SN/A} 10241060SN/A 10251060SN/Atemplate <class Impl> 10261060SN/Avoid 10272455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 10281060SN/A{ 10292455SN/A regFile.setFloatReg(reg_idx, val); 10301060SN/A} 10311060SN/A 10321060SN/Atemplate <class Impl> 10331060SN/Avoid 10342455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 10351060SN/A{ 10362455SN/A regFile.setFloatRegBits(reg_idx, val, width); 10372455SN/A} 10382455SN/A 10392455SN/Atemplate <class Impl> 10402455SN/Avoid 10412455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 10422455SN/A{ 10432455SN/A regFile.setFloatRegBits(reg_idx, val); 10441060SN/A} 10451060SN/A 10461060SN/Atemplate <class Impl> 10471060SN/Auint64_t 10482292SN/AFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 10491060SN/A{ 10502292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10512292SN/A 10522292SN/A return regFile.readIntReg(phys_reg); 10532292SN/A} 10542292SN/A 10552292SN/Atemplate <class Impl> 10562292SN/Afloat 10572292SN/AFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 10582292SN/A{ 10592307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 10602307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10612292SN/A 10622669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 10632292SN/A} 10642292SN/A 10652292SN/Atemplate <class Impl> 10662292SN/Adouble 10672292SN/AFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 10682292SN/A{ 10692307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 10702307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10712292SN/A 10722669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 10732292SN/A} 10742292SN/A 10752292SN/Atemplate <class Impl> 10762292SN/Auint64_t 10772292SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 10782292SN/A{ 10792307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 10802307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10812292SN/A 10822669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 10831060SN/A} 10841060SN/A 10851060SN/Atemplate <class Impl> 10861060SN/Avoid 10872292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 10881060SN/A{ 10892292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10902292SN/A 10912292SN/A regFile.setIntReg(phys_reg, val); 10921060SN/A} 10931060SN/A 10941060SN/Atemplate <class Impl> 10951060SN/Avoid 10962292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 10971060SN/A{ 10982918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 10992918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 11002292SN/A 11012669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 11021060SN/A} 11031060SN/A 11041060SN/Atemplate <class Impl> 11051060SN/Avoid 11062292SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 11071060SN/A{ 11082918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 11092918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 11102292SN/A 11112669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 11121060SN/A} 11131060SN/A 11141060SN/Atemplate <class Impl> 11151060SN/Avoid 11162292SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 11171060SN/A{ 11182918Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 11192918Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 11201060SN/A 11212669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 11222292SN/A} 11232292SN/A 11242292SN/Atemplate <class Impl> 11252292SN/Auint64_t 11262292SN/AFullO3CPU<Impl>::readPC(unsigned tid) 11272292SN/A{ 11282292SN/A return commit.readPC(tid); 11291060SN/A} 11301060SN/A 11311060SN/Atemplate <class Impl> 11321060SN/Avoid 11332292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 11341060SN/A{ 11352292SN/A commit.setPC(new_PC, tid); 11362292SN/A} 11371060SN/A 11382292SN/Atemplate <class Impl> 11392292SN/Auint64_t 11402292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 11412292SN/A{ 11422292SN/A return commit.readNextPC(tid); 11432292SN/A} 11441060SN/A 11452292SN/Atemplate <class Impl> 11462292SN/Avoid 11472292SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 11482292SN/A{ 11492292SN/A commit.setNextPC(val, tid); 11502292SN/A} 11511060SN/A 11522756Sksewell@umich.edutemplate <class Impl> 11532756Sksewell@umich.eduuint64_t 11542756Sksewell@umich.eduFullO3CPU<Impl>::readNextNPC(unsigned tid) 11552756Sksewell@umich.edu{ 11562756Sksewell@umich.edu return commit.readNextNPC(tid); 11572756Sksewell@umich.edu} 11582756Sksewell@umich.edu 11592756Sksewell@umich.edutemplate <class Impl> 11602756Sksewell@umich.eduvoid 11612935Sksewell@umich.eduFullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid) 11622756Sksewell@umich.edu{ 11632756Sksewell@umich.edu commit.setNextNPC(val, tid); 11642756Sksewell@umich.edu} 11652756Sksewell@umich.edu 11662292SN/Atemplate <class Impl> 11672292SN/Atypename FullO3CPU<Impl>::ListIt 11682292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 11692292SN/A{ 11702292SN/A instList.push_back(inst); 11711060SN/A 11722292SN/A return --(instList.end()); 11732292SN/A} 11741060SN/A 11752292SN/Atemplate <class Impl> 11762292SN/Avoid 11772292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 11782292SN/A{ 11792292SN/A // Keep an instruction count. 11802292SN/A thread[tid]->numInst++; 11812292SN/A thread[tid]->numInsts++; 11822292SN/A committedInsts[tid]++; 11832292SN/A totalCommittedInsts++; 11842292SN/A 11852292SN/A // Check for instruction-count-based events. 11862292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 11872292SN/A} 11882292SN/A 11892292SN/Atemplate <class Impl> 11902292SN/Avoid 11912292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 11922292SN/A{ 11932292SN/A removeInstsThisCycle = true; 11942292SN/A 11952292SN/A removeList.push(inst->getInstListIt()); 11961060SN/A} 11971060SN/A 11981060SN/Atemplate <class Impl> 11991060SN/Avoid 12001755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 12011060SN/A{ 12022733Sktlim@umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 12032292SN/A "[sn:%lli]\n", 12042303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 12051060SN/A 12062292SN/A removeInstsThisCycle = true; 12071060SN/A 12081060SN/A // Remove the front instruction. 12092292SN/A removeList.push(inst->getInstListIt()); 12101060SN/A} 12111060SN/A 12121060SN/Atemplate <class Impl> 12131060SN/Avoid 12142935Sksewell@umich.eduFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid, 12152935Sksewell@umich.edu bool squash_delay_slot, 12162935Sksewell@umich.edu const InstSeqNum &delay_slot_seq_num) 12171060SN/A{ 12182733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 12192292SN/A " list.\n", tid); 12201060SN/A 12212292SN/A ListIt end_it; 12221060SN/A 12232292SN/A bool rob_empty = false; 12242292SN/A 12252292SN/A if (instList.empty()) { 12262292SN/A return; 12272292SN/A } else if (rob.isEmpty(/*tid*/)) { 12282733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 12292292SN/A end_it = instList.begin(); 12302292SN/A rob_empty = true; 12312292SN/A } else { 12322292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 12332733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 12342292SN/A } 12352292SN/A 12362292SN/A removeInstsThisCycle = true; 12372292SN/A 12382292SN/A ListIt inst_it = instList.end(); 12392292SN/A 12402292SN/A inst_it--; 12412292SN/A 12422292SN/A // Walk through the instruction list, removing any instructions 12432292SN/A // that were inserted after the given instruction iterator, end_it. 12442292SN/A while (inst_it != end_it) { 12452292SN/A assert(!instList.empty()); 12462292SN/A 12473093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 12482935Sksewell@umich.edu if(!squash_delay_slot && 12492935Sksewell@umich.edu delay_slot_seq_num >= (*inst_it)->seqNum) { 12502935Sksewell@umich.edu break; 12512935Sksewell@umich.edu } 12522935Sksewell@umich.edu#endif 12532292SN/A squashInstIt(inst_it, tid); 12542292SN/A 12552292SN/A inst_it--; 12562292SN/A } 12572292SN/A 12582292SN/A // If the ROB was empty, then we actually need to remove the first 12592292SN/A // instruction as well. 12602292SN/A if (rob_empty) { 12612292SN/A squashInstIt(inst_it, tid); 12622292SN/A } 12631060SN/A} 12641060SN/A 12651060SN/Atemplate <class Impl> 12661060SN/Avoid 12672292SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 12682292SN/A unsigned tid) 12691062SN/A{ 12702292SN/A assert(!instList.empty()); 12712292SN/A 12722292SN/A removeInstsThisCycle = true; 12732292SN/A 12742292SN/A ListIt inst_iter = instList.end(); 12752292SN/A 12762292SN/A inst_iter--; 12772292SN/A 12782733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 12792292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 12802292SN/A tid, seq_num, (*inst_iter)->seqNum); 12811062SN/A 12822292SN/A while ((*inst_iter)->seqNum > seq_num) { 12831062SN/A 12842292SN/A bool break_loop = (inst_iter == instList.begin()); 12851062SN/A 12862292SN/A squashInstIt(inst_iter, tid); 12871062SN/A 12882292SN/A inst_iter--; 12891062SN/A 12902292SN/A if (break_loop) 12912292SN/A break; 12922292SN/A } 12932292SN/A} 12942292SN/A 12952292SN/Atemplate <class Impl> 12962292SN/Ainline void 12972292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 12982292SN/A{ 12992292SN/A if ((*instIt)->threadNumber == tid) { 13002733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 13012292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 13022292SN/A (*instIt)->threadNumber, 13032292SN/A (*instIt)->seqNum, 13042292SN/A (*instIt)->readPC()); 13051062SN/A 13061062SN/A // Mark it as squashed. 13072292SN/A (*instIt)->setSquashed(); 13082292SN/A 13092325SN/A // @todo: Formulate a consistent method for deleting 13102325SN/A // instructions from the instruction list 13112292SN/A // Remove the instruction from the list. 13122292SN/A removeList.push(instIt); 13132292SN/A } 13142292SN/A} 13152292SN/A 13162292SN/Atemplate <class Impl> 13172292SN/Avoid 13182292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 13192292SN/A{ 13202292SN/A while (!removeList.empty()) { 13212733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 13222292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 13232292SN/A (*removeList.front())->threadNumber, 13242292SN/A (*removeList.front())->seqNum, 13252292SN/A (*removeList.front())->readPC()); 13262292SN/A 13272292SN/A instList.erase(removeList.front()); 13282292SN/A 13292292SN/A removeList.pop(); 13301062SN/A } 13311062SN/A 13322292SN/A removeInstsThisCycle = false; 13331062SN/A} 13342325SN/A/* 13351062SN/Atemplate <class Impl> 13361062SN/Avoid 13371755SN/AFullO3CPU<Impl>::removeAllInsts() 13381060SN/A{ 13391060SN/A instList.clear(); 13401060SN/A} 13412325SN/A*/ 13421060SN/Atemplate <class Impl> 13431060SN/Avoid 13441755SN/AFullO3CPU<Impl>::dumpInsts() 13451060SN/A{ 13461060SN/A int num = 0; 13471060SN/A 13482292SN/A ListIt inst_list_it = instList.begin(); 13492292SN/A 13502292SN/A cprintf("Dumping Instruction List\n"); 13512292SN/A 13522292SN/A while (inst_list_it != instList.end()) { 13532292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 13542292SN/A "Squashed:%i\n\n", 13552292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 13562292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 13572292SN/A (*inst_list_it)->isSquashed()); 13581060SN/A inst_list_it++; 13591060SN/A ++num; 13601060SN/A } 13611060SN/A} 13622325SN/A/* 13631060SN/Atemplate <class Impl> 13641060SN/Avoid 13651755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 13661060SN/A{ 13671060SN/A iew.wakeDependents(inst); 13681060SN/A} 13692325SN/A*/ 13702292SN/Atemplate <class Impl> 13712292SN/Avoid 13722292SN/AFullO3CPU<Impl>::wakeCPU() 13732292SN/A{ 13742325SN/A if (activityRec.active() || tickEvent.scheduled()) { 13752325SN/A DPRINTF(Activity, "CPU already running.\n"); 13762292SN/A return; 13772292SN/A } 13782292SN/A 13792325SN/A DPRINTF(Activity, "Waking up CPU\n"); 13802325SN/A 13812325SN/A idleCycles += (curTick - 1) - lastRunningCycle; 13822292SN/A 13832292SN/A tickEvent.schedule(curTick); 13842292SN/A} 13852292SN/A 13862292SN/Atemplate <class Impl> 13872292SN/Aint 13882292SN/AFullO3CPU<Impl>::getFreeTid() 13892292SN/A{ 13902292SN/A for (int i=0; i < numThreads; i++) { 13912292SN/A if (!tids[i]) { 13922292SN/A tids[i] = true; 13932292SN/A return i; 13942292SN/A } 13952292SN/A } 13962292SN/A 13972292SN/A return -1; 13982292SN/A} 13992292SN/A 14002292SN/Atemplate <class Impl> 14012292SN/Avoid 14022292SN/AFullO3CPU<Impl>::doContextSwitch() 14032292SN/A{ 14042292SN/A if (contextSwitch) { 14052292SN/A 14062292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 14072292SN/A 14082292SN/A for (int tid=0; tid < cpuWaitList.size(); tid++) { 14092292SN/A activateWhenReady(tid); 14102292SN/A } 14112292SN/A 14122292SN/A if (cpuWaitList.size() == 0) 14132292SN/A contextSwitch = true; 14142292SN/A } 14152292SN/A} 14162292SN/A 14172292SN/Atemplate <class Impl> 14182292SN/Avoid 14192292SN/AFullO3CPU<Impl>::updateThreadPriority() 14202292SN/A{ 14212292SN/A if (activeThreads.size() > 1) 14222292SN/A { 14232292SN/A //DEFAULT TO ROUND ROBIN SCHEME 14242292SN/A //e.g. Move highest priority to end of thread list 14252292SN/A list<unsigned>::iterator list_begin = activeThreads.begin(); 14262292SN/A list<unsigned>::iterator list_end = activeThreads.end(); 14272292SN/A 14282292SN/A unsigned high_thread = *list_begin; 14292292SN/A 14302292SN/A activeThreads.erase(list_begin); 14312292SN/A 14322292SN/A activeThreads.push_back(high_thread); 14332292SN/A } 14342292SN/A} 14351060SN/A 14361755SN/A// Forward declaration of FullO3CPU. 14372818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1438