cpu.cc revision 2911
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 37897Shestness@cs.utexas.edu * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271689SN/A * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292665Ssaidi@eecs.umich.edu * Korey Sewell 302756Sksewell@umich.edu */ 317897Shestness@cs.utexas.edu 321689SN/A#include "config/full_system.hh" 331689SN/A#include "config/use_checker.hh" 341858SN/A 356658Snate@binkert.org#if FULL_SYSTEM 362733Sktlim@umich.edu#include "sim/system.hh" 378229Snate@binkert.org#else 388229Snate@binkert.org#include "sim/process.hh" 398229Snate@binkert.org#endif 404762Snate@binkert.org 414762Snate@binkert.org#include "cpu/activity.hh" 424762Snate@binkert.org#include "cpu/simple_thread.hh" 438232Snate@binkert.org#include "cpu/thread_context.hh" 448232Snate@binkert.org#include "cpu/o3/isa_specific.hh" 458232Snate@binkert.org#include "cpu/o3/cpu.hh" 464762Snate@binkert.org 474762Snate@binkert.org#include "sim/root.hh" 484762Snate@binkert.org#include "sim/stat_control.hh" 498460SAli.Saidi@ARM.com 504762Snate@binkert.org#if USE_CHECKER 511858SN/A#include "cpu/checker/cpu.hh" 522356SN/A#endif 531060SN/A 541060SN/Ausing namespace std; 551060SN/Ausing namespace TheISA; 561060SN/A 572794Sktlim@umich.eduBaseO3CPU::BaseO3CPU(Params *params) 582794Sktlim@umich.edu : BaseCPU(params), cpu_id(0) 592794Sktlim@umich.edu{ 602794Sktlim@umich.edu} 615702Ssaidi@eecs.umich.edu 625702Ssaidi@eecs.umich.eduvoid 638232Snate@binkert.orgBaseO3CPU::regStats() 645702Ssaidi@eecs.umich.edu{ 655702Ssaidi@eecs.umich.edu BaseCPU::regStats(); 665529Snate@binkert.org} 675529Snate@binkert.org 682669Sktlim@umich.edutemplate <class Impl> 696221Snate@binkert.orgFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 701060SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 715529Snate@binkert.org{ 725712Shsul@eecs.umich.edu} 731060SN/A 741060SN/Atemplate <class Impl> 751060SN/Avoid 762292SN/AFullO3CPU<Impl>::TickEvent::process() 772733Sktlim@umich.edu{ 782292SN/A cpu->tick(); 792292SN/A} 802292SN/A 812292SN/Atemplate <class Impl> 821060SN/Aconst char * 831755SN/AFullO3CPU<Impl>::TickEvent::description() 845606Snate@binkert.org{ 851060SN/A return "FullO3CPU tick event"; 861060SN/A} 871060SN/A 881060SN/Atemplate <class Impl> 891060SN/AFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 901755SN/A : Event(&mainEventQueue, CPU_Tick_Pri) 911060SN/A{ 921060SN/A} 931060SN/A 941060SN/Atemplate <class Impl> 951060SN/Avoid 961060SN/AFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 975336Shines@cs.fsu.edu FullO3CPU<Impl> *thread_cpu) 981060SN/A{ 994873Sstever@eecs.umich.edu tid = thread_num; 1001060SN/A cpu = thread_cpu; 1011060SN/A} 1021060SN/A 1032829Sksewell@umich.edutemplate <class Impl> 1045606Snate@binkert.orgvoid 1052829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1062829Sksewell@umich.edu{ 1072829Sksewell@umich.edu cpu->activateThread(tid); 1082829Sksewell@umich.edu} 1092829Sksewell@umich.edu 1102829Sksewell@umich.edutemplate <class Impl> 1112829Sksewell@umich.educonst char * 1122829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::description() 1132829Sksewell@umich.edu{ 1142829Sksewell@umich.edu return "FullO3CPU \"Activate Thread\" event"; 1152829Sksewell@umich.edu} 1162829Sksewell@umich.edu 1172829Sksewell@umich.edutemplate <class Impl> 1182829Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1192829Sksewell@umich.edu : Event(&mainEventQueue, CPU_Tick_Pri) 1202829Sksewell@umich.edu{ 1212829Sksewell@umich.edu} 1222829Sksewell@umich.edu 1232829Sksewell@umich.edutemplate <class Impl> 1242829Sksewell@umich.eduvoid 1252829Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1265336Shines@cs.fsu.edu FullO3CPU<Impl> *thread_cpu) 1272829Sksewell@umich.edu{ 1284873Sstever@eecs.umich.edu tid = thread_num; 1292829Sksewell@umich.edu cpu = thread_cpu; 1302829Sksewell@umich.edu} 1312829Sksewell@umich.edu 1322875Sksewell@umich.edutemplate <class Impl> 1335606Snate@binkert.orgvoid 1342875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1352875Sksewell@umich.edu{ 1362875Sksewell@umich.edu cpu->deactivateThread(tid); 1372875Sksewell@umich.edu cpu->removeThread(tid); 1382875Sksewell@umich.edu} 1392875Sksewell@umich.edu 1403859Sbinkertn@umich.edutemplate <class Impl> 1412875Sksewell@umich.educonst char * 1422875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::description() 1432875Sksewell@umich.edu{ 1443859Sbinkertn@umich.edu return "FullO3CPU \"Deallocate Context\" event"; 1452875Sksewell@umich.edu} 1462875Sksewell@umich.edu 1472875Sksewell@umich.edutemplate <class Impl> 1482875Sksewell@umich.eduFullO3CPU<Impl>::FullO3CPU(Params *params) 1492875Sksewell@umich.edu : BaseO3CPU(params), 1502875Sksewell@umich.edu tickEvent(this), 1512875Sksewell@umich.edu removeInstsThisCycle(false), 1523221Sktlim@umich.edu fetch(params), 1533221Sktlim@umich.edu decode(params), 1542875Sksewell@umich.edu rename(params), 1552875Sksewell@umich.edu iew(params), 1562875Sksewell@umich.edu commit(params), 1572875Sksewell@umich.edu 1585336Shines@cs.fsu.edu regFile(params->numPhysIntRegs, params->numPhysFloatRegs), 1592875Sksewell@umich.edu 1604873Sstever@eecs.umich.edu freeList(params->numberOfThreads, 1612875Sksewell@umich.edu TheISA::NumIntRegs, params->numPhysIntRegs, 1622875Sksewell@umich.edu TheISA::NumFloatRegs, params->numPhysFloatRegs), 1632875Sksewell@umich.edu 1645595Sgblack@eecs.umich.edu rob(params->numROBEntries, params->squashWidth, 1652733Sktlim@umich.edu params->smtROBPolicy, params->smtROBThreshold, 1663781Sgblack@eecs.umich.edu params->numberOfThreads), 1673781Sgblack@eecs.umich.edu 1681060SN/A scoreboard(params->numberOfThreads, 1695737Scws3k@cs.virginia.edu TheISA::NumIntRegs, params->numPhysIntRegs, 1705737Scws3k@cs.virginia.edu TheISA::NumFloatRegs, params->numPhysFloatRegs, 1715737Scws3k@cs.virginia.edu TheISA::NumMiscRegs * number_of_threads, 1722292SN/A TheISA::ZeroReg), 1735595Sgblack@eecs.umich.edu 1745595Sgblack@eecs.umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1755595Sgblack@eecs.umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1765595Sgblack@eecs.umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1775595Sgblack@eecs.umich.edu renameQueue(params->backComSize, params->forwardComSize), 1781060SN/A iewQueue(params->backComSize, params->forwardComSize), 1795595Sgblack@eecs.umich.edu activityRec(NumStages, 1804329Sktlim@umich.edu params->backComSize + params->forwardComSize, 1811060SN/A params->activity), 1825529Snate@binkert.org 1832292SN/A globalSeqNum(1), 1842292SN/A 1851060SN/A#if FULL_SYSTEM 1865595Sgblack@eecs.umich.edu system(params->system), 1874329Sktlim@umich.edu physmem(system->physmem), 1882292SN/A#endif // FULL_SYSTEM 1895529Snate@binkert.org mem(params->mem), 1901060SN/A drainCount(0), 1915529Snate@binkert.org deferRegistration(params->deferRegistration), 1922292SN/A numThreads(number_of_threads) 1932292SN/A{ 1946221Snate@binkert.org _status = Idle; 1952292SN/A 1961060SN/A checker = NULL; 1972873Sktlim@umich.edu 1982873Sktlim@umich.edu if (params->checker) { 1992873Sktlim@umich.edu#if USE_CHECKER 2002873Sktlim@umich.edu BaseCPU *temp_checker = params->checker; 2012873Sktlim@umich.edu checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2025804Snate@binkert.org checker->setMemory(mem); 2032873Sktlim@umich.edu#if FULL_SYSTEM 2042873Sktlim@umich.edu checker->setSystem(params->system); 2051060SN/A#endif 2061060SN/A#else 2072292SN/A panic("Checker enabled but not compiled in!"); 2082843Sktlim@umich.edu#endif // USE_CHECKER 2096221Snate@binkert.org } 2101060SN/A 2113221Sktlim@umich.edu#if !FULL_SYSTEM 2123221Sktlim@umich.edu thread.resize(number_of_threads); 2133221Sktlim@umich.edu tids.resize(number_of_threads); 2143221Sktlim@umich.edu#endif 2153221Sktlim@umich.edu 2161681SN/A // The stages also need their CPU pointer setup. However this 2174598Sbinkertn@umich.edu // must be done at the upper level CPU because they have pointers 2182794Sktlim@umich.edu // to the upper level CPU, and not this FullO3CPU. 2192316SN/A 2202316SN/A // Set up Pointers to the activeThreads list for each stage 2212316SN/A fetch.setActiveThreads(&activeThreads); 2222316SN/A decode.setActiveThreads(&activeThreads); 2232316SN/A rename.setActiveThreads(&activeThreads); 2244598Sbinkertn@umich.edu iew.setActiveThreads(&activeThreads); 2254598Sbinkertn@umich.edu commit.setActiveThreads(&activeThreads); 2264598Sbinkertn@umich.edu 2272794Sktlim@umich.edu // Give each of the stages the time buffer they will use. 2282316SN/A fetch.setTimeBuffer(&timeBuffer); 2291858SN/A decode.setTimeBuffer(&timeBuffer); 2306221Snate@binkert.org rename.setTimeBuffer(&timeBuffer); 2316221Snate@binkert.org iew.setTimeBuffer(&timeBuffer); 2321681SN/A commit.setTimeBuffer(&timeBuffer); 2331681SN/A 2342325SN/A // Also setup each of the stages' queues. 2352325SN/A fetch.setFetchQueue(&fetchQueue); 2362325SN/A decode.setFetchQueue(&fetchQueue); 2371060SN/A commit.setFetchQueue(&fetchQueue); 2382292SN/A decode.setDecodeQueue(&decodeQueue); 2392292SN/A rename.setDecodeQueue(&decodeQueue); 2402292SN/A rename.setRenameQueue(&renameQueue); 2412292SN/A iew.setRenameQueue(&renameQueue); 2422292SN/A iew.setIEWQueue(&iewQueue); 2432292SN/A commit.setIEWQueue(&iewQueue); 2441060SN/A commit.setRenameQueue(&renameQueue); 2451060SN/A 2461060SN/A commit.setIEWStage(&iew); 2471060SN/A rename.setIEWStage(&iew); 2481060SN/A rename.setCommitStage(&commit); 2491060SN/A 2501060SN/A#if !FULL_SYSTEM 2511060SN/A int active_threads = params->workload.size(); 2521060SN/A 2531060SN/A if (active_threads > Impl::MaxThreads) { 2541060SN/A panic("Workload Size too large. Increase the 'MaxThreads'" 2552292SN/A "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2561060SN/A "edit your workload size."); 2571060SN/A } 2581060SN/A#else 2591060SN/A int active_threads = 1; 2601060SN/A#endif 2611060SN/A 2621060SN/A //Make Sure That this a Valid Architeture 2631060SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2642292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2652292SN/A 2662292SN/A rename.setScoreboard(&scoreboard); 2672292SN/A iew.setScoreboard(&scoreboard); 2682292SN/A 2696221Snate@binkert.org // Setup the rename map for whichever stages need it. 2702831Sksewell@umich.edu PhysRegIndex lreg_idx = 0; 2712831Sksewell@umich.edu PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2722831Sksewell@umich.edu 2732831Sksewell@umich.edu for (int tid=0; tid < numThreads; tid++) { 2742831Sksewell@umich.edu bool bindRegs = (tid <= active_threads - 1); 2752831Sksewell@umich.edu 2762292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2776221Snate@binkert.org params->numPhysIntRegs, 2782292SN/A lreg_idx, //Index for Logical. Regs 2792292SN/A 2802316SN/A TheISA::NumFloatRegs, 2812292SN/A params->numPhysFloatRegs, 2822292SN/A freg_idx, //Index for Float Regs 2832292SN/A 2842292SN/A TheISA::NumMiscRegs, 2852292SN/A 2862292SN/A TheISA::ZeroReg, 2871060SN/A TheISA::ZeroReg, 2882292SN/A 2892292SN/A tid, 2901060SN/A false); 2916221Snate@binkert.org 2922307SN/A renameMap[tid].init(TheISA::NumIntRegs, 2932292SN/A params->numPhysIntRegs, 2942292SN/A lreg_idx, //Index for Logical. Regs 2952292SN/A 2962325SN/A TheISA::NumFloatRegs, 2972292SN/A params->numPhysFloatRegs, 2982292SN/A freg_idx, //Index for Float Regs 2992292SN/A 3002325SN/A TheISA::NumMiscRegs, 3012292SN/A 3022292SN/A TheISA::ZeroReg, 3032292SN/A TheISA::ZeroReg, 3042292SN/A 3052292SN/A tid, 3062292SN/A bindRegs); 3072292SN/A } 3082292SN/A 3092292SN/A rename.setRenameMap(renameMap); 3102292SN/A commit.setRenameMap(commitRenameMap); 3112292SN/A 3122325SN/A // Give renameMap & rename stage access to the freeList; 3132292SN/A for (int i=0; i < numThreads; i++) { 3142292SN/A renameMap[i].setFreeList(&freeList); 3152292SN/A } 3162325SN/A rename.setFreeList(&freeList); 3172292SN/A 3182292SN/A // Setup the ROB for whichever stages need it. 3192292SN/A commit.setROB(&rob); 3202292SN/A 3212292SN/A lastRunningCycle = curTick; 3222292SN/A 3232292SN/A lastActivatedCycle = -1; 3242292SN/A 3253221Sktlim@umich.edu contextSwitch = false; 3263221Sktlim@umich.edu} 3273221Sktlim@umich.edu 3282292SN/Atemplate <class Impl> 3292292SN/AFullO3CPU<Impl>::~FullO3CPU() 3302292SN/A{ 3312292SN/A} 3322292SN/A 3332292SN/Atemplate <class Impl> 3346221Snate@binkert.orgvoid 3356221Snate@binkert.orgFullO3CPU<Impl>::fullCPURegStats() 3361060SN/A{ 3372292SN/A BaseO3CPU::regStats(); 3381060SN/A 3391060SN/A // Register any of the O3CPU's stats here. 3402292SN/A timesIdled 3417823Ssteve.reinhardt@amd.com .name(name() + ".timesIdled") 3422292SN/A .desc("Number of times that the entire CPU went into an idle state and" 3432829Sksewell@umich.edu " unscheduled itself") 3446221Snate@binkert.org .prereq(timesIdled); 3453093Sksewell@umich.edu 3466221Snate@binkert.org idleCycles 3476221Snate@binkert.org .name(name() + ".idleCycles") 3486221Snate@binkert.org .desc("Total number of cycles that the CPU has spent unscheduled due " 3493093Sksewell@umich.edu "to idling") 3502292SN/A .prereq(idleCycles); 3515595Sgblack@eecs.umich.edu 3525595Sgblack@eecs.umich.edu // Number of Instructions simulated 3535595Sgblack@eecs.umich.edu // -------------------------------- 3545595Sgblack@eecs.umich.edu // Should probably be in Base CPU but need templated 3555595Sgblack@eecs.umich.edu // MaxThreads so put in here instead 3566221Snate@binkert.org committedInsts 3575595Sgblack@eecs.umich.edu .init(numThreads) 3585595Sgblack@eecs.umich.edu .name(name() + ".committedInsts") 3595595Sgblack@eecs.umich.edu .desc("Number of Instructions Simulated"); 3608766Sgblack@eecs.umich.edu 3615595Sgblack@eecs.umich.edu totalCommittedInsts 3626221Snate@binkert.org .name(name() + ".committedInsts_total") 3635595Sgblack@eecs.umich.edu .desc("Number of Instructions Simulated"); 3646221Snate@binkert.org 3656221Snate@binkert.org cpi 3665595Sgblack@eecs.umich.edu .name(name() + ".cpi") 3676331Sgblack@eecs.umich.edu .desc("CPI: Cycles Per Instruction") 3685595Sgblack@eecs.umich.edu .precision(6); 3696221Snate@binkert.org cpi = simTicks / committedInsts; 3706221Snate@binkert.org 3715595Sgblack@eecs.umich.edu totalCpi 3725595Sgblack@eecs.umich.edu .name(name() + ".cpi_total") 3735595Sgblack@eecs.umich.edu .desc("CPI: Total CPI of All Threads") 3745595Sgblack@eecs.umich.edu .precision(6); 3755595Sgblack@eecs.umich.edu totalCpi = simTicks / totalCommittedInsts; 3766221Snate@binkert.org 3775595Sgblack@eecs.umich.edu ipc 3786331Sgblack@eecs.umich.edu .name(name() + ".ipc") 3796221Snate@binkert.org .desc("IPC: Instructions Per Cycle") 3805595Sgblack@eecs.umich.edu .precision(6); 3815595Sgblack@eecs.umich.edu ipc = committedInsts / simTicks; 3825595Sgblack@eecs.umich.edu 3835595Sgblack@eecs.umich.edu totalIpc 3845595Sgblack@eecs.umich.edu .name(name() + ".ipc_total") 3855595Sgblack@eecs.umich.edu .desc("IPC: Total IPC of All Threads") 3865595Sgblack@eecs.umich.edu .precision(6); 3875595Sgblack@eecs.umich.edu totalIpc = totalCommittedInsts / simTicks; 3885595Sgblack@eecs.umich.edu 3895595Sgblack@eecs.umich.edu} 3905595Sgblack@eecs.umich.edu 3915595Sgblack@eecs.umich.edutemplate <class Impl> 3925595Sgblack@eecs.umich.eduPort * 3935595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 3945595Sgblack@eecs.umich.edu{ 3955595Sgblack@eecs.umich.edu if (if_name == "dcache_port") 3965595Sgblack@eecs.umich.edu return iew.getDcachePort(); 3975595Sgblack@eecs.umich.edu else if (if_name == "icache_port") 3985595Sgblack@eecs.umich.edu return fetch.getIcachePort(); 3995595Sgblack@eecs.umich.edu else 4005595Sgblack@eecs.umich.edu panic("No Such Port\n"); 4016221Snate@binkert.org} 4025595Sgblack@eecs.umich.edu 4035595Sgblack@eecs.umich.edutemplate <class Impl> 4045595Sgblack@eecs.umich.eduvoid 4056221Snate@binkert.orgFullO3CPU<Impl>::tick() 4065595Sgblack@eecs.umich.edu{ 4075595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 4086221Snate@binkert.org 4095595Sgblack@eecs.umich.edu ++numCycles; 4105595Sgblack@eecs.umich.edu 4115595Sgblack@eecs.umich.edu// activity = false; 4125595Sgblack@eecs.umich.edu 4135595Sgblack@eecs.umich.edu //Tick each of the stages 4146221Snate@binkert.org fetch.tick(); 4156221Snate@binkert.org 4165595Sgblack@eecs.umich.edu decode.tick(); 4175595Sgblack@eecs.umich.edu 4185595Sgblack@eecs.umich.edu rename.tick(); 4191060SN/A 4201060SN/A iew.tick(); 4211060SN/A 4221755SN/A commit.tick(); 4231060SN/A 4241060SN/A#if !FULL_SYSTEM 4251060SN/A doContextSwitch(); 4261060SN/A#endif 4271060SN/A 4285595Sgblack@eecs.umich.edu // Now advance the time buffers 4291062SN/A timeBuffer.advance(); 4302733Sktlim@umich.edu 4312292SN/A fetchQueue.advance(); 4322733Sktlim@umich.edu decodeQueue.advance(); 4332292SN/A renameQueue.advance(); 4342292SN/A iewQueue.advance(); 4352292SN/A 4362292SN/A activityRec.advance(); 4372292SN/A 4382292SN/A if (removeInstsThisCycle) { 4392292SN/A cleanUpRemovedInsts(); 4402292SN/A } 4412292SN/A 4422292SN/A if (!tickEvent.scheduled()) { 4432292SN/A if (_status == SwitchedOut || 4442292SN/A getState() == SimObject::Drained) { 4452292SN/A // increment stat 4462292SN/A lastRunningCycle = curTick; 4472292SN/A } else if (!activityRec.active()) { 4482292SN/A lastRunningCycle = curTick; 4492292SN/A timesIdled++; 4502292SN/A } else { 4512292SN/A tickEvent.schedule(curTick + cycles(1)); 4522292SN/A } 4532292SN/A } 4542292SN/A 4552292SN/A#if !FULL_SYSTEM 4562292SN/A updateThreadPriority(); 4572292SN/A#endif 4582292SN/A 4592292SN/A} 4602292SN/A 4612292SN/Atemplate <class Impl> 4624392Sktlim@umich.eduvoid 4632292SN/AFullO3CPU<Impl>::init() 4642292SN/A{ 4652292SN/A if (!deferRegistration) { 4662292SN/A registerThreadContexts(); 4672292SN/A } 4684392Sktlim@umich.edu 4692292SN/A // Set inSyscall so that the CPU doesn't squash when initially 4702292SN/A // setting up registers. 4712292SN/A for (int i = 0; i < number_of_threads; ++i) 4722292SN/A thread[i]->inSyscall = true; 4732292SN/A 4744392Sktlim@umich.edu for (int tid=0; tid < number_of_threads; tid++) { 4752292SN/A#if FULL_SYSTEM 4762292SN/A ThreadContext *src_tc = threadContexts[tid]; 4772292SN/A#else 4782292SN/A ThreadContext *src_tc = thread[tid]->getTC(); 4792292SN/A#endif 4804392Sktlim@umich.edu // Threads start in the Suspended State 4812292SN/A if (src_tc->status() != ThreadContext::Suspended) { 4825595Sgblack@eecs.umich.edu continue; 4835595Sgblack@eecs.umich.edu } 4845595Sgblack@eecs.umich.edu 4855595Sgblack@eecs.umich.edu#if FULL_SYSTEM 4865595Sgblack@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->readCpuId()); 4877897Shestness@cs.utexas.edu#endif 4887897Shestness@cs.utexas.edu } 4897897Shestness@cs.utexas.edu 4907897Shestness@cs.utexas.edu // Clear inSyscall. 4917897Shestness@cs.utexas.edu for (int i = 0; i < number_of_threads; ++i) 4927897Shestness@cs.utexas.edu thread[i]->inSyscall = false; 4937897Shestness@cs.utexas.edu 4947897Shestness@cs.utexas.edu // Initialize stages. 4957897Shestness@cs.utexas.edu fetch.initStage(); 4967897Shestness@cs.utexas.edu iew.initStage(); 4977897Shestness@cs.utexas.edu rename.initStage(); 4987897Shestness@cs.utexas.edu commit.initStage(); 4997897Shestness@cs.utexas.edu 5007897Shestness@cs.utexas.edu commit.setThreads(thread); 5017897Shestness@cs.utexas.edu} 5027897Shestness@cs.utexas.edu 5037897Shestness@cs.utexas.edutemplate <class Impl> 5047897Shestness@cs.utexas.eduvoid 5057897Shestness@cs.utexas.eduFullO3CPU<Impl>::activateThread(unsigned tid) 5067897Shestness@cs.utexas.edu{ 5077897Shestness@cs.utexas.edu list<unsigned>::iterator isActive = find( 5087897Shestness@cs.utexas.edu activeThreads.begin(), activeThreads.end(), tid); 5097897Shestness@cs.utexas.edu 5107897Shestness@cs.utexas.edu if (isActive == activeThreads.end()) { 5117897Shestness@cs.utexas.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 5127897Shestness@cs.utexas.edu tid); 5137897Shestness@cs.utexas.edu 5147897Shestness@cs.utexas.edu activeThreads.push_back(tid); 5157897Shestness@cs.utexas.edu } 5167897Shestness@cs.utexas.edu} 5177897Shestness@cs.utexas.edu 5181062SN/Atemplate <class Impl> 5191062SN/Avoid 5201062SN/AFullO3CPU<Impl>::deactivateThread(unsigned tid) 5212871Sktlim@umich.edu{ 5222871Sktlim@umich.edu //Remove From Active List, if Active 5232871Sktlim@umich.edu list<unsigned>::iterator thread_it = 5242871Sktlim@umich.edu find(activeThreads.begin(), activeThreads.end(), tid); 5252871Sktlim@umich.edu 5262871Sktlim@umich.edu if (thread_it != activeThreads.end()) { 5272871Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 5282871Sktlim@umich.edu tid); 5292871Sktlim@umich.edu activeThreads.erase(thread_it); 5302871Sktlim@umich.edu } 5312871Sktlim@umich.edu} 5322871Sktlim@umich.edu 5331062SN/Atemplate <class Impl> 5341755SN/Avoid 5351060SN/AFullO3CPU<Impl>::activateContext(int tid, int delay) 5362733Sktlim@umich.edu{ 5371060SN/A // Needs to set each stage to running as well. 5382292SN/A if (delay){ 5392292SN/A DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 5402325SN/A "on cycle %d\n", tid, curTick + cycles(delay)); 5412292SN/A scheduleActivateThreadEvent(tid, delay); 5422292SN/A } else { 5431060SN/A activateThread(tid); 5441060SN/A } 5451060SN/A 5461060SN/A if(lastActivatedCycle < curTick) { 5471060SN/A scheduleTickEvent(delay); 5481060SN/A 5491060SN/A // Be sure to signal that there's some activity so the CPU doesn't 5501060SN/A // deschedule itself. 5511060SN/A activityRec.activity(); 5521060SN/A fetch.wakeFromQuiesce(); 5532292SN/A 5542292SN/A lastActivatedCycle = curTick; 5552292SN/A 5562292SN/A _status = Running; 5572292SN/A } 5581060SN/A} 5591060SN/A 5601060SN/Atemplate <class Impl> 5611060SN/Avoid 5621060SN/AFullO3CPU<Impl>::deallocateContext(int tid, int delay) 5631060SN/A{ 5641060SN/A // Schedule removal of thread data from CPU 5652325SN/A if (delay){ 5662292SN/A DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 5672292SN/A "on cycle %d\n", tid, curTick + cycles(delay)); 5682292SN/A scheduleDeallocateContextEvent(tid, delay); 5692292SN/A } else { 5702292SN/A deactivateThread(tid); 5712325SN/A removeThread(tid); 5722867Sktlim@umich.edu } 5732905Sktlim@umich.edu} 5743226Sktlim@umich.edu 5752325SN/Atemplate <class Impl> 5767823Ssteve.reinhardt@amd.comvoid 5773221Sktlim@umich.eduFullO3CPU<Impl>::suspendContext(int tid) 5783226Sktlim@umich.edu{ 5797823Ssteve.reinhardt@amd.com DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 5802325SN/A deactivateThread(tid); 5812325SN/A if (activeThreads.size() == 0) 5827823Ssteve.reinhardt@amd.com unscheduleTickEvent(); 5833226Sktlim@umich.edu _status = Idle; 5842325SN/A} 5852292SN/A 5862292SN/Atemplate <class Impl> 5872292SN/Avoid 5882292SN/AFullO3CPU<Impl>::haltContext(int tid) 5892292SN/A{ 5901060SN/A //For now, this is the same as deallocate 5911060SN/A DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 5921060SN/A deallocateContext(tid, 1); 5931060SN/A} 5941755SN/A 5951060SN/Atemplate <class Impl> 5965714Shsul@eecs.umich.eduvoid 5971060SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 5982292SN/A{ 5992292SN/A DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 6006221Snate@binkert.org // Will change now that the PC and thread state is internal to the CPU 6016221Snate@binkert.org // and not in the ThreadContext. 6022292SN/A#if FULL_SYSTEM 6036034Ssteve.reinhardt@amd.com ThreadContext *src_tc = system->threadContexts[tid]; 6046221Snate@binkert.org#else 6052680Sktlim@umich.edu ThreadContext *src_tc = tcBase(tid); 6066034Ssteve.reinhardt@amd.com#endif 6076034Ssteve.reinhardt@amd.com 6081681SN/A //Bind Int Regs to Rename Map 6092292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 6102292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 6116221Snate@binkert.org 6126221Snate@binkert.org renameMap[tid].setEntry(ireg,phys_reg); 6132292SN/A scoreboard.setReg(phys_reg); 6142316SN/A } 6152292SN/A 6162292SN/A //Bind Float Regs to Rename Map 6172292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 6182292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 6192292SN/A 6202292SN/A renameMap[tid].setEntry(freg,phys_reg); 6212292SN/A scoreboard.setReg(phys_reg); 6222292SN/A } 6232292SN/A 6242292SN/A //Copy Thread Data Into RegFile 6256221Snate@binkert.org //this->copyFromTC(tid); 6262875Sksewell@umich.edu 6276221Snate@binkert.org //Set PC/NPC/NNPC 6285314Sstever@gmail.com setPC(src_tc->readPC(), tid); 6292875Sksewell@umich.edu setNextPC(src_tc->readNextPC(), tid); 6303226Sktlim@umich.edu#if THE_ISA != ALPHA_ISA 6313226Sktlim@umich.edu setNextNPC(src_tc->readNextNPC(), tid); 6322875Sksewell@umich.edu#endif 6332875Sksewell@umich.edu 6342875Sksewell@umich.edu src_tc->setStatus(ThreadContext::Active); 6352875Sksewell@umich.edu 6362875Sksewell@umich.edu activateContext(tid,1); 6372875Sksewell@umich.edu 6382875Sksewell@umich.edu //Reset ROB/IQ/LSQ Entries 6392875Sksewell@umich.edu commit.rob->resetEntries(); 6402875Sksewell@umich.edu iew.resetEntries(); 6412875Sksewell@umich.edu} 6426221Snate@binkert.org 6432875Sksewell@umich.edutemplate <class Impl> 6442875Sksewell@umich.eduvoid 6456221Snate@binkert.orgFullO3CPU<Impl>::removeThread(unsigned tid) 6465314Sstever@gmail.com{ 6472875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 6483226Sktlim@umich.edu 6493226Sktlim@umich.edu // Copy Thread Data From RegFile 6502875Sksewell@umich.edu // If thread is suspended, it might be re-allocated 6512875Sksewell@umich.edu //this->copyToTC(tid); 6522875Sksewell@umich.edu 6532875Sksewell@umich.edu // Unbind Int Regs from Rename Map 6542875Sksewell@umich.edu for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 6552875Sksewell@umich.edu PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 6562875Sksewell@umich.edu 6572875Sksewell@umich.edu scoreboard.unsetReg(phys_reg); 6586221Snate@binkert.org freeList.addReg(phys_reg); 6596221Snate@binkert.org } 6606221Snate@binkert.org 6616221Snate@binkert.org // Unbind Float Regs from Rename Map 6626221Snate@binkert.org for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 6636221Snate@binkert.org PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 6646221Snate@binkert.org 6656221Snate@binkert.org scoreboard.unsetReg(phys_reg); 6666221Snate@binkert.org freeList.addReg(phys_reg); 6676221Snate@binkert.org } 6686221Snate@binkert.org 6696221Snate@binkert.org // Squash Throughout Pipeline 6706221Snate@binkert.org fetch.squash(0,tid); 6712875Sksewell@umich.edu decode.squash(tid); 6726221Snate@binkert.org rename.squash(tid); 6732875Sksewell@umich.edu iew.squash(tid); 6742875Sksewell@umich.edu commit.rob->squash(commit.rob->readHeadInst(tid)->seqNum, tid); 6752875Sksewell@umich.edu 6762875Sksewell@umich.edu assert(iew.ldstQueue.getCount(tid) == 0); 6777823Ssteve.reinhardt@amd.com 6782875Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 6792875Sksewell@umich.edu if (activeThreads.size() >= 1) { 6802875Sksewell@umich.edu commit.rob->resetEntries(); 6812875Sksewell@umich.edu iew.resetEntries(); 6822875Sksewell@umich.edu } 6837823Ssteve.reinhardt@amd.com} 6842875Sksewell@umich.edu 6852875Sksewell@umich.edu 6862875Sksewell@umich.edutemplate <class Impl> 6872875Sksewell@umich.eduvoid 6882875Sksewell@umich.eduFullO3CPU<Impl>::activateWhenReady(int tid) 6892875Sksewell@umich.edu{ 6902875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 6917823Ssteve.reinhardt@amd.com "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 6922875Sksewell@umich.edu tid); 6932875Sksewell@umich.edu 6942875Sksewell@umich.edu bool ready = true; 6952875Sksewell@umich.edu 6962875Sksewell@umich.edu if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 6972875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 6983221Sktlim@umich.edu "Phys. Int. Regs.\n", 6996221Snate@binkert.org tid); 7002875Sksewell@umich.edu ready = false; 7012875Sksewell@umich.edu } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 7022875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7032875Sksewell@umich.edu "Phys. Float. Regs.\n", 7047823Ssteve.reinhardt@amd.com tid); 7053221Sktlim@umich.edu ready = false; 7063221Sktlim@umich.edu } else if (commit.rob->numFreeEntries() >= 7072875Sksewell@umich.edu commit.rob->entryAmount(activeThreads.size() + 1)) { 7082875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7093221Sktlim@umich.edu "ROB entries.\n", 7103221Sktlim@umich.edu tid); 7113221Sktlim@umich.edu ready = false; 7122875Sksewell@umich.edu } else if (iew.instQueue.numFreeEntries() >= 7132875Sksewell@umich.edu iew.instQueue.entryAmount(activeThreads.size() + 1)) { 7142875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7152875Sksewell@umich.edu "IQ entries.\n", 7162875Sksewell@umich.edu tid); 7176221Snate@binkert.org ready = false; 7182875Sksewell@umich.edu } else if (iew.ldstQueue.numFreeEntries() >= 7192875Sksewell@umich.edu iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 7203221Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7213221Sktlim@umich.edu "LSQ entries.\n", 7225570Snate@binkert.org tid); 7233859Sbinkertn@umich.edu ready = false; 7242910Sksewell@umich.edu } 7252875Sksewell@umich.edu 7262875Sksewell@umich.edu if (ready) { 7272875Sksewell@umich.edu insertThread(tid); 7282875Sksewell@umich.edu 7292875Sksewell@umich.edu contextSwitch = false; 7306221Snate@binkert.org 7312875Sksewell@umich.edu cpuWaitList.remove(tid); 7322910Sksewell@umich.edu } else { 7332910Sksewell@umich.edu suspendContext(tid); 7343221Sktlim@umich.edu 7352875Sksewell@umich.edu //blocks fetch 7362875Sksewell@umich.edu contextSwitch = true; 7372875Sksewell@umich.edu 7382875Sksewell@umich.edu //@todo: dont always add to waitlist 7396221Snate@binkert.org //do waitlist 7402292SN/A cpuWaitList.push_back(tid); 7412847Sksewell@umich.edu } 7422292SN/A} 7432683Sktlim@umich.edu 7442292SN/Atemplate <class Impl> 7452680Sktlim@umich.eduvoid 7462292SN/AFullO3CPU<Impl>::serialize(std::ostream &os) 7472847Sksewell@umich.edu{ 7482292SN/A SERIALIZE_ENUM(_status); 7492292SN/A BaseCPU::serialize(os); 7502292SN/A nameOut(os, csprintf("%s.tickEvent", name())); 7512292SN/A tickEvent.serialize(os); 7522292SN/A 7532292SN/A // Use SimpleThread's ability to checkpoint to make it easier to 7542292SN/A // write out the registers. Also make this static so it doesn't 7552292SN/A // get instantiated multiple times (causes a panic in statistics). 7562292SN/A static SimpleThread temp; 7572292SN/A 7582292SN/A for (int i = 0; i < thread.size(); i++) { 7592292SN/A nameOut(os, csprintf("%s.xc.%i", name(), i)); 7602292SN/A temp.copyTC(thread[i]->getTC()); 7612292SN/A temp.serialize(os); 7622292SN/A } 7632292SN/A} 7642292SN/A 7652292SN/Atemplate <class Impl> 7662292SN/Avoid 7672847Sksewell@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 7682292SN/A{ 7692847Sksewell@umich.edu UNSERIALIZE_ENUM(_status); 7707720Sgblack@eecs.umich.edu BaseCPU::unserialize(cp, section); 7712292SN/A tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 7722680Sktlim@umich.edu 7732292SN/A // Use SimpleThread's ability to checkpoint to make it easier to 7742292SN/A // read in the registers. Also make this static so it doesn't 7752292SN/A // get instantiated multiple times (causes a panic in statistics). 7762292SN/A static SimpleThread temp; 7772292SN/A 7782292SN/A for (int i = 0; i < thread.size(); i++) { 7792292SN/A temp.copyTC(thread[i]->getTC()); 7802292SN/A temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 7812292SN/A thread[i]->getTC()->copyArchRegs(temp.getTC()); 7822292SN/A } 7836221Snate@binkert.org} 7842292SN/A 7852877Sksewell@umich.edutemplate <class Impl> 7862847Sksewell@umich.eduunsigned int 7872847Sksewell@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 7882847Sksewell@umich.edu{ 7895364Sksewell@umich.edu drainCount = 0; 7905364Sksewell@umich.edu fetch.drain(); 7915364Sksewell@umich.edu decode.drain(); 7925364Sksewell@umich.edu rename.drain(); 7935364Sksewell@umich.edu iew.drain(); 7945364Sksewell@umich.edu commit.drain(); 7952847Sksewell@umich.edu 7962847Sksewell@umich.edu // Wake the CPU and record activity so everything can drain out if 7972292SN/A // the CPU was not able to immediately drain. 7982292SN/A if (getState() != SimObject::Drained) { 7992292SN/A // A bit of a hack...set the drainEvent after all the drain() 8002292SN/A // calls have been made, that way if all of the stages drain 8012292SN/A // immediately, the signalDrained() function knows not to call 8022292SN/A // process on the drain event. 8032292SN/A drainEvent = drain_event; 8042847Sksewell@umich.edu 8055362Sksewell@umich.edu wakeCPU(); 8062292SN/A activityRec.activity(); 8072292SN/A 8082292SN/A return 1; 8092292SN/A } else { 8102292SN/A return 0; 8112292SN/A } 8122847Sksewell@umich.edu} 8138138SAli.Saidi@ARM.com 8148138SAli.Saidi@ARM.comtemplate <class Impl> 8158138SAli.Saidi@ARM.comvoid 8162292SN/AFullO3CPU<Impl>::resume() 8172935Sksewell@umich.edu{ 8182875Sksewell@umich.edu assert(system->getMemoryMode() == System::Timing); 8195363Sksewell@umich.edu fetch.resume(); 8202935Sksewell@umich.edu decode.resume(); 8212292SN/A rename.resume(); 8225362Sksewell@umich.edu iew.resume(); 8235362Sksewell@umich.edu commit.resume(); 8242292SN/A 8252292SN/A changeState(SimObject::Running); 8262847Sksewell@umich.edu 8273229Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 8283229Sktlim@umich.edu return; 8293229Sktlim@umich.edu 8303229Sktlim@umich.edu if (!tickEvent.scheduled()) 8313229Sktlim@umich.edu tickEvent.schedule(curTick); 8323229Sktlim@umich.edu _status = Running; 8332292SN/A} 8342292SN/A 8352292SN/Atemplate <class Impl> 8362292SN/Avoid 8373229Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 8382292SN/A{ 8392292SN/A if (++drainCount == NumStages) { 8402292SN/A if (tickEvent.scheduled()) 8412292SN/A tickEvent.squash(); 8422292SN/A 8436221Snate@binkert.org changeState(SimObject::Drained); 8442292SN/A 8452733Sktlim@umich.edu if (drainEvent) { 8462292SN/A drainEvent->process(); 8472292SN/A drainEvent = NULL; 8482292SN/A } 8492292SN/A } 8502292SN/A assert(drainCount <= 5); 8512292SN/A} 8522733Sktlim@umich.edu 8532292SN/Atemplate <class Impl> 8542292SN/Avoid 8552292SN/AFullO3CPU<Impl>::switchOut() 8562292SN/A{ 8572733Sktlim@umich.edu fetch.switchOut(); 8582292SN/A rename.switchOut(); 8592292SN/A commit.switchOut(); 8602292SN/A instList.clear(); 8612292SN/A while (!removeList.empty()) { 8622292SN/A removeList.pop(); 8632733Sktlim@umich.edu } 8642292SN/A 8652292SN/A _status = SwitchedOut; 8662292SN/A#if USE_CHECKER 8672292SN/A if (checker) 8682292SN/A checker->switchOut(); 8692733Sktlim@umich.edu#endif 8702292SN/A} 8712292SN/A 8722292SN/Atemplate <class Impl> 8732292SN/Avoid 8742292SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 8752733Sktlim@umich.edu{ 8762292SN/A // Flush out any old data from the time buffers. 8772292SN/A for (int i = 0; i < timeBuffer.getSize(); ++i) { 8782292SN/A timeBuffer.advance(); 8792292SN/A fetchQueue.advance(); 8802292SN/A decodeQueue.advance(); 8812292SN/A renameQueue.advance(); 8822292SN/A iewQueue.advance(); 8832292SN/A } 8842292SN/A 8852292SN/A activityRec.reset(); 8862292SN/A 8872292SN/A BaseCPU::takeOverFrom(oldCPU); 8882292SN/A 8892292SN/A fetch.takeOverFrom(); 8902292SN/A decode.takeOverFrom(); 8912292SN/A rename.takeOverFrom(); 8922292SN/A iew.takeOverFrom(); 8932875Sksewell@umich.edu commit.takeOverFrom(); 8942292SN/A 8952292SN/A assert(!tickEvent.scheduled()); 8961060SN/A 8971060SN/A // @todo: Figure out how to properly select the tid to put onto 8981060SN/A // the active threads list. 8994192Sktlim@umich.edu int tid = 0; 9004192Sktlim@umich.edu 9015595Sgblack@eecs.umich.edu list<unsigned>::iterator isActive = find( 9026221Snate@binkert.org activeThreads.begin(), activeThreads.end(), tid); 9035702Ssaidi@eecs.umich.edu 9045702Ssaidi@eecs.umich.edu if (isActive == activeThreads.end()) { 9055702Ssaidi@eecs.umich.edu //May Need to Re-code this if the delay variable is the delay 9065702Ssaidi@eecs.umich.edu //needed for thread to activate 9075702Ssaidi@eecs.umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 9085702Ssaidi@eecs.umich.edu tid); 9095702Ssaidi@eecs.umich.edu 9105702Ssaidi@eecs.umich.edu activeThreads.push_back(tid); 9115702Ssaidi@eecs.umich.edu } 9125702Ssaidi@eecs.umich.edu 9135702Ssaidi@eecs.umich.edu // Set all statuses to active, schedule the CPU's tick event. 9145702Ssaidi@eecs.umich.edu // @todo: Fix up statuses so this is handled properly 9155702Ssaidi@eecs.umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 9165702Ssaidi@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 9176221Snate@binkert.org if (tc->status() == ThreadContext::Active && _status != Running) { 9185702Ssaidi@eecs.umich.edu _status = Running; 9195702Ssaidi@eecs.umich.edu tickEvent.schedule(curTick); 9205702Ssaidi@eecs.umich.edu } 9215702Ssaidi@eecs.umich.edu } 9225702Ssaidi@eecs.umich.edu if (!tickEvent.scheduled()) 9235702Ssaidi@eecs.umich.edu tickEvent.schedule(curTick); 9245702Ssaidi@eecs.umich.edu} 9255702Ssaidi@eecs.umich.edu 9265702Ssaidi@eecs.umich.edutemplate <class Impl> 9275702Ssaidi@eecs.umich.eduuint64_t 9285702Ssaidi@eecs.umich.eduFullO3CPU<Impl>::readIntReg(int reg_idx) 9295702Ssaidi@eecs.umich.edu{ 9305702Ssaidi@eecs.umich.edu return regFile.readIntReg(reg_idx); 9315702Ssaidi@eecs.umich.edu} 9325702Ssaidi@eecs.umich.edu 9335702Ssaidi@eecs.umich.edutemplate <class Impl> 9345702Ssaidi@eecs.umich.eduFloatReg 9355702Ssaidi@eecs.umich.eduFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 9365702Ssaidi@eecs.umich.edu{ 9375702Ssaidi@eecs.umich.edu return regFile.readFloatReg(reg_idx, width); 9385702Ssaidi@eecs.umich.edu} 9395702Ssaidi@eecs.umich.edu 9405702Ssaidi@eecs.umich.edutemplate <class Impl> 9415702Ssaidi@eecs.umich.eduFloatReg 9425702Ssaidi@eecs.umich.eduFullO3CPU<Impl>::readFloatReg(int reg_idx) 9435595Sgblack@eecs.umich.edu{ 9445595Sgblack@eecs.umich.edu return regFile.readFloatReg(reg_idx); 9455595Sgblack@eecs.umich.edu} 9465647Sgblack@eecs.umich.edu 9475595Sgblack@eecs.umich.edutemplate <class Impl> 9485595Sgblack@eecs.umich.eduFloatRegBits 9495595Sgblack@eecs.umich.eduFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 9505595Sgblack@eecs.umich.edu{ 9515595Sgblack@eecs.umich.edu return regFile.readFloatRegBits(reg_idx, width); 9525595Sgblack@eecs.umich.edu} 9535595Sgblack@eecs.umich.edu 9545595Sgblack@eecs.umich.edutemplate <class Impl> 9555595Sgblack@eecs.umich.eduFloatRegBits 9565595Sgblack@eecs.umich.eduFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 9575595Sgblack@eecs.umich.edu{ 9585595Sgblack@eecs.umich.edu return regFile.readFloatRegBits(reg_idx); 9595595Sgblack@eecs.umich.edu} 9605647Sgblack@eecs.umich.edu 9615595Sgblack@eecs.umich.edutemplate <class Impl> 9625595Sgblack@eecs.umich.eduvoid 9637684Sgblack@eecs.umich.eduFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 9645595Sgblack@eecs.umich.edu{ 9655595Sgblack@eecs.umich.edu regFile.setIntReg(reg_idx, val); 9665595Sgblack@eecs.umich.edu} 9675595Sgblack@eecs.umich.edu 9684192Sktlim@umich.edutemplate <class Impl> 9694192Sktlim@umich.eduvoid 9704192Sktlim@umich.eduFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 9714192Sktlim@umich.edu{ 9726221Snate@binkert.org regFile.setFloatReg(reg_idx, val, width); 9736221Snate@binkert.org} 9745497Ssaidi@eecs.umich.edu 9754192Sktlim@umich.edutemplate <class Impl> 9764192Sktlim@umich.eduvoid 9774192Sktlim@umich.eduFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 9781060SN/A{ 9792852Sktlim@umich.edu regFile.setFloatReg(reg_idx, val); 9807684Sgblack@eecs.umich.edu} 9815595Sgblack@eecs.umich.edu 9825595Sgblack@eecs.umich.edutemplate <class Impl> 9837684Sgblack@eecs.umich.eduvoid 9845595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 9855595Sgblack@eecs.umich.edu{ 9865595Sgblack@eecs.umich.edu regFile.setFloatRegBits(reg_idx, val, width); 9875595Sgblack@eecs.umich.edu} 9885595Sgblack@eecs.umich.edu 9895595Sgblack@eecs.umich.edutemplate <class Impl> 9906221Snate@binkert.orgvoid 9915595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 9925595Sgblack@eecs.umich.edu{ 9935595Sgblack@eecs.umich.edu regFile.setFloatRegBits(reg_idx, val); 9945595Sgblack@eecs.umich.edu} 9955595Sgblack@eecs.umich.edu 9965595Sgblack@eecs.umich.edutemplate <class Impl> 9975595Sgblack@eecs.umich.eduuint64_t 9985595Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 9995595Sgblack@eecs.umich.edu{ 10005595Sgblack@eecs.umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10015595Sgblack@eecs.umich.edu 10025595Sgblack@eecs.umich.edu return regFile.readIntReg(phys_reg); 10035595Sgblack@eecs.umich.edu} 10045595Sgblack@eecs.umich.edu 10055595Sgblack@eecs.umich.edutemplate <class Impl> 10065595Sgblack@eecs.umich.edufloat 10075595Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 10085595Sgblack@eecs.umich.edu{ 10095595Sgblack@eecs.umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 10105595Sgblack@eecs.umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10115595Sgblack@eecs.umich.edu 10122864Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 10132864Sktlim@umich.edu} 10142918Sktlim@umich.edu 10152918Sktlim@umich.edutemplate <class Impl> 10162864Sktlim@umich.edudouble 10172864Sktlim@umich.eduFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 10182864Sktlim@umich.edu{ 10192864Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 10202864Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10212864Sktlim@umich.edu 10222864Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 10232864Sktlim@umich.edu} 10242864Sktlim@umich.edu 10256221Snate@binkert.orgtemplate <class Impl> 10266221Snate@binkert.orguint64_t 10272864Sktlim@umich.eduFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 10282864Sktlim@umich.edu{ 10292864Sktlim@umich.edu int idx = reg_idx + TheISA::FP_Base_DepTag; 10302864Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10312864Sktlim@umich.edu 10322864Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 10332864Sktlim@umich.edu} 10342864Sktlim@umich.edu 10352864Sktlim@umich.edutemplate <class Impl> 10362864Sktlim@umich.eduvoid 10372918Sktlim@umich.eduFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 10382918Sktlim@umich.edu{ 10392864Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10402864Sktlim@umich.edu 10412864Sktlim@umich.edu regFile.setIntReg(phys_reg, val); 10422864Sktlim@umich.edu} 10432864Sktlim@umich.edu 10442864Sktlim@umich.edutemplate <class Impl> 10452864Sktlim@umich.eduvoid 10462864Sktlim@umich.eduFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 10476221Snate@binkert.org{ 10486221Snate@binkert.org PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10492864Sktlim@umich.edu 10502864Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 10512864Sktlim@umich.edu} 10522864Sktlim@umich.edu 10532864Sktlim@umich.edutemplate <class Impl> 10542864Sktlim@umich.eduvoid 10552864Sktlim@umich.eduFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 10562905Sktlim@umich.edu{ 10572843Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10581060SN/A 10593125Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 10603512Sktlim@umich.edu} 10613512Sktlim@umich.edu 10623512Sktlim@umich.edutemplate <class Impl> 10633512Sktlim@umich.eduvoid 10643512Sktlim@umich.eduFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 10653512Sktlim@umich.edu{ 10662843Sktlim@umich.edu PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10672843Sktlim@umich.edu 10682843Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 10692843Sktlim@umich.edu} 10702843Sktlim@umich.edu 10712843Sktlim@umich.edutemplate <class Impl> 10722325SN/Auint64_t 10732325SN/AFullO3CPU<Impl>::readPC(unsigned tid) 10742863Sktlim@umich.edu{ 10752905Sktlim@umich.edu return commit.readPC(tid); 10762864Sktlim@umich.edu} 10772864Sktlim@umich.edu 10782864Sktlim@umich.edutemplate <class Impl> 10792864Sktlim@umich.eduvoid 10802864Sktlim@umich.eduFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 10812843Sktlim@umich.edu{ 10822863Sktlim@umich.edu commit.setPC(new_PC, tid); 10832863Sktlim@umich.edu} 10842852Sktlim@umich.edu 10852905Sktlim@umich.edutemplate <class Impl> 10862863Sktlim@umich.eduuint64_t 10872905Sktlim@umich.eduFullO3CPU<Impl>::readNextPC(unsigned tid) 10882863Sktlim@umich.edu{ 10892316SN/A return commit.readNextPC(tid); 10902310SN/A} 10912316SN/A 10922316SN/Atemplate <class Impl> 10932843Sktlim@umich.eduvoid 10942316SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 10952843Sktlim@umich.edu{ 10962843Sktlim@umich.edu commit.setNextPC(val, tid); 10972843Sktlim@umich.edu} 10982843Sktlim@umich.edu 10992843Sktlim@umich.edu#if THE_ISA != ALPHA_ISA 11002316SN/Atemplate <class Impl> 11012905Sktlim@umich.eduuint64_t 11022905Sktlim@umich.eduFullO3CPU<Impl>::readNextNPC(unsigned tid) 11032864Sktlim@umich.edu{ 11042864Sktlim@umich.edu return commit.readNextNPC(tid); 11052864Sktlim@umich.edu} 11064762Snate@binkert.org 11073319Shsul@eecs.umich.edutemplate <class Impl> 11082843Sktlim@umich.eduvoid 11095606Snate@binkert.orgFullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid) 11102843Sktlim@umich.edu{ 11112843Sktlim@umich.edu commit.setNextNPC(val, tid); 11122316SN/A} 11132843Sktlim@umich.edu#endif 11142843Sktlim@umich.edu 11152843Sktlim@umich.edutemplate <class Impl> 11162843Sktlim@umich.edutypename FullO3CPU<Impl>::ListIt 11172843Sktlim@umich.eduFullO3CPU<Impl>::addInst(DynInstPtr &inst) 11182316SN/A{ 11192316SN/A instList.push_back(inst); 11202863Sktlim@umich.edu 11212905Sktlim@umich.edu return --(instList.end()); 11222863Sktlim@umich.edu} 11233126Sktlim@umich.edu 11243126Sktlim@umich.edutemplate <class Impl> 11252863Sktlim@umich.eduvoid 11262863Sktlim@umich.eduFullO3CPU<Impl>::instDone(unsigned tid) 11272863Sktlim@umich.edu{ 11282863Sktlim@umich.edu // Keep an instruction count. 11292310SN/A thread[tid]->numInst++; 11302843Sktlim@umich.edu thread[tid]->numInsts++; 11312843Sktlim@umich.edu committedInsts[tid]++; 11322843Sktlim@umich.edu totalCommittedInsts++; 11332843Sktlim@umich.edu 11342843Sktlim@umich.edu // Check for instruction-count-based events. 11352843Sktlim@umich.edu comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 11362843Sktlim@umich.edu} 11372843Sktlim@umich.edu 11382843Sktlim@umich.edutemplate <class Impl> 11392325SN/Avoid 11402843Sktlim@umich.eduFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 11412843Sktlim@umich.edu{ 11422843Sktlim@umich.edu removeInstsThisCycle = true; 11432843Sktlim@umich.edu 11442843Sktlim@umich.edu removeList.push(inst->getInstListIt()); 11452843Sktlim@umich.edu} 11462843Sktlim@umich.edu 11472843Sktlim@umich.edutemplate <class Impl> 11482843Sktlim@umich.eduvoid 11492843Sktlim@umich.eduFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 11502843Sktlim@umich.edu{ 11513126Sktlim@umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 11523126Sktlim@umich.edu "[sn:%lli]\n", 11531060SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 11541060SN/A 11551060SN/A removeInstsThisCycle = true; 11561060SN/A 11571755SN/A // Remove the front instruction. 11581060SN/A removeList.push(inst->getInstListIt()); 11592325SN/A} 11602873Sktlim@umich.edu 11612307SN/Atemplate <class Impl> 11622307SN/Avoid 11632307SN/AFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 11642307SN/A{ 11652307SN/A DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 11662307SN/A " list.\n", tid); 11672307SN/A 11682325SN/A ListIt end_it; 11692307SN/A 11704192Sktlim@umich.edu bool rob_empty = false; 11711060SN/A 11722307SN/A if (instList.empty()) { 11732307SN/A return; 11742307SN/A } else if (rob.isEmpty(/*tid*/)) { 11752307SN/A DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 11762307SN/A end_it = instList.begin(); 11772307SN/A rob_empty = true; 11787507Stjones1@inf.ed.ac.uk } else { 11791060SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 11802325SN/A DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 11812325SN/A } 11826221Snate@binkert.org 11832307SN/A removeInstsThisCycle = true; 11846221Snate@binkert.org 11855314Sstever@gmail.com ListIt inst_it = instList.end(); 11862307SN/A 11872307SN/A inst_it--; 11882325SN/A 11892325SN/A // Walk through the instruction list, removing any instructions 11902733Sktlim@umich.edu // that were inserted after the given instruction iterator, end_it. 11912307SN/A while (inst_it != end_it) { 11922307SN/A assert(!instList.empty()); 11932307SN/A 11942307SN/A squashInstIt(inst_it, tid); 11952307SN/A 11962325SN/A inst_it--; 11972307SN/A } 11986221Snate@binkert.org 11996221Snate@binkert.org // If the ROB was empty, then we actually need to remove the first 12002680Sktlim@umich.edu // instruction as well. 12012680Sktlim@umich.edu if (rob_empty) { 12021681SN/A squashInstIt(inst_it, tid); 12037507Stjones1@inf.ed.ac.uk } 12041681SN/A} 12051060SN/A 12062307SN/Atemplate <class Impl> 12075606Snate@binkert.orgvoid 12081060SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 12091060SN/A unsigned tid) 12101060SN/A{ 12115595Sgblack@eecs.umich.edu assert(!instList.empty()); 12126221Snate@binkert.org 12135595Sgblack@eecs.umich.edu removeInstsThisCycle = true; 12146313Sgblack@eecs.umich.edu 12155595Sgblack@eecs.umich.edu ListIt inst_iter = instList.end(); 12165595Sgblack@eecs.umich.edu 12175595Sgblack@eecs.umich.edu inst_iter--; 12185595Sgblack@eecs.umich.edu 12196221Snate@binkert.org DPRINTF(O3CPU, "Deleting instructions from instruction " 12205595Sgblack@eecs.umich.edu "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 12217897Shestness@cs.utexas.edu tid, seq_num, (*inst_iter)->seqNum); 12226313Sgblack@eecs.umich.edu 12235595Sgblack@eecs.umich.edu while ((*inst_iter)->seqNum > seq_num) { 12245595Sgblack@eecs.umich.edu 12255595Sgblack@eecs.umich.edu bool break_loop = (inst_iter == instList.begin()); 12265595Sgblack@eecs.umich.edu 12275595Sgblack@eecs.umich.edu squashInstIt(inst_iter, tid); 12286221Snate@binkert.org 12295595Sgblack@eecs.umich.edu inst_iter--; 12306313Sgblack@eecs.umich.edu 12315595Sgblack@eecs.umich.edu if (break_loop) 12325595Sgblack@eecs.umich.edu break; 12335595Sgblack@eecs.umich.edu } 12345595Sgblack@eecs.umich.edu} 12355595Sgblack@eecs.umich.edu 12366221Snate@binkert.orgtemplate <class Impl> 12375595Sgblack@eecs.umich.eduinline void 12387897Shestness@cs.utexas.eduFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 12396313Sgblack@eecs.umich.edu{ 12405595Sgblack@eecs.umich.edu if ((*instIt)->threadNumber == tid) { 12415595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Squashing instruction, " 12425595Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %#x\n", 12431060SN/A (*instIt)->threadNumber, 12441755SN/A (*instIt)->seqNum, 12451060SN/A (*instIt)->readPC()); 12467897Shestness@cs.utexas.edu 12471060SN/A // Mark it as squashed. 12481060SN/A (*instIt)->setSquashed(); 12491060SN/A 12501060SN/A // @todo: Formulate a consistent method for deleting 12512455SN/A // instructions from the instruction list 12522455SN/A // Remove the instruction from the list. 12531060SN/A removeList.push(instIt); 12547897Shestness@cs.utexas.edu } 12552455SN/A} 12561060SN/A 12571060SN/Atemplate <class Impl> 12581060SN/Avoid 12592455SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 12602455SN/A{ 12612455SN/A while (!removeList.empty()) { 12627897Shestness@cs.utexas.edu DPRINTF(O3CPU, "Removing instruction, " 12632455SN/A "[tid:%i] [sn:%lli] PC %#x\n", 12641060SN/A (*removeList.front())->threadNumber, 12651060SN/A (*removeList.front())->seqNum, 12661060SN/A (*removeList.front())->readPC()); 12671060SN/A 12681755SN/A instList.erase(removeList.front()); 12691060SN/A 12707897Shestness@cs.utexas.edu removeList.pop(); 12711060SN/A } 12721060SN/A 12731060SN/A removeInstsThisCycle = false; 12741060SN/A} 12751060SN/A/* 12762455SN/Atemplate <class Impl> 12771060SN/Avoid 12787897Shestness@cs.utexas.eduFullO3CPU<Impl>::removeAllInsts() 12792455SN/A{ 12801060SN/A instList.clear(); 12811060SN/A} 12821060SN/A*/ 12831060SN/Atemplate <class Impl> 12842455SN/Avoid 12852455SN/AFullO3CPU<Impl>::dumpInsts() 12867897Shestness@cs.utexas.edu{ 12872455SN/A int num = 0; 12881060SN/A 12891060SN/A ListIt inst_list_it = instList.begin(); 12901060SN/A 12911060SN/A cprintf("Dumping Instruction List\n"); 12926221Snate@binkert.org 12931060SN/A while (inst_list_it != instList.end()) { 12947897Shestness@cs.utexas.edu cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 12952292SN/A "Squashed:%i\n\n", 12962292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 12972292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 12982292SN/A (*inst_list_it)->isSquashed()); 12992292SN/A inst_list_it++; 13002292SN/A ++num; 13012292SN/A } 13026314Sgblack@eecs.umich.edu} 13032292SN/A/* 13047897Shestness@cs.utexas.edutemplate <class Impl> 13056032Ssteve.reinhardt@amd.comvoid 13062307SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 13072292SN/A{ 13082669Sktlim@umich.edu iew.wakeDependents(inst); 13092292SN/A} 13102292SN/A*/ 13112292SN/Atemplate <class Impl> 13122292SN/Avoid 13136221Snate@binkert.orgFullO3CPU<Impl>::wakeCPU() 13142292SN/A{ 13157897Shestness@cs.utexas.edu if (activityRec.active() || tickEvent.scheduled()) { 13166032Ssteve.reinhardt@amd.com DPRINTF(Activity, "CPU already running.\n"); 13172307SN/A return; 13182292SN/A } 13192669Sktlim@umich.edu 13201060SN/A DPRINTF(Activity, "Waking up CPU\n"); 13211060SN/A 13221060SN/A idleCycles += (curTick - 1) - lastRunningCycle; 13231060SN/A 13246221Snate@binkert.org tickEvent.schedule(curTick); 13251060SN/A} 13267897Shestness@cs.utexas.edu 13272292SN/Atemplate <class Impl> 13282292SN/Aint 13292292SN/AFullO3CPU<Impl>::getFreeTid() 13301060SN/A{ 13311060SN/A for (int i=0; i < numThreads; i++) { 13321060SN/A if (!tids[i]) { 13331060SN/A tids[i] = true; 13346314Sgblack@eecs.umich.edu return i; 13351060SN/A } 13367897Shestness@cs.utexas.edu } 13376032Ssteve.reinhardt@amd.com 13382918Sktlim@umich.edu return -1; 13392292SN/A} 13402669Sktlim@umich.edu 13411060SN/Atemplate <class Impl> 13421060SN/Avoid 13431060SN/AFullO3CPU<Impl>::doContextSwitch() 13441060SN/A{ 13456221Snate@binkert.org if (contextSwitch) { 13461060SN/A 13477897Shestness@cs.utexas.edu //ADD CODE TO DEACTIVE THREAD HERE (???) 13486032Ssteve.reinhardt@amd.com 13492918Sktlim@umich.edu for (int tid=0; tid < cpuWaitList.size(); tid++) { 13501060SN/A activateWhenReady(tid); 13512669Sktlim@umich.edu } 13522292SN/A 13532292SN/A if (cpuWaitList.size() == 0) 13542292SN/A contextSwitch = true; 13557720Sgblack@eecs.umich.edu } 13567720Sgblack@eecs.umich.edu} 13572292SN/A 13587720Sgblack@eecs.umich.edutemplate <class Impl> 13591060SN/Avoid 13601060SN/AFullO3CPU<Impl>::updateThreadPriority() 13611060SN/A{ 13621060SN/A if (activeThreads.size() > 1) 13637720Sgblack@eecs.umich.edu { 13641060SN/A //DEFAULT TO ROUND ROBIN SCHEME 13657720Sgblack@eecs.umich.edu //e.g. Move highest priority to end of thread list 13662292SN/A list<unsigned>::iterator list_begin = activeThreads.begin(); 13671060SN/A list<unsigned>::iterator list_end = activeThreads.end(); 13682292SN/A 13697720Sgblack@eecs.umich.edu unsigned high_thread = *list_begin; 13707720Sgblack@eecs.umich.edu 13714636Sgblack@eecs.umich.edu activeThreads.erase(list_begin); 13727720Sgblack@eecs.umich.edu 13734636Sgblack@eecs.umich.edu activeThreads.push_back(high_thread); 13744636Sgblack@eecs.umich.edu } 13754636Sgblack@eecs.umich.edu} 13767720Sgblack@eecs.umich.edu 13777720Sgblack@eecs.umich.edu// Forward declaration of FullO3CPU. 13784636Sgblack@eecs.umich.edutemplate class FullO3CPU<O3CPUImpl>; 13797720Sgblack@eecs.umich.edu