cpu.cc revision 2877
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 341858SN/A 351858SN/A#if FULL_SYSTEM 361060SN/A#include "sim/system.hh" 371060SN/A#else 381060SN/A#include "sim/process.hh" 391060SN/A#endif 401060SN/A 412325SN/A#include "cpu/activity.hh" 422683Sktlim@umich.edu#include "cpu/simple_thread.hh" 432680Sktlim@umich.edu#include "cpu/thread_context.hh" 442817Sksewell@umich.edu#include "cpu/o3/isa_specific.hh" 451717SN/A#include "cpu/o3/cpu.hh" 461060SN/A 472325SN/A#include "sim/root.hh" 482292SN/A#include "sim/stat_control.hh" 492292SN/A 502794Sktlim@umich.edu#if USE_CHECKER 512794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 522794Sktlim@umich.edu#endif 532794Sktlim@umich.edu 541060SN/Ausing namespace std; 552669Sktlim@umich.eduusing namespace TheISA; 561060SN/A 572733Sktlim@umich.eduBaseO3CPU::BaseO3CPU(Params *params) 582292SN/A : BaseCPU(params), cpu_id(0) 591060SN/A{ 601060SN/A} 611060SN/A 622292SN/Avoid 632733Sktlim@umich.eduBaseO3CPU::regStats() 642292SN/A{ 652292SN/A BaseCPU::regStats(); 662292SN/A} 672292SN/A 681060SN/Atemplate <class Impl> 691755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 701060SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 711060SN/A{ 721060SN/A} 731060SN/A 741060SN/Atemplate <class Impl> 751060SN/Avoid 761755SN/AFullO3CPU<Impl>::TickEvent::process() 771060SN/A{ 781060SN/A cpu->tick(); 791060SN/A} 801060SN/A 811060SN/Atemplate <class Impl> 821060SN/Aconst char * 831755SN/AFullO3CPU<Impl>::TickEvent::description() 841060SN/A{ 851755SN/A return "FullO3CPU tick event"; 861060SN/A} 871060SN/A 881060SN/Atemplate <class Impl> 892829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 902829Sksewell@umich.edu : Event(&mainEventQueue, CPU_Tick_Pri) 912829Sksewell@umich.edu{ 922829Sksewell@umich.edu} 932829Sksewell@umich.edu 942829Sksewell@umich.edutemplate <class Impl> 952829Sksewell@umich.eduvoid 962829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 972829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 982829Sksewell@umich.edu{ 992829Sksewell@umich.edu tid = thread_num; 1002829Sksewell@umich.edu cpu = thread_cpu; 1012829Sksewell@umich.edu} 1022829Sksewell@umich.edu 1032829Sksewell@umich.edutemplate <class Impl> 1042829Sksewell@umich.eduvoid 1052829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1062829Sksewell@umich.edu{ 1072829Sksewell@umich.edu cpu->activateThread(tid); 1082829Sksewell@umich.edu} 1092829Sksewell@umich.edu 1102829Sksewell@umich.edutemplate <class Impl> 1112829Sksewell@umich.educonst char * 1122829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::description() 1132829Sksewell@umich.edu{ 1142829Sksewell@umich.edu return "FullO3CPU \"Activate Thread\" event"; 1152829Sksewell@umich.edu} 1162829Sksewell@umich.edu 1172829Sksewell@umich.edutemplate <class Impl> 1182875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1192875Sksewell@umich.edu : Event(&mainEventQueue, CPU_Tick_Pri) 1202875Sksewell@umich.edu{ 1212875Sksewell@umich.edu} 1222875Sksewell@umich.edu 1232875Sksewell@umich.edutemplate <class Impl> 1242875Sksewell@umich.eduvoid 1252875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1262875Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1272875Sksewell@umich.edu{ 1282875Sksewell@umich.edu tid = thread_num; 1292875Sksewell@umich.edu cpu = thread_cpu; 1302875Sksewell@umich.edu} 1312875Sksewell@umich.edu 1322875Sksewell@umich.edutemplate <class Impl> 1332875Sksewell@umich.eduvoid 1342875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1352875Sksewell@umich.edu{ 1362875Sksewell@umich.edu cpu->deactivateThread(tid); 1372875Sksewell@umich.edu cpu->removeThread(tid); 1382875Sksewell@umich.edu} 1392875Sksewell@umich.edu 1402875Sksewell@umich.edutemplate <class Impl> 1412875Sksewell@umich.educonst char * 1422875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::description() 1432875Sksewell@umich.edu{ 1442875Sksewell@umich.edu return "FullO3CPU \"Deallocate Context\" event"; 1452875Sksewell@umich.edu} 1462875Sksewell@umich.edu 1472875Sksewell@umich.edutemplate <class Impl> 1482292SN/AFullO3CPU<Impl>::FullO3CPU(Params *params) 1492733Sktlim@umich.edu : BaseO3CPU(params), 1501060SN/A tickEvent(this), 1512292SN/A removeInstsThisCycle(false), 1521060SN/A fetch(params), 1531060SN/A decode(params), 1541060SN/A rename(params), 1551060SN/A iew(params), 1561060SN/A commit(params), 1571060SN/A 1582292SN/A regFile(params->numPhysIntRegs, params->numPhysFloatRegs), 1591060SN/A 1602831Sksewell@umich.edu freeList(params->numberOfThreads, 1612292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1622292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1631060SN/A 1642292SN/A rob(params->numROBEntries, params->squashWidth, 1652292SN/A params->smtROBPolicy, params->smtROBThreshold, 1662292SN/A params->numberOfThreads), 1671060SN/A 1682831Sksewell@umich.edu scoreboard(params->numberOfThreads, 1692292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1702292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1712292SN/A TheISA::NumMiscRegs * number_of_threads, 1722292SN/A TheISA::ZeroReg), 1731060SN/A 1741060SN/A // For now just have these time buffers be pretty big. 1752325SN/A // @todo: Make these time buffer sizes parameters or derived 1762325SN/A // from latencies 1771061SN/A timeBuffer(5, 5), 1781061SN/A fetchQueue(5, 5), 1791061SN/A decodeQueue(5, 5), 1801061SN/A renameQueue(5, 5), 1811061SN/A iewQueue(5, 5), 1822325SN/A activityRec(NumStages, 10, params->activity), 1831060SN/A 1841060SN/A globalSeqNum(1), 1851060SN/A 1861858SN/A#if FULL_SYSTEM 1872292SN/A system(params->system), 1881060SN/A physmem(system->physmem), 1891060SN/A#endif // FULL_SYSTEM 1902292SN/A mem(params->mem), 1912843Sktlim@umich.edu drainCount(0), 1922316SN/A deferRegistration(params->deferRegistration), 1932316SN/A numThreads(number_of_threads) 1941060SN/A{ 1951060SN/A _status = Idle; 1961681SN/A 1972733Sktlim@umich.edu checker = NULL; 1982733Sktlim@umich.edu 1992794Sktlim@umich.edu if (params->checker) { 2002733Sktlim@umich.edu#if USE_CHECKER 2012316SN/A BaseCPU *temp_checker = params->checker; 2022316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 2032316SN/A checker->setMemory(mem); 2042316SN/A#if FULL_SYSTEM 2052316SN/A checker->setSystem(params->system); 2062316SN/A#endif 2072794Sktlim@umich.edu#else 2082794Sktlim@umich.edu panic("Checker enabled but not compiled in!"); 2092794Sktlim@umich.edu#endif // USE_CHECKER 2102316SN/A } 2112316SN/A 2121858SN/A#if !FULL_SYSTEM 2132292SN/A thread.resize(number_of_threads); 2142292SN/A tids.resize(number_of_threads); 2151681SN/A#endif 2161681SN/A 2172325SN/A // The stages also need their CPU pointer setup. However this 2182325SN/A // must be done at the upper level CPU because they have pointers 2192325SN/A // to the upper level CPU, and not this FullO3CPU. 2201060SN/A 2212292SN/A // Set up Pointers to the activeThreads list for each stage 2222292SN/A fetch.setActiveThreads(&activeThreads); 2232292SN/A decode.setActiveThreads(&activeThreads); 2242292SN/A rename.setActiveThreads(&activeThreads); 2252292SN/A iew.setActiveThreads(&activeThreads); 2262292SN/A commit.setActiveThreads(&activeThreads); 2271060SN/A 2281060SN/A // Give each of the stages the time buffer they will use. 2291060SN/A fetch.setTimeBuffer(&timeBuffer); 2301060SN/A decode.setTimeBuffer(&timeBuffer); 2311060SN/A rename.setTimeBuffer(&timeBuffer); 2321060SN/A iew.setTimeBuffer(&timeBuffer); 2331060SN/A commit.setTimeBuffer(&timeBuffer); 2341060SN/A 2351060SN/A // Also setup each of the stages' queues. 2361060SN/A fetch.setFetchQueue(&fetchQueue); 2371060SN/A decode.setFetchQueue(&fetchQueue); 2382292SN/A commit.setFetchQueue(&fetchQueue); 2391060SN/A decode.setDecodeQueue(&decodeQueue); 2401060SN/A rename.setDecodeQueue(&decodeQueue); 2411060SN/A rename.setRenameQueue(&renameQueue); 2421060SN/A iew.setRenameQueue(&renameQueue); 2431060SN/A iew.setIEWQueue(&iewQueue); 2441060SN/A commit.setIEWQueue(&iewQueue); 2451060SN/A commit.setRenameQueue(&renameQueue); 2461060SN/A 2472316SN/A commit.setFetchStage(&fetch); 2482292SN/A commit.setIEWStage(&iew); 2492292SN/A rename.setIEWStage(&iew); 2502292SN/A rename.setCommitStage(&commit); 2512292SN/A 2522292SN/A#if !FULL_SYSTEM 2532307SN/A int active_threads = params->workload.size(); 2542831Sksewell@umich.edu 2552831Sksewell@umich.edu if (active_threads > Impl::MaxThreads) { 2562831Sksewell@umich.edu panic("Workload Size too large. Increase the 'MaxThreads'" 2572831Sksewell@umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2582831Sksewell@umich.edu "edit your workload size."); 2592831Sksewell@umich.edu } 2602292SN/A#else 2612307SN/A int active_threads = 1; 2622292SN/A#endif 2632292SN/A 2642316SN/A //Make Sure That this a Valid Architeture 2652292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2662292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2672292SN/A 2682292SN/A rename.setScoreboard(&scoreboard); 2692292SN/A iew.setScoreboard(&scoreboard); 2702292SN/A 2711060SN/A // Setup the rename map for whichever stages need it. 2722292SN/A PhysRegIndex lreg_idx = 0; 2732292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2741060SN/A 2752292SN/A for (int tid=0; tid < numThreads; tid++) { 2762307SN/A bool bindRegs = (tid <= active_threads - 1); 2772292SN/A 2782292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2792292SN/A params->numPhysIntRegs, 2802325SN/A lreg_idx, //Index for Logical. Regs 2812292SN/A 2822292SN/A TheISA::NumFloatRegs, 2832292SN/A params->numPhysFloatRegs, 2842325SN/A freg_idx, //Index for Float Regs 2852292SN/A 2862292SN/A TheISA::NumMiscRegs, 2872292SN/A 2882292SN/A TheISA::ZeroReg, 2892292SN/A TheISA::ZeroReg, 2902292SN/A 2912292SN/A tid, 2922292SN/A false); 2932292SN/A 2942292SN/A renameMap[tid].init(TheISA::NumIntRegs, 2952292SN/A params->numPhysIntRegs, 2962325SN/A lreg_idx, //Index for Logical. Regs 2972292SN/A 2982292SN/A TheISA::NumFloatRegs, 2992292SN/A params->numPhysFloatRegs, 3002325SN/A freg_idx, //Index for Float Regs 3012292SN/A 3022292SN/A TheISA::NumMiscRegs, 3032292SN/A 3042292SN/A TheISA::ZeroReg, 3052292SN/A TheISA::ZeroReg, 3062292SN/A 3072292SN/A tid, 3082292SN/A bindRegs); 3092292SN/A } 3102292SN/A 3112292SN/A rename.setRenameMap(renameMap); 3122292SN/A commit.setRenameMap(commitRenameMap); 3132292SN/A 3142292SN/A // Give renameMap & rename stage access to the freeList; 3152292SN/A for (int i=0; i < numThreads; i++) { 3162292SN/A renameMap[i].setFreeList(&freeList); 3172292SN/A } 3181060SN/A rename.setFreeList(&freeList); 3192292SN/A 3201060SN/A // Setup the ROB for whichever stages need it. 3211060SN/A commit.setROB(&rob); 3222292SN/A 3232292SN/A lastRunningCycle = curTick; 3242292SN/A 3252829Sksewell@umich.edu lastActivatedCycle = -1; 3262829Sksewell@umich.edu 3272292SN/A contextSwitch = false; 3281060SN/A} 3291060SN/A 3301060SN/Atemplate <class Impl> 3311755SN/AFullO3CPU<Impl>::~FullO3CPU() 3321060SN/A{ 3331060SN/A} 3341060SN/A 3351060SN/Atemplate <class Impl> 3361060SN/Avoid 3371755SN/AFullO3CPU<Impl>::fullCPURegStats() 3381062SN/A{ 3392733Sktlim@umich.edu BaseO3CPU::regStats(); 3402292SN/A 3412733Sktlim@umich.edu // Register any of the O3CPU's stats here. 3422292SN/A timesIdled 3432292SN/A .name(name() + ".timesIdled") 3442292SN/A .desc("Number of times that the entire CPU went into an idle state and" 3452292SN/A " unscheduled itself") 3462292SN/A .prereq(timesIdled); 3472292SN/A 3482292SN/A idleCycles 3492292SN/A .name(name() + ".idleCycles") 3502292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 3512292SN/A "to idling") 3522292SN/A .prereq(idleCycles); 3532292SN/A 3542292SN/A // Number of Instructions simulated 3552292SN/A // -------------------------------- 3562292SN/A // Should probably be in Base CPU but need templated 3572292SN/A // MaxThreads so put in here instead 3582292SN/A committedInsts 3592292SN/A .init(numThreads) 3602292SN/A .name(name() + ".committedInsts") 3612292SN/A .desc("Number of Instructions Simulated"); 3622292SN/A 3632292SN/A totalCommittedInsts 3642292SN/A .name(name() + ".committedInsts_total") 3652292SN/A .desc("Number of Instructions Simulated"); 3662292SN/A 3672292SN/A cpi 3682292SN/A .name(name() + ".cpi") 3692292SN/A .desc("CPI: Cycles Per Instruction") 3702292SN/A .precision(6); 3712292SN/A cpi = simTicks / committedInsts; 3722292SN/A 3732292SN/A totalCpi 3742292SN/A .name(name() + ".cpi_total") 3752292SN/A .desc("CPI: Total CPI of All Threads") 3762292SN/A .precision(6); 3772292SN/A totalCpi = simTicks / totalCommittedInsts; 3782292SN/A 3792292SN/A ipc 3802292SN/A .name(name() + ".ipc") 3812292SN/A .desc("IPC: Instructions Per Cycle") 3822292SN/A .precision(6); 3832292SN/A ipc = committedInsts / simTicks; 3842292SN/A 3852292SN/A totalIpc 3862292SN/A .name(name() + ".ipc_total") 3872292SN/A .desc("IPC: Total IPC of All Threads") 3882292SN/A .precision(6); 3892292SN/A totalIpc = totalCommittedInsts / simTicks; 3902292SN/A 3911062SN/A} 3921062SN/A 3931062SN/Atemplate <class Impl> 3941062SN/Avoid 3951755SN/AFullO3CPU<Impl>::tick() 3961060SN/A{ 3972733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 3981060SN/A 3992292SN/A ++numCycles; 4002292SN/A 4012325SN/A// activity = false; 4022292SN/A 4032292SN/A //Tick each of the stages 4041060SN/A fetch.tick(); 4051060SN/A 4061060SN/A decode.tick(); 4071060SN/A 4081060SN/A rename.tick(); 4091060SN/A 4101060SN/A iew.tick(); 4111060SN/A 4121060SN/A commit.tick(); 4131060SN/A 4142292SN/A#if !FULL_SYSTEM 4152292SN/A doContextSwitch(); 4162292SN/A#endif 4172292SN/A 4182292SN/A // Now advance the time buffers 4191060SN/A timeBuffer.advance(); 4201060SN/A 4211060SN/A fetchQueue.advance(); 4221060SN/A decodeQueue.advance(); 4231060SN/A renameQueue.advance(); 4241060SN/A iewQueue.advance(); 4251060SN/A 4262325SN/A activityRec.advance(); 4272292SN/A 4282292SN/A if (removeInstsThisCycle) { 4292292SN/A cleanUpRemovedInsts(); 4302292SN/A } 4312292SN/A 4322325SN/A if (!tickEvent.scheduled()) { 4332325SN/A if (_status == SwitchedOut) { 4342325SN/A // increment stat 4352325SN/A lastRunningCycle = curTick; 4362325SN/A } else if (!activityRec.active()) { 4372325SN/A lastRunningCycle = curTick; 4382325SN/A timesIdled++; 4392325SN/A } else { 4402325SN/A tickEvent.schedule(curTick + cycles(1)); 4412325SN/A } 4422292SN/A } 4432292SN/A 4442292SN/A#if !FULL_SYSTEM 4452292SN/A updateThreadPriority(); 4462292SN/A#endif 4472292SN/A 4481060SN/A} 4491060SN/A 4501060SN/Atemplate <class Impl> 4511060SN/Avoid 4521755SN/AFullO3CPU<Impl>::init() 4531060SN/A{ 4542307SN/A if (!deferRegistration) { 4552680Sktlim@umich.edu registerThreadContexts(); 4562292SN/A } 4571060SN/A 4582292SN/A // Set inSyscall so that the CPU doesn't squash when initially 4592292SN/A // setting up registers. 4602292SN/A for (int i = 0; i < number_of_threads; ++i) 4612292SN/A thread[i]->inSyscall = true; 4622292SN/A 4632292SN/A for (int tid=0; tid < number_of_threads; tid++) { 4641858SN/A#if FULL_SYSTEM 4652680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 4661681SN/A#else 4672680Sktlim@umich.edu ThreadContext *src_tc = thread[tid]->getTC(); 4681681SN/A#endif 4692292SN/A // Threads start in the Suspended State 4702680Sktlim@umich.edu if (src_tc->status() != ThreadContext::Suspended) { 4712292SN/A continue; 4721060SN/A } 4731060SN/A 4742292SN/A#if FULL_SYSTEM 4752680Sktlim@umich.edu TheISA::initCPU(src_tc, src_tc->readCpuId()); 4762292SN/A#endif 4772292SN/A } 4782292SN/A 4792292SN/A // Clear inSyscall. 4802292SN/A for (int i = 0; i < number_of_threads; ++i) 4812292SN/A thread[i]->inSyscall = false; 4822292SN/A 4832316SN/A // Initialize stages. 4842292SN/A fetch.initStage(); 4852292SN/A iew.initStage(); 4862292SN/A rename.initStage(); 4872292SN/A commit.initStage(); 4882292SN/A 4892292SN/A commit.setThreads(thread); 4902292SN/A} 4912292SN/A 4922292SN/Atemplate <class Impl> 4932292SN/Avoid 4942875Sksewell@umich.eduFullO3CPU<Impl>::activateThread(unsigned tid) 4952875Sksewell@umich.edu{ 4962875Sksewell@umich.edu list<unsigned>::iterator isActive = find( 4972875Sksewell@umich.edu activeThreads.begin(), activeThreads.end(), tid); 4982875Sksewell@umich.edu 4992875Sksewell@umich.edu if (isActive == activeThreads.end()) { 5002875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 5012875Sksewell@umich.edu tid); 5022875Sksewell@umich.edu 5032875Sksewell@umich.edu activeThreads.push_back(tid); 5042875Sksewell@umich.edu } 5052875Sksewell@umich.edu} 5062875Sksewell@umich.edu 5072875Sksewell@umich.edutemplate <class Impl> 5082875Sksewell@umich.eduvoid 5092875Sksewell@umich.eduFullO3CPU<Impl>::deactivateThread(unsigned tid) 5102875Sksewell@umich.edu{ 5112875Sksewell@umich.edu //Remove From Active List, if Active 5122875Sksewell@umich.edu list<unsigned>::iterator thread_it = 5132875Sksewell@umich.edu find(activeThreads.begin(), activeThreads.end(), tid); 5142875Sksewell@umich.edu 5152875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 5162875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 5172875Sksewell@umich.edu tid); 5182875Sksewell@umich.edu activeThreads.erase(thread_it); 5192875Sksewell@umich.edu } 5202875Sksewell@umich.edu} 5212875Sksewell@umich.edu 5222875Sksewell@umich.edutemplate <class Impl> 5232875Sksewell@umich.eduvoid 5242875Sksewell@umich.eduFullO3CPU<Impl>::activateContext(int tid, int delay) 5252875Sksewell@umich.edu{ 5262875Sksewell@umich.edu // Needs to set each stage to running as well. 5272875Sksewell@umich.edu if (delay){ 5282875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 5292875Sksewell@umich.edu "on cycle %d\n", tid, curTick + cycles(delay)); 5302875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 5312875Sksewell@umich.edu } else { 5322875Sksewell@umich.edu activateThread(tid); 5332875Sksewell@umich.edu } 5342875Sksewell@umich.edu 5352875Sksewell@umich.edu if(lastActivatedCycle < curTick) { 5362875Sksewell@umich.edu scheduleTickEvent(delay); 5372875Sksewell@umich.edu 5382875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 5392875Sksewell@umich.edu // deschedule itself. 5402875Sksewell@umich.edu activityRec.activity(); 5412875Sksewell@umich.edu fetch.wakeFromQuiesce(); 5422875Sksewell@umich.edu 5432875Sksewell@umich.edu lastActivatedCycle = curTick; 5442875Sksewell@umich.edu 5452875Sksewell@umich.edu _status = Running; 5462875Sksewell@umich.edu } 5472875Sksewell@umich.edu} 5482875Sksewell@umich.edu 5492875Sksewell@umich.edutemplate <class Impl> 5502875Sksewell@umich.eduvoid 5512875Sksewell@umich.eduFullO3CPU<Impl>::deallocateContext(int tid, int delay) 5522875Sksewell@umich.edu{ 5532875Sksewell@umich.edu // Schedule removal of thread data from CPU 5542875Sksewell@umich.edu if (delay){ 5552875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 5562875Sksewell@umich.edu "on cycle %d\n", tid, curTick + cycles(delay)); 5572875Sksewell@umich.edu scheduleDeallocateContextEvent(tid, delay); 5582875Sksewell@umich.edu } else { 5592875Sksewell@umich.edu deactivateThread(tid); 5602875Sksewell@umich.edu removeThread(tid); 5612875Sksewell@umich.edu } 5622875Sksewell@umich.edu} 5632875Sksewell@umich.edu 5642875Sksewell@umich.edutemplate <class Impl> 5652875Sksewell@umich.eduvoid 5662875Sksewell@umich.eduFullO3CPU<Impl>::suspendContext(int tid) 5672875Sksewell@umich.edu{ 5682875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 5692875Sksewell@umich.edu unscheduleTickEvent(); 5702875Sksewell@umich.edu _status = Idle; 5712875Sksewell@umich.edu/* 5722875Sksewell@umich.edu //Remove From Active List, if Active 5732875Sksewell@umich.edu list<unsigned>::iterator isActive = find( 5742875Sksewell@umich.edu activeThreads.begin(), activeThreads.end(), tid); 5752875Sksewell@umich.edu 5762875Sksewell@umich.edu if (isActive != activeThreads.end()) { 5772875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 5782875Sksewell@umich.edu tid); 5792875Sksewell@umich.edu activeThreads.erase(isActive); 5802875Sksewell@umich.edu } 5812875Sksewell@umich.edu*/ 5822875Sksewell@umich.edu} 5832875Sksewell@umich.edu 5842875Sksewell@umich.edutemplate <class Impl> 5852875Sksewell@umich.eduvoid 5862875Sksewell@umich.eduFullO3CPU<Impl>::haltContext(int tid) 5872875Sksewell@umich.edu{ 5882875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halting Thread Context", tid); 5892875Sksewell@umich.edu/* 5902875Sksewell@umich.edu //Remove From Active List, if Active 5912875Sksewell@umich.edu list<unsigned>::iterator isActive = find( 5922875Sksewell@umich.edu activeThreads.begin(), activeThreads.end(), tid); 5932875Sksewell@umich.edu 5942875Sksewell@umich.edu if (isActive != activeThreads.end()) { 5952875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 5962875Sksewell@umich.edu tid); 5972875Sksewell@umich.edu activeThreads.erase(isActive); 5982875Sksewell@umich.edu 5992875Sksewell@umich.edu removeThread(tid); 6002875Sksewell@umich.edu } 6012875Sksewell@umich.edu*/ 6022875Sksewell@umich.edu} 6032875Sksewell@umich.edu 6042875Sksewell@umich.edutemplate <class Impl> 6052875Sksewell@umich.eduvoid 6062292SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 6072292SN/A{ 6082847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 6092292SN/A // Will change now that the PC and thread state is internal to the CPU 6102683Sktlim@umich.edu // and not in the ThreadContext. 6112292SN/A#if FULL_SYSTEM 6122680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 6132292SN/A#else 6142847Sksewell@umich.edu ThreadContext *src_tc = tcBase(tid); 6152292SN/A#endif 6162292SN/A 6172292SN/A //Bind Int Regs to Rename Map 6182292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 6192292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 6202292SN/A 6212292SN/A renameMap[tid].setEntry(ireg,phys_reg); 6222292SN/A scoreboard.setReg(phys_reg); 6232292SN/A } 6242292SN/A 6252292SN/A //Bind Float Regs to Rename Map 6262292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 6272292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 6282292SN/A 6292292SN/A renameMap[tid].setEntry(freg,phys_reg); 6302292SN/A scoreboard.setReg(phys_reg); 6312292SN/A } 6322292SN/A 6332292SN/A //Copy Thread Data Into RegFile 6342847Sksewell@umich.edu //this->copyFromTC(tid); 6352292SN/A 6362847Sksewell@umich.edu //Set PC/NPC/NNPC 6372847Sksewell@umich.edu setPC(src_tc->readPC(), tid); 6382847Sksewell@umich.edu setNextPC(src_tc->readNextPC(), tid); 6392847Sksewell@umich.edu#if THE_ISA != ALPHA_ISA 6402847Sksewell@umich.edu setNextNPC(src_tc->readNextNPC(), tid); 6412847Sksewell@umich.edu#endif 6422292SN/A 6432680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 6442292SN/A 6452292SN/A activateContext(tid,1); 6462292SN/A 6472292SN/A //Reset ROB/IQ/LSQ Entries 6482292SN/A commit.rob->resetEntries(); 6492292SN/A iew.resetEntries(); 6502292SN/A} 6512292SN/A 6522292SN/Atemplate <class Impl> 6532292SN/Avoid 6542292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 6552292SN/A{ 6562877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 6572847Sksewell@umich.edu 6582847Sksewell@umich.edu // Copy Thread Data From RegFile 6592847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 6602847Sksewell@umich.edu //this->copyToTC(tid); 6612847Sksewell@umich.edu 6622847Sksewell@umich.edu // Unbind Int Regs from Rename Map 6632292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 6642292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 6652292SN/A 6662292SN/A scoreboard.unsetReg(phys_reg); 6672292SN/A freeList.addReg(phys_reg); 6682292SN/A } 6692292SN/A 6702847Sksewell@umich.edu // Unbind Float Regs from Rename Map 6712292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 6722292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 6732292SN/A 6742292SN/A scoreboard.unsetReg(phys_reg); 6752292SN/A freeList.addReg(phys_reg); 6762292SN/A } 6772292SN/A 6782847Sksewell@umich.edu // Squash Throughout Pipeline 6792292SN/A fetch.squash(0,tid); 6802292SN/A decode.squash(tid); 6812292SN/A rename.squash(tid); 6822875Sksewell@umich.edu iew.squash(tid); 6832875Sksewell@umich.edu commit.rob->squash(commit.rob->readHeadInst(tid)->seqNum, tid); 6842292SN/A 6852292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 6862292SN/A 6872847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 6882292SN/A if (activeThreads.size() >= 1) { 6892292SN/A commit.rob->resetEntries(); 6902292SN/A iew.resetEntries(); 6912292SN/A } 6922292SN/A} 6932292SN/A 6942292SN/A 6952292SN/Atemplate <class Impl> 6962292SN/Avoid 6972292SN/AFullO3CPU<Impl>::activateWhenReady(int tid) 6982292SN/A{ 6992733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 7002292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 7012292SN/A tid); 7022292SN/A 7032292SN/A bool ready = true; 7042292SN/A 7052292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 7062733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7072292SN/A "Phys. Int. Regs.\n", 7082292SN/A tid); 7092292SN/A ready = false; 7102292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 7112733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7122292SN/A "Phys. Float. Regs.\n", 7132292SN/A tid); 7142292SN/A ready = false; 7152292SN/A } else if (commit.rob->numFreeEntries() >= 7162292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 7172733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7182292SN/A "ROB entries.\n", 7192292SN/A tid); 7202292SN/A ready = false; 7212292SN/A } else if (iew.instQueue.numFreeEntries() >= 7222292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 7232733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7242292SN/A "IQ entries.\n", 7252292SN/A tid); 7262292SN/A ready = false; 7272292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 7282292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 7292733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 7302292SN/A "LSQ entries.\n", 7312292SN/A tid); 7322292SN/A ready = false; 7332292SN/A } 7342292SN/A 7352292SN/A if (ready) { 7362292SN/A insertThread(tid); 7372292SN/A 7382292SN/A contextSwitch = false; 7392292SN/A 7402292SN/A cpuWaitList.remove(tid); 7412292SN/A } else { 7422292SN/A suspendContext(tid); 7432292SN/A 7442292SN/A //blocks fetch 7452292SN/A contextSwitch = true; 7462292SN/A 7472875Sksewell@umich.edu //@todo: dont always add to waitlist 7482292SN/A //do waitlist 7492292SN/A cpuWaitList.push_back(tid); 7501060SN/A } 7511060SN/A} 7521060SN/A 7531060SN/Atemplate <class Impl> 7542843Sktlim@umich.edubool 7552843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 7561060SN/A{ 7572843Sktlim@umich.edu drainCount = 0; 7582843Sktlim@umich.edu drainEvent = drain_event; 7592843Sktlim@umich.edu fetch.drain(); 7602843Sktlim@umich.edu decode.drain(); 7612843Sktlim@umich.edu rename.drain(); 7622843Sktlim@umich.edu iew.drain(); 7632843Sktlim@umich.edu commit.drain(); 7642325SN/A 7652325SN/A // Wake the CPU and record activity so everything can drain out if 7662325SN/A // the CPU is currently idle. 7672325SN/A wakeCPU(); 7682325SN/A activityRec.activity(); 7692843Sktlim@umich.edu 7702843Sktlim@umich.edu return false; 7712316SN/A} 7722310SN/A 7732316SN/Atemplate <class Impl> 7742316SN/Avoid 7752843Sktlim@umich.eduFullO3CPU<Impl>::resume() 7762316SN/A{ 7772843Sktlim@umich.edu if (_status == SwitchedOut) 7782843Sktlim@umich.edu return; 7792843Sktlim@umich.edu fetch.resume(); 7802843Sktlim@umich.edu decode.resume(); 7812843Sktlim@umich.edu rename.resume(); 7822843Sktlim@umich.edu iew.resume(); 7832843Sktlim@umich.edu commit.resume(); 7842316SN/A 7852843Sktlim@umich.edu if (!tickEvent.scheduled()) 7862843Sktlim@umich.edu tickEvent.schedule(curTick); 7872843Sktlim@umich.edu _status = Running; 7882843Sktlim@umich.edu} 7892316SN/A 7902843Sktlim@umich.edutemplate <class Impl> 7912843Sktlim@umich.eduvoid 7922843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 7932843Sktlim@umich.edu{ 7942843Sktlim@umich.edu if (++drainCount == NumStages) { 7952316SN/A if (tickEvent.scheduled()) 7962316SN/A tickEvent.squash(); 7972843Sktlim@umich.edu _status = Drained; 7982843Sktlim@umich.edu drainEvent->process(); 7992310SN/A } 8002843Sktlim@umich.edu assert(drainCount <= 5); 8012843Sktlim@umich.edu} 8022843Sktlim@umich.edu 8032843Sktlim@umich.edutemplate <class Impl> 8042843Sktlim@umich.eduvoid 8052843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 8062843Sktlim@umich.edu{ 8072843Sktlim@umich.edu fetch.switchOut(); 8082843Sktlim@umich.edu rename.switchOut(); 8092843Sktlim@umich.edu commit.switchOut(); 8102843Sktlim@umich.edu instList.clear(); 8112843Sktlim@umich.edu while (!removeList.empty()) { 8122843Sktlim@umich.edu removeList.pop(); 8132843Sktlim@umich.edu } 8142843Sktlim@umich.edu 8152843Sktlim@umich.edu _status = SwitchedOut; 8162843Sktlim@umich.edu#if USE_CHECKER 8172843Sktlim@umich.edu if (checker) 8182843Sktlim@umich.edu checker->switchOut(); 8192843Sktlim@umich.edu#endif 8201060SN/A} 8211060SN/A 8221060SN/Atemplate <class Impl> 8231060SN/Avoid 8241755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 8251060SN/A{ 8262325SN/A // Flush out any old data from the time buffers. 8272325SN/A for (int i = 0; i < 10; ++i) { 8282307SN/A timeBuffer.advance(); 8292307SN/A fetchQueue.advance(); 8302307SN/A decodeQueue.advance(); 8312307SN/A renameQueue.advance(); 8322307SN/A iewQueue.advance(); 8332307SN/A } 8342307SN/A 8352325SN/A activityRec.reset(); 8362307SN/A 8371060SN/A BaseCPU::takeOverFrom(oldCPU); 8381060SN/A 8392307SN/A fetch.takeOverFrom(); 8402307SN/A decode.takeOverFrom(); 8412307SN/A rename.takeOverFrom(); 8422307SN/A iew.takeOverFrom(); 8432307SN/A commit.takeOverFrom(); 8442307SN/A 8451060SN/A assert(!tickEvent.scheduled()); 8461060SN/A 8472325SN/A // @todo: Figure out how to properly select the tid to put onto 8482325SN/A // the active threads list. 8492307SN/A int tid = 0; 8502307SN/A 8512307SN/A list<unsigned>::iterator isActive = find( 8522307SN/A activeThreads.begin(), activeThreads.end(), tid); 8532307SN/A 8542307SN/A if (isActive == activeThreads.end()) { 8552325SN/A //May Need to Re-code this if the delay variable is the delay 8562325SN/A //needed for thread to activate 8572733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 8582307SN/A tid); 8592307SN/A 8602307SN/A activeThreads.push_back(tid); 8612307SN/A } 8622307SN/A 8632325SN/A // Set all statuses to active, schedule the CPU's tick event. 8642307SN/A // @todo: Fix up statuses so this is handled properly 8652680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 8662680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 8672680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 8681681SN/A _status = Running; 8691681SN/A tickEvent.schedule(curTick); 8701681SN/A } 8711060SN/A } 8722307SN/A if (!tickEvent.scheduled()) 8732307SN/A tickEvent.schedule(curTick); 8741060SN/A} 8751060SN/A 8761060SN/Atemplate <class Impl> 8771060SN/Auint64_t 8781755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 8791060SN/A{ 8801060SN/A return regFile.readIntReg(reg_idx); 8811060SN/A} 8821060SN/A 8831060SN/Atemplate <class Impl> 8842455SN/AFloatReg 8852455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 8861060SN/A{ 8872455SN/A return regFile.readFloatReg(reg_idx, width); 8881060SN/A} 8891060SN/A 8901060SN/Atemplate <class Impl> 8912455SN/AFloatReg 8922455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 8931060SN/A{ 8942455SN/A return regFile.readFloatReg(reg_idx); 8951060SN/A} 8961060SN/A 8971060SN/Atemplate <class Impl> 8982455SN/AFloatRegBits 8992455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 9001060SN/A{ 9012455SN/A return regFile.readFloatRegBits(reg_idx, width); 9022455SN/A} 9032455SN/A 9042455SN/Atemplate <class Impl> 9052455SN/AFloatRegBits 9062455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 9072455SN/A{ 9082455SN/A return regFile.readFloatRegBits(reg_idx); 9091060SN/A} 9101060SN/A 9111060SN/Atemplate <class Impl> 9121060SN/Avoid 9131755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 9141060SN/A{ 9151060SN/A regFile.setIntReg(reg_idx, val); 9161060SN/A} 9171060SN/A 9181060SN/Atemplate <class Impl> 9191060SN/Avoid 9202455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 9211060SN/A{ 9222455SN/A regFile.setFloatReg(reg_idx, val, width); 9231060SN/A} 9241060SN/A 9251060SN/Atemplate <class Impl> 9261060SN/Avoid 9272455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 9281060SN/A{ 9292455SN/A regFile.setFloatReg(reg_idx, val); 9301060SN/A} 9311060SN/A 9321060SN/Atemplate <class Impl> 9331060SN/Avoid 9342455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 9351060SN/A{ 9362455SN/A regFile.setFloatRegBits(reg_idx, val, width); 9372455SN/A} 9382455SN/A 9392455SN/Atemplate <class Impl> 9402455SN/Avoid 9412455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 9422455SN/A{ 9432455SN/A regFile.setFloatRegBits(reg_idx, val); 9441060SN/A} 9451060SN/A 9461060SN/Atemplate <class Impl> 9471060SN/Auint64_t 9482292SN/AFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 9491060SN/A{ 9502292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 9512292SN/A 9522292SN/A return regFile.readIntReg(phys_reg); 9532292SN/A} 9542292SN/A 9552292SN/Atemplate <class Impl> 9562292SN/Afloat 9572292SN/AFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 9582292SN/A{ 9592307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 9602307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 9612292SN/A 9622669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 9632292SN/A} 9642292SN/A 9652292SN/Atemplate <class Impl> 9662292SN/Adouble 9672292SN/AFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 9682292SN/A{ 9692307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 9702307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 9712292SN/A 9722669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 9732292SN/A} 9742292SN/A 9752292SN/Atemplate <class Impl> 9762292SN/Auint64_t 9772292SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 9782292SN/A{ 9792307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 9802307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 9812292SN/A 9822669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 9831060SN/A} 9841060SN/A 9851060SN/Atemplate <class Impl> 9861060SN/Avoid 9872292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 9881060SN/A{ 9892292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 9902292SN/A 9912292SN/A regFile.setIntReg(phys_reg, val); 9921060SN/A} 9931060SN/A 9941060SN/Atemplate <class Impl> 9951060SN/Avoid 9962292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 9971060SN/A{ 9982292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 9992292SN/A 10002669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 10011060SN/A} 10021060SN/A 10031060SN/Atemplate <class Impl> 10041060SN/Avoid 10052292SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 10061060SN/A{ 10072292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10082292SN/A 10092669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 10101060SN/A} 10111060SN/A 10121060SN/Atemplate <class Impl> 10131060SN/Avoid 10142292SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 10151060SN/A{ 10162292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10171060SN/A 10182669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 10192292SN/A} 10202292SN/A 10212292SN/Atemplate <class Impl> 10222292SN/Auint64_t 10232292SN/AFullO3CPU<Impl>::readPC(unsigned tid) 10242292SN/A{ 10252292SN/A return commit.readPC(tid); 10261060SN/A} 10271060SN/A 10281060SN/Atemplate <class Impl> 10291060SN/Avoid 10302292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 10311060SN/A{ 10322292SN/A commit.setPC(new_PC, tid); 10332292SN/A} 10341060SN/A 10352292SN/Atemplate <class Impl> 10362292SN/Auint64_t 10372292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 10382292SN/A{ 10392292SN/A return commit.readNextPC(tid); 10402292SN/A} 10411060SN/A 10422292SN/Atemplate <class Impl> 10432292SN/Avoid 10442292SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 10452292SN/A{ 10462292SN/A commit.setNextPC(val, tid); 10472292SN/A} 10481060SN/A 10492756Sksewell@umich.edu#if THE_ISA != ALPHA_ISA 10502756Sksewell@umich.edutemplate <class Impl> 10512756Sksewell@umich.eduuint64_t 10522756Sksewell@umich.eduFullO3CPU<Impl>::readNextNPC(unsigned tid) 10532756Sksewell@umich.edu{ 10542756Sksewell@umich.edu return commit.readNextNPC(tid); 10552756Sksewell@umich.edu} 10562756Sksewell@umich.edu 10572756Sksewell@umich.edutemplate <class Impl> 10582756Sksewell@umich.eduvoid 10592756Sksewell@umich.eduFullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid) 10602756Sksewell@umich.edu{ 10612756Sksewell@umich.edu commit.setNextNPC(val, tid); 10622756Sksewell@umich.edu} 10632756Sksewell@umich.edu#endif 10642756Sksewell@umich.edu 10652292SN/Atemplate <class Impl> 10662292SN/Atypename FullO3CPU<Impl>::ListIt 10672292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 10682292SN/A{ 10692292SN/A instList.push_back(inst); 10701060SN/A 10712292SN/A return --(instList.end()); 10722292SN/A} 10731060SN/A 10742292SN/Atemplate <class Impl> 10752292SN/Avoid 10762292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 10772292SN/A{ 10782292SN/A // Keep an instruction count. 10792292SN/A thread[tid]->numInst++; 10802292SN/A thread[tid]->numInsts++; 10812292SN/A committedInsts[tid]++; 10822292SN/A totalCommittedInsts++; 10832292SN/A 10842292SN/A // Check for instruction-count-based events. 10852292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 10862292SN/A} 10872292SN/A 10882292SN/Atemplate <class Impl> 10892292SN/Avoid 10902292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 10912292SN/A{ 10922292SN/A removeInstsThisCycle = true; 10932292SN/A 10942292SN/A removeList.push(inst->getInstListIt()); 10951060SN/A} 10961060SN/A 10971060SN/Atemplate <class Impl> 10981060SN/Avoid 10991755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 11001060SN/A{ 11012733Sktlim@umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 11022292SN/A "[sn:%lli]\n", 11032303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 11041060SN/A 11052292SN/A removeInstsThisCycle = true; 11061060SN/A 11071060SN/A // Remove the front instruction. 11082292SN/A removeList.push(inst->getInstListIt()); 11091060SN/A} 11101060SN/A 11111060SN/Atemplate <class Impl> 11121060SN/Avoid 11132292SN/AFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 11141060SN/A{ 11152733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 11162292SN/A " list.\n", tid); 11171060SN/A 11182292SN/A ListIt end_it; 11191060SN/A 11202292SN/A bool rob_empty = false; 11212292SN/A 11222292SN/A if (instList.empty()) { 11232292SN/A return; 11242292SN/A } else if (rob.isEmpty(/*tid*/)) { 11252733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 11262292SN/A end_it = instList.begin(); 11272292SN/A rob_empty = true; 11282292SN/A } else { 11292292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 11302733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 11312292SN/A } 11322292SN/A 11332292SN/A removeInstsThisCycle = true; 11342292SN/A 11352292SN/A ListIt inst_it = instList.end(); 11362292SN/A 11372292SN/A inst_it--; 11382292SN/A 11392292SN/A // Walk through the instruction list, removing any instructions 11402292SN/A // that were inserted after the given instruction iterator, end_it. 11412292SN/A while (inst_it != end_it) { 11422292SN/A assert(!instList.empty()); 11432292SN/A 11442292SN/A squashInstIt(inst_it, tid); 11452292SN/A 11462292SN/A inst_it--; 11472292SN/A } 11482292SN/A 11492292SN/A // If the ROB was empty, then we actually need to remove the first 11502292SN/A // instruction as well. 11512292SN/A if (rob_empty) { 11522292SN/A squashInstIt(inst_it, tid); 11532292SN/A } 11541060SN/A} 11551060SN/A 11561060SN/Atemplate <class Impl> 11571060SN/Avoid 11582292SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 11592292SN/A unsigned tid) 11601062SN/A{ 11612292SN/A assert(!instList.empty()); 11622292SN/A 11632292SN/A removeInstsThisCycle = true; 11642292SN/A 11652292SN/A ListIt inst_iter = instList.end(); 11662292SN/A 11672292SN/A inst_iter--; 11682292SN/A 11692733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 11702292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 11712292SN/A tid, seq_num, (*inst_iter)->seqNum); 11721062SN/A 11732292SN/A while ((*inst_iter)->seqNum > seq_num) { 11741062SN/A 11752292SN/A bool break_loop = (inst_iter == instList.begin()); 11761062SN/A 11772292SN/A squashInstIt(inst_iter, tid); 11781062SN/A 11792292SN/A inst_iter--; 11801062SN/A 11812292SN/A if (break_loop) 11822292SN/A break; 11832292SN/A } 11842292SN/A} 11852292SN/A 11862292SN/Atemplate <class Impl> 11872292SN/Ainline void 11882292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 11892292SN/A{ 11902292SN/A if ((*instIt)->threadNumber == tid) { 11912733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 11922292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 11932292SN/A (*instIt)->threadNumber, 11942292SN/A (*instIt)->seqNum, 11952292SN/A (*instIt)->readPC()); 11961062SN/A 11971062SN/A // Mark it as squashed. 11982292SN/A (*instIt)->setSquashed(); 11992292SN/A 12002325SN/A // @todo: Formulate a consistent method for deleting 12012325SN/A // instructions from the instruction list 12022292SN/A // Remove the instruction from the list. 12032292SN/A removeList.push(instIt); 12042292SN/A } 12052292SN/A} 12062292SN/A 12072292SN/Atemplate <class Impl> 12082292SN/Avoid 12092292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 12102292SN/A{ 12112292SN/A while (!removeList.empty()) { 12122733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 12132292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 12142292SN/A (*removeList.front())->threadNumber, 12152292SN/A (*removeList.front())->seqNum, 12162292SN/A (*removeList.front())->readPC()); 12172292SN/A 12182292SN/A instList.erase(removeList.front()); 12192292SN/A 12202292SN/A removeList.pop(); 12211062SN/A } 12221062SN/A 12232292SN/A removeInstsThisCycle = false; 12241062SN/A} 12252325SN/A/* 12261062SN/Atemplate <class Impl> 12271062SN/Avoid 12281755SN/AFullO3CPU<Impl>::removeAllInsts() 12291060SN/A{ 12301060SN/A instList.clear(); 12311060SN/A} 12322325SN/A*/ 12331060SN/Atemplate <class Impl> 12341060SN/Avoid 12351755SN/AFullO3CPU<Impl>::dumpInsts() 12361060SN/A{ 12371060SN/A int num = 0; 12381060SN/A 12392292SN/A ListIt inst_list_it = instList.begin(); 12402292SN/A 12412292SN/A cprintf("Dumping Instruction List\n"); 12422292SN/A 12432292SN/A while (inst_list_it != instList.end()) { 12442292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 12452292SN/A "Squashed:%i\n\n", 12462292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 12472292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 12482292SN/A (*inst_list_it)->isSquashed()); 12491060SN/A inst_list_it++; 12501060SN/A ++num; 12511060SN/A } 12521060SN/A} 12532325SN/A/* 12541060SN/Atemplate <class Impl> 12551060SN/Avoid 12561755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 12571060SN/A{ 12581060SN/A iew.wakeDependents(inst); 12591060SN/A} 12602325SN/A*/ 12612292SN/Atemplate <class Impl> 12622292SN/Avoid 12632292SN/AFullO3CPU<Impl>::wakeCPU() 12642292SN/A{ 12652325SN/A if (activityRec.active() || tickEvent.scheduled()) { 12662325SN/A DPRINTF(Activity, "CPU already running.\n"); 12672292SN/A return; 12682292SN/A } 12692292SN/A 12702325SN/A DPRINTF(Activity, "Waking up CPU\n"); 12712325SN/A 12722325SN/A idleCycles += (curTick - 1) - lastRunningCycle; 12732292SN/A 12742292SN/A tickEvent.schedule(curTick); 12752292SN/A} 12762292SN/A 12772292SN/Atemplate <class Impl> 12782292SN/Aint 12792292SN/AFullO3CPU<Impl>::getFreeTid() 12802292SN/A{ 12812292SN/A for (int i=0; i < numThreads; i++) { 12822292SN/A if (!tids[i]) { 12832292SN/A tids[i] = true; 12842292SN/A return i; 12852292SN/A } 12862292SN/A } 12872292SN/A 12882292SN/A return -1; 12892292SN/A} 12902292SN/A 12912292SN/Atemplate <class Impl> 12922292SN/Avoid 12932292SN/AFullO3CPU<Impl>::doContextSwitch() 12942292SN/A{ 12952292SN/A if (contextSwitch) { 12962292SN/A 12972292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 12982292SN/A 12992292SN/A for (int tid=0; tid < cpuWaitList.size(); tid++) { 13002292SN/A activateWhenReady(tid); 13012292SN/A } 13022292SN/A 13032292SN/A if (cpuWaitList.size() == 0) 13042292SN/A contextSwitch = true; 13052292SN/A } 13062292SN/A} 13072292SN/A 13082292SN/Atemplate <class Impl> 13092292SN/Avoid 13102292SN/AFullO3CPU<Impl>::updateThreadPriority() 13112292SN/A{ 13122292SN/A if (activeThreads.size() > 1) 13132292SN/A { 13142292SN/A //DEFAULT TO ROUND ROBIN SCHEME 13152292SN/A //e.g. Move highest priority to end of thread list 13162292SN/A list<unsigned>::iterator list_begin = activeThreads.begin(); 13172292SN/A list<unsigned>::iterator list_end = activeThreads.end(); 13182292SN/A 13192292SN/A unsigned high_thread = *list_begin; 13202292SN/A 13212292SN/A activeThreads.erase(list_begin); 13222292SN/A 13232292SN/A activeThreads.push_back(high_thread); 13242292SN/A } 13252292SN/A} 13261060SN/A 13271755SN/A// Forward declaration of FullO3CPU. 13282818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1329