cpu.cc revision 2871
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 341858SN/A 351858SN/A#if FULL_SYSTEM 361060SN/A#include "sim/system.hh" 371060SN/A#else 381060SN/A#include "sim/process.hh" 391060SN/A#endif 401060SN/A 412325SN/A#include "cpu/activity.hh" 422683Sktlim@umich.edu#include "cpu/simple_thread.hh" 432680Sktlim@umich.edu#include "cpu/thread_context.hh" 442817Sksewell@umich.edu#include "cpu/o3/isa_specific.hh" 451717SN/A#include "cpu/o3/cpu.hh" 461060SN/A 472325SN/A#include "sim/root.hh" 482292SN/A#include "sim/stat_control.hh" 492292SN/A 502794Sktlim@umich.edu#if USE_CHECKER 512794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 522794Sktlim@umich.edu#endif 532794Sktlim@umich.edu 541060SN/Ausing namespace std; 552669Sktlim@umich.eduusing namespace TheISA; 561060SN/A 572733Sktlim@umich.eduBaseO3CPU::BaseO3CPU(Params *params) 582292SN/A : BaseCPU(params), cpu_id(0) 591060SN/A{ 601060SN/A} 611060SN/A 622292SN/Avoid 632733Sktlim@umich.eduBaseO3CPU::regStats() 642292SN/A{ 652292SN/A BaseCPU::regStats(); 662292SN/A} 672292SN/A 681060SN/Atemplate <class Impl> 691755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 701060SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 711060SN/A{ 721060SN/A} 731060SN/A 741060SN/Atemplate <class Impl> 751060SN/Avoid 761755SN/AFullO3CPU<Impl>::TickEvent::process() 771060SN/A{ 781060SN/A cpu->tick(); 791060SN/A} 801060SN/A 811060SN/Atemplate <class Impl> 821060SN/Aconst char * 831755SN/AFullO3CPU<Impl>::TickEvent::description() 841060SN/A{ 851755SN/A return "FullO3CPU tick event"; 861060SN/A} 871060SN/A 881060SN/Atemplate <class Impl> 892829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 902829Sksewell@umich.edu : Event(&mainEventQueue, CPU_Tick_Pri) 912829Sksewell@umich.edu{ 922829Sksewell@umich.edu} 932829Sksewell@umich.edu 942829Sksewell@umich.edutemplate <class Impl> 952829Sksewell@umich.eduvoid 962829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 972829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 982829Sksewell@umich.edu{ 992829Sksewell@umich.edu tid = thread_num; 1002829Sksewell@umich.edu cpu = thread_cpu; 1012829Sksewell@umich.edu} 1022829Sksewell@umich.edu 1032829Sksewell@umich.edutemplate <class Impl> 1042829Sksewell@umich.eduvoid 1052829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1062829Sksewell@umich.edu{ 1072829Sksewell@umich.edu cpu->activateThread(tid); 1082829Sksewell@umich.edu} 1092829Sksewell@umich.edu 1102829Sksewell@umich.edutemplate <class Impl> 1112829Sksewell@umich.educonst char * 1122829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::description() 1132829Sksewell@umich.edu{ 1142829Sksewell@umich.edu return "FullO3CPU \"Activate Thread\" event"; 1152829Sksewell@umich.edu} 1162829Sksewell@umich.edu 1172829Sksewell@umich.edutemplate <class Impl> 1182292SN/AFullO3CPU<Impl>::FullO3CPU(Params *params) 1192733Sktlim@umich.edu : BaseO3CPU(params), 1201060SN/A tickEvent(this), 1212292SN/A removeInstsThisCycle(false), 1221060SN/A fetch(params), 1231060SN/A decode(params), 1241060SN/A rename(params), 1251060SN/A iew(params), 1261060SN/A commit(params), 1271060SN/A 1282292SN/A regFile(params->numPhysIntRegs, params->numPhysFloatRegs), 1291060SN/A 1302831Sksewell@umich.edu freeList(params->numberOfThreads, 1312292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1322292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1331060SN/A 1342292SN/A rob(params->numROBEntries, params->squashWidth, 1352292SN/A params->smtROBPolicy, params->smtROBThreshold, 1362292SN/A params->numberOfThreads), 1371060SN/A 1382831Sksewell@umich.edu scoreboard(params->numberOfThreads, 1392292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1402292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1412292SN/A TheISA::NumMiscRegs * number_of_threads, 1422292SN/A TheISA::ZeroReg), 1431060SN/A 1441060SN/A // For now just have these time buffers be pretty big. 1452325SN/A // @todo: Make these time buffer sizes parameters or derived 1462325SN/A // from latencies 1471061SN/A timeBuffer(5, 5), 1481061SN/A fetchQueue(5, 5), 1491061SN/A decodeQueue(5, 5), 1501061SN/A renameQueue(5, 5), 1511061SN/A iewQueue(5, 5), 1522325SN/A activityRec(NumStages, 10, params->activity), 1531060SN/A 1541060SN/A globalSeqNum(1), 1551060SN/A 1561858SN/A#if FULL_SYSTEM 1572292SN/A system(params->system), 1581060SN/A physmem(system->physmem), 1591060SN/A#endif // FULL_SYSTEM 1602292SN/A mem(params->mem), 1612843Sktlim@umich.edu drainCount(0), 1622316SN/A deferRegistration(params->deferRegistration), 1632316SN/A numThreads(number_of_threads) 1641060SN/A{ 1651060SN/A _status = Idle; 1661681SN/A 1672733Sktlim@umich.edu checker = NULL; 1682733Sktlim@umich.edu 1692794Sktlim@umich.edu if (params->checker) { 1702733Sktlim@umich.edu#if USE_CHECKER 1712316SN/A BaseCPU *temp_checker = params->checker; 1722316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 1732316SN/A checker->setMemory(mem); 1742316SN/A#if FULL_SYSTEM 1752316SN/A checker->setSystem(params->system); 1762316SN/A#endif 1772794Sktlim@umich.edu#else 1782794Sktlim@umich.edu panic("Checker enabled but not compiled in!"); 1792794Sktlim@umich.edu#endif // USE_CHECKER 1802316SN/A } 1812316SN/A 1821858SN/A#if !FULL_SYSTEM 1832292SN/A thread.resize(number_of_threads); 1842292SN/A tids.resize(number_of_threads); 1851681SN/A#endif 1861681SN/A 1872325SN/A // The stages also need their CPU pointer setup. However this 1882325SN/A // must be done at the upper level CPU because they have pointers 1892325SN/A // to the upper level CPU, and not this FullO3CPU. 1901060SN/A 1912292SN/A // Set up Pointers to the activeThreads list for each stage 1922292SN/A fetch.setActiveThreads(&activeThreads); 1932292SN/A decode.setActiveThreads(&activeThreads); 1942292SN/A rename.setActiveThreads(&activeThreads); 1952292SN/A iew.setActiveThreads(&activeThreads); 1962292SN/A commit.setActiveThreads(&activeThreads); 1971060SN/A 1981060SN/A // Give each of the stages the time buffer they will use. 1991060SN/A fetch.setTimeBuffer(&timeBuffer); 2001060SN/A decode.setTimeBuffer(&timeBuffer); 2011060SN/A rename.setTimeBuffer(&timeBuffer); 2021060SN/A iew.setTimeBuffer(&timeBuffer); 2031060SN/A commit.setTimeBuffer(&timeBuffer); 2041060SN/A 2051060SN/A // Also setup each of the stages' queues. 2061060SN/A fetch.setFetchQueue(&fetchQueue); 2071060SN/A decode.setFetchQueue(&fetchQueue); 2082292SN/A commit.setFetchQueue(&fetchQueue); 2091060SN/A decode.setDecodeQueue(&decodeQueue); 2101060SN/A rename.setDecodeQueue(&decodeQueue); 2111060SN/A rename.setRenameQueue(&renameQueue); 2121060SN/A iew.setRenameQueue(&renameQueue); 2131060SN/A iew.setIEWQueue(&iewQueue); 2141060SN/A commit.setIEWQueue(&iewQueue); 2151060SN/A commit.setRenameQueue(&renameQueue); 2161060SN/A 2172316SN/A commit.setFetchStage(&fetch); 2182292SN/A commit.setIEWStage(&iew); 2192292SN/A rename.setIEWStage(&iew); 2202292SN/A rename.setCommitStage(&commit); 2212292SN/A 2222292SN/A#if !FULL_SYSTEM 2232307SN/A int active_threads = params->workload.size(); 2242831Sksewell@umich.edu 2252831Sksewell@umich.edu if (active_threads > Impl::MaxThreads) { 2262831Sksewell@umich.edu panic("Workload Size too large. Increase the 'MaxThreads'" 2272831Sksewell@umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2282831Sksewell@umich.edu "edit your workload size."); 2292831Sksewell@umich.edu } 2302292SN/A#else 2312307SN/A int active_threads = 1; 2322292SN/A#endif 2332292SN/A 2342316SN/A //Make Sure That this a Valid Architeture 2352292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2362292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2372292SN/A 2382292SN/A rename.setScoreboard(&scoreboard); 2392292SN/A iew.setScoreboard(&scoreboard); 2402292SN/A 2411060SN/A // Setup the rename map for whichever stages need it. 2422292SN/A PhysRegIndex lreg_idx = 0; 2432292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2441060SN/A 2452292SN/A for (int tid=0; tid < numThreads; tid++) { 2462307SN/A bool bindRegs = (tid <= active_threads - 1); 2472292SN/A 2482292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2492292SN/A params->numPhysIntRegs, 2502325SN/A lreg_idx, //Index for Logical. Regs 2512292SN/A 2522292SN/A TheISA::NumFloatRegs, 2532292SN/A params->numPhysFloatRegs, 2542325SN/A freg_idx, //Index for Float Regs 2552292SN/A 2562292SN/A TheISA::NumMiscRegs, 2572292SN/A 2582292SN/A TheISA::ZeroReg, 2592292SN/A TheISA::ZeroReg, 2602292SN/A 2612292SN/A tid, 2622292SN/A false); 2632292SN/A 2642292SN/A renameMap[tid].init(TheISA::NumIntRegs, 2652292SN/A params->numPhysIntRegs, 2662325SN/A lreg_idx, //Index for Logical. Regs 2672292SN/A 2682292SN/A TheISA::NumFloatRegs, 2692292SN/A params->numPhysFloatRegs, 2702325SN/A freg_idx, //Index for Float Regs 2712292SN/A 2722292SN/A TheISA::NumMiscRegs, 2732292SN/A 2742292SN/A TheISA::ZeroReg, 2752292SN/A TheISA::ZeroReg, 2762292SN/A 2772292SN/A tid, 2782292SN/A bindRegs); 2792292SN/A } 2802292SN/A 2812292SN/A rename.setRenameMap(renameMap); 2822292SN/A commit.setRenameMap(commitRenameMap); 2832292SN/A 2842292SN/A // Give renameMap & rename stage access to the freeList; 2852292SN/A for (int i=0; i < numThreads; i++) { 2862292SN/A renameMap[i].setFreeList(&freeList); 2872292SN/A } 2881060SN/A rename.setFreeList(&freeList); 2892292SN/A 2901060SN/A // Setup the ROB for whichever stages need it. 2911060SN/A commit.setROB(&rob); 2922292SN/A 2932292SN/A lastRunningCycle = curTick; 2942292SN/A 2952829Sksewell@umich.edu lastActivatedCycle = -1; 2962829Sksewell@umich.edu 2972292SN/A contextSwitch = false; 2981060SN/A} 2991060SN/A 3001060SN/Atemplate <class Impl> 3011755SN/AFullO3CPU<Impl>::~FullO3CPU() 3021060SN/A{ 3031060SN/A} 3041060SN/A 3051060SN/Atemplate <class Impl> 3061060SN/Avoid 3071755SN/AFullO3CPU<Impl>::fullCPURegStats() 3081062SN/A{ 3092733Sktlim@umich.edu BaseO3CPU::regStats(); 3102292SN/A 3112733Sktlim@umich.edu // Register any of the O3CPU's stats here. 3122292SN/A timesIdled 3132292SN/A .name(name() + ".timesIdled") 3142292SN/A .desc("Number of times that the entire CPU went into an idle state and" 3152292SN/A " unscheduled itself") 3162292SN/A .prereq(timesIdled); 3172292SN/A 3182292SN/A idleCycles 3192292SN/A .name(name() + ".idleCycles") 3202292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 3212292SN/A "to idling") 3222292SN/A .prereq(idleCycles); 3232292SN/A 3242292SN/A // Number of Instructions simulated 3252292SN/A // -------------------------------- 3262292SN/A // Should probably be in Base CPU but need templated 3272292SN/A // MaxThreads so put in here instead 3282292SN/A committedInsts 3292292SN/A .init(numThreads) 3302292SN/A .name(name() + ".committedInsts") 3312292SN/A .desc("Number of Instructions Simulated"); 3322292SN/A 3332292SN/A totalCommittedInsts 3342292SN/A .name(name() + ".committedInsts_total") 3352292SN/A .desc("Number of Instructions Simulated"); 3362292SN/A 3372292SN/A cpi 3382292SN/A .name(name() + ".cpi") 3392292SN/A .desc("CPI: Cycles Per Instruction") 3402292SN/A .precision(6); 3412292SN/A cpi = simTicks / committedInsts; 3422292SN/A 3432292SN/A totalCpi 3442292SN/A .name(name() + ".cpi_total") 3452292SN/A .desc("CPI: Total CPI of All Threads") 3462292SN/A .precision(6); 3472292SN/A totalCpi = simTicks / totalCommittedInsts; 3482292SN/A 3492292SN/A ipc 3502292SN/A .name(name() + ".ipc") 3512292SN/A .desc("IPC: Instructions Per Cycle") 3522292SN/A .precision(6); 3532292SN/A ipc = committedInsts / simTicks; 3542292SN/A 3552292SN/A totalIpc 3562292SN/A .name(name() + ".ipc_total") 3572292SN/A .desc("IPC: Total IPC of All Threads") 3582292SN/A .precision(6); 3592292SN/A totalIpc = totalCommittedInsts / simTicks; 3602292SN/A 3611062SN/A} 3621062SN/A 3631062SN/Atemplate <class Impl> 3642871Sktlim@umich.eduPort * 3652871Sktlim@umich.eduFullO3CPU<Impl>::getPort(const std::string &if_name, int idx) 3662871Sktlim@umich.edu{ 3672871Sktlim@umich.edu if (if_name == "dcache_port") 3682871Sktlim@umich.edu return iew.getDcachePort(); 3692871Sktlim@umich.edu else if (if_name == "icache_port") 3702871Sktlim@umich.edu return fetch.getIcachePort(); 3712871Sktlim@umich.edu else 3722871Sktlim@umich.edu panic("No Such Port\n"); 3732871Sktlim@umich.edu} 3742871Sktlim@umich.edu 3752871Sktlim@umich.edutemplate <class Impl> 3761062SN/Avoid 3771755SN/AFullO3CPU<Impl>::tick() 3781060SN/A{ 3792733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 3801060SN/A 3812292SN/A ++numCycles; 3822292SN/A 3832325SN/A// activity = false; 3842292SN/A 3852292SN/A //Tick each of the stages 3861060SN/A fetch.tick(); 3871060SN/A 3881060SN/A decode.tick(); 3891060SN/A 3901060SN/A rename.tick(); 3911060SN/A 3921060SN/A iew.tick(); 3931060SN/A 3941060SN/A commit.tick(); 3951060SN/A 3962292SN/A#if !FULL_SYSTEM 3972292SN/A doContextSwitch(); 3982292SN/A#endif 3992292SN/A 4002292SN/A // Now advance the time buffers 4011060SN/A timeBuffer.advance(); 4021060SN/A 4031060SN/A fetchQueue.advance(); 4041060SN/A decodeQueue.advance(); 4051060SN/A renameQueue.advance(); 4061060SN/A iewQueue.advance(); 4071060SN/A 4082325SN/A activityRec.advance(); 4092292SN/A 4102292SN/A if (removeInstsThisCycle) { 4112292SN/A cleanUpRemovedInsts(); 4122292SN/A } 4132292SN/A 4142325SN/A if (!tickEvent.scheduled()) { 4152867Sktlim@umich.edu if (_status == SwitchedOut || 4162867Sktlim@umich.edu getState() == SimObject::DrainedTiming) { 4172325SN/A // increment stat 4182325SN/A lastRunningCycle = curTick; 4192325SN/A } else if (!activityRec.active()) { 4202325SN/A lastRunningCycle = curTick; 4212325SN/A timesIdled++; 4222325SN/A } else { 4232325SN/A tickEvent.schedule(curTick + cycles(1)); 4242325SN/A } 4252292SN/A } 4262292SN/A 4272292SN/A#if !FULL_SYSTEM 4282292SN/A updateThreadPriority(); 4292292SN/A#endif 4302292SN/A 4311060SN/A} 4321060SN/A 4331060SN/Atemplate <class Impl> 4341060SN/Avoid 4351755SN/AFullO3CPU<Impl>::init() 4361060SN/A{ 4372307SN/A if (!deferRegistration) { 4382680Sktlim@umich.edu registerThreadContexts(); 4392292SN/A } 4401060SN/A 4412292SN/A // Set inSyscall so that the CPU doesn't squash when initially 4422292SN/A // setting up registers. 4432292SN/A for (int i = 0; i < number_of_threads; ++i) 4442292SN/A thread[i]->inSyscall = true; 4452292SN/A 4462292SN/A for (int tid=0; tid < number_of_threads; tid++) { 4471858SN/A#if FULL_SYSTEM 4482680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 4491681SN/A#else 4502680Sktlim@umich.edu ThreadContext *src_tc = thread[tid]->getTC(); 4511681SN/A#endif 4522292SN/A // Threads start in the Suspended State 4532680Sktlim@umich.edu if (src_tc->status() != ThreadContext::Suspended) { 4542292SN/A continue; 4551060SN/A } 4561060SN/A 4572292SN/A#if FULL_SYSTEM 4582680Sktlim@umich.edu TheISA::initCPU(src_tc, src_tc->readCpuId()); 4592292SN/A#endif 4602292SN/A } 4612292SN/A 4622292SN/A // Clear inSyscall. 4632292SN/A for (int i = 0; i < number_of_threads; ++i) 4642292SN/A thread[i]->inSyscall = false; 4652292SN/A 4662316SN/A // Initialize stages. 4672292SN/A fetch.initStage(); 4682292SN/A iew.initStage(); 4692292SN/A rename.initStage(); 4702292SN/A commit.initStage(); 4712292SN/A 4722292SN/A commit.setThreads(thread); 4732292SN/A} 4742292SN/A 4752292SN/Atemplate <class Impl> 4762292SN/Avoid 4772292SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 4782292SN/A{ 4792847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 4802292SN/A // Will change now that the PC and thread state is internal to the CPU 4812683Sktlim@umich.edu // and not in the ThreadContext. 4822292SN/A#if FULL_SYSTEM 4832680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 4842292SN/A#else 4852847Sksewell@umich.edu ThreadContext *src_tc = tcBase(tid); 4862292SN/A#endif 4872292SN/A 4882292SN/A //Bind Int Regs to Rename Map 4892292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 4902292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 4912292SN/A 4922292SN/A renameMap[tid].setEntry(ireg,phys_reg); 4932292SN/A scoreboard.setReg(phys_reg); 4942292SN/A } 4952292SN/A 4962292SN/A //Bind Float Regs to Rename Map 4972292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 4982292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 4992292SN/A 5002292SN/A renameMap[tid].setEntry(freg,phys_reg); 5012292SN/A scoreboard.setReg(phys_reg); 5022292SN/A } 5032292SN/A 5042292SN/A //Copy Thread Data Into RegFile 5052847Sksewell@umich.edu //this->copyFromTC(tid); 5062292SN/A 5072847Sksewell@umich.edu //Set PC/NPC/NNPC 5082847Sksewell@umich.edu setPC(src_tc->readPC(), tid); 5092847Sksewell@umich.edu setNextPC(src_tc->readNextPC(), tid); 5102847Sksewell@umich.edu#if THE_ISA != ALPHA_ISA 5112847Sksewell@umich.edu setNextNPC(src_tc->readNextNPC(), tid); 5122847Sksewell@umich.edu#endif 5132292SN/A 5142680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 5152292SN/A 5162292SN/A activateContext(tid,1); 5172292SN/A 5182292SN/A //Reset ROB/IQ/LSQ Entries 5192292SN/A commit.rob->resetEntries(); 5202292SN/A iew.resetEntries(); 5212292SN/A} 5222292SN/A 5232292SN/Atemplate <class Impl> 5242292SN/Avoid 5252292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 5262292SN/A{ 5272847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread from CPU."); 5282847Sksewell@umich.edu 5292847Sksewell@umich.edu // Copy Thread Data From RegFile 5302847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 5312847Sksewell@umich.edu //this->copyToTC(tid); 5322847Sksewell@umich.edu 5332847Sksewell@umich.edu // Unbind Int Regs from Rename Map 5342292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 5352292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 5362292SN/A 5372292SN/A scoreboard.unsetReg(phys_reg); 5382292SN/A freeList.addReg(phys_reg); 5392292SN/A } 5402292SN/A 5412847Sksewell@umich.edu // Unbind Float Regs from Rename Map 5422292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 5432292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 5442292SN/A 5452292SN/A scoreboard.unsetReg(phys_reg); 5462292SN/A freeList.addReg(phys_reg); 5472292SN/A } 5482292SN/A 5492847Sksewell@umich.edu // Squash Throughout Pipeline 5502292SN/A fetch.squash(0,tid); 5512292SN/A decode.squash(tid); 5522292SN/A rename.squash(tid); 5532292SN/A 5542292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 5552292SN/A 5562847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 5572292SN/A if (activeThreads.size() >= 1) { 5582292SN/A commit.rob->resetEntries(); 5592292SN/A iew.resetEntries(); 5602292SN/A } 5612292SN/A} 5622292SN/A 5632292SN/A 5642292SN/Atemplate <class Impl> 5652292SN/Avoid 5662292SN/AFullO3CPU<Impl>::activateWhenReady(int tid) 5672292SN/A{ 5682733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 5692292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 5702292SN/A tid); 5712292SN/A 5722292SN/A bool ready = true; 5732292SN/A 5742292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 5752733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5762292SN/A "Phys. Int. Regs.\n", 5772292SN/A tid); 5782292SN/A ready = false; 5792292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 5802733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5812292SN/A "Phys. Float. Regs.\n", 5822292SN/A tid); 5832292SN/A ready = false; 5842292SN/A } else if (commit.rob->numFreeEntries() >= 5852292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 5862733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5872292SN/A "ROB entries.\n", 5882292SN/A tid); 5892292SN/A ready = false; 5902292SN/A } else if (iew.instQueue.numFreeEntries() >= 5912292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 5922733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5932292SN/A "IQ entries.\n", 5942292SN/A tid); 5952292SN/A ready = false; 5962292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 5972292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 5982733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5992292SN/A "LSQ entries.\n", 6002292SN/A tid); 6012292SN/A ready = false; 6022292SN/A } 6032292SN/A 6042292SN/A if (ready) { 6052292SN/A insertThread(tid); 6062292SN/A 6072292SN/A contextSwitch = false; 6082292SN/A 6092292SN/A cpuWaitList.remove(tid); 6102292SN/A } else { 6112292SN/A suspendContext(tid); 6122292SN/A 6132292SN/A //blocks fetch 6142292SN/A contextSwitch = true; 6152292SN/A 6162292SN/A //do waitlist 6172292SN/A cpuWaitList.push_back(tid); 6181060SN/A } 6191060SN/A} 6201060SN/A 6211060SN/Atemplate <class Impl> 6221060SN/Avoid 6232829Sksewell@umich.eduFullO3CPU<Impl>::activateThread(unsigned int tid) 6241060SN/A{ 6252292SN/A list<unsigned>::iterator isActive = find( 6262292SN/A activeThreads.begin(), activeThreads.end(), tid); 6272292SN/A 6282292SN/A if (isActive == activeThreads.end()) { 6292829Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6302292SN/A tid); 6312292SN/A 6322292SN/A activeThreads.push_back(tid); 6332292SN/A } 6342829Sksewell@umich.edu} 6352292SN/A 6361060SN/A 6372829Sksewell@umich.edutemplate <class Impl> 6382829Sksewell@umich.eduvoid 6392829Sksewell@umich.eduFullO3CPU<Impl>::activateContext(int tid, int delay) 6402829Sksewell@umich.edu{ 6412829Sksewell@umich.edu // Needs to set each stage to running as well. 6422829Sksewell@umich.edu if (delay){ 6432829Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 6442829Sksewell@umich.edu "on cycle %d\n", tid, curTick + cycles(delay)); 6452829Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 6462829Sksewell@umich.edu } else { 6472829Sksewell@umich.edu activateThread(tid); 6482829Sksewell@umich.edu } 6491060SN/A 6502829Sksewell@umich.edu if(lastActivatedCycle < curTick) { 6512829Sksewell@umich.edu scheduleTickEvent(delay); 6522292SN/A 6532829Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 6542829Sksewell@umich.edu // deschedule itself. 6552829Sksewell@umich.edu activityRec.activity(); 6562829Sksewell@umich.edu fetch.wakeFromQuiesce(); 6572829Sksewell@umich.edu 6582829Sksewell@umich.edu lastActivatedCycle = curTick; 6592829Sksewell@umich.edu 6602829Sksewell@umich.edu _status = Running; 6612829Sksewell@umich.edu } 6621060SN/A} 6631060SN/A 6641060SN/Atemplate <class Impl> 6651060SN/Avoid 6662292SN/AFullO3CPU<Impl>::suspendContext(int tid) 6671060SN/A{ 6682847Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 6692292SN/A unscheduleTickEvent(); 6702292SN/A _status = Idle; 6712292SN/A/* 6722292SN/A //Remove From Active List, if Active 6732292SN/A list<unsigned>::iterator isActive = find( 6742292SN/A activeThreads.begin(), activeThreads.end(), tid); 6752292SN/A 6762292SN/A if (isActive != activeThreads.end()) { 6772733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6782292SN/A tid); 6792292SN/A activeThreads.erase(isActive); 6802292SN/A } 6812292SN/A*/ 6821060SN/A} 6831060SN/A 6841060SN/Atemplate <class Impl> 6851060SN/Avoid 6862292SN/AFullO3CPU<Impl>::deallocateContext(int tid) 6871060SN/A{ 6882847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Deallocating Thread Context", tid); 6892847Sksewell@umich.edu 6902292SN/A //Remove From Active List, if Active 6912847Sksewell@umich.edu list<unsigned>::iterator thread_it = 6922847Sksewell@umich.edu find(activeThreads.begin(), activeThreads.end(), tid); 6932292SN/A 6942847Sksewell@umich.edu if (thread_it != activeThreads.end()) { 6952733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6962292SN/A tid); 6972847Sksewell@umich.edu activeThreads.erase(thread_it); 6982292SN/A 6992292SN/A removeThread(tid); 7002292SN/A } 7011060SN/A} 7021060SN/A 7031060SN/Atemplate <class Impl> 7041060SN/Avoid 7052292SN/AFullO3CPU<Impl>::haltContext(int tid) 7061060SN/A{ 7072847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halting Thread Context", tid); 7082292SN/A/* 7092292SN/A //Remove From Active List, if Active 7102292SN/A list<unsigned>::iterator isActive = find( 7112292SN/A activeThreads.begin(), activeThreads.end(), tid); 7122292SN/A 7132292SN/A if (isActive != activeThreads.end()) { 7142733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 7152292SN/A tid); 7162292SN/A activeThreads.erase(isActive); 7172292SN/A 7182292SN/A removeThread(tid); 7192292SN/A } 7202292SN/A*/ 7211060SN/A} 7221060SN/A 7231060SN/Atemplate <class Impl> 7242864Sktlim@umich.eduvoid 7252864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 7262864Sktlim@umich.edu{ 7272864Sktlim@umich.edu SERIALIZE_ENUM(_status); 7282864Sktlim@umich.edu BaseCPU::serialize(os); 7292864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 7302864Sktlim@umich.edu tickEvent.serialize(os); 7312864Sktlim@umich.edu 7322864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 7332864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 7342864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 7352864Sktlim@umich.edu static SimpleThread temp; 7362864Sktlim@umich.edu 7372864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 7382864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 7392864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 7402864Sktlim@umich.edu temp.serialize(os); 7412864Sktlim@umich.edu } 7422864Sktlim@umich.edu} 7432864Sktlim@umich.edu 7442864Sktlim@umich.edutemplate <class Impl> 7452864Sktlim@umich.eduvoid 7462864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 7472864Sktlim@umich.edu{ 7482864Sktlim@umich.edu UNSERIALIZE_ENUM(_status); 7492864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 7502864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 7512864Sktlim@umich.edu 7522864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 7532864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 7542864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 7552864Sktlim@umich.edu static SimpleThread temp; 7562864Sktlim@umich.edu 7572864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 7582864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 7592864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 7602864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 7612864Sktlim@umich.edu } 7622864Sktlim@umich.edu} 7632864Sktlim@umich.edu 7642864Sktlim@umich.edutemplate <class Impl> 7652843Sktlim@umich.edubool 7662843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 7671060SN/A{ 7682843Sktlim@umich.edu drainCount = 0; 7692843Sktlim@umich.edu fetch.drain(); 7702843Sktlim@umich.edu decode.drain(); 7712843Sktlim@umich.edu rename.drain(); 7722843Sktlim@umich.edu iew.drain(); 7732843Sktlim@umich.edu commit.drain(); 7742325SN/A 7752325SN/A // Wake the CPU and record activity so everything can drain out if 7762863Sktlim@umich.edu // the CPU was not able to immediately drain. 7772864Sktlim@umich.edu if (getState() != SimObject::DrainedTiming) { 7782864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 7792864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 7802864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 7812864Sktlim@umich.edu // process on the drain event. 7822864Sktlim@umich.edu drainEvent = drain_event; 7832864Sktlim@umich.edu 7842863Sktlim@umich.edu wakeCPU(); 7852863Sktlim@umich.edu activityRec.activity(); 7862843Sktlim@umich.edu 7872863Sktlim@umich.edu return false; 7882863Sktlim@umich.edu } else { 7892863Sktlim@umich.edu return true; 7902863Sktlim@umich.edu } 7912316SN/A} 7922310SN/A 7932316SN/Atemplate <class Impl> 7942316SN/Avoid 7952843Sktlim@umich.eduFullO3CPU<Impl>::resume() 7962316SN/A{ 7972843Sktlim@umich.edu fetch.resume(); 7982843Sktlim@umich.edu decode.resume(); 7992843Sktlim@umich.edu rename.resume(); 8002843Sktlim@umich.edu iew.resume(); 8012843Sktlim@umich.edu commit.resume(); 8022316SN/A 8032864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 8042864Sktlim@umich.edu return; 8052864Sktlim@umich.edu 8062843Sktlim@umich.edu if (!tickEvent.scheduled()) 8072843Sktlim@umich.edu tickEvent.schedule(curTick); 8082843Sktlim@umich.edu _status = Running; 8092867Sktlim@umich.edu changeState(SimObject::Timing); 8102843Sktlim@umich.edu} 8112316SN/A 8122843Sktlim@umich.edutemplate <class Impl> 8132843Sktlim@umich.eduvoid 8142843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 8152843Sktlim@umich.edu{ 8162843Sktlim@umich.edu if (++drainCount == NumStages) { 8172316SN/A if (tickEvent.scheduled()) 8182316SN/A tickEvent.squash(); 8192863Sktlim@umich.edu 8202864Sktlim@umich.edu changeState(SimObject::DrainedTiming); 8212863Sktlim@umich.edu 8222863Sktlim@umich.edu if (drainEvent) { 8232863Sktlim@umich.edu drainEvent->process(); 8242863Sktlim@umich.edu drainEvent = NULL; 8252863Sktlim@umich.edu } 8262310SN/A } 8272843Sktlim@umich.edu assert(drainCount <= 5); 8282843Sktlim@umich.edu} 8292843Sktlim@umich.edu 8302843Sktlim@umich.edutemplate <class Impl> 8312843Sktlim@umich.eduvoid 8322843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 8332843Sktlim@umich.edu{ 8342843Sktlim@umich.edu fetch.switchOut(); 8352843Sktlim@umich.edu rename.switchOut(); 8362843Sktlim@umich.edu commit.switchOut(); 8372843Sktlim@umich.edu instList.clear(); 8382843Sktlim@umich.edu while (!removeList.empty()) { 8392843Sktlim@umich.edu removeList.pop(); 8402843Sktlim@umich.edu } 8412843Sktlim@umich.edu 8422843Sktlim@umich.edu _status = SwitchedOut; 8432843Sktlim@umich.edu#if USE_CHECKER 8442843Sktlim@umich.edu if (checker) 8452843Sktlim@umich.edu checker->switchOut(); 8462843Sktlim@umich.edu#endif 8471060SN/A} 8481060SN/A 8491060SN/Atemplate <class Impl> 8501060SN/Avoid 8511755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 8521060SN/A{ 8532325SN/A // Flush out any old data from the time buffers. 8542325SN/A for (int i = 0; i < 10; ++i) { 8552307SN/A timeBuffer.advance(); 8562307SN/A fetchQueue.advance(); 8572307SN/A decodeQueue.advance(); 8582307SN/A renameQueue.advance(); 8592307SN/A iewQueue.advance(); 8602307SN/A } 8612307SN/A 8622325SN/A activityRec.reset(); 8632307SN/A 8641060SN/A BaseCPU::takeOverFrom(oldCPU); 8651060SN/A 8662307SN/A fetch.takeOverFrom(); 8672307SN/A decode.takeOverFrom(); 8682307SN/A rename.takeOverFrom(); 8692307SN/A iew.takeOverFrom(); 8702307SN/A commit.takeOverFrom(); 8712307SN/A 8721060SN/A assert(!tickEvent.scheduled()); 8731060SN/A 8742325SN/A // @todo: Figure out how to properly select the tid to put onto 8752325SN/A // the active threads list. 8762307SN/A int tid = 0; 8772307SN/A 8782307SN/A list<unsigned>::iterator isActive = find( 8792307SN/A activeThreads.begin(), activeThreads.end(), tid); 8802307SN/A 8812307SN/A if (isActive == activeThreads.end()) { 8822325SN/A //May Need to Re-code this if the delay variable is the delay 8832325SN/A //needed for thread to activate 8842733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 8852307SN/A tid); 8862307SN/A 8872307SN/A activeThreads.push_back(tid); 8882307SN/A } 8892307SN/A 8902325SN/A // Set all statuses to active, schedule the CPU's tick event. 8912307SN/A // @todo: Fix up statuses so this is handled properly 8922680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 8932680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 8942680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 8951681SN/A _status = Running; 8961681SN/A tickEvent.schedule(curTick); 8971681SN/A } 8981060SN/A } 8992307SN/A if (!tickEvent.scheduled()) 9002307SN/A tickEvent.schedule(curTick); 9011060SN/A} 9021060SN/A 9031060SN/Atemplate <class Impl> 9041060SN/Auint64_t 9051755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 9061060SN/A{ 9071060SN/A return regFile.readIntReg(reg_idx); 9081060SN/A} 9091060SN/A 9101060SN/Atemplate <class Impl> 9112455SN/AFloatReg 9122455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 9131060SN/A{ 9142455SN/A return regFile.readFloatReg(reg_idx, width); 9151060SN/A} 9161060SN/A 9171060SN/Atemplate <class Impl> 9182455SN/AFloatReg 9192455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 9201060SN/A{ 9212455SN/A return regFile.readFloatReg(reg_idx); 9221060SN/A} 9231060SN/A 9241060SN/Atemplate <class Impl> 9252455SN/AFloatRegBits 9262455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 9271060SN/A{ 9282455SN/A return regFile.readFloatRegBits(reg_idx, width); 9292455SN/A} 9302455SN/A 9312455SN/Atemplate <class Impl> 9322455SN/AFloatRegBits 9332455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 9342455SN/A{ 9352455SN/A return regFile.readFloatRegBits(reg_idx); 9361060SN/A} 9371060SN/A 9381060SN/Atemplate <class Impl> 9391060SN/Avoid 9401755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 9411060SN/A{ 9421060SN/A regFile.setIntReg(reg_idx, val); 9431060SN/A} 9441060SN/A 9451060SN/Atemplate <class Impl> 9461060SN/Avoid 9472455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 9481060SN/A{ 9492455SN/A regFile.setFloatReg(reg_idx, val, width); 9501060SN/A} 9511060SN/A 9521060SN/Atemplate <class Impl> 9531060SN/Avoid 9542455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 9551060SN/A{ 9562455SN/A regFile.setFloatReg(reg_idx, val); 9571060SN/A} 9581060SN/A 9591060SN/Atemplate <class Impl> 9601060SN/Avoid 9612455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 9621060SN/A{ 9632455SN/A regFile.setFloatRegBits(reg_idx, val, width); 9642455SN/A} 9652455SN/A 9662455SN/Atemplate <class Impl> 9672455SN/Avoid 9682455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 9692455SN/A{ 9702455SN/A regFile.setFloatRegBits(reg_idx, val); 9711060SN/A} 9721060SN/A 9731060SN/Atemplate <class Impl> 9741060SN/Auint64_t 9752292SN/AFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 9761060SN/A{ 9772292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 9782292SN/A 9792292SN/A return regFile.readIntReg(phys_reg); 9802292SN/A} 9812292SN/A 9822292SN/Atemplate <class Impl> 9832292SN/Afloat 9842292SN/AFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 9852292SN/A{ 9862307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 9872307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 9882292SN/A 9892669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 9902292SN/A} 9912292SN/A 9922292SN/Atemplate <class Impl> 9932292SN/Adouble 9942292SN/AFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 9952292SN/A{ 9962307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 9972307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 9982292SN/A 9992669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 10002292SN/A} 10012292SN/A 10022292SN/Atemplate <class Impl> 10032292SN/Auint64_t 10042292SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 10052292SN/A{ 10062307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 10072307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 10082292SN/A 10092669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 10101060SN/A} 10111060SN/A 10121060SN/Atemplate <class Impl> 10131060SN/Avoid 10142292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 10151060SN/A{ 10162292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10172292SN/A 10182292SN/A regFile.setIntReg(phys_reg, val); 10191060SN/A} 10201060SN/A 10211060SN/Atemplate <class Impl> 10221060SN/Avoid 10232292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 10241060SN/A{ 10252292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10262292SN/A 10272669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 10281060SN/A} 10291060SN/A 10301060SN/Atemplate <class Impl> 10311060SN/Avoid 10322292SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 10331060SN/A{ 10342292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10352292SN/A 10362669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 10371060SN/A} 10381060SN/A 10391060SN/Atemplate <class Impl> 10401060SN/Avoid 10412292SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 10421060SN/A{ 10432292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10441060SN/A 10452669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 10462292SN/A} 10472292SN/A 10482292SN/Atemplate <class Impl> 10492292SN/Auint64_t 10502292SN/AFullO3CPU<Impl>::readPC(unsigned tid) 10512292SN/A{ 10522292SN/A return commit.readPC(tid); 10531060SN/A} 10541060SN/A 10551060SN/Atemplate <class Impl> 10561060SN/Avoid 10572292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 10581060SN/A{ 10592292SN/A commit.setPC(new_PC, tid); 10602292SN/A} 10611060SN/A 10622292SN/Atemplate <class Impl> 10632292SN/Auint64_t 10642292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 10652292SN/A{ 10662292SN/A return commit.readNextPC(tid); 10672292SN/A} 10681060SN/A 10692292SN/Atemplate <class Impl> 10702292SN/Avoid 10712292SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 10722292SN/A{ 10732292SN/A commit.setNextPC(val, tid); 10742292SN/A} 10751060SN/A 10762756Sksewell@umich.edu#if THE_ISA != ALPHA_ISA 10772756Sksewell@umich.edutemplate <class Impl> 10782756Sksewell@umich.eduuint64_t 10792756Sksewell@umich.eduFullO3CPU<Impl>::readNextNPC(unsigned tid) 10802756Sksewell@umich.edu{ 10812756Sksewell@umich.edu return commit.readNextNPC(tid); 10822756Sksewell@umich.edu} 10832756Sksewell@umich.edu 10842756Sksewell@umich.edutemplate <class Impl> 10852756Sksewell@umich.eduvoid 10862756Sksewell@umich.eduFullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid) 10872756Sksewell@umich.edu{ 10882756Sksewell@umich.edu commit.setNextNPC(val, tid); 10892756Sksewell@umich.edu} 10902756Sksewell@umich.edu#endif 10912756Sksewell@umich.edu 10922292SN/Atemplate <class Impl> 10932292SN/Atypename FullO3CPU<Impl>::ListIt 10942292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 10952292SN/A{ 10962292SN/A instList.push_back(inst); 10971060SN/A 10982292SN/A return --(instList.end()); 10992292SN/A} 11001060SN/A 11012292SN/Atemplate <class Impl> 11022292SN/Avoid 11032292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 11042292SN/A{ 11052292SN/A // Keep an instruction count. 11062292SN/A thread[tid]->numInst++; 11072292SN/A thread[tid]->numInsts++; 11082292SN/A committedInsts[tid]++; 11092292SN/A totalCommittedInsts++; 11102292SN/A 11112292SN/A // Check for instruction-count-based events. 11122292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 11132292SN/A} 11142292SN/A 11152292SN/Atemplate <class Impl> 11162292SN/Avoid 11172292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 11182292SN/A{ 11192292SN/A removeInstsThisCycle = true; 11202292SN/A 11212292SN/A removeList.push(inst->getInstListIt()); 11221060SN/A} 11231060SN/A 11241060SN/Atemplate <class Impl> 11251060SN/Avoid 11261755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 11271060SN/A{ 11282733Sktlim@umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 11292292SN/A "[sn:%lli]\n", 11302303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 11311060SN/A 11322292SN/A removeInstsThisCycle = true; 11331060SN/A 11341060SN/A // Remove the front instruction. 11352292SN/A removeList.push(inst->getInstListIt()); 11361060SN/A} 11371060SN/A 11381060SN/Atemplate <class Impl> 11391060SN/Avoid 11402292SN/AFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 11411060SN/A{ 11422733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 11432292SN/A " list.\n", tid); 11441060SN/A 11452292SN/A ListIt end_it; 11461060SN/A 11472292SN/A bool rob_empty = false; 11482292SN/A 11492292SN/A if (instList.empty()) { 11502292SN/A return; 11512292SN/A } else if (rob.isEmpty(/*tid*/)) { 11522733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 11532292SN/A end_it = instList.begin(); 11542292SN/A rob_empty = true; 11552292SN/A } else { 11562292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 11572733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 11582292SN/A } 11592292SN/A 11602292SN/A removeInstsThisCycle = true; 11612292SN/A 11622292SN/A ListIt inst_it = instList.end(); 11632292SN/A 11642292SN/A inst_it--; 11652292SN/A 11662292SN/A // Walk through the instruction list, removing any instructions 11672292SN/A // that were inserted after the given instruction iterator, end_it. 11682292SN/A while (inst_it != end_it) { 11692292SN/A assert(!instList.empty()); 11702292SN/A 11712292SN/A squashInstIt(inst_it, tid); 11722292SN/A 11732292SN/A inst_it--; 11742292SN/A } 11752292SN/A 11762292SN/A // If the ROB was empty, then we actually need to remove the first 11772292SN/A // instruction as well. 11782292SN/A if (rob_empty) { 11792292SN/A squashInstIt(inst_it, tid); 11802292SN/A } 11811060SN/A} 11821060SN/A 11831060SN/Atemplate <class Impl> 11841060SN/Avoid 11852292SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 11862292SN/A unsigned tid) 11871062SN/A{ 11882292SN/A assert(!instList.empty()); 11892292SN/A 11902292SN/A removeInstsThisCycle = true; 11912292SN/A 11922292SN/A ListIt inst_iter = instList.end(); 11932292SN/A 11942292SN/A inst_iter--; 11952292SN/A 11962733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 11972292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 11982292SN/A tid, seq_num, (*inst_iter)->seqNum); 11991062SN/A 12002292SN/A while ((*inst_iter)->seqNum > seq_num) { 12011062SN/A 12022292SN/A bool break_loop = (inst_iter == instList.begin()); 12031062SN/A 12042292SN/A squashInstIt(inst_iter, tid); 12051062SN/A 12062292SN/A inst_iter--; 12071062SN/A 12082292SN/A if (break_loop) 12092292SN/A break; 12102292SN/A } 12112292SN/A} 12122292SN/A 12132292SN/Atemplate <class Impl> 12142292SN/Ainline void 12152292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 12162292SN/A{ 12172292SN/A if ((*instIt)->threadNumber == tid) { 12182733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 12192292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 12202292SN/A (*instIt)->threadNumber, 12212292SN/A (*instIt)->seqNum, 12222292SN/A (*instIt)->readPC()); 12231062SN/A 12241062SN/A // Mark it as squashed. 12252292SN/A (*instIt)->setSquashed(); 12262292SN/A 12272325SN/A // @todo: Formulate a consistent method for deleting 12282325SN/A // instructions from the instruction list 12292292SN/A // Remove the instruction from the list. 12302292SN/A removeList.push(instIt); 12312292SN/A } 12322292SN/A} 12332292SN/A 12342292SN/Atemplate <class Impl> 12352292SN/Avoid 12362292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 12372292SN/A{ 12382292SN/A while (!removeList.empty()) { 12392733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 12402292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 12412292SN/A (*removeList.front())->threadNumber, 12422292SN/A (*removeList.front())->seqNum, 12432292SN/A (*removeList.front())->readPC()); 12442292SN/A 12452292SN/A instList.erase(removeList.front()); 12462292SN/A 12472292SN/A removeList.pop(); 12481062SN/A } 12491062SN/A 12502292SN/A removeInstsThisCycle = false; 12511062SN/A} 12522325SN/A/* 12531062SN/Atemplate <class Impl> 12541062SN/Avoid 12551755SN/AFullO3CPU<Impl>::removeAllInsts() 12561060SN/A{ 12571060SN/A instList.clear(); 12581060SN/A} 12592325SN/A*/ 12601060SN/Atemplate <class Impl> 12611060SN/Avoid 12621755SN/AFullO3CPU<Impl>::dumpInsts() 12631060SN/A{ 12641060SN/A int num = 0; 12651060SN/A 12662292SN/A ListIt inst_list_it = instList.begin(); 12672292SN/A 12682292SN/A cprintf("Dumping Instruction List\n"); 12692292SN/A 12702292SN/A while (inst_list_it != instList.end()) { 12712292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 12722292SN/A "Squashed:%i\n\n", 12732292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 12742292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 12752292SN/A (*inst_list_it)->isSquashed()); 12761060SN/A inst_list_it++; 12771060SN/A ++num; 12781060SN/A } 12791060SN/A} 12802325SN/A/* 12811060SN/Atemplate <class Impl> 12821060SN/Avoid 12831755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 12841060SN/A{ 12851060SN/A iew.wakeDependents(inst); 12861060SN/A} 12872325SN/A*/ 12882292SN/Atemplate <class Impl> 12892292SN/Avoid 12902292SN/AFullO3CPU<Impl>::wakeCPU() 12912292SN/A{ 12922325SN/A if (activityRec.active() || tickEvent.scheduled()) { 12932325SN/A DPRINTF(Activity, "CPU already running.\n"); 12942292SN/A return; 12952292SN/A } 12962292SN/A 12972325SN/A DPRINTF(Activity, "Waking up CPU\n"); 12982325SN/A 12992325SN/A idleCycles += (curTick - 1) - lastRunningCycle; 13002292SN/A 13012292SN/A tickEvent.schedule(curTick); 13022292SN/A} 13032292SN/A 13042292SN/Atemplate <class Impl> 13052292SN/Aint 13062292SN/AFullO3CPU<Impl>::getFreeTid() 13072292SN/A{ 13082292SN/A for (int i=0; i < numThreads; i++) { 13092292SN/A if (!tids[i]) { 13102292SN/A tids[i] = true; 13112292SN/A return i; 13122292SN/A } 13132292SN/A } 13142292SN/A 13152292SN/A return -1; 13162292SN/A} 13172292SN/A 13182292SN/Atemplate <class Impl> 13192292SN/Avoid 13202292SN/AFullO3CPU<Impl>::doContextSwitch() 13212292SN/A{ 13222292SN/A if (contextSwitch) { 13232292SN/A 13242292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 13252292SN/A 13262292SN/A for (int tid=0; tid < cpuWaitList.size(); tid++) { 13272292SN/A activateWhenReady(tid); 13282292SN/A } 13292292SN/A 13302292SN/A if (cpuWaitList.size() == 0) 13312292SN/A contextSwitch = true; 13322292SN/A } 13332292SN/A} 13342292SN/A 13352292SN/Atemplate <class Impl> 13362292SN/Avoid 13372292SN/AFullO3CPU<Impl>::updateThreadPriority() 13382292SN/A{ 13392292SN/A if (activeThreads.size() > 1) 13402292SN/A { 13412292SN/A //DEFAULT TO ROUND ROBIN SCHEME 13422292SN/A //e.g. Move highest priority to end of thread list 13432292SN/A list<unsigned>::iterator list_begin = activeThreads.begin(); 13442292SN/A list<unsigned>::iterator list_end = activeThreads.end(); 13452292SN/A 13462292SN/A unsigned high_thread = *list_begin; 13472292SN/A 13482292SN/A activeThreads.erase(list_begin); 13492292SN/A 13502292SN/A activeThreads.push_back(high_thread); 13512292SN/A } 13522292SN/A} 13531060SN/A 13541755SN/A// Forward declaration of FullO3CPU. 13552818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1356