cpu.cc revision 2867
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 341858SN/A 351858SN/A#if FULL_SYSTEM 361060SN/A#include "sim/system.hh" 371060SN/A#else 381060SN/A#include "sim/process.hh" 391060SN/A#endif 401060SN/A 412325SN/A#include "cpu/activity.hh" 422683Sktlim@umich.edu#include "cpu/simple_thread.hh" 432680Sktlim@umich.edu#include "cpu/thread_context.hh" 442817Sksewell@umich.edu#include "cpu/o3/isa_specific.hh" 451717SN/A#include "cpu/o3/cpu.hh" 461060SN/A 472325SN/A#include "sim/root.hh" 482292SN/A#include "sim/stat_control.hh" 492292SN/A 502794Sktlim@umich.edu#if USE_CHECKER 512794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 522794Sktlim@umich.edu#endif 532794Sktlim@umich.edu 541060SN/Ausing namespace std; 552669Sktlim@umich.eduusing namespace TheISA; 561060SN/A 572733Sktlim@umich.eduBaseO3CPU::BaseO3CPU(Params *params) 582292SN/A : BaseCPU(params), cpu_id(0) 591060SN/A{ 601060SN/A} 611060SN/A 622292SN/Avoid 632733Sktlim@umich.eduBaseO3CPU::regStats() 642292SN/A{ 652292SN/A BaseCPU::regStats(); 662292SN/A} 672292SN/A 681060SN/Atemplate <class Impl> 691755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 701060SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 711060SN/A{ 721060SN/A} 731060SN/A 741060SN/Atemplate <class Impl> 751060SN/Avoid 761755SN/AFullO3CPU<Impl>::TickEvent::process() 771060SN/A{ 781060SN/A cpu->tick(); 791060SN/A} 801060SN/A 811060SN/Atemplate <class Impl> 821060SN/Aconst char * 831755SN/AFullO3CPU<Impl>::TickEvent::description() 841060SN/A{ 851755SN/A return "FullO3CPU tick event"; 861060SN/A} 871060SN/A 881060SN/Atemplate <class Impl> 892829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 902829Sksewell@umich.edu : Event(&mainEventQueue, CPU_Tick_Pri) 912829Sksewell@umich.edu{ 922829Sksewell@umich.edu} 932829Sksewell@umich.edu 942829Sksewell@umich.edutemplate <class Impl> 952829Sksewell@umich.eduvoid 962829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 972829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 982829Sksewell@umich.edu{ 992829Sksewell@umich.edu tid = thread_num; 1002829Sksewell@umich.edu cpu = thread_cpu; 1012829Sksewell@umich.edu} 1022829Sksewell@umich.edu 1032829Sksewell@umich.edutemplate <class Impl> 1042829Sksewell@umich.eduvoid 1052829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1062829Sksewell@umich.edu{ 1072829Sksewell@umich.edu cpu->activateThread(tid); 1082829Sksewell@umich.edu} 1092829Sksewell@umich.edu 1102829Sksewell@umich.edutemplate <class Impl> 1112829Sksewell@umich.educonst char * 1122829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::description() 1132829Sksewell@umich.edu{ 1142829Sksewell@umich.edu return "FullO3CPU \"Activate Thread\" event"; 1152829Sksewell@umich.edu} 1162829Sksewell@umich.edu 1172829Sksewell@umich.edutemplate <class Impl> 1182292SN/AFullO3CPU<Impl>::FullO3CPU(Params *params) 1192733Sktlim@umich.edu : BaseO3CPU(params), 1201060SN/A tickEvent(this), 1212292SN/A removeInstsThisCycle(false), 1221060SN/A fetch(params), 1231060SN/A decode(params), 1241060SN/A rename(params), 1251060SN/A iew(params), 1261060SN/A commit(params), 1271060SN/A 1282292SN/A regFile(params->numPhysIntRegs, params->numPhysFloatRegs), 1291060SN/A 1302831Sksewell@umich.edu freeList(params->numberOfThreads, 1312292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1322292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1331060SN/A 1342292SN/A rob(params->numROBEntries, params->squashWidth, 1352292SN/A params->smtROBPolicy, params->smtROBThreshold, 1362292SN/A params->numberOfThreads), 1371060SN/A 1382831Sksewell@umich.edu scoreboard(params->numberOfThreads, 1392292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1402292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1412292SN/A TheISA::NumMiscRegs * number_of_threads, 1422292SN/A TheISA::ZeroReg), 1431060SN/A 1441060SN/A // For now just have these time buffers be pretty big. 1452325SN/A // @todo: Make these time buffer sizes parameters or derived 1462325SN/A // from latencies 1471061SN/A timeBuffer(5, 5), 1481061SN/A fetchQueue(5, 5), 1491061SN/A decodeQueue(5, 5), 1501061SN/A renameQueue(5, 5), 1511061SN/A iewQueue(5, 5), 1522325SN/A activityRec(NumStages, 10, params->activity), 1531060SN/A 1541060SN/A globalSeqNum(1), 1551060SN/A 1561858SN/A#if FULL_SYSTEM 1572292SN/A system(params->system), 1581060SN/A physmem(system->physmem), 1591060SN/A#endif // FULL_SYSTEM 1602292SN/A mem(params->mem), 1612843Sktlim@umich.edu drainCount(0), 1622316SN/A deferRegistration(params->deferRegistration), 1632316SN/A numThreads(number_of_threads) 1641060SN/A{ 1651060SN/A _status = Idle; 1661681SN/A 1672733Sktlim@umich.edu checker = NULL; 1682733Sktlim@umich.edu 1692794Sktlim@umich.edu if (params->checker) { 1702733Sktlim@umich.edu#if USE_CHECKER 1712316SN/A BaseCPU *temp_checker = params->checker; 1722316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 1732316SN/A checker->setMemory(mem); 1742316SN/A#if FULL_SYSTEM 1752316SN/A checker->setSystem(params->system); 1762316SN/A#endif 1772794Sktlim@umich.edu#else 1782794Sktlim@umich.edu panic("Checker enabled but not compiled in!"); 1792794Sktlim@umich.edu#endif // USE_CHECKER 1802316SN/A } 1812316SN/A 1821858SN/A#if !FULL_SYSTEM 1832292SN/A thread.resize(number_of_threads); 1842292SN/A tids.resize(number_of_threads); 1851681SN/A#endif 1861681SN/A 1872325SN/A // The stages also need their CPU pointer setup. However this 1882325SN/A // must be done at the upper level CPU because they have pointers 1892325SN/A // to the upper level CPU, and not this FullO3CPU. 1901060SN/A 1912292SN/A // Set up Pointers to the activeThreads list for each stage 1922292SN/A fetch.setActiveThreads(&activeThreads); 1932292SN/A decode.setActiveThreads(&activeThreads); 1942292SN/A rename.setActiveThreads(&activeThreads); 1952292SN/A iew.setActiveThreads(&activeThreads); 1962292SN/A commit.setActiveThreads(&activeThreads); 1971060SN/A 1981060SN/A // Give each of the stages the time buffer they will use. 1991060SN/A fetch.setTimeBuffer(&timeBuffer); 2001060SN/A decode.setTimeBuffer(&timeBuffer); 2011060SN/A rename.setTimeBuffer(&timeBuffer); 2021060SN/A iew.setTimeBuffer(&timeBuffer); 2031060SN/A commit.setTimeBuffer(&timeBuffer); 2041060SN/A 2051060SN/A // Also setup each of the stages' queues. 2061060SN/A fetch.setFetchQueue(&fetchQueue); 2071060SN/A decode.setFetchQueue(&fetchQueue); 2082292SN/A commit.setFetchQueue(&fetchQueue); 2091060SN/A decode.setDecodeQueue(&decodeQueue); 2101060SN/A rename.setDecodeQueue(&decodeQueue); 2111060SN/A rename.setRenameQueue(&renameQueue); 2121060SN/A iew.setRenameQueue(&renameQueue); 2131060SN/A iew.setIEWQueue(&iewQueue); 2141060SN/A commit.setIEWQueue(&iewQueue); 2151060SN/A commit.setRenameQueue(&renameQueue); 2161060SN/A 2172316SN/A commit.setFetchStage(&fetch); 2182292SN/A commit.setIEWStage(&iew); 2192292SN/A rename.setIEWStage(&iew); 2202292SN/A rename.setCommitStage(&commit); 2212292SN/A 2222292SN/A#if !FULL_SYSTEM 2232307SN/A int active_threads = params->workload.size(); 2242831Sksewell@umich.edu 2252831Sksewell@umich.edu if (active_threads > Impl::MaxThreads) { 2262831Sksewell@umich.edu panic("Workload Size too large. Increase the 'MaxThreads'" 2272831Sksewell@umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2282831Sksewell@umich.edu "edit your workload size."); 2292831Sksewell@umich.edu } 2302292SN/A#else 2312307SN/A int active_threads = 1; 2322292SN/A#endif 2332292SN/A 2342316SN/A //Make Sure That this a Valid Architeture 2352292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2362292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2372292SN/A 2382292SN/A rename.setScoreboard(&scoreboard); 2392292SN/A iew.setScoreboard(&scoreboard); 2402292SN/A 2411060SN/A // Setup the rename map for whichever stages need it. 2422292SN/A PhysRegIndex lreg_idx = 0; 2432292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2441060SN/A 2452292SN/A for (int tid=0; tid < numThreads; tid++) { 2462307SN/A bool bindRegs = (tid <= active_threads - 1); 2472292SN/A 2482292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2492292SN/A params->numPhysIntRegs, 2502325SN/A lreg_idx, //Index for Logical. Regs 2512292SN/A 2522292SN/A TheISA::NumFloatRegs, 2532292SN/A params->numPhysFloatRegs, 2542325SN/A freg_idx, //Index for Float Regs 2552292SN/A 2562292SN/A TheISA::NumMiscRegs, 2572292SN/A 2582292SN/A TheISA::ZeroReg, 2592292SN/A TheISA::ZeroReg, 2602292SN/A 2612292SN/A tid, 2622292SN/A false); 2632292SN/A 2642292SN/A renameMap[tid].init(TheISA::NumIntRegs, 2652292SN/A params->numPhysIntRegs, 2662325SN/A lreg_idx, //Index for Logical. Regs 2672292SN/A 2682292SN/A TheISA::NumFloatRegs, 2692292SN/A params->numPhysFloatRegs, 2702325SN/A freg_idx, //Index for Float Regs 2712292SN/A 2722292SN/A TheISA::NumMiscRegs, 2732292SN/A 2742292SN/A TheISA::ZeroReg, 2752292SN/A TheISA::ZeroReg, 2762292SN/A 2772292SN/A tid, 2782292SN/A bindRegs); 2792292SN/A } 2802292SN/A 2812292SN/A rename.setRenameMap(renameMap); 2822292SN/A commit.setRenameMap(commitRenameMap); 2832292SN/A 2842292SN/A // Give renameMap & rename stage access to the freeList; 2852292SN/A for (int i=0; i < numThreads; i++) { 2862292SN/A renameMap[i].setFreeList(&freeList); 2872292SN/A } 2881060SN/A rename.setFreeList(&freeList); 2892292SN/A 2901060SN/A // Setup the ROB for whichever stages need it. 2911060SN/A commit.setROB(&rob); 2922292SN/A 2932292SN/A lastRunningCycle = curTick; 2942292SN/A 2952829Sksewell@umich.edu lastActivatedCycle = -1; 2962829Sksewell@umich.edu 2972292SN/A contextSwitch = false; 2981060SN/A} 2991060SN/A 3001060SN/Atemplate <class Impl> 3011755SN/AFullO3CPU<Impl>::~FullO3CPU() 3021060SN/A{ 3031060SN/A} 3041060SN/A 3051060SN/Atemplate <class Impl> 3061060SN/Avoid 3071755SN/AFullO3CPU<Impl>::fullCPURegStats() 3081062SN/A{ 3092733Sktlim@umich.edu BaseO3CPU::regStats(); 3102292SN/A 3112733Sktlim@umich.edu // Register any of the O3CPU's stats here. 3122292SN/A timesIdled 3132292SN/A .name(name() + ".timesIdled") 3142292SN/A .desc("Number of times that the entire CPU went into an idle state and" 3152292SN/A " unscheduled itself") 3162292SN/A .prereq(timesIdled); 3172292SN/A 3182292SN/A idleCycles 3192292SN/A .name(name() + ".idleCycles") 3202292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 3212292SN/A "to idling") 3222292SN/A .prereq(idleCycles); 3232292SN/A 3242292SN/A // Number of Instructions simulated 3252292SN/A // -------------------------------- 3262292SN/A // Should probably be in Base CPU but need templated 3272292SN/A // MaxThreads so put in here instead 3282292SN/A committedInsts 3292292SN/A .init(numThreads) 3302292SN/A .name(name() + ".committedInsts") 3312292SN/A .desc("Number of Instructions Simulated"); 3322292SN/A 3332292SN/A totalCommittedInsts 3342292SN/A .name(name() + ".committedInsts_total") 3352292SN/A .desc("Number of Instructions Simulated"); 3362292SN/A 3372292SN/A cpi 3382292SN/A .name(name() + ".cpi") 3392292SN/A .desc("CPI: Cycles Per Instruction") 3402292SN/A .precision(6); 3412292SN/A cpi = simTicks / committedInsts; 3422292SN/A 3432292SN/A totalCpi 3442292SN/A .name(name() + ".cpi_total") 3452292SN/A .desc("CPI: Total CPI of All Threads") 3462292SN/A .precision(6); 3472292SN/A totalCpi = simTicks / totalCommittedInsts; 3482292SN/A 3492292SN/A ipc 3502292SN/A .name(name() + ".ipc") 3512292SN/A .desc("IPC: Instructions Per Cycle") 3522292SN/A .precision(6); 3532292SN/A ipc = committedInsts / simTicks; 3542292SN/A 3552292SN/A totalIpc 3562292SN/A .name(name() + ".ipc_total") 3572292SN/A .desc("IPC: Total IPC of All Threads") 3582292SN/A .precision(6); 3592292SN/A totalIpc = totalCommittedInsts / simTicks; 3602292SN/A 3611062SN/A} 3621062SN/A 3631062SN/Atemplate <class Impl> 3641062SN/Avoid 3651755SN/AFullO3CPU<Impl>::tick() 3661060SN/A{ 3672733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 3681060SN/A 3692292SN/A ++numCycles; 3702292SN/A 3712325SN/A// activity = false; 3722292SN/A 3732292SN/A //Tick each of the stages 3741060SN/A fetch.tick(); 3751060SN/A 3761060SN/A decode.tick(); 3771060SN/A 3781060SN/A rename.tick(); 3791060SN/A 3801060SN/A iew.tick(); 3811060SN/A 3821060SN/A commit.tick(); 3831060SN/A 3842292SN/A#if !FULL_SYSTEM 3852292SN/A doContextSwitch(); 3862292SN/A#endif 3872292SN/A 3882292SN/A // Now advance the time buffers 3891060SN/A timeBuffer.advance(); 3901060SN/A 3911060SN/A fetchQueue.advance(); 3921060SN/A decodeQueue.advance(); 3931060SN/A renameQueue.advance(); 3941060SN/A iewQueue.advance(); 3951060SN/A 3962325SN/A activityRec.advance(); 3972292SN/A 3982292SN/A if (removeInstsThisCycle) { 3992292SN/A cleanUpRemovedInsts(); 4002292SN/A } 4012292SN/A 4022325SN/A if (!tickEvent.scheduled()) { 4032867Sktlim@umich.edu if (_status == SwitchedOut || 4042867Sktlim@umich.edu getState() == SimObject::DrainedTiming) { 4052325SN/A // increment stat 4062325SN/A lastRunningCycle = curTick; 4072325SN/A } else if (!activityRec.active()) { 4082325SN/A lastRunningCycle = curTick; 4092325SN/A timesIdled++; 4102325SN/A } else { 4112325SN/A tickEvent.schedule(curTick + cycles(1)); 4122325SN/A } 4132292SN/A } 4142292SN/A 4152292SN/A#if !FULL_SYSTEM 4162292SN/A updateThreadPriority(); 4172292SN/A#endif 4182292SN/A 4191060SN/A} 4201060SN/A 4211060SN/Atemplate <class Impl> 4221060SN/Avoid 4231755SN/AFullO3CPU<Impl>::init() 4241060SN/A{ 4252307SN/A if (!deferRegistration) { 4262680Sktlim@umich.edu registerThreadContexts(); 4272292SN/A } 4281060SN/A 4292292SN/A // Set inSyscall so that the CPU doesn't squash when initially 4302292SN/A // setting up registers. 4312292SN/A for (int i = 0; i < number_of_threads; ++i) 4322292SN/A thread[i]->inSyscall = true; 4332292SN/A 4342292SN/A for (int tid=0; tid < number_of_threads; tid++) { 4351858SN/A#if FULL_SYSTEM 4362680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 4371681SN/A#else 4382680Sktlim@umich.edu ThreadContext *src_tc = thread[tid]->getTC(); 4391681SN/A#endif 4402292SN/A // Threads start in the Suspended State 4412680Sktlim@umich.edu if (src_tc->status() != ThreadContext::Suspended) { 4422292SN/A continue; 4431060SN/A } 4441060SN/A 4452292SN/A#if FULL_SYSTEM 4462680Sktlim@umich.edu TheISA::initCPU(src_tc, src_tc->readCpuId()); 4472292SN/A#endif 4482292SN/A } 4492292SN/A 4502292SN/A // Clear inSyscall. 4512292SN/A for (int i = 0; i < number_of_threads; ++i) 4522292SN/A thread[i]->inSyscall = false; 4532292SN/A 4542316SN/A // Initialize stages. 4552292SN/A fetch.initStage(); 4562292SN/A iew.initStage(); 4572292SN/A rename.initStage(); 4582292SN/A commit.initStage(); 4592292SN/A 4602292SN/A commit.setThreads(thread); 4612292SN/A} 4622292SN/A 4632292SN/Atemplate <class Impl> 4642292SN/Avoid 4652292SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 4662292SN/A{ 4672847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 4682292SN/A // Will change now that the PC and thread state is internal to the CPU 4692683Sktlim@umich.edu // and not in the ThreadContext. 4702292SN/A#if FULL_SYSTEM 4712680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 4722292SN/A#else 4732847Sksewell@umich.edu ThreadContext *src_tc = tcBase(tid); 4742292SN/A#endif 4752292SN/A 4762292SN/A //Bind Int Regs to Rename Map 4772292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 4782292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 4792292SN/A 4802292SN/A renameMap[tid].setEntry(ireg,phys_reg); 4812292SN/A scoreboard.setReg(phys_reg); 4822292SN/A } 4832292SN/A 4842292SN/A //Bind Float Regs to Rename Map 4852292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 4862292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 4872292SN/A 4882292SN/A renameMap[tid].setEntry(freg,phys_reg); 4892292SN/A scoreboard.setReg(phys_reg); 4902292SN/A } 4912292SN/A 4922292SN/A //Copy Thread Data Into RegFile 4932847Sksewell@umich.edu //this->copyFromTC(tid); 4942292SN/A 4952847Sksewell@umich.edu //Set PC/NPC/NNPC 4962847Sksewell@umich.edu setPC(src_tc->readPC(), tid); 4972847Sksewell@umich.edu setNextPC(src_tc->readNextPC(), tid); 4982847Sksewell@umich.edu#if THE_ISA != ALPHA_ISA 4992847Sksewell@umich.edu setNextNPC(src_tc->readNextNPC(), tid); 5002847Sksewell@umich.edu#endif 5012292SN/A 5022680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 5032292SN/A 5042292SN/A activateContext(tid,1); 5052292SN/A 5062292SN/A //Reset ROB/IQ/LSQ Entries 5072292SN/A commit.rob->resetEntries(); 5082292SN/A iew.resetEntries(); 5092292SN/A} 5102292SN/A 5112292SN/Atemplate <class Impl> 5122292SN/Avoid 5132292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 5142292SN/A{ 5152847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread from CPU."); 5162847Sksewell@umich.edu 5172847Sksewell@umich.edu // Copy Thread Data From RegFile 5182847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 5192847Sksewell@umich.edu //this->copyToTC(tid); 5202847Sksewell@umich.edu 5212847Sksewell@umich.edu // Unbind Int Regs from Rename Map 5222292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 5232292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 5242292SN/A 5252292SN/A scoreboard.unsetReg(phys_reg); 5262292SN/A freeList.addReg(phys_reg); 5272292SN/A } 5282292SN/A 5292847Sksewell@umich.edu // Unbind Float Regs from Rename Map 5302292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 5312292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 5322292SN/A 5332292SN/A scoreboard.unsetReg(phys_reg); 5342292SN/A freeList.addReg(phys_reg); 5352292SN/A } 5362292SN/A 5372847Sksewell@umich.edu // Squash Throughout Pipeline 5382292SN/A fetch.squash(0,tid); 5392292SN/A decode.squash(tid); 5402292SN/A rename.squash(tid); 5412292SN/A 5422292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 5432292SN/A 5442847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 5452292SN/A if (activeThreads.size() >= 1) { 5462292SN/A commit.rob->resetEntries(); 5472292SN/A iew.resetEntries(); 5482292SN/A } 5492292SN/A} 5502292SN/A 5512292SN/A 5522292SN/Atemplate <class Impl> 5532292SN/Avoid 5542292SN/AFullO3CPU<Impl>::activateWhenReady(int tid) 5552292SN/A{ 5562733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 5572292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 5582292SN/A tid); 5592292SN/A 5602292SN/A bool ready = true; 5612292SN/A 5622292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 5632733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5642292SN/A "Phys. Int. Regs.\n", 5652292SN/A tid); 5662292SN/A ready = false; 5672292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 5682733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5692292SN/A "Phys. Float. Regs.\n", 5702292SN/A tid); 5712292SN/A ready = false; 5722292SN/A } else if (commit.rob->numFreeEntries() >= 5732292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 5742733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5752292SN/A "ROB entries.\n", 5762292SN/A tid); 5772292SN/A ready = false; 5782292SN/A } else if (iew.instQueue.numFreeEntries() >= 5792292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 5802733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5812292SN/A "IQ entries.\n", 5822292SN/A tid); 5832292SN/A ready = false; 5842292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 5852292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 5862733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5872292SN/A "LSQ entries.\n", 5882292SN/A tid); 5892292SN/A ready = false; 5902292SN/A } 5912292SN/A 5922292SN/A if (ready) { 5932292SN/A insertThread(tid); 5942292SN/A 5952292SN/A contextSwitch = false; 5962292SN/A 5972292SN/A cpuWaitList.remove(tid); 5982292SN/A } else { 5992292SN/A suspendContext(tid); 6002292SN/A 6012292SN/A //blocks fetch 6022292SN/A contextSwitch = true; 6032292SN/A 6042292SN/A //do waitlist 6052292SN/A cpuWaitList.push_back(tid); 6061060SN/A } 6071060SN/A} 6081060SN/A 6091060SN/Atemplate <class Impl> 6101060SN/Avoid 6112829Sksewell@umich.eduFullO3CPU<Impl>::activateThread(unsigned int tid) 6121060SN/A{ 6132292SN/A list<unsigned>::iterator isActive = find( 6142292SN/A activeThreads.begin(), activeThreads.end(), tid); 6152292SN/A 6162292SN/A if (isActive == activeThreads.end()) { 6172829Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6182292SN/A tid); 6192292SN/A 6202292SN/A activeThreads.push_back(tid); 6212292SN/A } 6222829Sksewell@umich.edu} 6232292SN/A 6241060SN/A 6252829Sksewell@umich.edutemplate <class Impl> 6262829Sksewell@umich.eduvoid 6272829Sksewell@umich.eduFullO3CPU<Impl>::activateContext(int tid, int delay) 6282829Sksewell@umich.edu{ 6292829Sksewell@umich.edu // Needs to set each stage to running as well. 6302829Sksewell@umich.edu if (delay){ 6312829Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 6322829Sksewell@umich.edu "on cycle %d\n", tid, curTick + cycles(delay)); 6332829Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 6342829Sksewell@umich.edu } else { 6352829Sksewell@umich.edu activateThread(tid); 6362829Sksewell@umich.edu } 6371060SN/A 6382829Sksewell@umich.edu if(lastActivatedCycle < curTick) { 6392829Sksewell@umich.edu scheduleTickEvent(delay); 6402292SN/A 6412829Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 6422829Sksewell@umich.edu // deschedule itself. 6432829Sksewell@umich.edu activityRec.activity(); 6442829Sksewell@umich.edu fetch.wakeFromQuiesce(); 6452829Sksewell@umich.edu 6462829Sksewell@umich.edu lastActivatedCycle = curTick; 6472829Sksewell@umich.edu 6482829Sksewell@umich.edu _status = Running; 6492829Sksewell@umich.edu } 6501060SN/A} 6511060SN/A 6521060SN/Atemplate <class Impl> 6531060SN/Avoid 6542292SN/AFullO3CPU<Impl>::suspendContext(int tid) 6551060SN/A{ 6562847Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 6572292SN/A unscheduleTickEvent(); 6582292SN/A _status = Idle; 6592292SN/A/* 6602292SN/A //Remove From Active List, if Active 6612292SN/A list<unsigned>::iterator isActive = find( 6622292SN/A activeThreads.begin(), activeThreads.end(), tid); 6632292SN/A 6642292SN/A if (isActive != activeThreads.end()) { 6652733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6662292SN/A tid); 6672292SN/A activeThreads.erase(isActive); 6682292SN/A } 6692292SN/A*/ 6701060SN/A} 6711060SN/A 6721060SN/Atemplate <class Impl> 6731060SN/Avoid 6742292SN/AFullO3CPU<Impl>::deallocateContext(int tid) 6751060SN/A{ 6762847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Deallocating Thread Context", tid); 6772847Sksewell@umich.edu 6782292SN/A //Remove From Active List, if Active 6792847Sksewell@umich.edu list<unsigned>::iterator thread_it = 6802847Sksewell@umich.edu find(activeThreads.begin(), activeThreads.end(), tid); 6812292SN/A 6822847Sksewell@umich.edu if (thread_it != activeThreads.end()) { 6832733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6842292SN/A tid); 6852847Sksewell@umich.edu activeThreads.erase(thread_it); 6862292SN/A 6872292SN/A removeThread(tid); 6882292SN/A } 6891060SN/A} 6901060SN/A 6911060SN/Atemplate <class Impl> 6921060SN/Avoid 6932292SN/AFullO3CPU<Impl>::haltContext(int tid) 6941060SN/A{ 6952847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halting Thread Context", tid); 6962292SN/A/* 6972292SN/A //Remove From Active List, if Active 6982292SN/A list<unsigned>::iterator isActive = find( 6992292SN/A activeThreads.begin(), activeThreads.end(), tid); 7002292SN/A 7012292SN/A if (isActive != activeThreads.end()) { 7022733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 7032292SN/A tid); 7042292SN/A activeThreads.erase(isActive); 7052292SN/A 7062292SN/A removeThread(tid); 7072292SN/A } 7082292SN/A*/ 7091060SN/A} 7101060SN/A 7111060SN/Atemplate <class Impl> 7122864Sktlim@umich.eduvoid 7132864Sktlim@umich.eduFullO3CPU<Impl>::serialize(std::ostream &os) 7142864Sktlim@umich.edu{ 7152864Sktlim@umich.edu SERIALIZE_ENUM(_status); 7162864Sktlim@umich.edu BaseCPU::serialize(os); 7172864Sktlim@umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 7182864Sktlim@umich.edu tickEvent.serialize(os); 7192864Sktlim@umich.edu 7202864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 7212864Sktlim@umich.edu // write out the registers. Also make this static so it doesn't 7222864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 7232864Sktlim@umich.edu static SimpleThread temp; 7242864Sktlim@umich.edu 7252864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 7262864Sktlim@umich.edu nameOut(os, csprintf("%s.xc.%i", name(), i)); 7272864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 7282864Sktlim@umich.edu temp.serialize(os); 7292864Sktlim@umich.edu } 7302864Sktlim@umich.edu} 7312864Sktlim@umich.edu 7322864Sktlim@umich.edutemplate <class Impl> 7332864Sktlim@umich.eduvoid 7342864Sktlim@umich.eduFullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) 7352864Sktlim@umich.edu{ 7362864Sktlim@umich.edu UNSERIALIZE_ENUM(_status); 7372864Sktlim@umich.edu BaseCPU::unserialize(cp, section); 7382864Sktlim@umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 7392864Sktlim@umich.edu 7402864Sktlim@umich.edu // Use SimpleThread's ability to checkpoint to make it easier to 7412864Sktlim@umich.edu // read in the registers. Also make this static so it doesn't 7422864Sktlim@umich.edu // get instantiated multiple times (causes a panic in statistics). 7432864Sktlim@umich.edu static SimpleThread temp; 7442864Sktlim@umich.edu 7452864Sktlim@umich.edu for (int i = 0; i < thread.size(); i++) { 7462864Sktlim@umich.edu temp.copyTC(thread[i]->getTC()); 7472864Sktlim@umich.edu temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); 7482864Sktlim@umich.edu thread[i]->getTC()->copyArchRegs(temp.getTC()); 7492864Sktlim@umich.edu } 7502864Sktlim@umich.edu} 7512864Sktlim@umich.edu 7522864Sktlim@umich.edutemplate <class Impl> 7532843Sktlim@umich.edubool 7542843Sktlim@umich.eduFullO3CPU<Impl>::drain(Event *drain_event) 7551060SN/A{ 7562843Sktlim@umich.edu drainCount = 0; 7572843Sktlim@umich.edu fetch.drain(); 7582843Sktlim@umich.edu decode.drain(); 7592843Sktlim@umich.edu rename.drain(); 7602843Sktlim@umich.edu iew.drain(); 7612843Sktlim@umich.edu commit.drain(); 7622325SN/A 7632325SN/A // Wake the CPU and record activity so everything can drain out if 7642863Sktlim@umich.edu // the CPU was not able to immediately drain. 7652864Sktlim@umich.edu if (getState() != SimObject::DrainedTiming) { 7662864Sktlim@umich.edu // A bit of a hack...set the drainEvent after all the drain() 7672864Sktlim@umich.edu // calls have been made, that way if all of the stages drain 7682864Sktlim@umich.edu // immediately, the signalDrained() function knows not to call 7692864Sktlim@umich.edu // process on the drain event. 7702864Sktlim@umich.edu drainEvent = drain_event; 7712864Sktlim@umich.edu 7722863Sktlim@umich.edu wakeCPU(); 7732863Sktlim@umich.edu activityRec.activity(); 7742843Sktlim@umich.edu 7752863Sktlim@umich.edu return false; 7762863Sktlim@umich.edu } else { 7772863Sktlim@umich.edu return true; 7782863Sktlim@umich.edu } 7792316SN/A} 7802310SN/A 7812316SN/Atemplate <class Impl> 7822316SN/Avoid 7832843Sktlim@umich.eduFullO3CPU<Impl>::resume() 7842316SN/A{ 7852843Sktlim@umich.edu fetch.resume(); 7862843Sktlim@umich.edu decode.resume(); 7872843Sktlim@umich.edu rename.resume(); 7882843Sktlim@umich.edu iew.resume(); 7892843Sktlim@umich.edu commit.resume(); 7902316SN/A 7912864Sktlim@umich.edu if (_status == SwitchedOut || _status == Idle) 7922864Sktlim@umich.edu return; 7932864Sktlim@umich.edu 7942843Sktlim@umich.edu if (!tickEvent.scheduled()) 7952843Sktlim@umich.edu tickEvent.schedule(curTick); 7962843Sktlim@umich.edu _status = Running; 7972867Sktlim@umich.edu changeState(SimObject::Timing); 7982843Sktlim@umich.edu} 7992316SN/A 8002843Sktlim@umich.edutemplate <class Impl> 8012843Sktlim@umich.eduvoid 8022843Sktlim@umich.eduFullO3CPU<Impl>::signalDrained() 8032843Sktlim@umich.edu{ 8042843Sktlim@umich.edu if (++drainCount == NumStages) { 8052316SN/A if (tickEvent.scheduled()) 8062316SN/A tickEvent.squash(); 8072863Sktlim@umich.edu 8082864Sktlim@umich.edu changeState(SimObject::DrainedTiming); 8092863Sktlim@umich.edu 8102863Sktlim@umich.edu if (drainEvent) { 8112863Sktlim@umich.edu drainEvent->process(); 8122863Sktlim@umich.edu drainEvent = NULL; 8132863Sktlim@umich.edu } 8142310SN/A } 8152843Sktlim@umich.edu assert(drainCount <= 5); 8162843Sktlim@umich.edu} 8172843Sktlim@umich.edu 8182843Sktlim@umich.edutemplate <class Impl> 8192843Sktlim@umich.eduvoid 8202843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 8212843Sktlim@umich.edu{ 8222843Sktlim@umich.edu fetch.switchOut(); 8232843Sktlim@umich.edu rename.switchOut(); 8242843Sktlim@umich.edu commit.switchOut(); 8252843Sktlim@umich.edu instList.clear(); 8262843Sktlim@umich.edu while (!removeList.empty()) { 8272843Sktlim@umich.edu removeList.pop(); 8282843Sktlim@umich.edu } 8292843Sktlim@umich.edu 8302843Sktlim@umich.edu _status = SwitchedOut; 8312843Sktlim@umich.edu#if USE_CHECKER 8322843Sktlim@umich.edu if (checker) 8332843Sktlim@umich.edu checker->switchOut(); 8342843Sktlim@umich.edu#endif 8351060SN/A} 8361060SN/A 8371060SN/Atemplate <class Impl> 8381060SN/Avoid 8391755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 8401060SN/A{ 8412325SN/A // Flush out any old data from the time buffers. 8422325SN/A for (int i = 0; i < 10; ++i) { 8432307SN/A timeBuffer.advance(); 8442307SN/A fetchQueue.advance(); 8452307SN/A decodeQueue.advance(); 8462307SN/A renameQueue.advance(); 8472307SN/A iewQueue.advance(); 8482307SN/A } 8492307SN/A 8502325SN/A activityRec.reset(); 8512307SN/A 8521060SN/A BaseCPU::takeOverFrom(oldCPU); 8531060SN/A 8542307SN/A fetch.takeOverFrom(); 8552307SN/A decode.takeOverFrom(); 8562307SN/A rename.takeOverFrom(); 8572307SN/A iew.takeOverFrom(); 8582307SN/A commit.takeOverFrom(); 8592307SN/A 8601060SN/A assert(!tickEvent.scheduled()); 8611060SN/A 8622325SN/A // @todo: Figure out how to properly select the tid to put onto 8632325SN/A // the active threads list. 8642307SN/A int tid = 0; 8652307SN/A 8662307SN/A list<unsigned>::iterator isActive = find( 8672307SN/A activeThreads.begin(), activeThreads.end(), tid); 8682307SN/A 8692307SN/A if (isActive == activeThreads.end()) { 8702325SN/A //May Need to Re-code this if the delay variable is the delay 8712325SN/A //needed for thread to activate 8722733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 8732307SN/A tid); 8742307SN/A 8752307SN/A activeThreads.push_back(tid); 8762307SN/A } 8772307SN/A 8782325SN/A // Set all statuses to active, schedule the CPU's tick event. 8792307SN/A // @todo: Fix up statuses so this is handled properly 8802680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 8812680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 8822680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 8831681SN/A _status = Running; 8841681SN/A tickEvent.schedule(curTick); 8851681SN/A } 8861060SN/A } 8872307SN/A if (!tickEvent.scheduled()) 8882307SN/A tickEvent.schedule(curTick); 8891060SN/A} 8901060SN/A 8911060SN/Atemplate <class Impl> 8921060SN/Auint64_t 8931755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 8941060SN/A{ 8951060SN/A return regFile.readIntReg(reg_idx); 8961060SN/A} 8971060SN/A 8981060SN/Atemplate <class Impl> 8992455SN/AFloatReg 9002455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 9011060SN/A{ 9022455SN/A return regFile.readFloatReg(reg_idx, width); 9031060SN/A} 9041060SN/A 9051060SN/Atemplate <class Impl> 9062455SN/AFloatReg 9072455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 9081060SN/A{ 9092455SN/A return regFile.readFloatReg(reg_idx); 9101060SN/A} 9111060SN/A 9121060SN/Atemplate <class Impl> 9132455SN/AFloatRegBits 9142455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 9151060SN/A{ 9162455SN/A return regFile.readFloatRegBits(reg_idx, width); 9172455SN/A} 9182455SN/A 9192455SN/Atemplate <class Impl> 9202455SN/AFloatRegBits 9212455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 9222455SN/A{ 9232455SN/A return regFile.readFloatRegBits(reg_idx); 9241060SN/A} 9251060SN/A 9261060SN/Atemplate <class Impl> 9271060SN/Avoid 9281755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 9291060SN/A{ 9301060SN/A regFile.setIntReg(reg_idx, val); 9311060SN/A} 9321060SN/A 9331060SN/Atemplate <class Impl> 9341060SN/Avoid 9352455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 9361060SN/A{ 9372455SN/A regFile.setFloatReg(reg_idx, val, width); 9381060SN/A} 9391060SN/A 9401060SN/Atemplate <class Impl> 9411060SN/Avoid 9422455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 9431060SN/A{ 9442455SN/A regFile.setFloatReg(reg_idx, val); 9451060SN/A} 9461060SN/A 9471060SN/Atemplate <class Impl> 9481060SN/Avoid 9492455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 9501060SN/A{ 9512455SN/A regFile.setFloatRegBits(reg_idx, val, width); 9522455SN/A} 9532455SN/A 9542455SN/Atemplate <class Impl> 9552455SN/Avoid 9562455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 9572455SN/A{ 9582455SN/A regFile.setFloatRegBits(reg_idx, val); 9591060SN/A} 9601060SN/A 9611060SN/Atemplate <class Impl> 9621060SN/Auint64_t 9632292SN/AFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 9641060SN/A{ 9652292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 9662292SN/A 9672292SN/A return regFile.readIntReg(phys_reg); 9682292SN/A} 9692292SN/A 9702292SN/Atemplate <class Impl> 9712292SN/Afloat 9722292SN/AFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 9732292SN/A{ 9742307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 9752307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 9762292SN/A 9772669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 9782292SN/A} 9792292SN/A 9802292SN/Atemplate <class Impl> 9812292SN/Adouble 9822292SN/AFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 9832292SN/A{ 9842307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 9852307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 9862292SN/A 9872669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 9882292SN/A} 9892292SN/A 9902292SN/Atemplate <class Impl> 9912292SN/Auint64_t 9922292SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 9932292SN/A{ 9942307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 9952307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 9962292SN/A 9972669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 9981060SN/A} 9991060SN/A 10001060SN/Atemplate <class Impl> 10011060SN/Avoid 10022292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 10031060SN/A{ 10042292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10052292SN/A 10062292SN/A regFile.setIntReg(phys_reg, val); 10071060SN/A} 10081060SN/A 10091060SN/Atemplate <class Impl> 10101060SN/Avoid 10112292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 10121060SN/A{ 10132292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10142292SN/A 10152669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 10161060SN/A} 10171060SN/A 10181060SN/Atemplate <class Impl> 10191060SN/Avoid 10202292SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 10211060SN/A{ 10222292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10232292SN/A 10242669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 10251060SN/A} 10261060SN/A 10271060SN/Atemplate <class Impl> 10281060SN/Avoid 10292292SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 10301060SN/A{ 10312292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 10321060SN/A 10332669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 10342292SN/A} 10352292SN/A 10362292SN/Atemplate <class Impl> 10372292SN/Auint64_t 10382292SN/AFullO3CPU<Impl>::readPC(unsigned tid) 10392292SN/A{ 10402292SN/A return commit.readPC(tid); 10411060SN/A} 10421060SN/A 10431060SN/Atemplate <class Impl> 10441060SN/Avoid 10452292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 10461060SN/A{ 10472292SN/A commit.setPC(new_PC, tid); 10482292SN/A} 10491060SN/A 10502292SN/Atemplate <class Impl> 10512292SN/Auint64_t 10522292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 10532292SN/A{ 10542292SN/A return commit.readNextPC(tid); 10552292SN/A} 10561060SN/A 10572292SN/Atemplate <class Impl> 10582292SN/Avoid 10592292SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 10602292SN/A{ 10612292SN/A commit.setNextPC(val, tid); 10622292SN/A} 10631060SN/A 10642756Sksewell@umich.edu#if THE_ISA != ALPHA_ISA 10652756Sksewell@umich.edutemplate <class Impl> 10662756Sksewell@umich.eduuint64_t 10672756Sksewell@umich.eduFullO3CPU<Impl>::readNextNPC(unsigned tid) 10682756Sksewell@umich.edu{ 10692756Sksewell@umich.edu return commit.readNextNPC(tid); 10702756Sksewell@umich.edu} 10712756Sksewell@umich.edu 10722756Sksewell@umich.edutemplate <class Impl> 10732756Sksewell@umich.eduvoid 10742756Sksewell@umich.eduFullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid) 10752756Sksewell@umich.edu{ 10762756Sksewell@umich.edu commit.setNextNPC(val, tid); 10772756Sksewell@umich.edu} 10782756Sksewell@umich.edu#endif 10792756Sksewell@umich.edu 10802292SN/Atemplate <class Impl> 10812292SN/Atypename FullO3CPU<Impl>::ListIt 10822292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 10832292SN/A{ 10842292SN/A instList.push_back(inst); 10851060SN/A 10862292SN/A return --(instList.end()); 10872292SN/A} 10881060SN/A 10892292SN/Atemplate <class Impl> 10902292SN/Avoid 10912292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 10922292SN/A{ 10932292SN/A // Keep an instruction count. 10942292SN/A thread[tid]->numInst++; 10952292SN/A thread[tid]->numInsts++; 10962292SN/A committedInsts[tid]++; 10972292SN/A totalCommittedInsts++; 10982292SN/A 10992292SN/A // Check for instruction-count-based events. 11002292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 11012292SN/A} 11022292SN/A 11032292SN/Atemplate <class Impl> 11042292SN/Avoid 11052292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 11062292SN/A{ 11072292SN/A removeInstsThisCycle = true; 11082292SN/A 11092292SN/A removeList.push(inst->getInstListIt()); 11101060SN/A} 11111060SN/A 11121060SN/Atemplate <class Impl> 11131060SN/Avoid 11141755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 11151060SN/A{ 11162733Sktlim@umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 11172292SN/A "[sn:%lli]\n", 11182303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 11191060SN/A 11202292SN/A removeInstsThisCycle = true; 11211060SN/A 11221060SN/A // Remove the front instruction. 11232292SN/A removeList.push(inst->getInstListIt()); 11241060SN/A} 11251060SN/A 11261060SN/Atemplate <class Impl> 11271060SN/Avoid 11282292SN/AFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 11291060SN/A{ 11302733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 11312292SN/A " list.\n", tid); 11321060SN/A 11332292SN/A ListIt end_it; 11341060SN/A 11352292SN/A bool rob_empty = false; 11362292SN/A 11372292SN/A if (instList.empty()) { 11382292SN/A return; 11392292SN/A } else if (rob.isEmpty(/*tid*/)) { 11402733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 11412292SN/A end_it = instList.begin(); 11422292SN/A rob_empty = true; 11432292SN/A } else { 11442292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 11452733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 11462292SN/A } 11472292SN/A 11482292SN/A removeInstsThisCycle = true; 11492292SN/A 11502292SN/A ListIt inst_it = instList.end(); 11512292SN/A 11522292SN/A inst_it--; 11532292SN/A 11542292SN/A // Walk through the instruction list, removing any instructions 11552292SN/A // that were inserted after the given instruction iterator, end_it. 11562292SN/A while (inst_it != end_it) { 11572292SN/A assert(!instList.empty()); 11582292SN/A 11592292SN/A squashInstIt(inst_it, tid); 11602292SN/A 11612292SN/A inst_it--; 11622292SN/A } 11632292SN/A 11642292SN/A // If the ROB was empty, then we actually need to remove the first 11652292SN/A // instruction as well. 11662292SN/A if (rob_empty) { 11672292SN/A squashInstIt(inst_it, tid); 11682292SN/A } 11691060SN/A} 11701060SN/A 11711060SN/Atemplate <class Impl> 11721060SN/Avoid 11732292SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 11742292SN/A unsigned tid) 11751062SN/A{ 11762292SN/A assert(!instList.empty()); 11772292SN/A 11782292SN/A removeInstsThisCycle = true; 11792292SN/A 11802292SN/A ListIt inst_iter = instList.end(); 11812292SN/A 11822292SN/A inst_iter--; 11832292SN/A 11842733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 11852292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 11862292SN/A tid, seq_num, (*inst_iter)->seqNum); 11871062SN/A 11882292SN/A while ((*inst_iter)->seqNum > seq_num) { 11891062SN/A 11902292SN/A bool break_loop = (inst_iter == instList.begin()); 11911062SN/A 11922292SN/A squashInstIt(inst_iter, tid); 11931062SN/A 11942292SN/A inst_iter--; 11951062SN/A 11962292SN/A if (break_loop) 11972292SN/A break; 11982292SN/A } 11992292SN/A} 12002292SN/A 12012292SN/Atemplate <class Impl> 12022292SN/Ainline void 12032292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 12042292SN/A{ 12052292SN/A if ((*instIt)->threadNumber == tid) { 12062733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 12072292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 12082292SN/A (*instIt)->threadNumber, 12092292SN/A (*instIt)->seqNum, 12102292SN/A (*instIt)->readPC()); 12111062SN/A 12121062SN/A // Mark it as squashed. 12132292SN/A (*instIt)->setSquashed(); 12142292SN/A 12152325SN/A // @todo: Formulate a consistent method for deleting 12162325SN/A // instructions from the instruction list 12172292SN/A // Remove the instruction from the list. 12182292SN/A removeList.push(instIt); 12192292SN/A } 12202292SN/A} 12212292SN/A 12222292SN/Atemplate <class Impl> 12232292SN/Avoid 12242292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 12252292SN/A{ 12262292SN/A while (!removeList.empty()) { 12272733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 12282292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 12292292SN/A (*removeList.front())->threadNumber, 12302292SN/A (*removeList.front())->seqNum, 12312292SN/A (*removeList.front())->readPC()); 12322292SN/A 12332292SN/A instList.erase(removeList.front()); 12342292SN/A 12352292SN/A removeList.pop(); 12361062SN/A } 12371062SN/A 12382292SN/A removeInstsThisCycle = false; 12391062SN/A} 12402325SN/A/* 12411062SN/Atemplate <class Impl> 12421062SN/Avoid 12431755SN/AFullO3CPU<Impl>::removeAllInsts() 12441060SN/A{ 12451060SN/A instList.clear(); 12461060SN/A} 12472325SN/A*/ 12481060SN/Atemplate <class Impl> 12491060SN/Avoid 12501755SN/AFullO3CPU<Impl>::dumpInsts() 12511060SN/A{ 12521060SN/A int num = 0; 12531060SN/A 12542292SN/A ListIt inst_list_it = instList.begin(); 12552292SN/A 12562292SN/A cprintf("Dumping Instruction List\n"); 12572292SN/A 12582292SN/A while (inst_list_it != instList.end()) { 12592292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 12602292SN/A "Squashed:%i\n\n", 12612292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 12622292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 12632292SN/A (*inst_list_it)->isSquashed()); 12641060SN/A inst_list_it++; 12651060SN/A ++num; 12661060SN/A } 12671060SN/A} 12682325SN/A/* 12691060SN/Atemplate <class Impl> 12701060SN/Avoid 12711755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 12721060SN/A{ 12731060SN/A iew.wakeDependents(inst); 12741060SN/A} 12752325SN/A*/ 12762292SN/Atemplate <class Impl> 12772292SN/Avoid 12782292SN/AFullO3CPU<Impl>::wakeCPU() 12792292SN/A{ 12802325SN/A if (activityRec.active() || tickEvent.scheduled()) { 12812325SN/A DPRINTF(Activity, "CPU already running.\n"); 12822292SN/A return; 12832292SN/A } 12842292SN/A 12852325SN/A DPRINTF(Activity, "Waking up CPU\n"); 12862325SN/A 12872325SN/A idleCycles += (curTick - 1) - lastRunningCycle; 12882292SN/A 12892292SN/A tickEvent.schedule(curTick); 12902292SN/A} 12912292SN/A 12922292SN/Atemplate <class Impl> 12932292SN/Aint 12942292SN/AFullO3CPU<Impl>::getFreeTid() 12952292SN/A{ 12962292SN/A for (int i=0; i < numThreads; i++) { 12972292SN/A if (!tids[i]) { 12982292SN/A tids[i] = true; 12992292SN/A return i; 13002292SN/A } 13012292SN/A } 13022292SN/A 13032292SN/A return -1; 13042292SN/A} 13052292SN/A 13062292SN/Atemplate <class Impl> 13072292SN/Avoid 13082292SN/AFullO3CPU<Impl>::doContextSwitch() 13092292SN/A{ 13102292SN/A if (contextSwitch) { 13112292SN/A 13122292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 13132292SN/A 13142292SN/A for (int tid=0; tid < cpuWaitList.size(); tid++) { 13152292SN/A activateWhenReady(tid); 13162292SN/A } 13172292SN/A 13182292SN/A if (cpuWaitList.size() == 0) 13192292SN/A contextSwitch = true; 13202292SN/A } 13212292SN/A} 13222292SN/A 13232292SN/Atemplate <class Impl> 13242292SN/Avoid 13252292SN/AFullO3CPU<Impl>::updateThreadPriority() 13262292SN/A{ 13272292SN/A if (activeThreads.size() > 1) 13282292SN/A { 13292292SN/A //DEFAULT TO ROUND ROBIN SCHEME 13302292SN/A //e.g. Move highest priority to end of thread list 13312292SN/A list<unsigned>::iterator list_begin = activeThreads.begin(); 13322292SN/A list<unsigned>::iterator list_end = activeThreads.end(); 13332292SN/A 13342292SN/A unsigned high_thread = *list_begin; 13352292SN/A 13362292SN/A activeThreads.erase(list_begin); 13372292SN/A 13382292SN/A activeThreads.push_back(high_thread); 13392292SN/A } 13402292SN/A} 13411060SN/A 13421755SN/A// Forward declaration of FullO3CPU. 13432818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1344