cpu.cc revision 2847
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 341858SN/A 351858SN/A#if FULL_SYSTEM 361060SN/A#include "sim/system.hh" 371060SN/A#else 381060SN/A#include "sim/process.hh" 391060SN/A#endif 401060SN/A 412325SN/A#include "cpu/activity.hh" 422683Sktlim@umich.edu#include "cpu/simple_thread.hh" 432680Sktlim@umich.edu#include "cpu/thread_context.hh" 442817Sksewell@umich.edu#include "cpu/o3/isa_specific.hh" 451717SN/A#include "cpu/o3/cpu.hh" 461060SN/A 472325SN/A#include "sim/root.hh" 482292SN/A#include "sim/stat_control.hh" 492292SN/A 502794Sktlim@umich.edu#if USE_CHECKER 512794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 522794Sktlim@umich.edu#endif 532794Sktlim@umich.edu 541060SN/Ausing namespace std; 552669Sktlim@umich.eduusing namespace TheISA; 561060SN/A 572733Sktlim@umich.eduBaseO3CPU::BaseO3CPU(Params *params) 582292SN/A : BaseCPU(params), cpu_id(0) 591060SN/A{ 601060SN/A} 611060SN/A 622292SN/Avoid 632733Sktlim@umich.eduBaseO3CPU::regStats() 642292SN/A{ 652292SN/A BaseCPU::regStats(); 662292SN/A} 672292SN/A 681060SN/Atemplate <class Impl> 691755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 701060SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 711060SN/A{ 721060SN/A} 731060SN/A 741060SN/Atemplate <class Impl> 751060SN/Avoid 761755SN/AFullO3CPU<Impl>::TickEvent::process() 771060SN/A{ 781060SN/A cpu->tick(); 791060SN/A} 801060SN/A 811060SN/Atemplate <class Impl> 821060SN/Aconst char * 831755SN/AFullO3CPU<Impl>::TickEvent::description() 841060SN/A{ 851755SN/A return "FullO3CPU tick event"; 861060SN/A} 871060SN/A 881060SN/Atemplate <class Impl> 892829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 902829Sksewell@umich.edu : Event(&mainEventQueue, CPU_Tick_Pri) 912829Sksewell@umich.edu{ 922829Sksewell@umich.edu} 932829Sksewell@umich.edu 942829Sksewell@umich.edutemplate <class Impl> 952829Sksewell@umich.eduvoid 962829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 972829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 982829Sksewell@umich.edu{ 992829Sksewell@umich.edu tid = thread_num; 1002829Sksewell@umich.edu cpu = thread_cpu; 1012829Sksewell@umich.edu} 1022829Sksewell@umich.edu 1032829Sksewell@umich.edutemplate <class Impl> 1042829Sksewell@umich.eduvoid 1052829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1062829Sksewell@umich.edu{ 1072829Sksewell@umich.edu cpu->activateThread(tid); 1082829Sksewell@umich.edu} 1092829Sksewell@umich.edu 1102829Sksewell@umich.edutemplate <class Impl> 1112829Sksewell@umich.educonst char * 1122829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::description() 1132829Sksewell@umich.edu{ 1142829Sksewell@umich.edu return "FullO3CPU \"Activate Thread\" event"; 1152829Sksewell@umich.edu} 1162829Sksewell@umich.edu 1172829Sksewell@umich.edutemplate <class Impl> 1182292SN/AFullO3CPU<Impl>::FullO3CPU(Params *params) 1192733Sktlim@umich.edu : BaseO3CPU(params), 1201060SN/A tickEvent(this), 1212292SN/A removeInstsThisCycle(false), 1221060SN/A fetch(params), 1231060SN/A decode(params), 1241060SN/A rename(params), 1251060SN/A iew(params), 1261060SN/A commit(params), 1271060SN/A 1282292SN/A regFile(params->numPhysIntRegs, params->numPhysFloatRegs), 1291060SN/A 1302831Sksewell@umich.edu freeList(params->numberOfThreads, 1312292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1322292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1331060SN/A 1342292SN/A rob(params->numROBEntries, params->squashWidth, 1352292SN/A params->smtROBPolicy, params->smtROBThreshold, 1362292SN/A params->numberOfThreads), 1371060SN/A 1382831Sksewell@umich.edu scoreboard(params->numberOfThreads, 1392292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1402292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1412292SN/A TheISA::NumMiscRegs * number_of_threads, 1422292SN/A TheISA::ZeroReg), 1431060SN/A 1441060SN/A // For now just have these time buffers be pretty big. 1452325SN/A // @todo: Make these time buffer sizes parameters or derived 1462325SN/A // from latencies 1471061SN/A timeBuffer(5, 5), 1481061SN/A fetchQueue(5, 5), 1491061SN/A decodeQueue(5, 5), 1501061SN/A renameQueue(5, 5), 1511061SN/A iewQueue(5, 5), 1522325SN/A activityRec(NumStages, 10, params->activity), 1531060SN/A 1541060SN/A globalSeqNum(1), 1551060SN/A 1561858SN/A#if FULL_SYSTEM 1572292SN/A system(params->system), 1581060SN/A physmem(system->physmem), 1591060SN/A#endif // FULL_SYSTEM 1602292SN/A mem(params->mem), 1612316SN/A switchCount(0), 1622316SN/A deferRegistration(params->deferRegistration), 1632316SN/A numThreads(number_of_threads) 1641060SN/A{ 1651060SN/A _status = Idle; 1661681SN/A 1672733Sktlim@umich.edu checker = NULL; 1682733Sktlim@umich.edu 1692794Sktlim@umich.edu if (params->checker) { 1702733Sktlim@umich.edu#if USE_CHECKER 1712316SN/A BaseCPU *temp_checker = params->checker; 1722316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 1732316SN/A checker->setMemory(mem); 1742316SN/A#if FULL_SYSTEM 1752316SN/A checker->setSystem(params->system); 1762316SN/A#endif 1772794Sktlim@umich.edu#else 1782794Sktlim@umich.edu panic("Checker enabled but not compiled in!"); 1792794Sktlim@umich.edu#endif // USE_CHECKER 1802316SN/A } 1812316SN/A 1821858SN/A#if !FULL_SYSTEM 1832292SN/A thread.resize(number_of_threads); 1842292SN/A tids.resize(number_of_threads); 1851681SN/A#endif 1861681SN/A 1872325SN/A // The stages also need their CPU pointer setup. However this 1882325SN/A // must be done at the upper level CPU because they have pointers 1892325SN/A // to the upper level CPU, and not this FullO3CPU. 1901060SN/A 1912292SN/A // Set up Pointers to the activeThreads list for each stage 1922292SN/A fetch.setActiveThreads(&activeThreads); 1932292SN/A decode.setActiveThreads(&activeThreads); 1942292SN/A rename.setActiveThreads(&activeThreads); 1952292SN/A iew.setActiveThreads(&activeThreads); 1962292SN/A commit.setActiveThreads(&activeThreads); 1971060SN/A 1981060SN/A // Give each of the stages the time buffer they will use. 1991060SN/A fetch.setTimeBuffer(&timeBuffer); 2001060SN/A decode.setTimeBuffer(&timeBuffer); 2011060SN/A rename.setTimeBuffer(&timeBuffer); 2021060SN/A iew.setTimeBuffer(&timeBuffer); 2031060SN/A commit.setTimeBuffer(&timeBuffer); 2041060SN/A 2051060SN/A // Also setup each of the stages' queues. 2061060SN/A fetch.setFetchQueue(&fetchQueue); 2071060SN/A decode.setFetchQueue(&fetchQueue); 2082292SN/A commit.setFetchQueue(&fetchQueue); 2091060SN/A decode.setDecodeQueue(&decodeQueue); 2101060SN/A rename.setDecodeQueue(&decodeQueue); 2111060SN/A rename.setRenameQueue(&renameQueue); 2121060SN/A iew.setRenameQueue(&renameQueue); 2131060SN/A iew.setIEWQueue(&iewQueue); 2141060SN/A commit.setIEWQueue(&iewQueue); 2151060SN/A commit.setRenameQueue(&renameQueue); 2161060SN/A 2172316SN/A commit.setFetchStage(&fetch); 2182292SN/A commit.setIEWStage(&iew); 2192292SN/A rename.setIEWStage(&iew); 2202292SN/A rename.setCommitStage(&commit); 2212292SN/A 2222292SN/A#if !FULL_SYSTEM 2232307SN/A int active_threads = params->workload.size(); 2242831Sksewell@umich.edu 2252831Sksewell@umich.edu if (active_threads > Impl::MaxThreads) { 2262831Sksewell@umich.edu panic("Workload Size too large. Increase the 'MaxThreads'" 2272831Sksewell@umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or " 2282831Sksewell@umich.edu "edit your workload size."); 2292831Sksewell@umich.edu } 2302292SN/A#else 2312307SN/A int active_threads = 1; 2322292SN/A#endif 2332292SN/A 2342316SN/A //Make Sure That this a Valid Architeture 2352292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2362292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2372292SN/A 2382292SN/A rename.setScoreboard(&scoreboard); 2392292SN/A iew.setScoreboard(&scoreboard); 2402292SN/A 2411060SN/A // Setup the rename map for whichever stages need it. 2422292SN/A PhysRegIndex lreg_idx = 0; 2432292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2441060SN/A 2452292SN/A for (int tid=0; tid < numThreads; tid++) { 2462307SN/A bool bindRegs = (tid <= active_threads - 1); 2472292SN/A 2482292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2492292SN/A params->numPhysIntRegs, 2502325SN/A lreg_idx, //Index for Logical. Regs 2512292SN/A 2522292SN/A TheISA::NumFloatRegs, 2532292SN/A params->numPhysFloatRegs, 2542325SN/A freg_idx, //Index for Float Regs 2552292SN/A 2562292SN/A TheISA::NumMiscRegs, 2572292SN/A 2582292SN/A TheISA::ZeroReg, 2592292SN/A TheISA::ZeroReg, 2602292SN/A 2612292SN/A tid, 2622292SN/A false); 2632292SN/A 2642292SN/A renameMap[tid].init(TheISA::NumIntRegs, 2652292SN/A params->numPhysIntRegs, 2662325SN/A lreg_idx, //Index for Logical. Regs 2672292SN/A 2682292SN/A TheISA::NumFloatRegs, 2692292SN/A params->numPhysFloatRegs, 2702325SN/A freg_idx, //Index for Float Regs 2712292SN/A 2722292SN/A TheISA::NumMiscRegs, 2732292SN/A 2742292SN/A TheISA::ZeroReg, 2752292SN/A TheISA::ZeroReg, 2762292SN/A 2772292SN/A tid, 2782292SN/A bindRegs); 2792292SN/A } 2802292SN/A 2812292SN/A rename.setRenameMap(renameMap); 2822292SN/A commit.setRenameMap(commitRenameMap); 2832292SN/A 2842292SN/A // Give renameMap & rename stage access to the freeList; 2852292SN/A for (int i=0; i < numThreads; i++) { 2862292SN/A renameMap[i].setFreeList(&freeList); 2872292SN/A } 2881060SN/A rename.setFreeList(&freeList); 2892292SN/A 2901060SN/A // Setup the ROB for whichever stages need it. 2911060SN/A commit.setROB(&rob); 2922292SN/A 2932292SN/A lastRunningCycle = curTick; 2942292SN/A 2952829Sksewell@umich.edu lastActivatedCycle = -1; 2962829Sksewell@umich.edu 2972292SN/A contextSwitch = false; 2981060SN/A} 2991060SN/A 3001060SN/Atemplate <class Impl> 3011755SN/AFullO3CPU<Impl>::~FullO3CPU() 3021060SN/A{ 3031060SN/A} 3041060SN/A 3051060SN/Atemplate <class Impl> 3061060SN/Avoid 3071755SN/AFullO3CPU<Impl>::fullCPURegStats() 3081062SN/A{ 3092733Sktlim@umich.edu BaseO3CPU::regStats(); 3102292SN/A 3112733Sktlim@umich.edu // Register any of the O3CPU's stats here. 3122292SN/A timesIdled 3132292SN/A .name(name() + ".timesIdled") 3142292SN/A .desc("Number of times that the entire CPU went into an idle state and" 3152292SN/A " unscheduled itself") 3162292SN/A .prereq(timesIdled); 3172292SN/A 3182292SN/A idleCycles 3192292SN/A .name(name() + ".idleCycles") 3202292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 3212292SN/A "to idling") 3222292SN/A .prereq(idleCycles); 3232292SN/A 3242292SN/A // Number of Instructions simulated 3252292SN/A // -------------------------------- 3262292SN/A // Should probably be in Base CPU but need templated 3272292SN/A // MaxThreads so put in here instead 3282292SN/A committedInsts 3292292SN/A .init(numThreads) 3302292SN/A .name(name() + ".committedInsts") 3312292SN/A .desc("Number of Instructions Simulated"); 3322292SN/A 3332292SN/A totalCommittedInsts 3342292SN/A .name(name() + ".committedInsts_total") 3352292SN/A .desc("Number of Instructions Simulated"); 3362292SN/A 3372292SN/A cpi 3382292SN/A .name(name() + ".cpi") 3392292SN/A .desc("CPI: Cycles Per Instruction") 3402292SN/A .precision(6); 3412292SN/A cpi = simTicks / committedInsts; 3422292SN/A 3432292SN/A totalCpi 3442292SN/A .name(name() + ".cpi_total") 3452292SN/A .desc("CPI: Total CPI of All Threads") 3462292SN/A .precision(6); 3472292SN/A totalCpi = simTicks / totalCommittedInsts; 3482292SN/A 3492292SN/A ipc 3502292SN/A .name(name() + ".ipc") 3512292SN/A .desc("IPC: Instructions Per Cycle") 3522292SN/A .precision(6); 3532292SN/A ipc = committedInsts / simTicks; 3542292SN/A 3552292SN/A totalIpc 3562292SN/A .name(name() + ".ipc_total") 3572292SN/A .desc("IPC: Total IPC of All Threads") 3582292SN/A .precision(6); 3592292SN/A totalIpc = totalCommittedInsts / simTicks; 3602292SN/A 3611062SN/A} 3621062SN/A 3631062SN/Atemplate <class Impl> 3641062SN/Avoid 3651755SN/AFullO3CPU<Impl>::tick() 3661060SN/A{ 3672733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 3681060SN/A 3692292SN/A ++numCycles; 3702292SN/A 3712325SN/A// activity = false; 3722292SN/A 3732292SN/A //Tick each of the stages 3741060SN/A fetch.tick(); 3751060SN/A 3761060SN/A decode.tick(); 3771060SN/A 3781060SN/A rename.tick(); 3791060SN/A 3801060SN/A iew.tick(); 3811060SN/A 3821060SN/A commit.tick(); 3831060SN/A 3842292SN/A#if !FULL_SYSTEM 3852292SN/A doContextSwitch(); 3862292SN/A#endif 3872292SN/A 3882292SN/A // Now advance the time buffers 3891060SN/A timeBuffer.advance(); 3901060SN/A 3911060SN/A fetchQueue.advance(); 3921060SN/A decodeQueue.advance(); 3931060SN/A renameQueue.advance(); 3941060SN/A iewQueue.advance(); 3951060SN/A 3962325SN/A activityRec.advance(); 3972292SN/A 3982292SN/A if (removeInstsThisCycle) { 3992292SN/A cleanUpRemovedInsts(); 4002292SN/A } 4012292SN/A 4022325SN/A if (!tickEvent.scheduled()) { 4032325SN/A if (_status == SwitchedOut) { 4042325SN/A // increment stat 4052325SN/A lastRunningCycle = curTick; 4062325SN/A } else if (!activityRec.active()) { 4072325SN/A lastRunningCycle = curTick; 4082325SN/A timesIdled++; 4092325SN/A } else { 4102325SN/A tickEvent.schedule(curTick + cycles(1)); 4112325SN/A } 4122292SN/A } 4132292SN/A 4142292SN/A#if !FULL_SYSTEM 4152292SN/A updateThreadPriority(); 4162292SN/A#endif 4172292SN/A 4181060SN/A} 4191060SN/A 4201060SN/Atemplate <class Impl> 4211060SN/Avoid 4221755SN/AFullO3CPU<Impl>::init() 4231060SN/A{ 4242307SN/A if (!deferRegistration) { 4252680Sktlim@umich.edu registerThreadContexts(); 4262292SN/A } 4271060SN/A 4282292SN/A // Set inSyscall so that the CPU doesn't squash when initially 4292292SN/A // setting up registers. 4302292SN/A for (int i = 0; i < number_of_threads; ++i) 4312292SN/A thread[i]->inSyscall = true; 4322292SN/A 4332292SN/A for (int tid=0; tid < number_of_threads; tid++) { 4341858SN/A#if FULL_SYSTEM 4352680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 4361681SN/A#else 4372680Sktlim@umich.edu ThreadContext *src_tc = thread[tid]->getTC(); 4381681SN/A#endif 4392292SN/A // Threads start in the Suspended State 4402680Sktlim@umich.edu if (src_tc->status() != ThreadContext::Suspended) { 4412292SN/A continue; 4421060SN/A } 4431060SN/A 4442292SN/A#if FULL_SYSTEM 4452680Sktlim@umich.edu TheISA::initCPU(src_tc, src_tc->readCpuId()); 4462292SN/A#endif 4472292SN/A } 4482292SN/A 4492292SN/A // Clear inSyscall. 4502292SN/A for (int i = 0; i < number_of_threads; ++i) 4512292SN/A thread[i]->inSyscall = false; 4522292SN/A 4532316SN/A // Initialize stages. 4542292SN/A fetch.initStage(); 4552292SN/A iew.initStage(); 4562292SN/A rename.initStage(); 4572292SN/A commit.initStage(); 4582292SN/A 4592292SN/A commit.setThreads(thread); 4602292SN/A} 4612292SN/A 4622292SN/Atemplate <class Impl> 4632292SN/Avoid 4642292SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 4652292SN/A{ 4662847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 4672292SN/A // Will change now that the PC and thread state is internal to the CPU 4682683Sktlim@umich.edu // and not in the ThreadContext. 4692292SN/A#if FULL_SYSTEM 4702680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 4712292SN/A#else 4722847Sksewell@umich.edu ThreadContext *src_tc = tcBase(tid); 4732292SN/A#endif 4742292SN/A 4752292SN/A //Bind Int Regs to Rename Map 4762292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 4772292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 4782292SN/A 4792292SN/A renameMap[tid].setEntry(ireg,phys_reg); 4802292SN/A scoreboard.setReg(phys_reg); 4812292SN/A } 4822292SN/A 4832292SN/A //Bind Float Regs to Rename Map 4842292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 4852292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 4862292SN/A 4872292SN/A renameMap[tid].setEntry(freg,phys_reg); 4882292SN/A scoreboard.setReg(phys_reg); 4892292SN/A } 4902292SN/A 4912292SN/A //Copy Thread Data Into RegFile 4922847Sksewell@umich.edu //this->copyFromTC(tid); 4932292SN/A 4942847Sksewell@umich.edu //Set PC/NPC/NNPC 4952847Sksewell@umich.edu setPC(src_tc->readPC(), tid); 4962847Sksewell@umich.edu setNextPC(src_tc->readNextPC(), tid); 4972847Sksewell@umich.edu#if THE_ISA != ALPHA_ISA 4982847Sksewell@umich.edu setNextNPC(src_tc->readNextNPC(), tid); 4992847Sksewell@umich.edu#endif 5002292SN/A 5012680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 5022292SN/A 5032292SN/A activateContext(tid,1); 5042292SN/A 5052292SN/A //Reset ROB/IQ/LSQ Entries 5062292SN/A commit.rob->resetEntries(); 5072292SN/A iew.resetEntries(); 5082292SN/A} 5092292SN/A 5102292SN/Atemplate <class Impl> 5112292SN/Avoid 5122292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 5132292SN/A{ 5142847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread from CPU."); 5152847Sksewell@umich.edu 5162847Sksewell@umich.edu // Copy Thread Data From RegFile 5172847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 5182847Sksewell@umich.edu //this->copyToTC(tid); 5192847Sksewell@umich.edu 5202847Sksewell@umich.edu // Unbind Int Regs from Rename Map 5212292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 5222292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 5232292SN/A 5242292SN/A scoreboard.unsetReg(phys_reg); 5252292SN/A freeList.addReg(phys_reg); 5262292SN/A } 5272292SN/A 5282847Sksewell@umich.edu // Unbind Float Regs from Rename Map 5292292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 5302292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 5312292SN/A 5322292SN/A scoreboard.unsetReg(phys_reg); 5332292SN/A freeList.addReg(phys_reg); 5342292SN/A } 5352292SN/A 5362847Sksewell@umich.edu // Squash Throughout Pipeline 5372292SN/A fetch.squash(0,tid); 5382292SN/A decode.squash(tid); 5392292SN/A rename.squash(tid); 5402292SN/A 5412292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 5422292SN/A 5432847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 5442292SN/A if (activeThreads.size() >= 1) { 5452292SN/A commit.rob->resetEntries(); 5462292SN/A iew.resetEntries(); 5472292SN/A } 5482292SN/A} 5492292SN/A 5502292SN/A 5512292SN/Atemplate <class Impl> 5522292SN/Avoid 5532292SN/AFullO3CPU<Impl>::activateWhenReady(int tid) 5542292SN/A{ 5552733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 5562292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 5572292SN/A tid); 5582292SN/A 5592292SN/A bool ready = true; 5602292SN/A 5612292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 5622733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5632292SN/A "Phys. Int. Regs.\n", 5642292SN/A tid); 5652292SN/A ready = false; 5662292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 5672733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5682292SN/A "Phys. Float. Regs.\n", 5692292SN/A tid); 5702292SN/A ready = false; 5712292SN/A } else if (commit.rob->numFreeEntries() >= 5722292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 5732733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5742292SN/A "ROB entries.\n", 5752292SN/A tid); 5762292SN/A ready = false; 5772292SN/A } else if (iew.instQueue.numFreeEntries() >= 5782292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 5792733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5802292SN/A "IQ entries.\n", 5812292SN/A tid); 5822292SN/A ready = false; 5832292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 5842292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 5852733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5862292SN/A "LSQ entries.\n", 5872292SN/A tid); 5882292SN/A ready = false; 5892292SN/A } 5902292SN/A 5912292SN/A if (ready) { 5922292SN/A insertThread(tid); 5932292SN/A 5942292SN/A contextSwitch = false; 5952292SN/A 5962292SN/A cpuWaitList.remove(tid); 5972292SN/A } else { 5982292SN/A suspendContext(tid); 5992292SN/A 6002292SN/A //blocks fetch 6012292SN/A contextSwitch = true; 6022292SN/A 6032292SN/A //do waitlist 6042292SN/A cpuWaitList.push_back(tid); 6051060SN/A } 6061060SN/A} 6071060SN/A 6081060SN/Atemplate <class Impl> 6091060SN/Avoid 6102829Sksewell@umich.eduFullO3CPU<Impl>::activateThread(unsigned int tid) 6111060SN/A{ 6122292SN/A list<unsigned>::iterator isActive = find( 6132292SN/A activeThreads.begin(), activeThreads.end(), tid); 6142292SN/A 6152292SN/A if (isActive == activeThreads.end()) { 6162829Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6172292SN/A tid); 6182292SN/A 6192292SN/A activeThreads.push_back(tid); 6202292SN/A } 6212829Sksewell@umich.edu} 6222292SN/A 6231060SN/A 6242829Sksewell@umich.edutemplate <class Impl> 6252829Sksewell@umich.eduvoid 6262829Sksewell@umich.eduFullO3CPU<Impl>::activateContext(int tid, int delay) 6272829Sksewell@umich.edu{ 6282829Sksewell@umich.edu // Needs to set each stage to running as well. 6292829Sksewell@umich.edu if (delay){ 6302829Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 6312829Sksewell@umich.edu "on cycle %d\n", tid, curTick + cycles(delay)); 6322829Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 6332829Sksewell@umich.edu } else { 6342829Sksewell@umich.edu activateThread(tid); 6352829Sksewell@umich.edu } 6361060SN/A 6372829Sksewell@umich.edu if(lastActivatedCycle < curTick) { 6382829Sksewell@umich.edu scheduleTickEvent(delay); 6392292SN/A 6402829Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 6412829Sksewell@umich.edu // deschedule itself. 6422829Sksewell@umich.edu activityRec.activity(); 6432829Sksewell@umich.edu fetch.wakeFromQuiesce(); 6442829Sksewell@umich.edu 6452829Sksewell@umich.edu lastActivatedCycle = curTick; 6462829Sksewell@umich.edu 6472829Sksewell@umich.edu _status = Running; 6482829Sksewell@umich.edu } 6491060SN/A} 6501060SN/A 6511060SN/Atemplate <class Impl> 6521060SN/Avoid 6532292SN/AFullO3CPU<Impl>::suspendContext(int tid) 6541060SN/A{ 6552847Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 6562292SN/A unscheduleTickEvent(); 6572292SN/A _status = Idle; 6582292SN/A/* 6592292SN/A //Remove From Active List, if Active 6602292SN/A list<unsigned>::iterator isActive = find( 6612292SN/A activeThreads.begin(), activeThreads.end(), tid); 6622292SN/A 6632292SN/A if (isActive != activeThreads.end()) { 6642733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6652292SN/A tid); 6662292SN/A activeThreads.erase(isActive); 6672292SN/A } 6682292SN/A*/ 6691060SN/A} 6701060SN/A 6711060SN/Atemplate <class Impl> 6721060SN/Avoid 6732292SN/AFullO3CPU<Impl>::deallocateContext(int tid) 6741060SN/A{ 6752847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Deallocating Thread Context", tid); 6762847Sksewell@umich.edu 6772292SN/A //Remove From Active List, if Active 6782847Sksewell@umich.edu list<unsigned>::iterator thread_it = 6792847Sksewell@umich.edu find(activeThreads.begin(), activeThreads.end(), tid); 6802292SN/A 6812847Sksewell@umich.edu if (thread_it != activeThreads.end()) { 6822733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6832292SN/A tid); 6842847Sksewell@umich.edu activeThreads.erase(thread_it); 6852292SN/A 6862292SN/A removeThread(tid); 6872292SN/A } 6881060SN/A} 6891060SN/A 6901060SN/Atemplate <class Impl> 6911060SN/Avoid 6922292SN/AFullO3CPU<Impl>::haltContext(int tid) 6931060SN/A{ 6942847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halting Thread Context", tid); 6952292SN/A/* 6962292SN/A //Remove From Active List, if Active 6972292SN/A list<unsigned>::iterator isActive = find( 6982292SN/A activeThreads.begin(), activeThreads.end(), tid); 6992292SN/A 7002292SN/A if (isActive != activeThreads.end()) { 7012733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 7022292SN/A tid); 7032292SN/A activeThreads.erase(isActive); 7042292SN/A 7052292SN/A removeThread(tid); 7062292SN/A } 7072292SN/A*/ 7081060SN/A} 7091060SN/A 7101060SN/Atemplate <class Impl> 7111060SN/Avoid 7122316SN/AFullO3CPU<Impl>::switchOut(Sampler *_sampler) 7131060SN/A{ 7142316SN/A sampler = _sampler; 7152316SN/A switchCount = 0; 7162307SN/A fetch.switchOut(); 7172307SN/A decode.switchOut(); 7182307SN/A rename.switchOut(); 7192307SN/A iew.switchOut(); 7202307SN/A commit.switchOut(); 7212325SN/A 7222325SN/A // Wake the CPU and record activity so everything can drain out if 7232325SN/A // the CPU is currently idle. 7242325SN/A wakeCPU(); 7252325SN/A activityRec.activity(); 7262316SN/A} 7272310SN/A 7282316SN/Atemplate <class Impl> 7292316SN/Avoid 7302316SN/AFullO3CPU<Impl>::signalSwitched() 7312316SN/A{ 7322325SN/A if (++switchCount == NumStages) { 7332316SN/A fetch.doSwitchOut(); 7342316SN/A rename.doSwitchOut(); 7352316SN/A commit.doSwitchOut(); 7362316SN/A instList.clear(); 7372316SN/A while (!removeList.empty()) { 7382316SN/A removeList.pop(); 7392316SN/A } 7402316SN/A 7412794Sktlim@umich.edu#if USE_CHECKER 7422316SN/A if (checker) 7432316SN/A checker->switchOut(sampler); 7442794Sktlim@umich.edu#endif 7452316SN/A 7462316SN/A if (tickEvent.scheduled()) 7472316SN/A tickEvent.squash(); 7482316SN/A sampler->signalSwitched(); 7492316SN/A _status = SwitchedOut; 7502310SN/A } 7512316SN/A assert(switchCount <= 5); 7521060SN/A} 7531060SN/A 7541060SN/Atemplate <class Impl> 7551060SN/Avoid 7561755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 7571060SN/A{ 7582325SN/A // Flush out any old data from the time buffers. 7592325SN/A for (int i = 0; i < 10; ++i) { 7602307SN/A timeBuffer.advance(); 7612307SN/A fetchQueue.advance(); 7622307SN/A decodeQueue.advance(); 7632307SN/A renameQueue.advance(); 7642307SN/A iewQueue.advance(); 7652307SN/A } 7662307SN/A 7672325SN/A activityRec.reset(); 7682307SN/A 7691060SN/A BaseCPU::takeOverFrom(oldCPU); 7701060SN/A 7712307SN/A fetch.takeOverFrom(); 7722307SN/A decode.takeOverFrom(); 7732307SN/A rename.takeOverFrom(); 7742307SN/A iew.takeOverFrom(); 7752307SN/A commit.takeOverFrom(); 7762307SN/A 7771060SN/A assert(!tickEvent.scheduled()); 7781060SN/A 7792325SN/A // @todo: Figure out how to properly select the tid to put onto 7802325SN/A // the active threads list. 7812307SN/A int tid = 0; 7822307SN/A 7832307SN/A list<unsigned>::iterator isActive = find( 7842307SN/A activeThreads.begin(), activeThreads.end(), tid); 7852307SN/A 7862307SN/A if (isActive == activeThreads.end()) { 7872325SN/A //May Need to Re-code this if the delay variable is the delay 7882325SN/A //needed for thread to activate 7892733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 7902307SN/A tid); 7912307SN/A 7922307SN/A activeThreads.push_back(tid); 7932307SN/A } 7942307SN/A 7952325SN/A // Set all statuses to active, schedule the CPU's tick event. 7962307SN/A // @todo: Fix up statuses so this is handled properly 7972680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 7982680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 7992680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 8001681SN/A _status = Running; 8011681SN/A tickEvent.schedule(curTick); 8021681SN/A } 8031060SN/A } 8042307SN/A if (!tickEvent.scheduled()) 8052307SN/A tickEvent.schedule(curTick); 8061060SN/A} 8071060SN/A 8081060SN/Atemplate <class Impl> 8091060SN/Auint64_t 8101755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 8111060SN/A{ 8121060SN/A return regFile.readIntReg(reg_idx); 8131060SN/A} 8141060SN/A 8151060SN/Atemplate <class Impl> 8162455SN/AFloatReg 8172455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 8181060SN/A{ 8192455SN/A return regFile.readFloatReg(reg_idx, width); 8201060SN/A} 8211060SN/A 8221060SN/Atemplate <class Impl> 8232455SN/AFloatReg 8242455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 8251060SN/A{ 8262455SN/A return regFile.readFloatReg(reg_idx); 8271060SN/A} 8281060SN/A 8291060SN/Atemplate <class Impl> 8302455SN/AFloatRegBits 8312455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 8321060SN/A{ 8332455SN/A return regFile.readFloatRegBits(reg_idx, width); 8342455SN/A} 8352455SN/A 8362455SN/Atemplate <class Impl> 8372455SN/AFloatRegBits 8382455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 8392455SN/A{ 8402455SN/A return regFile.readFloatRegBits(reg_idx); 8411060SN/A} 8421060SN/A 8431060SN/Atemplate <class Impl> 8441060SN/Avoid 8451755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 8461060SN/A{ 8471060SN/A regFile.setIntReg(reg_idx, val); 8481060SN/A} 8491060SN/A 8501060SN/Atemplate <class Impl> 8511060SN/Avoid 8522455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 8531060SN/A{ 8542455SN/A regFile.setFloatReg(reg_idx, val, width); 8551060SN/A} 8561060SN/A 8571060SN/Atemplate <class Impl> 8581060SN/Avoid 8592455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 8601060SN/A{ 8612455SN/A regFile.setFloatReg(reg_idx, val); 8621060SN/A} 8631060SN/A 8641060SN/Atemplate <class Impl> 8651060SN/Avoid 8662455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 8671060SN/A{ 8682455SN/A regFile.setFloatRegBits(reg_idx, val, width); 8692455SN/A} 8702455SN/A 8712455SN/Atemplate <class Impl> 8722455SN/Avoid 8732455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 8742455SN/A{ 8752455SN/A regFile.setFloatRegBits(reg_idx, val); 8761060SN/A} 8771060SN/A 8781060SN/Atemplate <class Impl> 8791060SN/Auint64_t 8802292SN/AFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 8811060SN/A{ 8822292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8832292SN/A 8842292SN/A return regFile.readIntReg(phys_reg); 8852292SN/A} 8862292SN/A 8872292SN/Atemplate <class Impl> 8882292SN/Afloat 8892292SN/AFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 8902292SN/A{ 8912307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 8922307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 8932292SN/A 8942669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 8952292SN/A} 8962292SN/A 8972292SN/Atemplate <class Impl> 8982292SN/Adouble 8992292SN/AFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 9002292SN/A{ 9012307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 9022307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 9032292SN/A 9042669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 9052292SN/A} 9062292SN/A 9072292SN/Atemplate <class Impl> 9082292SN/Auint64_t 9092292SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 9102292SN/A{ 9112307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 9122307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 9132292SN/A 9142669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 9151060SN/A} 9161060SN/A 9171060SN/Atemplate <class Impl> 9181060SN/Avoid 9192292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 9201060SN/A{ 9212292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 9222292SN/A 9232292SN/A regFile.setIntReg(phys_reg, val); 9241060SN/A} 9251060SN/A 9261060SN/Atemplate <class Impl> 9271060SN/Avoid 9282292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 9291060SN/A{ 9302292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 9312292SN/A 9322669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 9331060SN/A} 9341060SN/A 9351060SN/Atemplate <class Impl> 9361060SN/Avoid 9372292SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 9381060SN/A{ 9392292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 9402292SN/A 9412669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 9421060SN/A} 9431060SN/A 9441060SN/Atemplate <class Impl> 9451060SN/Avoid 9462292SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 9471060SN/A{ 9482292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 9491060SN/A 9502669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 9512292SN/A} 9522292SN/A 9532292SN/Atemplate <class Impl> 9542292SN/Auint64_t 9552292SN/AFullO3CPU<Impl>::readPC(unsigned tid) 9562292SN/A{ 9572292SN/A return commit.readPC(tid); 9581060SN/A} 9591060SN/A 9601060SN/Atemplate <class Impl> 9611060SN/Avoid 9622292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 9631060SN/A{ 9642292SN/A commit.setPC(new_PC, tid); 9652292SN/A} 9661060SN/A 9672292SN/Atemplate <class Impl> 9682292SN/Auint64_t 9692292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 9702292SN/A{ 9712292SN/A return commit.readNextPC(tid); 9722292SN/A} 9731060SN/A 9742292SN/Atemplate <class Impl> 9752292SN/Avoid 9762292SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 9772292SN/A{ 9782292SN/A commit.setNextPC(val, tid); 9792292SN/A} 9801060SN/A 9812756Sksewell@umich.edu#if THE_ISA != ALPHA_ISA 9822756Sksewell@umich.edutemplate <class Impl> 9832756Sksewell@umich.eduuint64_t 9842756Sksewell@umich.eduFullO3CPU<Impl>::readNextNPC(unsigned tid) 9852756Sksewell@umich.edu{ 9862756Sksewell@umich.edu return commit.readNextNPC(tid); 9872756Sksewell@umich.edu} 9882756Sksewell@umich.edu 9892756Sksewell@umich.edutemplate <class Impl> 9902756Sksewell@umich.eduvoid 9912756Sksewell@umich.eduFullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid) 9922756Sksewell@umich.edu{ 9932756Sksewell@umich.edu commit.setNextNPC(val, tid); 9942756Sksewell@umich.edu} 9952756Sksewell@umich.edu#endif 9962756Sksewell@umich.edu 9972292SN/Atemplate <class Impl> 9982292SN/Atypename FullO3CPU<Impl>::ListIt 9992292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 10002292SN/A{ 10012292SN/A instList.push_back(inst); 10021060SN/A 10032292SN/A return --(instList.end()); 10042292SN/A} 10051060SN/A 10062292SN/Atemplate <class Impl> 10072292SN/Avoid 10082292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 10092292SN/A{ 10102292SN/A // Keep an instruction count. 10112292SN/A thread[tid]->numInst++; 10122292SN/A thread[tid]->numInsts++; 10132292SN/A committedInsts[tid]++; 10142292SN/A totalCommittedInsts++; 10152292SN/A 10162292SN/A // Check for instruction-count-based events. 10172292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 10182292SN/A} 10192292SN/A 10202292SN/Atemplate <class Impl> 10212292SN/Avoid 10222292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 10232292SN/A{ 10242292SN/A removeInstsThisCycle = true; 10252292SN/A 10262292SN/A removeList.push(inst->getInstListIt()); 10271060SN/A} 10281060SN/A 10291060SN/Atemplate <class Impl> 10301060SN/Avoid 10311755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 10321060SN/A{ 10332733Sktlim@umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 10342292SN/A "[sn:%lli]\n", 10352303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 10361060SN/A 10372292SN/A removeInstsThisCycle = true; 10381060SN/A 10391060SN/A // Remove the front instruction. 10402292SN/A removeList.push(inst->getInstListIt()); 10411060SN/A} 10421060SN/A 10431060SN/Atemplate <class Impl> 10441060SN/Avoid 10452292SN/AFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 10461060SN/A{ 10472733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 10482292SN/A " list.\n", tid); 10491060SN/A 10502292SN/A ListIt end_it; 10511060SN/A 10522292SN/A bool rob_empty = false; 10532292SN/A 10542292SN/A if (instList.empty()) { 10552292SN/A return; 10562292SN/A } else if (rob.isEmpty(/*tid*/)) { 10572733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 10582292SN/A end_it = instList.begin(); 10592292SN/A rob_empty = true; 10602292SN/A } else { 10612292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 10622733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 10632292SN/A } 10642292SN/A 10652292SN/A removeInstsThisCycle = true; 10662292SN/A 10672292SN/A ListIt inst_it = instList.end(); 10682292SN/A 10692292SN/A inst_it--; 10702292SN/A 10712292SN/A // Walk through the instruction list, removing any instructions 10722292SN/A // that were inserted after the given instruction iterator, end_it. 10732292SN/A while (inst_it != end_it) { 10742292SN/A assert(!instList.empty()); 10752292SN/A 10762292SN/A squashInstIt(inst_it, tid); 10772292SN/A 10782292SN/A inst_it--; 10792292SN/A } 10802292SN/A 10812292SN/A // If the ROB was empty, then we actually need to remove the first 10822292SN/A // instruction as well. 10832292SN/A if (rob_empty) { 10842292SN/A squashInstIt(inst_it, tid); 10852292SN/A } 10861060SN/A} 10871060SN/A 10881060SN/Atemplate <class Impl> 10891060SN/Avoid 10902292SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 10912292SN/A unsigned tid) 10921062SN/A{ 10932292SN/A assert(!instList.empty()); 10942292SN/A 10952292SN/A removeInstsThisCycle = true; 10962292SN/A 10972292SN/A ListIt inst_iter = instList.end(); 10982292SN/A 10992292SN/A inst_iter--; 11002292SN/A 11012733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 11022292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 11032292SN/A tid, seq_num, (*inst_iter)->seqNum); 11041062SN/A 11052292SN/A while ((*inst_iter)->seqNum > seq_num) { 11061062SN/A 11072292SN/A bool break_loop = (inst_iter == instList.begin()); 11081062SN/A 11092292SN/A squashInstIt(inst_iter, tid); 11101062SN/A 11112292SN/A inst_iter--; 11121062SN/A 11132292SN/A if (break_loop) 11142292SN/A break; 11152292SN/A } 11162292SN/A} 11172292SN/A 11182292SN/Atemplate <class Impl> 11192292SN/Ainline void 11202292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 11212292SN/A{ 11222292SN/A if ((*instIt)->threadNumber == tid) { 11232733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 11242292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 11252292SN/A (*instIt)->threadNumber, 11262292SN/A (*instIt)->seqNum, 11272292SN/A (*instIt)->readPC()); 11281062SN/A 11291062SN/A // Mark it as squashed. 11302292SN/A (*instIt)->setSquashed(); 11312292SN/A 11322325SN/A // @todo: Formulate a consistent method for deleting 11332325SN/A // instructions from the instruction list 11342292SN/A // Remove the instruction from the list. 11352292SN/A removeList.push(instIt); 11362292SN/A } 11372292SN/A} 11382292SN/A 11392292SN/Atemplate <class Impl> 11402292SN/Avoid 11412292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 11422292SN/A{ 11432292SN/A while (!removeList.empty()) { 11442733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 11452292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 11462292SN/A (*removeList.front())->threadNumber, 11472292SN/A (*removeList.front())->seqNum, 11482292SN/A (*removeList.front())->readPC()); 11492292SN/A 11502292SN/A instList.erase(removeList.front()); 11512292SN/A 11522292SN/A removeList.pop(); 11531062SN/A } 11541062SN/A 11552292SN/A removeInstsThisCycle = false; 11561062SN/A} 11572325SN/A/* 11581062SN/Atemplate <class Impl> 11591062SN/Avoid 11601755SN/AFullO3CPU<Impl>::removeAllInsts() 11611060SN/A{ 11621060SN/A instList.clear(); 11631060SN/A} 11642325SN/A*/ 11651060SN/Atemplate <class Impl> 11661060SN/Avoid 11671755SN/AFullO3CPU<Impl>::dumpInsts() 11681060SN/A{ 11691060SN/A int num = 0; 11701060SN/A 11712292SN/A ListIt inst_list_it = instList.begin(); 11722292SN/A 11732292SN/A cprintf("Dumping Instruction List\n"); 11742292SN/A 11752292SN/A while (inst_list_it != instList.end()) { 11762292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 11772292SN/A "Squashed:%i\n\n", 11782292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 11792292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 11802292SN/A (*inst_list_it)->isSquashed()); 11811060SN/A inst_list_it++; 11821060SN/A ++num; 11831060SN/A } 11841060SN/A} 11852325SN/A/* 11861060SN/Atemplate <class Impl> 11871060SN/Avoid 11881755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 11891060SN/A{ 11901060SN/A iew.wakeDependents(inst); 11911060SN/A} 11922325SN/A*/ 11932292SN/Atemplate <class Impl> 11942292SN/Avoid 11952292SN/AFullO3CPU<Impl>::wakeCPU() 11962292SN/A{ 11972325SN/A if (activityRec.active() || tickEvent.scheduled()) { 11982325SN/A DPRINTF(Activity, "CPU already running.\n"); 11992292SN/A return; 12002292SN/A } 12012292SN/A 12022325SN/A DPRINTF(Activity, "Waking up CPU\n"); 12032325SN/A 12042325SN/A idleCycles += (curTick - 1) - lastRunningCycle; 12052292SN/A 12062292SN/A tickEvent.schedule(curTick); 12072292SN/A} 12082292SN/A 12092292SN/Atemplate <class Impl> 12102292SN/Aint 12112292SN/AFullO3CPU<Impl>::getFreeTid() 12122292SN/A{ 12132292SN/A for (int i=0; i < numThreads; i++) { 12142292SN/A if (!tids[i]) { 12152292SN/A tids[i] = true; 12162292SN/A return i; 12172292SN/A } 12182292SN/A } 12192292SN/A 12202292SN/A return -1; 12212292SN/A} 12222292SN/A 12232292SN/Atemplate <class Impl> 12242292SN/Avoid 12252292SN/AFullO3CPU<Impl>::doContextSwitch() 12262292SN/A{ 12272292SN/A if (contextSwitch) { 12282292SN/A 12292292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 12302292SN/A 12312292SN/A for (int tid=0; tid < cpuWaitList.size(); tid++) { 12322292SN/A activateWhenReady(tid); 12332292SN/A } 12342292SN/A 12352292SN/A if (cpuWaitList.size() == 0) 12362292SN/A contextSwitch = true; 12372292SN/A } 12382292SN/A} 12392292SN/A 12402292SN/Atemplate <class Impl> 12412292SN/Avoid 12422292SN/AFullO3CPU<Impl>::updateThreadPriority() 12432292SN/A{ 12442292SN/A if (activeThreads.size() > 1) 12452292SN/A { 12462292SN/A //DEFAULT TO ROUND ROBIN SCHEME 12472292SN/A //e.g. Move highest priority to end of thread list 12482292SN/A list<unsigned>::iterator list_begin = activeThreads.begin(); 12492292SN/A list<unsigned>::iterator list_end = activeThreads.end(); 12502292SN/A 12512292SN/A unsigned high_thread = *list_begin; 12522292SN/A 12532292SN/A activeThreads.erase(list_begin); 12542292SN/A 12552292SN/A activeThreads.push_back(high_thread); 12562292SN/A } 12572292SN/A} 12581060SN/A 12591755SN/A// Forward declaration of FullO3CPU. 12602818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1261