cpu.cc revision 2829
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 341858SN/A 351858SN/A#if FULL_SYSTEM 361060SN/A#include "sim/system.hh" 371060SN/A#else 381060SN/A#include "sim/process.hh" 391060SN/A#endif 401060SN/A 412325SN/A#include "cpu/activity.hh" 422683Sktlim@umich.edu#include "cpu/simple_thread.hh" 432680Sktlim@umich.edu#include "cpu/thread_context.hh" 442817Sksewell@umich.edu#include "cpu/o3/isa_specific.hh" 451717SN/A#include "cpu/o3/cpu.hh" 461060SN/A 472325SN/A#include "sim/root.hh" 482292SN/A#include "sim/stat_control.hh" 492292SN/A 502794Sktlim@umich.edu#if USE_CHECKER 512794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 522794Sktlim@umich.edu#endif 532794Sktlim@umich.edu 541060SN/Ausing namespace std; 552669Sktlim@umich.eduusing namespace TheISA; 561060SN/A 572733Sktlim@umich.eduBaseO3CPU::BaseO3CPU(Params *params) 582292SN/A : BaseCPU(params), cpu_id(0) 591060SN/A{ 601060SN/A} 611060SN/A 622292SN/Avoid 632733Sktlim@umich.eduBaseO3CPU::regStats() 642292SN/A{ 652292SN/A BaseCPU::regStats(); 662292SN/A} 672292SN/A 681060SN/Atemplate <class Impl> 691755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 701060SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 711060SN/A{ 721060SN/A} 731060SN/A 741060SN/Atemplate <class Impl> 751060SN/Avoid 761755SN/AFullO3CPU<Impl>::TickEvent::process() 771060SN/A{ 781060SN/A cpu->tick(); 791060SN/A} 801060SN/A 811060SN/Atemplate <class Impl> 821060SN/Aconst char * 831755SN/AFullO3CPU<Impl>::TickEvent::description() 841060SN/A{ 851755SN/A return "FullO3CPU tick event"; 861060SN/A} 871060SN/A 881060SN/Atemplate <class Impl> 892829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 902829Sksewell@umich.edu : Event(&mainEventQueue, CPU_Tick_Pri) 912829Sksewell@umich.edu{ 922829Sksewell@umich.edu} 932829Sksewell@umich.edu 942829Sksewell@umich.edutemplate <class Impl> 952829Sksewell@umich.eduvoid 962829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 972829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 982829Sksewell@umich.edu{ 992829Sksewell@umich.edu tid = thread_num; 1002829Sksewell@umich.edu cpu = thread_cpu; 1012829Sksewell@umich.edu} 1022829Sksewell@umich.edu 1032829Sksewell@umich.edutemplate <class Impl> 1042829Sksewell@umich.eduvoid 1052829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1062829Sksewell@umich.edu{ 1072829Sksewell@umich.edu cpu->activateThread(tid); 1082829Sksewell@umich.edu} 1092829Sksewell@umich.edu 1102829Sksewell@umich.edutemplate <class Impl> 1112829Sksewell@umich.educonst char * 1122829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::description() 1132829Sksewell@umich.edu{ 1142829Sksewell@umich.edu return "FullO3CPU \"Activate Thread\" event"; 1152829Sksewell@umich.edu} 1162829Sksewell@umich.edu 1172829Sksewell@umich.edutemplate <class Impl> 1182292SN/AFullO3CPU<Impl>::FullO3CPU(Params *params) 1192733Sktlim@umich.edu : BaseO3CPU(params), 1201060SN/A tickEvent(this), 1212292SN/A removeInstsThisCycle(false), 1221060SN/A fetch(params), 1231060SN/A decode(params), 1241060SN/A rename(params), 1251060SN/A iew(params), 1261060SN/A commit(params), 1271060SN/A 1282292SN/A regFile(params->numPhysIntRegs, params->numPhysFloatRegs), 1291060SN/A 1302292SN/A freeList(params->numberOfThreads,//number of activeThreads 1312292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1322292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1331060SN/A 1342292SN/A rob(params->numROBEntries, params->squashWidth, 1352292SN/A params->smtROBPolicy, params->smtROBThreshold, 1362292SN/A params->numberOfThreads), 1371060SN/A 1382292SN/A scoreboard(params->numberOfThreads,//number of activeThreads 1392292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1402292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1412292SN/A TheISA::NumMiscRegs * number_of_threads, 1422292SN/A TheISA::ZeroReg), 1431060SN/A 1441060SN/A // For now just have these time buffers be pretty big. 1452325SN/A // @todo: Make these time buffer sizes parameters or derived 1462325SN/A // from latencies 1471061SN/A timeBuffer(5, 5), 1481061SN/A fetchQueue(5, 5), 1491061SN/A decodeQueue(5, 5), 1501061SN/A renameQueue(5, 5), 1511061SN/A iewQueue(5, 5), 1522325SN/A activityRec(NumStages, 10, params->activity), 1531060SN/A 1541060SN/A globalSeqNum(1), 1551060SN/A 1561858SN/A#if FULL_SYSTEM 1572292SN/A system(params->system), 1581060SN/A physmem(system->physmem), 1591060SN/A#endif // FULL_SYSTEM 1602292SN/A mem(params->mem), 1612316SN/A switchCount(0), 1622316SN/A deferRegistration(params->deferRegistration), 1632316SN/A numThreads(number_of_threads) 1641060SN/A{ 1651060SN/A _status = Idle; 1661681SN/A 1672733Sktlim@umich.edu checker = NULL; 1682733Sktlim@umich.edu 1692794Sktlim@umich.edu if (params->checker) { 1702733Sktlim@umich.edu#if USE_CHECKER 1712316SN/A BaseCPU *temp_checker = params->checker; 1722316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 1732316SN/A checker->setMemory(mem); 1742316SN/A#if FULL_SYSTEM 1752316SN/A checker->setSystem(params->system); 1762316SN/A#endif 1772794Sktlim@umich.edu#else 1782794Sktlim@umich.edu panic("Checker enabled but not compiled in!"); 1792794Sktlim@umich.edu#endif // USE_CHECKER 1802316SN/A } 1812316SN/A 1821858SN/A#if !FULL_SYSTEM 1832292SN/A thread.resize(number_of_threads); 1842292SN/A tids.resize(number_of_threads); 1851681SN/A#endif 1861681SN/A 1872325SN/A // The stages also need their CPU pointer setup. However this 1882325SN/A // must be done at the upper level CPU because they have pointers 1892325SN/A // to the upper level CPU, and not this FullO3CPU. 1901060SN/A 1912292SN/A // Set up Pointers to the activeThreads list for each stage 1922292SN/A fetch.setActiveThreads(&activeThreads); 1932292SN/A decode.setActiveThreads(&activeThreads); 1942292SN/A rename.setActiveThreads(&activeThreads); 1952292SN/A iew.setActiveThreads(&activeThreads); 1962292SN/A commit.setActiveThreads(&activeThreads); 1971060SN/A 1981060SN/A // Give each of the stages the time buffer they will use. 1991060SN/A fetch.setTimeBuffer(&timeBuffer); 2001060SN/A decode.setTimeBuffer(&timeBuffer); 2011060SN/A rename.setTimeBuffer(&timeBuffer); 2021060SN/A iew.setTimeBuffer(&timeBuffer); 2031060SN/A commit.setTimeBuffer(&timeBuffer); 2041060SN/A 2051060SN/A // Also setup each of the stages' queues. 2061060SN/A fetch.setFetchQueue(&fetchQueue); 2071060SN/A decode.setFetchQueue(&fetchQueue); 2082292SN/A commit.setFetchQueue(&fetchQueue); 2091060SN/A decode.setDecodeQueue(&decodeQueue); 2101060SN/A rename.setDecodeQueue(&decodeQueue); 2111060SN/A rename.setRenameQueue(&renameQueue); 2121060SN/A iew.setRenameQueue(&renameQueue); 2131060SN/A iew.setIEWQueue(&iewQueue); 2141060SN/A commit.setIEWQueue(&iewQueue); 2151060SN/A commit.setRenameQueue(&renameQueue); 2161060SN/A 2172316SN/A commit.setFetchStage(&fetch); 2182292SN/A commit.setIEWStage(&iew); 2192292SN/A rename.setIEWStage(&iew); 2202292SN/A rename.setCommitStage(&commit); 2212292SN/A 2222292SN/A#if !FULL_SYSTEM 2232307SN/A int active_threads = params->workload.size(); 2242292SN/A#else 2252307SN/A int active_threads = 1; 2262292SN/A#endif 2272292SN/A 2282316SN/A //Make Sure That this a Valid Architeture 2292292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2302292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2312292SN/A 2322292SN/A rename.setScoreboard(&scoreboard); 2332292SN/A iew.setScoreboard(&scoreboard); 2342292SN/A 2351060SN/A // Setup the rename map for whichever stages need it. 2362292SN/A PhysRegIndex lreg_idx = 0; 2372292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2381060SN/A 2392292SN/A for (int tid=0; tid < numThreads; tid++) { 2402307SN/A bool bindRegs = (tid <= active_threads - 1); 2412292SN/A 2422292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2432292SN/A params->numPhysIntRegs, 2442325SN/A lreg_idx, //Index for Logical. Regs 2452292SN/A 2462292SN/A TheISA::NumFloatRegs, 2472292SN/A params->numPhysFloatRegs, 2482325SN/A freg_idx, //Index for Float Regs 2492292SN/A 2502292SN/A TheISA::NumMiscRegs, 2512292SN/A 2522292SN/A TheISA::ZeroReg, 2532292SN/A TheISA::ZeroReg, 2542292SN/A 2552292SN/A tid, 2562292SN/A false); 2572292SN/A 2582292SN/A renameMap[tid].init(TheISA::NumIntRegs, 2592292SN/A params->numPhysIntRegs, 2602325SN/A lreg_idx, //Index for Logical. Regs 2612292SN/A 2622292SN/A TheISA::NumFloatRegs, 2632292SN/A params->numPhysFloatRegs, 2642325SN/A freg_idx, //Index for Float Regs 2652292SN/A 2662292SN/A TheISA::NumMiscRegs, 2672292SN/A 2682292SN/A TheISA::ZeroReg, 2692292SN/A TheISA::ZeroReg, 2702292SN/A 2712292SN/A tid, 2722292SN/A bindRegs); 2732292SN/A } 2742292SN/A 2752292SN/A rename.setRenameMap(renameMap); 2762292SN/A commit.setRenameMap(commitRenameMap); 2772292SN/A 2782292SN/A // Give renameMap & rename stage access to the freeList; 2792292SN/A for (int i=0; i < numThreads; i++) { 2802292SN/A renameMap[i].setFreeList(&freeList); 2812292SN/A } 2821060SN/A rename.setFreeList(&freeList); 2832292SN/A 2841060SN/A // Setup the ROB for whichever stages need it. 2851060SN/A commit.setROB(&rob); 2862292SN/A 2872292SN/A lastRunningCycle = curTick; 2882292SN/A 2892829Sksewell@umich.edu lastActivatedCycle = -1; 2902829Sksewell@umich.edu 2912292SN/A contextSwitch = false; 2921060SN/A} 2931060SN/A 2941060SN/Atemplate <class Impl> 2951755SN/AFullO3CPU<Impl>::~FullO3CPU() 2961060SN/A{ 2971060SN/A} 2981060SN/A 2991060SN/Atemplate <class Impl> 3001060SN/Avoid 3011755SN/AFullO3CPU<Impl>::fullCPURegStats() 3021062SN/A{ 3032733Sktlim@umich.edu BaseO3CPU::regStats(); 3042292SN/A 3052733Sktlim@umich.edu // Register any of the O3CPU's stats here. 3062292SN/A timesIdled 3072292SN/A .name(name() + ".timesIdled") 3082292SN/A .desc("Number of times that the entire CPU went into an idle state and" 3092292SN/A " unscheduled itself") 3102292SN/A .prereq(timesIdled); 3112292SN/A 3122292SN/A idleCycles 3132292SN/A .name(name() + ".idleCycles") 3142292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 3152292SN/A "to idling") 3162292SN/A .prereq(idleCycles); 3172292SN/A 3182292SN/A // Number of Instructions simulated 3192292SN/A // -------------------------------- 3202292SN/A // Should probably be in Base CPU but need templated 3212292SN/A // MaxThreads so put in here instead 3222292SN/A committedInsts 3232292SN/A .init(numThreads) 3242292SN/A .name(name() + ".committedInsts") 3252292SN/A .desc("Number of Instructions Simulated"); 3262292SN/A 3272292SN/A totalCommittedInsts 3282292SN/A .name(name() + ".committedInsts_total") 3292292SN/A .desc("Number of Instructions Simulated"); 3302292SN/A 3312292SN/A cpi 3322292SN/A .name(name() + ".cpi") 3332292SN/A .desc("CPI: Cycles Per Instruction") 3342292SN/A .precision(6); 3352292SN/A cpi = simTicks / committedInsts; 3362292SN/A 3372292SN/A totalCpi 3382292SN/A .name(name() + ".cpi_total") 3392292SN/A .desc("CPI: Total CPI of All Threads") 3402292SN/A .precision(6); 3412292SN/A totalCpi = simTicks / totalCommittedInsts; 3422292SN/A 3432292SN/A ipc 3442292SN/A .name(name() + ".ipc") 3452292SN/A .desc("IPC: Instructions Per Cycle") 3462292SN/A .precision(6); 3472292SN/A ipc = committedInsts / simTicks; 3482292SN/A 3492292SN/A totalIpc 3502292SN/A .name(name() + ".ipc_total") 3512292SN/A .desc("IPC: Total IPC of All Threads") 3522292SN/A .precision(6); 3532292SN/A totalIpc = totalCommittedInsts / simTicks; 3542292SN/A 3551062SN/A} 3561062SN/A 3571062SN/Atemplate <class Impl> 3581062SN/Avoid 3591755SN/AFullO3CPU<Impl>::tick() 3601060SN/A{ 3612733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 3621060SN/A 3632292SN/A ++numCycles; 3642292SN/A 3652325SN/A// activity = false; 3662292SN/A 3672292SN/A //Tick each of the stages 3681060SN/A fetch.tick(); 3691060SN/A 3701060SN/A decode.tick(); 3711060SN/A 3721060SN/A rename.tick(); 3731060SN/A 3741060SN/A iew.tick(); 3751060SN/A 3761060SN/A commit.tick(); 3771060SN/A 3782292SN/A#if !FULL_SYSTEM 3792292SN/A doContextSwitch(); 3802292SN/A#endif 3812292SN/A 3822292SN/A // Now advance the time buffers 3831060SN/A timeBuffer.advance(); 3841060SN/A 3851060SN/A fetchQueue.advance(); 3861060SN/A decodeQueue.advance(); 3871060SN/A renameQueue.advance(); 3881060SN/A iewQueue.advance(); 3891060SN/A 3902325SN/A activityRec.advance(); 3912292SN/A 3922292SN/A if (removeInstsThisCycle) { 3932292SN/A cleanUpRemovedInsts(); 3942292SN/A } 3952292SN/A 3962325SN/A if (!tickEvent.scheduled()) { 3972325SN/A if (_status == SwitchedOut) { 3982325SN/A // increment stat 3992325SN/A lastRunningCycle = curTick; 4002325SN/A } else if (!activityRec.active()) { 4012325SN/A lastRunningCycle = curTick; 4022325SN/A timesIdled++; 4032325SN/A } else { 4042325SN/A tickEvent.schedule(curTick + cycles(1)); 4052325SN/A } 4062292SN/A } 4072292SN/A 4082292SN/A#if !FULL_SYSTEM 4092292SN/A updateThreadPriority(); 4102292SN/A#endif 4112292SN/A 4121060SN/A} 4131060SN/A 4141060SN/Atemplate <class Impl> 4151060SN/Avoid 4161755SN/AFullO3CPU<Impl>::init() 4171060SN/A{ 4182307SN/A if (!deferRegistration) { 4192680Sktlim@umich.edu registerThreadContexts(); 4202292SN/A } 4211060SN/A 4222292SN/A // Set inSyscall so that the CPU doesn't squash when initially 4232292SN/A // setting up registers. 4242292SN/A for (int i = 0; i < number_of_threads; ++i) 4252292SN/A thread[i]->inSyscall = true; 4262292SN/A 4272292SN/A for (int tid=0; tid < number_of_threads; tid++) { 4281858SN/A#if FULL_SYSTEM 4292680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 4301681SN/A#else 4312680Sktlim@umich.edu ThreadContext *src_tc = thread[tid]->getTC(); 4321681SN/A#endif 4332292SN/A // Threads start in the Suspended State 4342680Sktlim@umich.edu if (src_tc->status() != ThreadContext::Suspended) { 4352292SN/A continue; 4361060SN/A } 4371060SN/A 4382292SN/A#if FULL_SYSTEM 4392680Sktlim@umich.edu TheISA::initCPU(src_tc, src_tc->readCpuId()); 4402292SN/A#endif 4412292SN/A } 4422292SN/A 4432292SN/A // Clear inSyscall. 4442292SN/A for (int i = 0; i < number_of_threads; ++i) 4452292SN/A thread[i]->inSyscall = false; 4462292SN/A 4472316SN/A // Initialize stages. 4482292SN/A fetch.initStage(); 4492292SN/A iew.initStage(); 4502292SN/A rename.initStage(); 4512292SN/A commit.initStage(); 4522292SN/A 4532292SN/A commit.setThreads(thread); 4542292SN/A} 4552292SN/A 4562292SN/Atemplate <class Impl> 4572292SN/Avoid 4582292SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 4592292SN/A{ 4602733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread data"); 4612292SN/A // Will change now that the PC and thread state is internal to the CPU 4622683Sktlim@umich.edu // and not in the ThreadContext. 4632292SN/A#if 0 4642292SN/A#if FULL_SYSTEM 4652680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 4662292SN/A#else 4672683Sktlim@umich.edu ThreadContext *src_tc = thread[tid]; 4682292SN/A#endif 4692292SN/A 4702292SN/A //Bind Int Regs to Rename Map 4712292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 4722292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 4732292SN/A 4742292SN/A renameMap[tid].setEntry(ireg,phys_reg); 4752292SN/A scoreboard.setReg(phys_reg); 4762292SN/A } 4772292SN/A 4782292SN/A //Bind Float Regs to Rename Map 4792292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 4802292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 4812292SN/A 4822292SN/A renameMap[tid].setEntry(freg,phys_reg); 4832292SN/A scoreboard.setReg(phys_reg); 4842292SN/A } 4852292SN/A 4862292SN/A //Copy Thread Data Into RegFile 4872680Sktlim@umich.edu this->copyFromTC(tid); 4882292SN/A 4892292SN/A //Set PC/NPC 4902680Sktlim@umich.edu regFile.pc[tid] = src_tc->readPC(); 4912680Sktlim@umich.edu regFile.npc[tid] = src_tc->readNextPC(); 4922292SN/A 4932680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 4942292SN/A 4952292SN/A activateContext(tid,1); 4962292SN/A 4972292SN/A //Reset ROB/IQ/LSQ Entries 4982292SN/A commit.rob->resetEntries(); 4992292SN/A iew.resetEntries(); 5002292SN/A#endif 5012292SN/A} 5022292SN/A 5032292SN/Atemplate <class Impl> 5042292SN/Avoid 5052292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 5062292SN/A{ 5072733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread data"); 5082292SN/A#if 0 5092292SN/A //Unbind Int Regs from Rename Map 5102292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 5112292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 5122292SN/A 5132292SN/A scoreboard.unsetReg(phys_reg); 5142292SN/A freeList.addReg(phys_reg); 5152292SN/A } 5162292SN/A 5172292SN/A //Unbind Float Regs from Rename Map 5182292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 5192292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 5202292SN/A 5212292SN/A scoreboard.unsetReg(phys_reg); 5222292SN/A freeList.addReg(phys_reg); 5232292SN/A } 5242292SN/A 5252292SN/A //Copy Thread Data From RegFile 5262292SN/A /* Fix Me: 5272292SN/A * Do we really need to do this if we are removing a thread 5282292SN/A * in the sense that it's finished (exiting)? If the thread is just 5292292SN/A * being suspended we might... 5302292SN/A */ 5312680Sktlim@umich.edu// this->copyToTC(tid); 5322292SN/A 5332292SN/A //Squash Throughout Pipeline 5342292SN/A fetch.squash(0,tid); 5352292SN/A decode.squash(tid); 5362292SN/A rename.squash(tid); 5372292SN/A 5382292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 5392292SN/A 5402292SN/A //Reset ROB/IQ/LSQ Entries 5412292SN/A if (activeThreads.size() >= 1) { 5422292SN/A commit.rob->resetEntries(); 5432292SN/A iew.resetEntries(); 5442292SN/A } 5452292SN/A#endif 5462292SN/A} 5472292SN/A 5482292SN/A 5492292SN/Atemplate <class Impl> 5502292SN/Avoid 5512292SN/AFullO3CPU<Impl>::activateWhenReady(int tid) 5522292SN/A{ 5532733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 5542292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 5552292SN/A tid); 5562292SN/A 5572292SN/A bool ready = true; 5582292SN/A 5592292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 5602733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5612292SN/A "Phys. Int. Regs.\n", 5622292SN/A tid); 5632292SN/A ready = false; 5642292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 5652733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5662292SN/A "Phys. Float. Regs.\n", 5672292SN/A tid); 5682292SN/A ready = false; 5692292SN/A } else if (commit.rob->numFreeEntries() >= 5702292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 5712733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5722292SN/A "ROB entries.\n", 5732292SN/A tid); 5742292SN/A ready = false; 5752292SN/A } else if (iew.instQueue.numFreeEntries() >= 5762292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 5772733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5782292SN/A "IQ entries.\n", 5792292SN/A tid); 5802292SN/A ready = false; 5812292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 5822292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 5832733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5842292SN/A "LSQ entries.\n", 5852292SN/A tid); 5862292SN/A ready = false; 5872292SN/A } 5882292SN/A 5892292SN/A if (ready) { 5902292SN/A insertThread(tid); 5912292SN/A 5922292SN/A contextSwitch = false; 5932292SN/A 5942292SN/A cpuWaitList.remove(tid); 5952292SN/A } else { 5962292SN/A suspendContext(tid); 5972292SN/A 5982292SN/A //blocks fetch 5992292SN/A contextSwitch = true; 6002292SN/A 6012292SN/A //do waitlist 6022292SN/A cpuWaitList.push_back(tid); 6031060SN/A } 6041060SN/A} 6051060SN/A 6061060SN/Atemplate <class Impl> 6071060SN/Avoid 6082829Sksewell@umich.eduFullO3CPU<Impl>::activateThread(unsigned int tid) 6091060SN/A{ 6102292SN/A list<unsigned>::iterator isActive = find( 6112292SN/A activeThreads.begin(), activeThreads.end(), tid); 6122292SN/A 6132292SN/A if (isActive == activeThreads.end()) { 6142829Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6152292SN/A tid); 6162292SN/A 6172292SN/A activeThreads.push_back(tid); 6182292SN/A } 6192829Sksewell@umich.edu} 6202292SN/A 6211060SN/A 6222829Sksewell@umich.edutemplate <class Impl> 6232829Sksewell@umich.eduvoid 6242829Sksewell@umich.eduFullO3CPU<Impl>::activateContext(int tid, int delay) 6252829Sksewell@umich.edu{ 6262829Sksewell@umich.edu // Needs to set each stage to running as well. 6272829Sksewell@umich.edu if (delay){ 6282829Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 6292829Sksewell@umich.edu "on cycle %d\n", tid, curTick + cycles(delay)); 6302829Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 6312829Sksewell@umich.edu } else { 6322829Sksewell@umich.edu activateThread(tid); 6332829Sksewell@umich.edu } 6341060SN/A 6352829Sksewell@umich.edu if(lastActivatedCycle < curTick) { 6362829Sksewell@umich.edu scheduleTickEvent(delay); 6372292SN/A 6382829Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 6392829Sksewell@umich.edu // deschedule itself. 6402829Sksewell@umich.edu activityRec.activity(); 6412829Sksewell@umich.edu fetch.wakeFromQuiesce(); 6422829Sksewell@umich.edu 6432829Sksewell@umich.edu lastActivatedCycle = curTick; 6442829Sksewell@umich.edu 6452829Sksewell@umich.edu _status = Running; 6462829Sksewell@umich.edu } 6471060SN/A} 6481060SN/A 6491060SN/Atemplate <class Impl> 6501060SN/Avoid 6512292SN/AFullO3CPU<Impl>::suspendContext(int tid) 6521060SN/A{ 6532733Sktlim@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspended ...\n", tid); 6542292SN/A unscheduleTickEvent(); 6552292SN/A _status = Idle; 6562292SN/A/* 6572292SN/A //Remove From Active List, if Active 6582292SN/A list<unsigned>::iterator isActive = find( 6592292SN/A activeThreads.begin(), activeThreads.end(), tid); 6602292SN/A 6612292SN/A if (isActive != activeThreads.end()) { 6622733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6632292SN/A tid); 6642292SN/A activeThreads.erase(isActive); 6652292SN/A } 6662292SN/A*/ 6671060SN/A} 6681060SN/A 6691060SN/Atemplate <class Impl> 6701060SN/Avoid 6712292SN/AFullO3CPU<Impl>::deallocateContext(int tid) 6721060SN/A{ 6732733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Deallocating ...", tid); 6742292SN/A/* 6752292SN/A //Remove From Active List, if Active 6762292SN/A list<unsigned>::iterator isActive = find( 6772292SN/A activeThreads.begin(), activeThreads.end(), tid); 6782292SN/A 6792292SN/A if (isActive != activeThreads.end()) { 6802733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6812292SN/A tid); 6822292SN/A activeThreads.erase(isActive); 6832292SN/A 6842292SN/A removeThread(tid); 6852292SN/A } 6862292SN/A*/ 6871060SN/A} 6881060SN/A 6891060SN/Atemplate <class Impl> 6901060SN/Avoid 6912292SN/AFullO3CPU<Impl>::haltContext(int tid) 6921060SN/A{ 6932733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halted ...", tid); 6942292SN/A/* 6952292SN/A //Remove From Active List, if Active 6962292SN/A list<unsigned>::iterator isActive = find( 6972292SN/A activeThreads.begin(), activeThreads.end(), tid); 6982292SN/A 6992292SN/A if (isActive != activeThreads.end()) { 7002733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 7012292SN/A tid); 7022292SN/A activeThreads.erase(isActive); 7032292SN/A 7042292SN/A removeThread(tid); 7052292SN/A } 7062292SN/A*/ 7071060SN/A} 7081060SN/A 7091060SN/Atemplate <class Impl> 7101060SN/Avoid 7112316SN/AFullO3CPU<Impl>::switchOut(Sampler *_sampler) 7121060SN/A{ 7132316SN/A sampler = _sampler; 7142316SN/A switchCount = 0; 7152307SN/A fetch.switchOut(); 7162307SN/A decode.switchOut(); 7172307SN/A rename.switchOut(); 7182307SN/A iew.switchOut(); 7192307SN/A commit.switchOut(); 7202325SN/A 7212325SN/A // Wake the CPU and record activity so everything can drain out if 7222325SN/A // the CPU is currently idle. 7232325SN/A wakeCPU(); 7242325SN/A activityRec.activity(); 7252316SN/A} 7262310SN/A 7272316SN/Atemplate <class Impl> 7282316SN/Avoid 7292316SN/AFullO3CPU<Impl>::signalSwitched() 7302316SN/A{ 7312325SN/A if (++switchCount == NumStages) { 7322316SN/A fetch.doSwitchOut(); 7332316SN/A rename.doSwitchOut(); 7342316SN/A commit.doSwitchOut(); 7352316SN/A instList.clear(); 7362316SN/A while (!removeList.empty()) { 7372316SN/A removeList.pop(); 7382316SN/A } 7392316SN/A 7402794Sktlim@umich.edu#if USE_CHECKER 7412316SN/A if (checker) 7422316SN/A checker->switchOut(sampler); 7432794Sktlim@umich.edu#endif 7442316SN/A 7452316SN/A if (tickEvent.scheduled()) 7462316SN/A tickEvent.squash(); 7472316SN/A sampler->signalSwitched(); 7482316SN/A _status = SwitchedOut; 7492310SN/A } 7502316SN/A assert(switchCount <= 5); 7511060SN/A} 7521060SN/A 7531060SN/Atemplate <class Impl> 7541060SN/Avoid 7551755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 7561060SN/A{ 7572325SN/A // Flush out any old data from the time buffers. 7582325SN/A for (int i = 0; i < 10; ++i) { 7592307SN/A timeBuffer.advance(); 7602307SN/A fetchQueue.advance(); 7612307SN/A decodeQueue.advance(); 7622307SN/A renameQueue.advance(); 7632307SN/A iewQueue.advance(); 7642307SN/A } 7652307SN/A 7662325SN/A activityRec.reset(); 7672307SN/A 7681060SN/A BaseCPU::takeOverFrom(oldCPU); 7691060SN/A 7702307SN/A fetch.takeOverFrom(); 7712307SN/A decode.takeOverFrom(); 7722307SN/A rename.takeOverFrom(); 7732307SN/A iew.takeOverFrom(); 7742307SN/A commit.takeOverFrom(); 7752307SN/A 7761060SN/A assert(!tickEvent.scheduled()); 7771060SN/A 7782325SN/A // @todo: Figure out how to properly select the tid to put onto 7792325SN/A // the active threads list. 7802307SN/A int tid = 0; 7812307SN/A 7822307SN/A list<unsigned>::iterator isActive = find( 7832307SN/A activeThreads.begin(), activeThreads.end(), tid); 7842307SN/A 7852307SN/A if (isActive == activeThreads.end()) { 7862325SN/A //May Need to Re-code this if the delay variable is the delay 7872325SN/A //needed for thread to activate 7882733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 7892307SN/A tid); 7902307SN/A 7912307SN/A activeThreads.push_back(tid); 7922307SN/A } 7932307SN/A 7942325SN/A // Set all statuses to active, schedule the CPU's tick event. 7952307SN/A // @todo: Fix up statuses so this is handled properly 7962680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 7972680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 7982680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 7991681SN/A _status = Running; 8001681SN/A tickEvent.schedule(curTick); 8011681SN/A } 8021060SN/A } 8032307SN/A if (!tickEvent.scheduled()) 8042307SN/A tickEvent.schedule(curTick); 8051060SN/A} 8061060SN/A 8071060SN/Atemplate <class Impl> 8081060SN/Auint64_t 8091755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 8101060SN/A{ 8111060SN/A return regFile.readIntReg(reg_idx); 8121060SN/A} 8131060SN/A 8141060SN/Atemplate <class Impl> 8152455SN/AFloatReg 8162455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 8171060SN/A{ 8182455SN/A return regFile.readFloatReg(reg_idx, width); 8191060SN/A} 8201060SN/A 8211060SN/Atemplate <class Impl> 8222455SN/AFloatReg 8232455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 8241060SN/A{ 8252455SN/A return regFile.readFloatReg(reg_idx); 8261060SN/A} 8271060SN/A 8281060SN/Atemplate <class Impl> 8292455SN/AFloatRegBits 8302455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 8311060SN/A{ 8322455SN/A return regFile.readFloatRegBits(reg_idx, width); 8332455SN/A} 8342455SN/A 8352455SN/Atemplate <class Impl> 8362455SN/AFloatRegBits 8372455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 8382455SN/A{ 8392455SN/A return regFile.readFloatRegBits(reg_idx); 8401060SN/A} 8411060SN/A 8421060SN/Atemplate <class Impl> 8431060SN/Avoid 8441755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 8451060SN/A{ 8461060SN/A regFile.setIntReg(reg_idx, val); 8471060SN/A} 8481060SN/A 8491060SN/Atemplate <class Impl> 8501060SN/Avoid 8512455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 8521060SN/A{ 8532455SN/A regFile.setFloatReg(reg_idx, val, width); 8541060SN/A} 8551060SN/A 8561060SN/Atemplate <class Impl> 8571060SN/Avoid 8582455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 8591060SN/A{ 8602455SN/A regFile.setFloatReg(reg_idx, val); 8611060SN/A} 8621060SN/A 8631060SN/Atemplate <class Impl> 8641060SN/Avoid 8652455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 8661060SN/A{ 8672455SN/A regFile.setFloatRegBits(reg_idx, val, width); 8682455SN/A} 8692455SN/A 8702455SN/Atemplate <class Impl> 8712455SN/Avoid 8722455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 8732455SN/A{ 8742455SN/A regFile.setFloatRegBits(reg_idx, val); 8751060SN/A} 8761060SN/A 8771060SN/Atemplate <class Impl> 8781060SN/Auint64_t 8792292SN/AFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 8801060SN/A{ 8812292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8822292SN/A 8832292SN/A return regFile.readIntReg(phys_reg); 8842292SN/A} 8852292SN/A 8862292SN/Atemplate <class Impl> 8872292SN/Afloat 8882292SN/AFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 8892292SN/A{ 8902307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 8912307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 8922292SN/A 8932669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 8942292SN/A} 8952292SN/A 8962292SN/Atemplate <class Impl> 8972292SN/Adouble 8982292SN/AFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 8992292SN/A{ 9002307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 9012307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 9022292SN/A 9032669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 9042292SN/A} 9052292SN/A 9062292SN/Atemplate <class Impl> 9072292SN/Auint64_t 9082292SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 9092292SN/A{ 9102307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 9112307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 9122292SN/A 9132669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 9141060SN/A} 9151060SN/A 9161060SN/Atemplate <class Impl> 9171060SN/Avoid 9182292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 9191060SN/A{ 9202292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 9212292SN/A 9222292SN/A regFile.setIntReg(phys_reg, val); 9231060SN/A} 9241060SN/A 9251060SN/Atemplate <class Impl> 9261060SN/Avoid 9272292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 9281060SN/A{ 9292292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 9302292SN/A 9312669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 9321060SN/A} 9331060SN/A 9341060SN/Atemplate <class Impl> 9351060SN/Avoid 9362292SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 9371060SN/A{ 9382292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 9392292SN/A 9402669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 9411060SN/A} 9421060SN/A 9431060SN/Atemplate <class Impl> 9441060SN/Avoid 9452292SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 9461060SN/A{ 9472292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 9481060SN/A 9492669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 9502292SN/A} 9512292SN/A 9522292SN/Atemplate <class Impl> 9532292SN/Auint64_t 9542292SN/AFullO3CPU<Impl>::readPC(unsigned tid) 9552292SN/A{ 9562292SN/A return commit.readPC(tid); 9571060SN/A} 9581060SN/A 9591060SN/Atemplate <class Impl> 9601060SN/Avoid 9612292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 9621060SN/A{ 9632292SN/A commit.setPC(new_PC, tid); 9642292SN/A} 9651060SN/A 9662292SN/Atemplate <class Impl> 9672292SN/Auint64_t 9682292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 9692292SN/A{ 9702292SN/A return commit.readNextPC(tid); 9712292SN/A} 9721060SN/A 9732292SN/Atemplate <class Impl> 9742292SN/Avoid 9752292SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 9762292SN/A{ 9772292SN/A commit.setNextPC(val, tid); 9782292SN/A} 9791060SN/A 9802756Sksewell@umich.edu#if THE_ISA != ALPHA_ISA 9812756Sksewell@umich.edutemplate <class Impl> 9822756Sksewell@umich.eduuint64_t 9832756Sksewell@umich.eduFullO3CPU<Impl>::readNextNPC(unsigned tid) 9842756Sksewell@umich.edu{ 9852756Sksewell@umich.edu return commit.readNextNPC(tid); 9862756Sksewell@umich.edu} 9872756Sksewell@umich.edu 9882756Sksewell@umich.edutemplate <class Impl> 9892756Sksewell@umich.eduvoid 9902756Sksewell@umich.eduFullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid) 9912756Sksewell@umich.edu{ 9922756Sksewell@umich.edu commit.setNextNPC(val, tid); 9932756Sksewell@umich.edu} 9942756Sksewell@umich.edu#endif 9952756Sksewell@umich.edu 9962292SN/Atemplate <class Impl> 9972292SN/Atypename FullO3CPU<Impl>::ListIt 9982292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 9992292SN/A{ 10002292SN/A instList.push_back(inst); 10011060SN/A 10022292SN/A return --(instList.end()); 10032292SN/A} 10041060SN/A 10052292SN/Atemplate <class Impl> 10062292SN/Avoid 10072292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 10082292SN/A{ 10092292SN/A // Keep an instruction count. 10102292SN/A thread[tid]->numInst++; 10112292SN/A thread[tid]->numInsts++; 10122292SN/A committedInsts[tid]++; 10132292SN/A totalCommittedInsts++; 10142292SN/A 10152292SN/A // Check for instruction-count-based events. 10162292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 10172292SN/A} 10182292SN/A 10192292SN/Atemplate <class Impl> 10202292SN/Avoid 10212292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 10222292SN/A{ 10232292SN/A removeInstsThisCycle = true; 10242292SN/A 10252292SN/A removeList.push(inst->getInstListIt()); 10261060SN/A} 10271060SN/A 10281060SN/Atemplate <class Impl> 10291060SN/Avoid 10301755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 10311060SN/A{ 10322733Sktlim@umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 10332292SN/A "[sn:%lli]\n", 10342303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 10351060SN/A 10362292SN/A removeInstsThisCycle = true; 10371060SN/A 10381060SN/A // Remove the front instruction. 10392292SN/A removeList.push(inst->getInstListIt()); 10401060SN/A} 10411060SN/A 10421060SN/Atemplate <class Impl> 10431060SN/Avoid 10442292SN/AFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 10451060SN/A{ 10462733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 10472292SN/A " list.\n", tid); 10481060SN/A 10492292SN/A ListIt end_it; 10501060SN/A 10512292SN/A bool rob_empty = false; 10522292SN/A 10532292SN/A if (instList.empty()) { 10542292SN/A return; 10552292SN/A } else if (rob.isEmpty(/*tid*/)) { 10562733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 10572292SN/A end_it = instList.begin(); 10582292SN/A rob_empty = true; 10592292SN/A } else { 10602292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 10612733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 10622292SN/A } 10632292SN/A 10642292SN/A removeInstsThisCycle = true; 10652292SN/A 10662292SN/A ListIt inst_it = instList.end(); 10672292SN/A 10682292SN/A inst_it--; 10692292SN/A 10702292SN/A // Walk through the instruction list, removing any instructions 10712292SN/A // that were inserted after the given instruction iterator, end_it. 10722292SN/A while (inst_it != end_it) { 10732292SN/A assert(!instList.empty()); 10742292SN/A 10752292SN/A squashInstIt(inst_it, tid); 10762292SN/A 10772292SN/A inst_it--; 10782292SN/A } 10792292SN/A 10802292SN/A // If the ROB was empty, then we actually need to remove the first 10812292SN/A // instruction as well. 10822292SN/A if (rob_empty) { 10832292SN/A squashInstIt(inst_it, tid); 10842292SN/A } 10851060SN/A} 10861060SN/A 10871060SN/Atemplate <class Impl> 10881060SN/Avoid 10892292SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 10902292SN/A unsigned tid) 10911062SN/A{ 10922292SN/A assert(!instList.empty()); 10932292SN/A 10942292SN/A removeInstsThisCycle = true; 10952292SN/A 10962292SN/A ListIt inst_iter = instList.end(); 10972292SN/A 10982292SN/A inst_iter--; 10992292SN/A 11002733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 11012292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 11022292SN/A tid, seq_num, (*inst_iter)->seqNum); 11031062SN/A 11042292SN/A while ((*inst_iter)->seqNum > seq_num) { 11051062SN/A 11062292SN/A bool break_loop = (inst_iter == instList.begin()); 11071062SN/A 11082292SN/A squashInstIt(inst_iter, tid); 11091062SN/A 11102292SN/A inst_iter--; 11111062SN/A 11122292SN/A if (break_loop) 11132292SN/A break; 11142292SN/A } 11152292SN/A} 11162292SN/A 11172292SN/Atemplate <class Impl> 11182292SN/Ainline void 11192292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 11202292SN/A{ 11212292SN/A if ((*instIt)->threadNumber == tid) { 11222733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 11232292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 11242292SN/A (*instIt)->threadNumber, 11252292SN/A (*instIt)->seqNum, 11262292SN/A (*instIt)->readPC()); 11271062SN/A 11281062SN/A // Mark it as squashed. 11292292SN/A (*instIt)->setSquashed(); 11302292SN/A 11312325SN/A // @todo: Formulate a consistent method for deleting 11322325SN/A // instructions from the instruction list 11332292SN/A // Remove the instruction from the list. 11342292SN/A removeList.push(instIt); 11352292SN/A } 11362292SN/A} 11372292SN/A 11382292SN/Atemplate <class Impl> 11392292SN/Avoid 11402292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 11412292SN/A{ 11422292SN/A while (!removeList.empty()) { 11432733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 11442292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 11452292SN/A (*removeList.front())->threadNumber, 11462292SN/A (*removeList.front())->seqNum, 11472292SN/A (*removeList.front())->readPC()); 11482292SN/A 11492292SN/A instList.erase(removeList.front()); 11502292SN/A 11512292SN/A removeList.pop(); 11521062SN/A } 11531062SN/A 11542292SN/A removeInstsThisCycle = false; 11551062SN/A} 11562325SN/A/* 11571062SN/Atemplate <class Impl> 11581062SN/Avoid 11591755SN/AFullO3CPU<Impl>::removeAllInsts() 11601060SN/A{ 11611060SN/A instList.clear(); 11621060SN/A} 11632325SN/A*/ 11641060SN/Atemplate <class Impl> 11651060SN/Avoid 11661755SN/AFullO3CPU<Impl>::dumpInsts() 11671060SN/A{ 11681060SN/A int num = 0; 11691060SN/A 11702292SN/A ListIt inst_list_it = instList.begin(); 11712292SN/A 11722292SN/A cprintf("Dumping Instruction List\n"); 11732292SN/A 11742292SN/A while (inst_list_it != instList.end()) { 11752292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 11762292SN/A "Squashed:%i\n\n", 11772292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 11782292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 11792292SN/A (*inst_list_it)->isSquashed()); 11801060SN/A inst_list_it++; 11811060SN/A ++num; 11821060SN/A } 11831060SN/A} 11842325SN/A/* 11851060SN/Atemplate <class Impl> 11861060SN/Avoid 11871755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 11881060SN/A{ 11891060SN/A iew.wakeDependents(inst); 11901060SN/A} 11912325SN/A*/ 11922292SN/Atemplate <class Impl> 11932292SN/Avoid 11942292SN/AFullO3CPU<Impl>::wakeCPU() 11952292SN/A{ 11962325SN/A if (activityRec.active() || tickEvent.scheduled()) { 11972325SN/A DPRINTF(Activity, "CPU already running.\n"); 11982292SN/A return; 11992292SN/A } 12002292SN/A 12012325SN/A DPRINTF(Activity, "Waking up CPU\n"); 12022325SN/A 12032325SN/A idleCycles += (curTick - 1) - lastRunningCycle; 12042292SN/A 12052292SN/A tickEvent.schedule(curTick); 12062292SN/A} 12072292SN/A 12082292SN/Atemplate <class Impl> 12092292SN/Aint 12102292SN/AFullO3CPU<Impl>::getFreeTid() 12112292SN/A{ 12122292SN/A for (int i=0; i < numThreads; i++) { 12132292SN/A if (!tids[i]) { 12142292SN/A tids[i] = true; 12152292SN/A return i; 12162292SN/A } 12172292SN/A } 12182292SN/A 12192292SN/A return -1; 12202292SN/A} 12212292SN/A 12222292SN/Atemplate <class Impl> 12232292SN/Avoid 12242292SN/AFullO3CPU<Impl>::doContextSwitch() 12252292SN/A{ 12262292SN/A if (contextSwitch) { 12272292SN/A 12282292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 12292292SN/A 12302292SN/A for (int tid=0; tid < cpuWaitList.size(); tid++) { 12312292SN/A activateWhenReady(tid); 12322292SN/A } 12332292SN/A 12342292SN/A if (cpuWaitList.size() == 0) 12352292SN/A contextSwitch = true; 12362292SN/A } 12372292SN/A} 12382292SN/A 12392292SN/Atemplate <class Impl> 12402292SN/Avoid 12412292SN/AFullO3CPU<Impl>::updateThreadPriority() 12422292SN/A{ 12432292SN/A if (activeThreads.size() > 1) 12442292SN/A { 12452292SN/A //DEFAULT TO ROUND ROBIN SCHEME 12462292SN/A //e.g. Move highest priority to end of thread list 12472292SN/A list<unsigned>::iterator list_begin = activeThreads.begin(); 12482292SN/A list<unsigned>::iterator list_end = activeThreads.end(); 12492292SN/A 12502292SN/A unsigned high_thread = *list_begin; 12512292SN/A 12522292SN/A activeThreads.erase(list_begin); 12532292SN/A 12542292SN/A activeThreads.push_back(high_thread); 12552292SN/A } 12562292SN/A} 12571060SN/A 12581755SN/A// Forward declaration of FullO3CPU. 12592818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1260