cpu.cc revision 2794
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292756Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 332733Sktlim@umich.edu#include "config/use_checker.hh" 341858SN/A 351858SN/A#if FULL_SYSTEM 361060SN/A#include "sim/system.hh" 371060SN/A#else 381060SN/A#include "sim/process.hh" 391060SN/A#endif 401060SN/A 412325SN/A#include "cpu/activity.hh" 422683Sktlim@umich.edu#include "cpu/simple_thread.hh" 432680Sktlim@umich.edu#include "cpu/thread_context.hh" 441717SN/A#include "cpu/o3/alpha_dyn_inst.hh" 451717SN/A#include "cpu/o3/alpha_impl.hh" 461717SN/A#include "cpu/o3/cpu.hh" 471060SN/A 482325SN/A#include "sim/root.hh" 492292SN/A#include "sim/stat_control.hh" 502292SN/A 512794Sktlim@umich.edu#if USE_CHECKER 522794Sktlim@umich.edu#include "cpu/checker/cpu.hh" 532794Sktlim@umich.edu#endif 542794Sktlim@umich.edu 551060SN/Ausing namespace std; 562669Sktlim@umich.eduusing namespace TheISA; 571060SN/A 582733Sktlim@umich.eduBaseO3CPU::BaseO3CPU(Params *params) 592292SN/A : BaseCPU(params), cpu_id(0) 601060SN/A{ 611060SN/A} 621060SN/A 632292SN/Avoid 642733Sktlim@umich.eduBaseO3CPU::regStats() 652292SN/A{ 662292SN/A BaseCPU::regStats(); 672292SN/A} 682292SN/A 691060SN/Atemplate <class Impl> 701755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 711060SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 721060SN/A{ 731060SN/A} 741060SN/A 751060SN/Atemplate <class Impl> 761060SN/Avoid 771755SN/AFullO3CPU<Impl>::TickEvent::process() 781060SN/A{ 791060SN/A cpu->tick(); 801060SN/A} 811060SN/A 821060SN/Atemplate <class Impl> 831060SN/Aconst char * 841755SN/AFullO3CPU<Impl>::TickEvent::description() 851060SN/A{ 861755SN/A return "FullO3CPU tick event"; 871060SN/A} 881060SN/A 891060SN/Atemplate <class Impl> 902292SN/AFullO3CPU<Impl>::FullO3CPU(Params *params) 912733Sktlim@umich.edu : BaseO3CPU(params), 921060SN/A tickEvent(this), 932292SN/A removeInstsThisCycle(false), 941060SN/A fetch(params), 951060SN/A decode(params), 961060SN/A rename(params), 971060SN/A iew(params), 981060SN/A commit(params), 991060SN/A 1002292SN/A regFile(params->numPhysIntRegs, params->numPhysFloatRegs), 1011060SN/A 1022292SN/A freeList(params->numberOfThreads,//number of activeThreads 1032292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1042292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 1051060SN/A 1062292SN/A rob(params->numROBEntries, params->squashWidth, 1072292SN/A params->smtROBPolicy, params->smtROBThreshold, 1082292SN/A params->numberOfThreads), 1091060SN/A 1102292SN/A scoreboard(params->numberOfThreads,//number of activeThreads 1112292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1122292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1132292SN/A TheISA::NumMiscRegs * number_of_threads, 1142292SN/A TheISA::ZeroReg), 1151060SN/A 1161060SN/A // For now just have these time buffers be pretty big. 1172325SN/A // @todo: Make these time buffer sizes parameters or derived 1182325SN/A // from latencies 1191061SN/A timeBuffer(5, 5), 1201061SN/A fetchQueue(5, 5), 1211061SN/A decodeQueue(5, 5), 1221061SN/A renameQueue(5, 5), 1231061SN/A iewQueue(5, 5), 1242325SN/A activityRec(NumStages, 10, params->activity), 1251060SN/A 1261060SN/A globalSeqNum(1), 1271060SN/A 1281858SN/A#if FULL_SYSTEM 1292292SN/A system(params->system), 1301060SN/A physmem(system->physmem), 1311060SN/A#endif // FULL_SYSTEM 1322292SN/A mem(params->mem), 1332316SN/A switchCount(0), 1342316SN/A deferRegistration(params->deferRegistration), 1352316SN/A numThreads(number_of_threads) 1361060SN/A{ 1371060SN/A _status = Idle; 1381681SN/A 1392733Sktlim@umich.edu checker = NULL; 1402733Sktlim@umich.edu 1412794Sktlim@umich.edu if (params->checker) { 1422733Sktlim@umich.edu#if USE_CHECKER 1432316SN/A BaseCPU *temp_checker = params->checker; 1442316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 1452316SN/A checker->setMemory(mem); 1462316SN/A#if FULL_SYSTEM 1472316SN/A checker->setSystem(params->system); 1482316SN/A#endif 1492794Sktlim@umich.edu#else 1502794Sktlim@umich.edu panic("Checker enabled but not compiled in!"); 1512794Sktlim@umich.edu#endif // USE_CHECKER 1522316SN/A } 1532316SN/A 1541858SN/A#if !FULL_SYSTEM 1552292SN/A thread.resize(number_of_threads); 1562292SN/A tids.resize(number_of_threads); 1571681SN/A#endif 1581681SN/A 1592325SN/A // The stages also need their CPU pointer setup. However this 1602325SN/A // must be done at the upper level CPU because they have pointers 1612325SN/A // to the upper level CPU, and not this FullO3CPU. 1621060SN/A 1632292SN/A // Set up Pointers to the activeThreads list for each stage 1642292SN/A fetch.setActiveThreads(&activeThreads); 1652292SN/A decode.setActiveThreads(&activeThreads); 1662292SN/A rename.setActiveThreads(&activeThreads); 1672292SN/A iew.setActiveThreads(&activeThreads); 1682292SN/A commit.setActiveThreads(&activeThreads); 1691060SN/A 1701060SN/A // Give each of the stages the time buffer they will use. 1711060SN/A fetch.setTimeBuffer(&timeBuffer); 1721060SN/A decode.setTimeBuffer(&timeBuffer); 1731060SN/A rename.setTimeBuffer(&timeBuffer); 1741060SN/A iew.setTimeBuffer(&timeBuffer); 1751060SN/A commit.setTimeBuffer(&timeBuffer); 1761060SN/A 1771060SN/A // Also setup each of the stages' queues. 1781060SN/A fetch.setFetchQueue(&fetchQueue); 1791060SN/A decode.setFetchQueue(&fetchQueue); 1802292SN/A commit.setFetchQueue(&fetchQueue); 1811060SN/A decode.setDecodeQueue(&decodeQueue); 1821060SN/A rename.setDecodeQueue(&decodeQueue); 1831060SN/A rename.setRenameQueue(&renameQueue); 1841060SN/A iew.setRenameQueue(&renameQueue); 1851060SN/A iew.setIEWQueue(&iewQueue); 1861060SN/A commit.setIEWQueue(&iewQueue); 1871060SN/A commit.setRenameQueue(&renameQueue); 1881060SN/A 1892316SN/A commit.setFetchStage(&fetch); 1902292SN/A commit.setIEWStage(&iew); 1912292SN/A rename.setIEWStage(&iew); 1922292SN/A rename.setCommitStage(&commit); 1932292SN/A 1942292SN/A#if !FULL_SYSTEM 1952307SN/A int active_threads = params->workload.size(); 1962292SN/A#else 1972307SN/A int active_threads = 1; 1982292SN/A#endif 1992292SN/A 2002316SN/A //Make Sure That this a Valid Architeture 2012292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2022292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2032292SN/A 2042292SN/A rename.setScoreboard(&scoreboard); 2052292SN/A iew.setScoreboard(&scoreboard); 2062292SN/A 2071060SN/A // Setup the rename map for whichever stages need it. 2082292SN/A PhysRegIndex lreg_idx = 0; 2092292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2101060SN/A 2112292SN/A for (int tid=0; tid < numThreads; tid++) { 2122307SN/A bool bindRegs = (tid <= active_threads - 1); 2132292SN/A 2142292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2152292SN/A params->numPhysIntRegs, 2162325SN/A lreg_idx, //Index for Logical. Regs 2172292SN/A 2182292SN/A TheISA::NumFloatRegs, 2192292SN/A params->numPhysFloatRegs, 2202325SN/A freg_idx, //Index for Float Regs 2212292SN/A 2222292SN/A TheISA::NumMiscRegs, 2232292SN/A 2242292SN/A TheISA::ZeroReg, 2252292SN/A TheISA::ZeroReg, 2262292SN/A 2272292SN/A tid, 2282292SN/A false); 2292292SN/A 2302292SN/A renameMap[tid].init(TheISA::NumIntRegs, 2312292SN/A params->numPhysIntRegs, 2322325SN/A lreg_idx, //Index for Logical. Regs 2332292SN/A 2342292SN/A TheISA::NumFloatRegs, 2352292SN/A params->numPhysFloatRegs, 2362325SN/A freg_idx, //Index for Float Regs 2372292SN/A 2382292SN/A TheISA::NumMiscRegs, 2392292SN/A 2402292SN/A TheISA::ZeroReg, 2412292SN/A TheISA::ZeroReg, 2422292SN/A 2432292SN/A tid, 2442292SN/A bindRegs); 2452292SN/A } 2462292SN/A 2472292SN/A rename.setRenameMap(renameMap); 2482292SN/A commit.setRenameMap(commitRenameMap); 2492292SN/A 2502292SN/A // Give renameMap & rename stage access to the freeList; 2512292SN/A for (int i=0; i < numThreads; i++) { 2522292SN/A renameMap[i].setFreeList(&freeList); 2532292SN/A } 2541060SN/A rename.setFreeList(&freeList); 2552292SN/A 2561060SN/A // Setup the ROB for whichever stages need it. 2571060SN/A commit.setROB(&rob); 2582292SN/A 2592292SN/A lastRunningCycle = curTick; 2602292SN/A 2612292SN/A contextSwitch = false; 2621060SN/A} 2631060SN/A 2641060SN/Atemplate <class Impl> 2651755SN/AFullO3CPU<Impl>::~FullO3CPU() 2661060SN/A{ 2671060SN/A} 2681060SN/A 2691060SN/Atemplate <class Impl> 2701060SN/Avoid 2711755SN/AFullO3CPU<Impl>::fullCPURegStats() 2721062SN/A{ 2732733Sktlim@umich.edu BaseO3CPU::regStats(); 2742292SN/A 2752733Sktlim@umich.edu // Register any of the O3CPU's stats here. 2762292SN/A timesIdled 2772292SN/A .name(name() + ".timesIdled") 2782292SN/A .desc("Number of times that the entire CPU went into an idle state and" 2792292SN/A " unscheduled itself") 2802292SN/A .prereq(timesIdled); 2812292SN/A 2822292SN/A idleCycles 2832292SN/A .name(name() + ".idleCycles") 2842292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 2852292SN/A "to idling") 2862292SN/A .prereq(idleCycles); 2872292SN/A 2882292SN/A // Number of Instructions simulated 2892292SN/A // -------------------------------- 2902292SN/A // Should probably be in Base CPU but need templated 2912292SN/A // MaxThreads so put in here instead 2922292SN/A committedInsts 2932292SN/A .init(numThreads) 2942292SN/A .name(name() + ".committedInsts") 2952292SN/A .desc("Number of Instructions Simulated"); 2962292SN/A 2972292SN/A totalCommittedInsts 2982292SN/A .name(name() + ".committedInsts_total") 2992292SN/A .desc("Number of Instructions Simulated"); 3002292SN/A 3012292SN/A cpi 3022292SN/A .name(name() + ".cpi") 3032292SN/A .desc("CPI: Cycles Per Instruction") 3042292SN/A .precision(6); 3052292SN/A cpi = simTicks / committedInsts; 3062292SN/A 3072292SN/A totalCpi 3082292SN/A .name(name() + ".cpi_total") 3092292SN/A .desc("CPI: Total CPI of All Threads") 3102292SN/A .precision(6); 3112292SN/A totalCpi = simTicks / totalCommittedInsts; 3122292SN/A 3132292SN/A ipc 3142292SN/A .name(name() + ".ipc") 3152292SN/A .desc("IPC: Instructions Per Cycle") 3162292SN/A .precision(6); 3172292SN/A ipc = committedInsts / simTicks; 3182292SN/A 3192292SN/A totalIpc 3202292SN/A .name(name() + ".ipc_total") 3212292SN/A .desc("IPC: Total IPC of All Threads") 3222292SN/A .precision(6); 3232292SN/A totalIpc = totalCommittedInsts / simTicks; 3242292SN/A 3251062SN/A} 3261062SN/A 3271062SN/Atemplate <class Impl> 3281062SN/Avoid 3291755SN/AFullO3CPU<Impl>::tick() 3301060SN/A{ 3312733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 3321060SN/A 3332292SN/A ++numCycles; 3342292SN/A 3352325SN/A// activity = false; 3362292SN/A 3372292SN/A //Tick each of the stages 3381060SN/A fetch.tick(); 3391060SN/A 3401060SN/A decode.tick(); 3411060SN/A 3421060SN/A rename.tick(); 3431060SN/A 3441060SN/A iew.tick(); 3451060SN/A 3461060SN/A commit.tick(); 3471060SN/A 3482292SN/A#if !FULL_SYSTEM 3492292SN/A doContextSwitch(); 3502292SN/A#endif 3512292SN/A 3522292SN/A // Now advance the time buffers 3531060SN/A timeBuffer.advance(); 3541060SN/A 3551060SN/A fetchQueue.advance(); 3561060SN/A decodeQueue.advance(); 3571060SN/A renameQueue.advance(); 3581060SN/A iewQueue.advance(); 3591060SN/A 3602325SN/A activityRec.advance(); 3612292SN/A 3622292SN/A if (removeInstsThisCycle) { 3632292SN/A cleanUpRemovedInsts(); 3642292SN/A } 3652292SN/A 3662325SN/A if (!tickEvent.scheduled()) { 3672325SN/A if (_status == SwitchedOut) { 3682325SN/A // increment stat 3692325SN/A lastRunningCycle = curTick; 3702325SN/A } else if (!activityRec.active()) { 3712325SN/A lastRunningCycle = curTick; 3722325SN/A timesIdled++; 3732325SN/A } else { 3742325SN/A tickEvent.schedule(curTick + cycles(1)); 3752325SN/A } 3762292SN/A } 3772292SN/A 3782292SN/A#if !FULL_SYSTEM 3792292SN/A updateThreadPriority(); 3802292SN/A#endif 3812292SN/A 3821060SN/A} 3831060SN/A 3841060SN/Atemplate <class Impl> 3851060SN/Avoid 3861755SN/AFullO3CPU<Impl>::init() 3871060SN/A{ 3882307SN/A if (!deferRegistration) { 3892680Sktlim@umich.edu registerThreadContexts(); 3902292SN/A } 3911060SN/A 3922292SN/A // Set inSyscall so that the CPU doesn't squash when initially 3932292SN/A // setting up registers. 3942292SN/A for (int i = 0; i < number_of_threads; ++i) 3952292SN/A thread[i]->inSyscall = true; 3962292SN/A 3972292SN/A for (int tid=0; tid < number_of_threads; tid++) { 3981858SN/A#if FULL_SYSTEM 3992680Sktlim@umich.edu ThreadContext *src_tc = threadContexts[tid]; 4001681SN/A#else 4012680Sktlim@umich.edu ThreadContext *src_tc = thread[tid]->getTC(); 4021681SN/A#endif 4032292SN/A // Threads start in the Suspended State 4042680Sktlim@umich.edu if (src_tc->status() != ThreadContext::Suspended) { 4052292SN/A continue; 4061060SN/A } 4071060SN/A 4082292SN/A#if FULL_SYSTEM 4092680Sktlim@umich.edu TheISA::initCPU(src_tc, src_tc->readCpuId()); 4102292SN/A#endif 4112292SN/A } 4122292SN/A 4132292SN/A // Clear inSyscall. 4142292SN/A for (int i = 0; i < number_of_threads; ++i) 4152292SN/A thread[i]->inSyscall = false; 4162292SN/A 4172316SN/A // Initialize stages. 4182292SN/A fetch.initStage(); 4192292SN/A iew.initStage(); 4202292SN/A rename.initStage(); 4212292SN/A commit.initStage(); 4222292SN/A 4232292SN/A commit.setThreads(thread); 4242292SN/A} 4252292SN/A 4262292SN/Atemplate <class Impl> 4272292SN/Avoid 4282292SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 4292292SN/A{ 4302733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread data"); 4312292SN/A // Will change now that the PC and thread state is internal to the CPU 4322683Sktlim@umich.edu // and not in the ThreadContext. 4332292SN/A#if 0 4342292SN/A#if FULL_SYSTEM 4352680Sktlim@umich.edu ThreadContext *src_tc = system->threadContexts[tid]; 4362292SN/A#else 4372683Sktlim@umich.edu ThreadContext *src_tc = thread[tid]; 4382292SN/A#endif 4392292SN/A 4402292SN/A //Bind Int Regs to Rename Map 4412292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 4422292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 4432292SN/A 4442292SN/A renameMap[tid].setEntry(ireg,phys_reg); 4452292SN/A scoreboard.setReg(phys_reg); 4462292SN/A } 4472292SN/A 4482292SN/A //Bind Float Regs to Rename Map 4492292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 4502292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 4512292SN/A 4522292SN/A renameMap[tid].setEntry(freg,phys_reg); 4532292SN/A scoreboard.setReg(phys_reg); 4542292SN/A } 4552292SN/A 4562292SN/A //Copy Thread Data Into RegFile 4572680Sktlim@umich.edu this->copyFromTC(tid); 4582292SN/A 4592292SN/A //Set PC/NPC 4602680Sktlim@umich.edu regFile.pc[tid] = src_tc->readPC(); 4612680Sktlim@umich.edu regFile.npc[tid] = src_tc->readNextPC(); 4622292SN/A 4632680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 4642292SN/A 4652292SN/A activateContext(tid,1); 4662292SN/A 4672292SN/A //Reset ROB/IQ/LSQ Entries 4682292SN/A commit.rob->resetEntries(); 4692292SN/A iew.resetEntries(); 4702292SN/A#endif 4712292SN/A} 4722292SN/A 4732292SN/Atemplate <class Impl> 4742292SN/Avoid 4752292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 4762292SN/A{ 4772733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread data"); 4782292SN/A#if 0 4792292SN/A //Unbind Int Regs from Rename Map 4802292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 4812292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 4822292SN/A 4832292SN/A scoreboard.unsetReg(phys_reg); 4842292SN/A freeList.addReg(phys_reg); 4852292SN/A } 4862292SN/A 4872292SN/A //Unbind Float Regs from Rename Map 4882292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 4892292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 4902292SN/A 4912292SN/A scoreboard.unsetReg(phys_reg); 4922292SN/A freeList.addReg(phys_reg); 4932292SN/A } 4942292SN/A 4952292SN/A //Copy Thread Data From RegFile 4962292SN/A /* Fix Me: 4972292SN/A * Do we really need to do this if we are removing a thread 4982292SN/A * in the sense that it's finished (exiting)? If the thread is just 4992292SN/A * being suspended we might... 5002292SN/A */ 5012680Sktlim@umich.edu// this->copyToTC(tid); 5022292SN/A 5032292SN/A //Squash Throughout Pipeline 5042292SN/A fetch.squash(0,tid); 5052292SN/A decode.squash(tid); 5062292SN/A rename.squash(tid); 5072292SN/A 5082292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 5092292SN/A 5102292SN/A //Reset ROB/IQ/LSQ Entries 5112292SN/A if (activeThreads.size() >= 1) { 5122292SN/A commit.rob->resetEntries(); 5132292SN/A iew.resetEntries(); 5142292SN/A } 5152292SN/A#endif 5162292SN/A} 5172292SN/A 5182292SN/A 5192292SN/Atemplate <class Impl> 5202292SN/Avoid 5212292SN/AFullO3CPU<Impl>::activateWhenReady(int tid) 5222292SN/A{ 5232733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 5242292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 5252292SN/A tid); 5262292SN/A 5272292SN/A bool ready = true; 5282292SN/A 5292292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 5302733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5312292SN/A "Phys. Int. Regs.\n", 5322292SN/A tid); 5332292SN/A ready = false; 5342292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 5352733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5362292SN/A "Phys. Float. Regs.\n", 5372292SN/A tid); 5382292SN/A ready = false; 5392292SN/A } else if (commit.rob->numFreeEntries() >= 5402292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 5412733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5422292SN/A "ROB entries.\n", 5432292SN/A tid); 5442292SN/A ready = false; 5452292SN/A } else if (iew.instQueue.numFreeEntries() >= 5462292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 5472733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5482292SN/A "IQ entries.\n", 5492292SN/A tid); 5502292SN/A ready = false; 5512292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 5522292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 5532733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 5542292SN/A "LSQ entries.\n", 5552292SN/A tid); 5562292SN/A ready = false; 5572292SN/A } 5582292SN/A 5592292SN/A if (ready) { 5602292SN/A insertThread(tid); 5612292SN/A 5622292SN/A contextSwitch = false; 5632292SN/A 5642292SN/A cpuWaitList.remove(tid); 5652292SN/A } else { 5662292SN/A suspendContext(tid); 5672292SN/A 5682292SN/A //blocks fetch 5692292SN/A contextSwitch = true; 5702292SN/A 5712292SN/A //do waitlist 5722292SN/A cpuWaitList.push_back(tid); 5731060SN/A } 5741060SN/A} 5751060SN/A 5761060SN/Atemplate <class Impl> 5771060SN/Avoid 5782292SN/AFullO3CPU<Impl>::activateContext(int tid, int delay) 5791060SN/A{ 5801060SN/A // Needs to set each stage to running as well. 5812292SN/A list<unsigned>::iterator isActive = find( 5822292SN/A activeThreads.begin(), activeThreads.end(), tid); 5832292SN/A 5842292SN/A if (isActive == activeThreads.end()) { 5852292SN/A //May Need to Re-code this if the delay variable is the 5862292SN/A //delay needed for thread to activate 5872733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 5882292SN/A tid); 5892292SN/A 5902292SN/A activeThreads.push_back(tid); 5912292SN/A } 5922292SN/A 5932307SN/A assert(_status == Idle || _status == SwitchedOut); 5941060SN/A 5951060SN/A scheduleTickEvent(delay); 5961060SN/A 5972292SN/A // Be sure to signal that there's some activity so the CPU doesn't 5982292SN/A // deschedule itself. 5992325SN/A activityRec.activity(); 6002292SN/A fetch.wakeFromQuiesce(); 6012292SN/A 6021060SN/A _status = Running; 6031060SN/A} 6041060SN/A 6051060SN/Atemplate <class Impl> 6061060SN/Avoid 6072292SN/AFullO3CPU<Impl>::suspendContext(int tid) 6081060SN/A{ 6092733Sktlim@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspended ...\n", tid); 6102292SN/A unscheduleTickEvent(); 6112292SN/A _status = Idle; 6122292SN/A/* 6132292SN/A //Remove From Active List, if Active 6142292SN/A list<unsigned>::iterator isActive = find( 6152292SN/A activeThreads.begin(), activeThreads.end(), tid); 6162292SN/A 6172292SN/A if (isActive != activeThreads.end()) { 6182733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6192292SN/A tid); 6202292SN/A activeThreads.erase(isActive); 6212292SN/A } 6222292SN/A*/ 6231060SN/A} 6241060SN/A 6251060SN/Atemplate <class Impl> 6261060SN/Avoid 6272292SN/AFullO3CPU<Impl>::deallocateContext(int tid) 6281060SN/A{ 6292733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Deallocating ...", tid); 6302292SN/A/* 6312292SN/A //Remove From Active List, if Active 6322292SN/A list<unsigned>::iterator isActive = find( 6332292SN/A activeThreads.begin(), activeThreads.end(), tid); 6342292SN/A 6352292SN/A if (isActive != activeThreads.end()) { 6362733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6372292SN/A tid); 6382292SN/A activeThreads.erase(isActive); 6392292SN/A 6402292SN/A removeThread(tid); 6412292SN/A } 6422292SN/A*/ 6431060SN/A} 6441060SN/A 6451060SN/Atemplate <class Impl> 6461060SN/Avoid 6472292SN/AFullO3CPU<Impl>::haltContext(int tid) 6481060SN/A{ 6492733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halted ...", tid); 6502292SN/A/* 6512292SN/A //Remove From Active List, if Active 6522292SN/A list<unsigned>::iterator isActive = find( 6532292SN/A activeThreads.begin(), activeThreads.end(), tid); 6542292SN/A 6552292SN/A if (isActive != activeThreads.end()) { 6562733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6572292SN/A tid); 6582292SN/A activeThreads.erase(isActive); 6592292SN/A 6602292SN/A removeThread(tid); 6612292SN/A } 6622292SN/A*/ 6631060SN/A} 6641060SN/A 6651060SN/Atemplate <class Impl> 6661060SN/Avoid 6672316SN/AFullO3CPU<Impl>::switchOut(Sampler *_sampler) 6681060SN/A{ 6692316SN/A sampler = _sampler; 6702316SN/A switchCount = 0; 6712307SN/A fetch.switchOut(); 6722307SN/A decode.switchOut(); 6732307SN/A rename.switchOut(); 6742307SN/A iew.switchOut(); 6752307SN/A commit.switchOut(); 6762325SN/A 6772325SN/A // Wake the CPU and record activity so everything can drain out if 6782325SN/A // the CPU is currently idle. 6792325SN/A wakeCPU(); 6802325SN/A activityRec.activity(); 6812316SN/A} 6822310SN/A 6832316SN/Atemplate <class Impl> 6842316SN/Avoid 6852316SN/AFullO3CPU<Impl>::signalSwitched() 6862316SN/A{ 6872325SN/A if (++switchCount == NumStages) { 6882316SN/A fetch.doSwitchOut(); 6892316SN/A rename.doSwitchOut(); 6902316SN/A commit.doSwitchOut(); 6912316SN/A instList.clear(); 6922316SN/A while (!removeList.empty()) { 6932316SN/A removeList.pop(); 6942316SN/A } 6952316SN/A 6962794Sktlim@umich.edu#if USE_CHECKER 6972316SN/A if (checker) 6982316SN/A checker->switchOut(sampler); 6992794Sktlim@umich.edu#endif 7002316SN/A 7012316SN/A if (tickEvent.scheduled()) 7022316SN/A tickEvent.squash(); 7032316SN/A sampler->signalSwitched(); 7042316SN/A _status = SwitchedOut; 7052310SN/A } 7062316SN/A assert(switchCount <= 5); 7071060SN/A} 7081060SN/A 7091060SN/Atemplate <class Impl> 7101060SN/Avoid 7111755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 7121060SN/A{ 7132325SN/A // Flush out any old data from the time buffers. 7142325SN/A for (int i = 0; i < 10; ++i) { 7152307SN/A timeBuffer.advance(); 7162307SN/A fetchQueue.advance(); 7172307SN/A decodeQueue.advance(); 7182307SN/A renameQueue.advance(); 7192307SN/A iewQueue.advance(); 7202307SN/A } 7212307SN/A 7222325SN/A activityRec.reset(); 7232307SN/A 7241060SN/A BaseCPU::takeOverFrom(oldCPU); 7251060SN/A 7262307SN/A fetch.takeOverFrom(); 7272307SN/A decode.takeOverFrom(); 7282307SN/A rename.takeOverFrom(); 7292307SN/A iew.takeOverFrom(); 7302307SN/A commit.takeOverFrom(); 7312307SN/A 7321060SN/A assert(!tickEvent.scheduled()); 7331060SN/A 7342325SN/A // @todo: Figure out how to properly select the tid to put onto 7352325SN/A // the active threads list. 7362307SN/A int tid = 0; 7372307SN/A 7382307SN/A list<unsigned>::iterator isActive = find( 7392307SN/A activeThreads.begin(), activeThreads.end(), tid); 7402307SN/A 7412307SN/A if (isActive == activeThreads.end()) { 7422325SN/A //May Need to Re-code this if the delay variable is the delay 7432325SN/A //needed for thread to activate 7442733Sktlim@umich.edu DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", 7452307SN/A tid); 7462307SN/A 7472307SN/A activeThreads.push_back(tid); 7482307SN/A } 7492307SN/A 7502325SN/A // Set all statuses to active, schedule the CPU's tick event. 7512307SN/A // @todo: Fix up statuses so this is handled properly 7522680Sktlim@umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 7532680Sktlim@umich.edu ThreadContext *tc = threadContexts[i]; 7542680Sktlim@umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 7551681SN/A _status = Running; 7561681SN/A tickEvent.schedule(curTick); 7571681SN/A } 7581060SN/A } 7592307SN/A if (!tickEvent.scheduled()) 7602307SN/A tickEvent.schedule(curTick); 7611060SN/A} 7621060SN/A 7631060SN/Atemplate <class Impl> 7641060SN/Auint64_t 7651755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 7661060SN/A{ 7671060SN/A return regFile.readIntReg(reg_idx); 7681060SN/A} 7691060SN/A 7701060SN/Atemplate <class Impl> 7712455SN/AFloatReg 7722455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 7731060SN/A{ 7742455SN/A return regFile.readFloatReg(reg_idx, width); 7751060SN/A} 7761060SN/A 7771060SN/Atemplate <class Impl> 7782455SN/AFloatReg 7792455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 7801060SN/A{ 7812455SN/A return regFile.readFloatReg(reg_idx); 7821060SN/A} 7831060SN/A 7841060SN/Atemplate <class Impl> 7852455SN/AFloatRegBits 7862455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 7871060SN/A{ 7882455SN/A return regFile.readFloatRegBits(reg_idx, width); 7892455SN/A} 7902455SN/A 7912455SN/Atemplate <class Impl> 7922455SN/AFloatRegBits 7932455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 7942455SN/A{ 7952455SN/A return regFile.readFloatRegBits(reg_idx); 7961060SN/A} 7971060SN/A 7981060SN/Atemplate <class Impl> 7991060SN/Avoid 8001755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 8011060SN/A{ 8021060SN/A regFile.setIntReg(reg_idx, val); 8031060SN/A} 8041060SN/A 8051060SN/Atemplate <class Impl> 8061060SN/Avoid 8072455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 8081060SN/A{ 8092455SN/A regFile.setFloatReg(reg_idx, val, width); 8101060SN/A} 8111060SN/A 8121060SN/Atemplate <class Impl> 8131060SN/Avoid 8142455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 8151060SN/A{ 8162455SN/A regFile.setFloatReg(reg_idx, val); 8171060SN/A} 8181060SN/A 8191060SN/Atemplate <class Impl> 8201060SN/Avoid 8212455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 8221060SN/A{ 8232455SN/A regFile.setFloatRegBits(reg_idx, val, width); 8242455SN/A} 8252455SN/A 8262455SN/Atemplate <class Impl> 8272455SN/Avoid 8282455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 8292455SN/A{ 8302455SN/A regFile.setFloatRegBits(reg_idx, val); 8311060SN/A} 8321060SN/A 8331060SN/Atemplate <class Impl> 8341060SN/Auint64_t 8352292SN/AFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 8361060SN/A{ 8372292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8382292SN/A 8392292SN/A return regFile.readIntReg(phys_reg); 8402292SN/A} 8412292SN/A 8422292SN/Atemplate <class Impl> 8432292SN/Afloat 8442292SN/AFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 8452292SN/A{ 8462307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 8472307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 8482292SN/A 8492669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 8502292SN/A} 8512292SN/A 8522292SN/Atemplate <class Impl> 8532292SN/Adouble 8542292SN/AFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 8552292SN/A{ 8562307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 8572307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 8582292SN/A 8592669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 8602292SN/A} 8612292SN/A 8622292SN/Atemplate <class Impl> 8632292SN/Auint64_t 8642292SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 8652292SN/A{ 8662307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 8672307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 8682292SN/A 8692669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 8701060SN/A} 8711060SN/A 8721060SN/Atemplate <class Impl> 8731060SN/Avoid 8742292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 8751060SN/A{ 8762292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8772292SN/A 8782292SN/A regFile.setIntReg(phys_reg, val); 8791060SN/A} 8801060SN/A 8811060SN/Atemplate <class Impl> 8821060SN/Avoid 8832292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 8841060SN/A{ 8852292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8862292SN/A 8872669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 8881060SN/A} 8891060SN/A 8901060SN/Atemplate <class Impl> 8911060SN/Avoid 8922292SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 8931060SN/A{ 8942292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8952292SN/A 8962669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 8971060SN/A} 8981060SN/A 8991060SN/Atemplate <class Impl> 9001060SN/Avoid 9012292SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 9021060SN/A{ 9032292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 9041060SN/A 9052669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 9062292SN/A} 9072292SN/A 9082292SN/Atemplate <class Impl> 9092292SN/Auint64_t 9102292SN/AFullO3CPU<Impl>::readPC(unsigned tid) 9112292SN/A{ 9122292SN/A return commit.readPC(tid); 9131060SN/A} 9141060SN/A 9151060SN/Atemplate <class Impl> 9161060SN/Avoid 9172292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 9181060SN/A{ 9192292SN/A commit.setPC(new_PC, tid); 9202292SN/A} 9211060SN/A 9222292SN/Atemplate <class Impl> 9232292SN/Auint64_t 9242292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 9252292SN/A{ 9262292SN/A return commit.readNextPC(tid); 9272292SN/A} 9281060SN/A 9292292SN/Atemplate <class Impl> 9302292SN/Avoid 9312292SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 9322292SN/A{ 9332292SN/A commit.setNextPC(val, tid); 9342292SN/A} 9351060SN/A 9362756Sksewell@umich.edu#if THE_ISA != ALPHA_ISA 9372756Sksewell@umich.edutemplate <class Impl> 9382756Sksewell@umich.eduuint64_t 9392756Sksewell@umich.eduFullO3CPU<Impl>::readNextNPC(unsigned tid) 9402756Sksewell@umich.edu{ 9412756Sksewell@umich.edu return commit.readNextNPC(tid); 9422756Sksewell@umich.edu} 9432756Sksewell@umich.edu 9442756Sksewell@umich.edutemplate <class Impl> 9452756Sksewell@umich.eduvoid 9462756Sksewell@umich.eduFullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid) 9472756Sksewell@umich.edu{ 9482756Sksewell@umich.edu commit.setNextNPC(val, tid); 9492756Sksewell@umich.edu} 9502756Sksewell@umich.edu#endif 9512756Sksewell@umich.edu 9522292SN/Atemplate <class Impl> 9532292SN/Atypename FullO3CPU<Impl>::ListIt 9542292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 9552292SN/A{ 9562292SN/A instList.push_back(inst); 9571060SN/A 9582292SN/A return --(instList.end()); 9592292SN/A} 9601060SN/A 9612292SN/Atemplate <class Impl> 9622292SN/Avoid 9632292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 9642292SN/A{ 9652292SN/A // Keep an instruction count. 9662292SN/A thread[tid]->numInst++; 9672292SN/A thread[tid]->numInsts++; 9682292SN/A committedInsts[tid]++; 9692292SN/A totalCommittedInsts++; 9702292SN/A 9712292SN/A // Check for instruction-count-based events. 9722292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 9732292SN/A} 9742292SN/A 9752292SN/Atemplate <class Impl> 9762292SN/Avoid 9772292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 9782292SN/A{ 9792292SN/A removeInstsThisCycle = true; 9802292SN/A 9812292SN/A removeList.push(inst->getInstListIt()); 9821060SN/A} 9831060SN/A 9841060SN/Atemplate <class Impl> 9851060SN/Avoid 9861755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 9871060SN/A{ 9882733Sktlim@umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " 9892292SN/A "[sn:%lli]\n", 9902303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 9911060SN/A 9922292SN/A removeInstsThisCycle = true; 9931060SN/A 9941060SN/A // Remove the front instruction. 9952292SN/A removeList.push(inst->getInstListIt()); 9961060SN/A} 9971060SN/A 9981060SN/Atemplate <class Impl> 9991060SN/Avoid 10002292SN/AFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 10011060SN/A{ 10022733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 10032292SN/A " list.\n", tid); 10041060SN/A 10052292SN/A ListIt end_it; 10061060SN/A 10072292SN/A bool rob_empty = false; 10082292SN/A 10092292SN/A if (instList.empty()) { 10102292SN/A return; 10112292SN/A } else if (rob.isEmpty(/*tid*/)) { 10122733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 10132292SN/A end_it = instList.begin(); 10142292SN/A rob_empty = true; 10152292SN/A } else { 10162292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 10172733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 10182292SN/A } 10192292SN/A 10202292SN/A removeInstsThisCycle = true; 10212292SN/A 10222292SN/A ListIt inst_it = instList.end(); 10232292SN/A 10242292SN/A inst_it--; 10252292SN/A 10262292SN/A // Walk through the instruction list, removing any instructions 10272292SN/A // that were inserted after the given instruction iterator, end_it. 10282292SN/A while (inst_it != end_it) { 10292292SN/A assert(!instList.empty()); 10302292SN/A 10312292SN/A squashInstIt(inst_it, tid); 10322292SN/A 10332292SN/A inst_it--; 10342292SN/A } 10352292SN/A 10362292SN/A // If the ROB was empty, then we actually need to remove the first 10372292SN/A // instruction as well. 10382292SN/A if (rob_empty) { 10392292SN/A squashInstIt(inst_it, tid); 10402292SN/A } 10411060SN/A} 10421060SN/A 10431060SN/Atemplate <class Impl> 10441060SN/Avoid 10452292SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 10462292SN/A unsigned tid) 10471062SN/A{ 10482292SN/A assert(!instList.empty()); 10492292SN/A 10502292SN/A removeInstsThisCycle = true; 10512292SN/A 10522292SN/A ListIt inst_iter = instList.end(); 10532292SN/A 10542292SN/A inst_iter--; 10552292SN/A 10562733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 10572292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 10582292SN/A tid, seq_num, (*inst_iter)->seqNum); 10591062SN/A 10602292SN/A while ((*inst_iter)->seqNum > seq_num) { 10611062SN/A 10622292SN/A bool break_loop = (inst_iter == instList.begin()); 10631062SN/A 10642292SN/A squashInstIt(inst_iter, tid); 10651062SN/A 10662292SN/A inst_iter--; 10671062SN/A 10682292SN/A if (break_loop) 10692292SN/A break; 10702292SN/A } 10712292SN/A} 10722292SN/A 10732292SN/Atemplate <class Impl> 10742292SN/Ainline void 10752292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 10762292SN/A{ 10772292SN/A if ((*instIt)->threadNumber == tid) { 10782733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 10792292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 10802292SN/A (*instIt)->threadNumber, 10812292SN/A (*instIt)->seqNum, 10822292SN/A (*instIt)->readPC()); 10831062SN/A 10841062SN/A // Mark it as squashed. 10852292SN/A (*instIt)->setSquashed(); 10862292SN/A 10872325SN/A // @todo: Formulate a consistent method for deleting 10882325SN/A // instructions from the instruction list 10892292SN/A // Remove the instruction from the list. 10902292SN/A removeList.push(instIt); 10912292SN/A } 10922292SN/A} 10932292SN/A 10942292SN/Atemplate <class Impl> 10952292SN/Avoid 10962292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 10972292SN/A{ 10982292SN/A while (!removeList.empty()) { 10992733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 11002292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 11012292SN/A (*removeList.front())->threadNumber, 11022292SN/A (*removeList.front())->seqNum, 11032292SN/A (*removeList.front())->readPC()); 11042292SN/A 11052292SN/A instList.erase(removeList.front()); 11062292SN/A 11072292SN/A removeList.pop(); 11081062SN/A } 11091062SN/A 11102292SN/A removeInstsThisCycle = false; 11111062SN/A} 11122325SN/A/* 11131062SN/Atemplate <class Impl> 11141062SN/Avoid 11151755SN/AFullO3CPU<Impl>::removeAllInsts() 11161060SN/A{ 11171060SN/A instList.clear(); 11181060SN/A} 11192325SN/A*/ 11201060SN/Atemplate <class Impl> 11211060SN/Avoid 11221755SN/AFullO3CPU<Impl>::dumpInsts() 11231060SN/A{ 11241060SN/A int num = 0; 11251060SN/A 11262292SN/A ListIt inst_list_it = instList.begin(); 11272292SN/A 11282292SN/A cprintf("Dumping Instruction List\n"); 11292292SN/A 11302292SN/A while (inst_list_it != instList.end()) { 11312292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 11322292SN/A "Squashed:%i\n\n", 11332292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 11342292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 11352292SN/A (*inst_list_it)->isSquashed()); 11361060SN/A inst_list_it++; 11371060SN/A ++num; 11381060SN/A } 11391060SN/A} 11402325SN/A/* 11411060SN/Atemplate <class Impl> 11421060SN/Avoid 11431755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 11441060SN/A{ 11451060SN/A iew.wakeDependents(inst); 11461060SN/A} 11472325SN/A*/ 11482292SN/Atemplate <class Impl> 11492292SN/Avoid 11502292SN/AFullO3CPU<Impl>::wakeCPU() 11512292SN/A{ 11522325SN/A if (activityRec.active() || tickEvent.scheduled()) { 11532325SN/A DPRINTF(Activity, "CPU already running.\n"); 11542292SN/A return; 11552292SN/A } 11562292SN/A 11572325SN/A DPRINTF(Activity, "Waking up CPU\n"); 11582325SN/A 11592325SN/A idleCycles += (curTick - 1) - lastRunningCycle; 11602292SN/A 11612292SN/A tickEvent.schedule(curTick); 11622292SN/A} 11632292SN/A 11642292SN/Atemplate <class Impl> 11652292SN/Aint 11662292SN/AFullO3CPU<Impl>::getFreeTid() 11672292SN/A{ 11682292SN/A for (int i=0; i < numThreads; i++) { 11692292SN/A if (!tids[i]) { 11702292SN/A tids[i] = true; 11712292SN/A return i; 11722292SN/A } 11732292SN/A } 11742292SN/A 11752292SN/A return -1; 11762292SN/A} 11772292SN/A 11782292SN/Atemplate <class Impl> 11792292SN/Avoid 11802292SN/AFullO3CPU<Impl>::doContextSwitch() 11812292SN/A{ 11822292SN/A if (contextSwitch) { 11832292SN/A 11842292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 11852292SN/A 11862292SN/A for (int tid=0; tid < cpuWaitList.size(); tid++) { 11872292SN/A activateWhenReady(tid); 11882292SN/A } 11892292SN/A 11902292SN/A if (cpuWaitList.size() == 0) 11912292SN/A contextSwitch = true; 11922292SN/A } 11932292SN/A} 11942292SN/A 11952292SN/Atemplate <class Impl> 11962292SN/Avoid 11972292SN/AFullO3CPU<Impl>::updateThreadPriority() 11982292SN/A{ 11992292SN/A if (activeThreads.size() > 1) 12002292SN/A { 12012292SN/A //DEFAULT TO ROUND ROBIN SCHEME 12022292SN/A //e.g. Move highest priority to end of thread list 12032292SN/A list<unsigned>::iterator list_begin = activeThreads.begin(); 12042292SN/A list<unsigned>::iterator list_end = activeThreads.end(); 12052292SN/A 12062292SN/A unsigned high_thread = *list_begin; 12072292SN/A 12082292SN/A activeThreads.erase(list_begin); 12092292SN/A 12102292SN/A activeThreads.push_back(high_thread); 12112292SN/A } 12122292SN/A} 12131060SN/A 12141755SN/A// Forward declaration of FullO3CPU. 12151755SN/Atemplate class FullO3CPU<AlphaSimpleImpl>; 1216