cpu.cc revision 2669
11689SN/A/* 22325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271689SN/A */ 281689SN/A 291858SN/A#include "config/full_system.hh" 301858SN/A 311858SN/A#if FULL_SYSTEM 321060SN/A#include "sim/system.hh" 331060SN/A#else 341060SN/A#include "sim/process.hh" 351060SN/A#endif 361060SN/A 372325SN/A#include "cpu/activity.hh" 382316SN/A#include "cpu/checker/cpu.hh" 392190SN/A#include "cpu/cpu_exec_context.hh" 402190SN/A#include "cpu/exec_context.hh" 411717SN/A#include "cpu/o3/alpha_dyn_inst.hh" 421717SN/A#include "cpu/o3/alpha_impl.hh" 431717SN/A#include "cpu/o3/cpu.hh" 441060SN/A 452325SN/A#include "sim/root.hh" 462292SN/A#include "sim/stat_control.hh" 472292SN/A 481060SN/Ausing namespace std; 492669Sktlim@umich.eduusing namespace TheISA; 501060SN/A 512292SN/ABaseFullCPU::BaseFullCPU(Params *params) 522292SN/A : BaseCPU(params), cpu_id(0) 531060SN/A{ 541060SN/A} 551060SN/A 562292SN/Avoid 572292SN/ABaseFullCPU::regStats() 582292SN/A{ 592292SN/A BaseCPU::regStats(); 602292SN/A} 612292SN/A 621060SN/Atemplate <class Impl> 631755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 641060SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 651060SN/A{ 661060SN/A} 671060SN/A 681060SN/Atemplate <class Impl> 691060SN/Avoid 701755SN/AFullO3CPU<Impl>::TickEvent::process() 711060SN/A{ 721060SN/A cpu->tick(); 731060SN/A} 741060SN/A 751060SN/Atemplate <class Impl> 761060SN/Aconst char * 771755SN/AFullO3CPU<Impl>::TickEvent::description() 781060SN/A{ 791755SN/A return "FullO3CPU tick event"; 801060SN/A} 811060SN/A 821060SN/Atemplate <class Impl> 832292SN/AFullO3CPU<Impl>::FullO3CPU(Params *params) 841061SN/A : BaseFullCPU(params), 851060SN/A tickEvent(this), 862292SN/A removeInstsThisCycle(false), 871060SN/A fetch(params), 881060SN/A decode(params), 891060SN/A rename(params), 901060SN/A iew(params), 911060SN/A commit(params), 921060SN/A 932292SN/A regFile(params->numPhysIntRegs, params->numPhysFloatRegs), 941060SN/A 952292SN/A freeList(params->numberOfThreads,//number of activeThreads 962292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 972292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs), 981060SN/A 992292SN/A rob(params->numROBEntries, params->squashWidth, 1002292SN/A params->smtROBPolicy, params->smtROBThreshold, 1012292SN/A params->numberOfThreads), 1021060SN/A 1032292SN/A scoreboard(params->numberOfThreads,//number of activeThreads 1042292SN/A TheISA::NumIntRegs, params->numPhysIntRegs, 1052292SN/A TheISA::NumFloatRegs, params->numPhysFloatRegs, 1062292SN/A TheISA::NumMiscRegs * number_of_threads, 1072292SN/A TheISA::ZeroReg), 1081060SN/A 1091060SN/A // For now just have these time buffers be pretty big. 1102325SN/A // @todo: Make these time buffer sizes parameters or derived 1112325SN/A // from latencies 1121061SN/A timeBuffer(5, 5), 1131061SN/A fetchQueue(5, 5), 1141061SN/A decodeQueue(5, 5), 1151061SN/A renameQueue(5, 5), 1161061SN/A iewQueue(5, 5), 1172325SN/A activityRec(NumStages, 10, params->activity), 1181060SN/A 1191060SN/A globalSeqNum(1), 1201060SN/A 1211858SN/A#if FULL_SYSTEM 1222292SN/A system(params->system), 1231681SN/A memCtrl(system->memctrl), 1241060SN/A physmem(system->physmem), 1252669Sktlim@umich.edu#endif // FULL_SYSTEM 1262292SN/A mem(params->mem), 1272316SN/A switchCount(0), 1282316SN/A deferRegistration(params->deferRegistration), 1292316SN/A numThreads(number_of_threads) 1301060SN/A{ 1311060SN/A _status = Idle; 1321681SN/A 1332316SN/A if (params->checker) { 1342316SN/A BaseCPU *temp_checker = params->checker; 1352316SN/A checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker); 1362316SN/A checker->setMemory(mem); 1372316SN/A#if FULL_SYSTEM 1382316SN/A checker->setSystem(params->system); 1392316SN/A#endif 1402316SN/A } else { 1412316SN/A checker = NULL; 1422316SN/A } 1432316SN/A 1441858SN/A#if !FULL_SYSTEM 1452292SN/A thread.resize(number_of_threads); 1462292SN/A tids.resize(number_of_threads); 1471681SN/A#endif 1481681SN/A 1492325SN/A // The stages also need their CPU pointer setup. However this 1502325SN/A // must be done at the upper level CPU because they have pointers 1512325SN/A // to the upper level CPU, and not this FullO3CPU. 1521060SN/A 1532292SN/A // Set up Pointers to the activeThreads list for each stage 1542292SN/A fetch.setActiveThreads(&activeThreads); 1552292SN/A decode.setActiveThreads(&activeThreads); 1562292SN/A rename.setActiveThreads(&activeThreads); 1572292SN/A iew.setActiveThreads(&activeThreads); 1582292SN/A commit.setActiveThreads(&activeThreads); 1591060SN/A 1601060SN/A // Give each of the stages the time buffer they will use. 1611060SN/A fetch.setTimeBuffer(&timeBuffer); 1621060SN/A decode.setTimeBuffer(&timeBuffer); 1631060SN/A rename.setTimeBuffer(&timeBuffer); 1641060SN/A iew.setTimeBuffer(&timeBuffer); 1651060SN/A commit.setTimeBuffer(&timeBuffer); 1661060SN/A 1671060SN/A // Also setup each of the stages' queues. 1681060SN/A fetch.setFetchQueue(&fetchQueue); 1691060SN/A decode.setFetchQueue(&fetchQueue); 1702292SN/A commit.setFetchQueue(&fetchQueue); 1711060SN/A decode.setDecodeQueue(&decodeQueue); 1721060SN/A rename.setDecodeQueue(&decodeQueue); 1731060SN/A rename.setRenameQueue(&renameQueue); 1741060SN/A iew.setRenameQueue(&renameQueue); 1751060SN/A iew.setIEWQueue(&iewQueue); 1761060SN/A commit.setIEWQueue(&iewQueue); 1771060SN/A commit.setRenameQueue(&renameQueue); 1781060SN/A 1792316SN/A commit.setFetchStage(&fetch); 1802292SN/A commit.setIEWStage(&iew); 1812292SN/A rename.setIEWStage(&iew); 1822292SN/A rename.setCommitStage(&commit); 1832292SN/A 1842292SN/A#if !FULL_SYSTEM 1852307SN/A int active_threads = params->workload.size(); 1862292SN/A#else 1872307SN/A int active_threads = 1; 1882292SN/A#endif 1892292SN/A 1902316SN/A //Make Sure That this a Valid Architeture 1912292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 1922292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 1932292SN/A 1942292SN/A rename.setScoreboard(&scoreboard); 1952292SN/A iew.setScoreboard(&scoreboard); 1962292SN/A 1971060SN/A // Setup the rename map for whichever stages need it. 1982292SN/A PhysRegIndex lreg_idx = 0; 1992292SN/A PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs 2001060SN/A 2012292SN/A for (int tid=0; tid < numThreads; tid++) { 2022307SN/A bool bindRegs = (tid <= active_threads - 1); 2032292SN/A 2042292SN/A commitRenameMap[tid].init(TheISA::NumIntRegs, 2052292SN/A params->numPhysIntRegs, 2062325SN/A lreg_idx, //Index for Logical. Regs 2072292SN/A 2082292SN/A TheISA::NumFloatRegs, 2092292SN/A params->numPhysFloatRegs, 2102325SN/A freg_idx, //Index for Float Regs 2112292SN/A 2122292SN/A TheISA::NumMiscRegs, 2132292SN/A 2142292SN/A TheISA::ZeroReg, 2152292SN/A TheISA::ZeroReg, 2162292SN/A 2172292SN/A tid, 2182292SN/A false); 2192292SN/A 2202292SN/A renameMap[tid].init(TheISA::NumIntRegs, 2212292SN/A params->numPhysIntRegs, 2222325SN/A lreg_idx, //Index for Logical. Regs 2232292SN/A 2242292SN/A TheISA::NumFloatRegs, 2252292SN/A params->numPhysFloatRegs, 2262325SN/A freg_idx, //Index for Float Regs 2272292SN/A 2282292SN/A TheISA::NumMiscRegs, 2292292SN/A 2302292SN/A TheISA::ZeroReg, 2312292SN/A TheISA::ZeroReg, 2322292SN/A 2332292SN/A tid, 2342292SN/A bindRegs); 2352292SN/A } 2362292SN/A 2372292SN/A rename.setRenameMap(renameMap); 2382292SN/A commit.setRenameMap(commitRenameMap); 2392292SN/A 2402292SN/A // Give renameMap & rename stage access to the freeList; 2412292SN/A for (int i=0; i < numThreads; i++) { 2422292SN/A renameMap[i].setFreeList(&freeList); 2432292SN/A } 2441060SN/A rename.setFreeList(&freeList); 2452292SN/A 2462292SN/A // Setup the page table for whichever stages need it. 2472292SN/A#if !FULL_SYSTEM 2482303SN/A// fetch.setPageTable(pTable); 2492303SN/A// iew.setPageTable(pTable); 2502292SN/A#endif 2511060SN/A 2521060SN/A // Setup the ROB for whichever stages need it. 2531060SN/A commit.setROB(&rob); 2542292SN/A 2552292SN/A lastRunningCycle = curTick; 2562292SN/A 2572292SN/A contextSwitch = false; 2581060SN/A} 2591060SN/A 2601060SN/Atemplate <class Impl> 2611755SN/AFullO3CPU<Impl>::~FullO3CPU() 2621060SN/A{ 2631060SN/A} 2641060SN/A 2651060SN/Atemplate <class Impl> 2661060SN/Avoid 2671755SN/AFullO3CPU<Impl>::fullCPURegStats() 2681062SN/A{ 2692292SN/A BaseFullCPU::regStats(); 2702292SN/A 2711062SN/A // Register any of the FullCPU's stats here. 2722292SN/A timesIdled 2732292SN/A .name(name() + ".timesIdled") 2742292SN/A .desc("Number of times that the entire CPU went into an idle state and" 2752292SN/A " unscheduled itself") 2762292SN/A .prereq(timesIdled); 2772292SN/A 2782292SN/A idleCycles 2792292SN/A .name(name() + ".idleCycles") 2802292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 2812292SN/A "to idling") 2822292SN/A .prereq(idleCycles); 2832292SN/A 2842292SN/A // Number of Instructions simulated 2852292SN/A // -------------------------------- 2862292SN/A // Should probably be in Base CPU but need templated 2872292SN/A // MaxThreads so put in here instead 2882292SN/A committedInsts 2892292SN/A .init(numThreads) 2902292SN/A .name(name() + ".committedInsts") 2912292SN/A .desc("Number of Instructions Simulated"); 2922292SN/A 2932292SN/A totalCommittedInsts 2942292SN/A .name(name() + ".committedInsts_total") 2952292SN/A .desc("Number of Instructions Simulated"); 2962292SN/A 2972292SN/A cpi 2982292SN/A .name(name() + ".cpi") 2992292SN/A .desc("CPI: Cycles Per Instruction") 3002292SN/A .precision(6); 3012292SN/A cpi = simTicks / committedInsts; 3022292SN/A 3032292SN/A totalCpi 3042292SN/A .name(name() + ".cpi_total") 3052292SN/A .desc("CPI: Total CPI of All Threads") 3062292SN/A .precision(6); 3072292SN/A totalCpi = simTicks / totalCommittedInsts; 3082292SN/A 3092292SN/A ipc 3102292SN/A .name(name() + ".ipc") 3112292SN/A .desc("IPC: Instructions Per Cycle") 3122292SN/A .precision(6); 3132292SN/A ipc = committedInsts / simTicks; 3142292SN/A 3152292SN/A totalIpc 3162292SN/A .name(name() + ".ipc_total") 3172292SN/A .desc("IPC: Total IPC of All Threads") 3182292SN/A .precision(6); 3192292SN/A totalIpc = totalCommittedInsts / simTicks; 3202292SN/A 3211062SN/A} 3221062SN/A 3231062SN/Atemplate <class Impl> 3241062SN/Avoid 3251755SN/AFullO3CPU<Impl>::tick() 3261060SN/A{ 3271755SN/A DPRINTF(FullCPU, "\n\nFullCPU: Ticking main, FullO3CPU.\n"); 3281060SN/A 3292292SN/A ++numCycles; 3302292SN/A 3312325SN/A// activity = false; 3322292SN/A 3332292SN/A //Tick each of the stages 3341060SN/A fetch.tick(); 3351060SN/A 3361060SN/A decode.tick(); 3371060SN/A 3381060SN/A rename.tick(); 3391060SN/A 3401060SN/A iew.tick(); 3411060SN/A 3421060SN/A commit.tick(); 3431060SN/A 3442292SN/A#if !FULL_SYSTEM 3452292SN/A doContextSwitch(); 3462292SN/A#endif 3472292SN/A 3482292SN/A // Now advance the time buffers 3491060SN/A timeBuffer.advance(); 3501060SN/A 3511060SN/A fetchQueue.advance(); 3521060SN/A decodeQueue.advance(); 3531060SN/A renameQueue.advance(); 3541060SN/A iewQueue.advance(); 3551060SN/A 3562325SN/A activityRec.advance(); 3572292SN/A 3582292SN/A if (removeInstsThisCycle) { 3592292SN/A cleanUpRemovedInsts(); 3602292SN/A } 3612292SN/A 3622325SN/A if (!tickEvent.scheduled()) { 3632325SN/A if (_status == SwitchedOut) { 3642325SN/A // increment stat 3652325SN/A lastRunningCycle = curTick; 3662325SN/A } else if (!activityRec.active()) { 3672325SN/A lastRunningCycle = curTick; 3682325SN/A timesIdled++; 3692325SN/A } else { 3702325SN/A tickEvent.schedule(curTick + cycles(1)); 3712325SN/A } 3722292SN/A } 3732292SN/A 3742292SN/A#if !FULL_SYSTEM 3752292SN/A updateThreadPriority(); 3762292SN/A#endif 3772292SN/A 3781060SN/A} 3791060SN/A 3801060SN/Atemplate <class Impl> 3811060SN/Avoid 3821755SN/AFullO3CPU<Impl>::init() 3831060SN/A{ 3842307SN/A if (!deferRegistration) { 3852307SN/A registerExecContexts(); 3862292SN/A } 3871060SN/A 3882292SN/A // Set inSyscall so that the CPU doesn't squash when initially 3892292SN/A // setting up registers. 3902292SN/A for (int i = 0; i < number_of_threads; ++i) 3912292SN/A thread[i]->inSyscall = true; 3922292SN/A 3932292SN/A for (int tid=0; tid < number_of_threads; tid++) { 3941858SN/A#if FULL_SYSTEM 3952307SN/A ExecContext *src_xc = execContexts[tid]; 3961681SN/A#else 3972292SN/A ExecContext *src_xc = thread[tid]->getXCProxy(); 3981681SN/A#endif 3992292SN/A // Threads start in the Suspended State 4002292SN/A if (src_xc->status() != ExecContext::Suspended) { 4012292SN/A continue; 4021060SN/A } 4031060SN/A 4042292SN/A#if FULL_SYSTEM 4052292SN/A TheISA::initCPU(src_xc, src_xc->readCpuId()); 4062292SN/A#endif 4072292SN/A } 4082292SN/A 4092292SN/A // Clear inSyscall. 4102292SN/A for (int i = 0; i < number_of_threads; ++i) 4112292SN/A thread[i]->inSyscall = false; 4122292SN/A 4132316SN/A // Initialize stages. 4142292SN/A fetch.initStage(); 4152292SN/A iew.initStage(); 4162292SN/A rename.initStage(); 4172292SN/A commit.initStage(); 4182292SN/A 4192292SN/A commit.setThreads(thread); 4202292SN/A} 4212292SN/A 4222292SN/Atemplate <class Impl> 4232292SN/Avoid 4242292SN/AFullO3CPU<Impl>::insertThread(unsigned tid) 4252292SN/A{ 4262292SN/A DPRINTF(FullCPU,"[tid:%i] Initializing thread data"); 4272292SN/A // Will change now that the PC and thread state is internal to the CPU 4282292SN/A // and not in the CPUExecContext. 4292292SN/A#if 0 4302292SN/A#if FULL_SYSTEM 4312292SN/A ExecContext *src_xc = system->execContexts[tid]; 4322292SN/A#else 4332292SN/A CPUExecContext *src_xc = thread[tid]; 4342292SN/A#endif 4352292SN/A 4362292SN/A //Bind Int Regs to Rename Map 4372292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 4382292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 4392292SN/A 4402292SN/A renameMap[tid].setEntry(ireg,phys_reg); 4412292SN/A scoreboard.setReg(phys_reg); 4422292SN/A } 4432292SN/A 4442292SN/A //Bind Float Regs to Rename Map 4452292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 4462292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 4472292SN/A 4482292SN/A renameMap[tid].setEntry(freg,phys_reg); 4492292SN/A scoreboard.setReg(phys_reg); 4502292SN/A } 4512292SN/A 4522292SN/A //Copy Thread Data Into RegFile 4532292SN/A this->copyFromXC(tid); 4542292SN/A 4552292SN/A //Set PC/NPC 4562292SN/A regFile.pc[tid] = src_xc->readPC(); 4572292SN/A regFile.npc[tid] = src_xc->readNextPC(); 4582292SN/A 4592292SN/A src_xc->setStatus(ExecContext::Active); 4602292SN/A 4612292SN/A activateContext(tid,1); 4622292SN/A 4632292SN/A //Reset ROB/IQ/LSQ Entries 4642292SN/A commit.rob->resetEntries(); 4652292SN/A iew.resetEntries(); 4662292SN/A#endif 4672292SN/A} 4682292SN/A 4692292SN/Atemplate <class Impl> 4702292SN/Avoid 4712292SN/AFullO3CPU<Impl>::removeThread(unsigned tid) 4722292SN/A{ 4732292SN/A DPRINTF(FullCPU,"[tid:%i] Removing thread data"); 4742292SN/A#if 0 4752292SN/A //Unbind Int Regs from Rename Map 4762292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 4772292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 4782292SN/A 4792292SN/A scoreboard.unsetReg(phys_reg); 4802292SN/A freeList.addReg(phys_reg); 4812292SN/A } 4822292SN/A 4832292SN/A //Unbind Float Regs from Rename Map 4842292SN/A for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) { 4852292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 4862292SN/A 4872292SN/A scoreboard.unsetReg(phys_reg); 4882292SN/A freeList.addReg(phys_reg); 4892292SN/A } 4902292SN/A 4912292SN/A //Copy Thread Data From RegFile 4922292SN/A /* Fix Me: 4932292SN/A * Do we really need to do this if we are removing a thread 4942292SN/A * in the sense that it's finished (exiting)? If the thread is just 4952292SN/A * being suspended we might... 4962292SN/A */ 4972292SN/A// this->copyToXC(tid); 4982292SN/A 4992292SN/A //Squash Throughout Pipeline 5002292SN/A fetch.squash(0,tid); 5012292SN/A decode.squash(tid); 5022292SN/A rename.squash(tid); 5032292SN/A 5042292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 5052292SN/A 5062292SN/A //Reset ROB/IQ/LSQ Entries 5072292SN/A if (activeThreads.size() >= 1) { 5082292SN/A commit.rob->resetEntries(); 5092292SN/A iew.resetEntries(); 5102292SN/A } 5112292SN/A#endif 5122292SN/A} 5132292SN/A 5142292SN/A 5152292SN/Atemplate <class Impl> 5162292SN/Avoid 5172292SN/AFullO3CPU<Impl>::activateWhenReady(int tid) 5182292SN/A{ 5192292SN/A DPRINTF(FullCPU,"[tid:%i]: Checking if resources are available for incoming" 5202292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 5212292SN/A tid); 5222292SN/A 5232292SN/A bool ready = true; 5242292SN/A 5252292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 5262292SN/A DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " 5272292SN/A "Phys. Int. Regs.\n", 5282292SN/A tid); 5292292SN/A ready = false; 5302292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 5312292SN/A DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " 5322292SN/A "Phys. Float. Regs.\n", 5332292SN/A tid); 5342292SN/A ready = false; 5352292SN/A } else if (commit.rob->numFreeEntries() >= 5362292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 5372292SN/A DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " 5382292SN/A "ROB entries.\n", 5392292SN/A tid); 5402292SN/A ready = false; 5412292SN/A } else if (iew.instQueue.numFreeEntries() >= 5422292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 5432292SN/A DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " 5442292SN/A "IQ entries.\n", 5452292SN/A tid); 5462292SN/A ready = false; 5472292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 5482292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 5492292SN/A DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " 5502292SN/A "LSQ entries.\n", 5512292SN/A tid); 5522292SN/A ready = false; 5532292SN/A } 5542292SN/A 5552292SN/A if (ready) { 5562292SN/A insertThread(tid); 5572292SN/A 5582292SN/A contextSwitch = false; 5592292SN/A 5602292SN/A cpuWaitList.remove(tid); 5612292SN/A } else { 5622292SN/A suspendContext(tid); 5632292SN/A 5642292SN/A //blocks fetch 5652292SN/A contextSwitch = true; 5662292SN/A 5672292SN/A //do waitlist 5682292SN/A cpuWaitList.push_back(tid); 5691060SN/A } 5701060SN/A} 5711060SN/A 5721060SN/Atemplate <class Impl> 5731060SN/Avoid 5742292SN/AFullO3CPU<Impl>::activateContext(int tid, int delay) 5751060SN/A{ 5761060SN/A // Needs to set each stage to running as well. 5772292SN/A list<unsigned>::iterator isActive = find( 5782292SN/A activeThreads.begin(), activeThreads.end(), tid); 5792292SN/A 5802292SN/A if (isActive == activeThreads.end()) { 5812292SN/A //May Need to Re-code this if the delay variable is the 5822292SN/A //delay needed for thread to activate 5832292SN/A DPRINTF(FullCPU, "Adding Thread %i to active threads list\n", 5842292SN/A tid); 5852292SN/A 5862292SN/A activeThreads.push_back(tid); 5872292SN/A } 5882292SN/A 5892307SN/A assert(_status == Idle || _status == SwitchedOut); 5901060SN/A 5911060SN/A scheduleTickEvent(delay); 5921060SN/A 5932292SN/A // Be sure to signal that there's some activity so the CPU doesn't 5942292SN/A // deschedule itself. 5952325SN/A activityRec.activity(); 5962292SN/A fetch.wakeFromQuiesce(); 5972292SN/A 5981060SN/A _status = Running; 5991060SN/A} 6001060SN/A 6011060SN/Atemplate <class Impl> 6021060SN/Avoid 6032292SN/AFullO3CPU<Impl>::suspendContext(int tid) 6041060SN/A{ 6052292SN/A DPRINTF(FullCPU,"[tid: %i]: Suspended ...\n", tid); 6062292SN/A unscheduleTickEvent(); 6072292SN/A _status = Idle; 6082292SN/A/* 6092292SN/A //Remove From Active List, if Active 6102292SN/A list<unsigned>::iterator isActive = find( 6112292SN/A activeThreads.begin(), activeThreads.end(), tid); 6122292SN/A 6132292SN/A if (isActive != activeThreads.end()) { 6142292SN/A DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n", 6152292SN/A tid); 6162292SN/A activeThreads.erase(isActive); 6172292SN/A } 6182292SN/A*/ 6191060SN/A} 6201060SN/A 6211060SN/Atemplate <class Impl> 6221060SN/Avoid 6232292SN/AFullO3CPU<Impl>::deallocateContext(int tid) 6241060SN/A{ 6252292SN/A DPRINTF(FullCPU,"[tid:%i]: Deallocating ...", tid); 6262292SN/A/* 6272292SN/A //Remove From Active List, if Active 6282292SN/A list<unsigned>::iterator isActive = find( 6292292SN/A activeThreads.begin(), activeThreads.end(), tid); 6302292SN/A 6312292SN/A if (isActive != activeThreads.end()) { 6322292SN/A DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n", 6332292SN/A tid); 6342292SN/A activeThreads.erase(isActive); 6352292SN/A 6362292SN/A removeThread(tid); 6372292SN/A } 6382292SN/A*/ 6391060SN/A} 6401060SN/A 6411060SN/Atemplate <class Impl> 6421060SN/Avoid 6432292SN/AFullO3CPU<Impl>::haltContext(int tid) 6441060SN/A{ 6452292SN/A DPRINTF(FullCPU,"[tid:%i]: Halted ...", tid); 6462292SN/A/* 6472292SN/A //Remove From Active List, if Active 6482292SN/A list<unsigned>::iterator isActive = find( 6492292SN/A activeThreads.begin(), activeThreads.end(), tid); 6502292SN/A 6512292SN/A if (isActive != activeThreads.end()) { 6522292SN/A DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n", 6532292SN/A tid); 6542292SN/A activeThreads.erase(isActive); 6552292SN/A 6562292SN/A removeThread(tid); 6572292SN/A } 6582292SN/A*/ 6591060SN/A} 6601060SN/A 6611060SN/Atemplate <class Impl> 6621060SN/Avoid 6632316SN/AFullO3CPU<Impl>::switchOut(Sampler *_sampler) 6641060SN/A{ 6652316SN/A sampler = _sampler; 6662316SN/A switchCount = 0; 6672307SN/A fetch.switchOut(); 6682307SN/A decode.switchOut(); 6692307SN/A rename.switchOut(); 6702307SN/A iew.switchOut(); 6712307SN/A commit.switchOut(); 6722325SN/A 6732325SN/A // Wake the CPU and record activity so everything can drain out if 6742325SN/A // the CPU is currently idle. 6752325SN/A wakeCPU(); 6762325SN/A activityRec.activity(); 6772316SN/A} 6782310SN/A 6792316SN/Atemplate <class Impl> 6802316SN/Avoid 6812316SN/AFullO3CPU<Impl>::signalSwitched() 6822316SN/A{ 6832325SN/A if (++switchCount == NumStages) { 6842316SN/A fetch.doSwitchOut(); 6852316SN/A rename.doSwitchOut(); 6862316SN/A commit.doSwitchOut(); 6872316SN/A instList.clear(); 6882316SN/A while (!removeList.empty()) { 6892316SN/A removeList.pop(); 6902316SN/A } 6912316SN/A 6922316SN/A if (checker) 6932316SN/A checker->switchOut(sampler); 6942316SN/A 6952316SN/A if (tickEvent.scheduled()) 6962316SN/A tickEvent.squash(); 6972316SN/A sampler->signalSwitched(); 6982316SN/A _status = SwitchedOut; 6992310SN/A } 7002316SN/A assert(switchCount <= 5); 7011060SN/A} 7021060SN/A 7031060SN/Atemplate <class Impl> 7041060SN/Avoid 7051755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 7061060SN/A{ 7072325SN/A // Flush out any old data from the time buffers. 7082325SN/A for (int i = 0; i < 10; ++i) { 7092307SN/A timeBuffer.advance(); 7102307SN/A fetchQueue.advance(); 7112307SN/A decodeQueue.advance(); 7122307SN/A renameQueue.advance(); 7132307SN/A iewQueue.advance(); 7142307SN/A } 7152307SN/A 7162325SN/A activityRec.reset(); 7172307SN/A 7181060SN/A BaseCPU::takeOverFrom(oldCPU); 7191060SN/A 7202307SN/A fetch.takeOverFrom(); 7212307SN/A decode.takeOverFrom(); 7222307SN/A rename.takeOverFrom(); 7232307SN/A iew.takeOverFrom(); 7242307SN/A commit.takeOverFrom(); 7252307SN/A 7261060SN/A assert(!tickEvent.scheduled()); 7271060SN/A 7282325SN/A // @todo: Figure out how to properly select the tid to put onto 7292325SN/A // the active threads list. 7302307SN/A int tid = 0; 7312307SN/A 7322307SN/A list<unsigned>::iterator isActive = find( 7332307SN/A activeThreads.begin(), activeThreads.end(), tid); 7342307SN/A 7352307SN/A if (isActive == activeThreads.end()) { 7362325SN/A //May Need to Re-code this if the delay variable is the delay 7372325SN/A //needed for thread to activate 7382307SN/A DPRINTF(FullCPU, "Adding Thread %i to active threads list\n", 7392307SN/A tid); 7402307SN/A 7412307SN/A activeThreads.push_back(tid); 7422307SN/A } 7432307SN/A 7442325SN/A // Set all statuses to active, schedule the CPU's tick event. 7452307SN/A // @todo: Fix up statuses so this is handled properly 7461060SN/A for (int i = 0; i < execContexts.size(); ++i) { 7471681SN/A ExecContext *xc = execContexts[i]; 7481681SN/A if (xc->status() == ExecContext::Active && _status != Running) { 7491681SN/A _status = Running; 7501681SN/A tickEvent.schedule(curTick); 7511681SN/A } 7521060SN/A } 7532307SN/A if (!tickEvent.scheduled()) 7542307SN/A tickEvent.schedule(curTick); 7551060SN/A} 7561060SN/A 7571060SN/Atemplate <class Impl> 7581060SN/Auint64_t 7591755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 7601060SN/A{ 7611060SN/A return regFile.readIntReg(reg_idx); 7621060SN/A} 7631060SN/A 7641060SN/Atemplate <class Impl> 7652455SN/AFloatReg 7662455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 7671060SN/A{ 7682455SN/A return regFile.readFloatReg(reg_idx, width); 7691060SN/A} 7701060SN/A 7711060SN/Atemplate <class Impl> 7722455SN/AFloatReg 7732455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 7741060SN/A{ 7752455SN/A return regFile.readFloatReg(reg_idx); 7761060SN/A} 7771060SN/A 7781060SN/Atemplate <class Impl> 7792455SN/AFloatRegBits 7802455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 7812669Sktlim@umich.edu{ 7822455SN/A return regFile.readFloatRegBits(reg_idx, width); 7832455SN/A} 7842455SN/A 7852455SN/Atemplate <class Impl> 7862455SN/AFloatRegBits 7872455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 7882455SN/A{ 7892455SN/A return regFile.readFloatRegBits(reg_idx); 7901060SN/A} 7911060SN/A 7921060SN/Atemplate <class Impl> 7931060SN/Avoid 7941755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 7951060SN/A{ 7961060SN/A regFile.setIntReg(reg_idx, val); 7971060SN/A} 7981060SN/A 7991060SN/Atemplate <class Impl> 8001060SN/Avoid 8012455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 8021060SN/A{ 8032455SN/A regFile.setFloatReg(reg_idx, val, width); 8041060SN/A} 8051060SN/A 8061060SN/Atemplate <class Impl> 8071060SN/Avoid 8082455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 8091060SN/A{ 8102455SN/A regFile.setFloatReg(reg_idx, val); 8111060SN/A} 8121060SN/A 8131060SN/Atemplate <class Impl> 8141060SN/Avoid 8152455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 8161060SN/A{ 8172455SN/A regFile.setFloatRegBits(reg_idx, val, width); 8182455SN/A} 8192455SN/A 8202455SN/Atemplate <class Impl> 8212455SN/Avoid 8222455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 8232455SN/A{ 8242455SN/A regFile.setFloatRegBits(reg_idx, val); 8251060SN/A} 8261060SN/A 8271060SN/Atemplate <class Impl> 8281060SN/Auint64_t 8292292SN/AFullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid) 8301060SN/A{ 8312292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8322292SN/A 8332292SN/A return regFile.readIntReg(phys_reg); 8342292SN/A} 8352292SN/A 8362292SN/Atemplate <class Impl> 8372292SN/Afloat 8382292SN/AFullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid) 8392292SN/A{ 8402307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 8412307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 8422292SN/A 8432669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 8442292SN/A} 8452292SN/A 8462292SN/Atemplate <class Impl> 8472292SN/Adouble 8482292SN/AFullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid) 8492292SN/A{ 8502307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 8512307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 8522292SN/A 8532669Sktlim@umich.edu return regFile.readFloatReg(phys_reg, 64); 8542292SN/A} 8552292SN/A 8562292SN/Atemplate <class Impl> 8572292SN/Auint64_t 8582292SN/AFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid) 8592292SN/A{ 8602307SN/A int idx = reg_idx + TheISA::FP_Base_DepTag; 8612307SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); 8622292SN/A 8632669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 8641060SN/A} 8651060SN/A 8661060SN/Atemplate <class Impl> 8671060SN/Avoid 8682292SN/AFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid) 8691060SN/A{ 8702292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8712292SN/A 8722292SN/A regFile.setIntReg(phys_reg, val); 8731060SN/A} 8741060SN/A 8751060SN/Atemplate <class Impl> 8761060SN/Avoid 8772292SN/AFullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) 8781060SN/A{ 8792292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8802292SN/A 8812669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 8821060SN/A} 8831060SN/A 8841060SN/Atemplate <class Impl> 8851060SN/Avoid 8862292SN/AFullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) 8871060SN/A{ 8882292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8892292SN/A 8902669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val, 64); 8911060SN/A} 8921060SN/A 8931060SN/Atemplate <class Impl> 8941060SN/Avoid 8952292SN/AFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) 8961060SN/A{ 8972292SN/A PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); 8981060SN/A 8992669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 9002292SN/A} 9012292SN/A 9022292SN/Atemplate <class Impl> 9032292SN/Auint64_t 9042292SN/AFullO3CPU<Impl>::readPC(unsigned tid) 9052292SN/A{ 9062292SN/A return commit.readPC(tid); 9071060SN/A} 9081060SN/A 9091060SN/Atemplate <class Impl> 9101060SN/Avoid 9112292SN/AFullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid) 9121060SN/A{ 9132292SN/A commit.setPC(new_PC, tid); 9142292SN/A} 9151060SN/A 9162292SN/Atemplate <class Impl> 9172292SN/Auint64_t 9182292SN/AFullO3CPU<Impl>::readNextPC(unsigned tid) 9192292SN/A{ 9202292SN/A return commit.readNextPC(tid); 9212292SN/A} 9221060SN/A 9232292SN/Atemplate <class Impl> 9242292SN/Avoid 9252292SN/AFullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid) 9262292SN/A{ 9272292SN/A commit.setNextPC(val, tid); 9282292SN/A} 9291060SN/A 9302292SN/Atemplate <class Impl> 9312292SN/Atypename FullO3CPU<Impl>::ListIt 9322292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 9332292SN/A{ 9342292SN/A instList.push_back(inst); 9351060SN/A 9362292SN/A return --(instList.end()); 9372292SN/A} 9381060SN/A 9392292SN/Atemplate <class Impl> 9402292SN/Avoid 9412292SN/AFullO3CPU<Impl>::instDone(unsigned tid) 9422292SN/A{ 9432292SN/A // Keep an instruction count. 9442292SN/A thread[tid]->numInst++; 9452292SN/A thread[tid]->numInsts++; 9462292SN/A committedInsts[tid]++; 9472292SN/A totalCommittedInsts++; 9482292SN/A 9492292SN/A // Check for instruction-count-based events. 9502292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 9512292SN/A} 9522292SN/A 9532292SN/Atemplate <class Impl> 9542292SN/Avoid 9552292SN/AFullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst) 9562292SN/A{ 9572292SN/A removeInstsThisCycle = true; 9582292SN/A 9592292SN/A removeList.push(inst->getInstListIt()); 9601060SN/A} 9611060SN/A 9621060SN/Atemplate <class Impl> 9631060SN/Avoid 9641755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 9651060SN/A{ 9662292SN/A DPRINTF(FullCPU, "FullCPU: Removing committed instruction [tid:%i] PC %#x " 9672292SN/A "[sn:%lli]\n", 9682303SN/A inst->threadNumber, inst->readPC(), inst->seqNum); 9691060SN/A 9702292SN/A removeInstsThisCycle = true; 9711060SN/A 9721060SN/A // Remove the front instruction. 9732292SN/A removeList.push(inst->getInstListIt()); 9741060SN/A} 9751060SN/A 9761060SN/Atemplate <class Impl> 9771060SN/Avoid 9782292SN/AFullO3CPU<Impl>::removeInstsNotInROB(unsigned tid) 9791060SN/A{ 9802292SN/A DPRINTF(FullCPU, "FullCPU: Thread %i: Deleting instructions from instruction" 9812292SN/A " list.\n", tid); 9821060SN/A 9832292SN/A ListIt end_it; 9841060SN/A 9852292SN/A bool rob_empty = false; 9862292SN/A 9872292SN/A if (instList.empty()) { 9882292SN/A return; 9892292SN/A } else if (rob.isEmpty(/*tid*/)) { 9902292SN/A DPRINTF(FullCPU, "FullCPU: ROB is empty, squashing all insts.\n"); 9912292SN/A end_it = instList.begin(); 9922292SN/A rob_empty = true; 9932292SN/A } else { 9942292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 9952292SN/A DPRINTF(FullCPU, "FullCPU: ROB is not empty, squashing insts not in ROB.\n"); 9962292SN/A } 9972292SN/A 9982292SN/A removeInstsThisCycle = true; 9992292SN/A 10002292SN/A ListIt inst_it = instList.end(); 10012292SN/A 10022292SN/A inst_it--; 10032292SN/A 10042292SN/A // Walk through the instruction list, removing any instructions 10052292SN/A // that were inserted after the given instruction iterator, end_it. 10062292SN/A while (inst_it != end_it) { 10072292SN/A assert(!instList.empty()); 10082292SN/A 10092292SN/A squashInstIt(inst_it, tid); 10102292SN/A 10112292SN/A inst_it--; 10122292SN/A } 10132292SN/A 10142292SN/A // If the ROB was empty, then we actually need to remove the first 10152292SN/A // instruction as well. 10162292SN/A if (rob_empty) { 10172292SN/A squashInstIt(inst_it, tid); 10182292SN/A } 10191060SN/A} 10201060SN/A 10211060SN/Atemplate <class Impl> 10221060SN/Avoid 10232292SN/AFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, 10242292SN/A unsigned tid) 10251062SN/A{ 10262292SN/A assert(!instList.empty()); 10272292SN/A 10282292SN/A removeInstsThisCycle = true; 10292292SN/A 10302292SN/A ListIt inst_iter = instList.end(); 10312292SN/A 10322292SN/A inst_iter--; 10332292SN/A 10341062SN/A DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction " 10352292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 10362292SN/A tid, seq_num, (*inst_iter)->seqNum); 10371062SN/A 10382292SN/A while ((*inst_iter)->seqNum > seq_num) { 10391062SN/A 10402292SN/A bool break_loop = (inst_iter == instList.begin()); 10411062SN/A 10422292SN/A squashInstIt(inst_iter, tid); 10431062SN/A 10442292SN/A inst_iter--; 10451062SN/A 10462292SN/A if (break_loop) 10472292SN/A break; 10482292SN/A } 10492292SN/A} 10502292SN/A 10512292SN/Atemplate <class Impl> 10522292SN/Ainline void 10532292SN/AFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid) 10542292SN/A{ 10552292SN/A if ((*instIt)->threadNumber == tid) { 10562292SN/A DPRINTF(FullCPU, "FullCPU: Squashing instruction, " 10572292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 10582292SN/A (*instIt)->threadNumber, 10592292SN/A (*instIt)->seqNum, 10602292SN/A (*instIt)->readPC()); 10611062SN/A 10621062SN/A // Mark it as squashed. 10632292SN/A (*instIt)->setSquashed(); 10642292SN/A 10652325SN/A // @todo: Formulate a consistent method for deleting 10662325SN/A // instructions from the instruction list 10672292SN/A // Remove the instruction from the list. 10682292SN/A removeList.push(instIt); 10692292SN/A } 10702292SN/A} 10712292SN/A 10722292SN/Atemplate <class Impl> 10732292SN/Avoid 10742292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 10752292SN/A{ 10762292SN/A while (!removeList.empty()) { 10772292SN/A DPRINTF(FullCPU, "FullCPU: Removing instruction, " 10782292SN/A "[tid:%i] [sn:%lli] PC %#x\n", 10792292SN/A (*removeList.front())->threadNumber, 10802292SN/A (*removeList.front())->seqNum, 10812292SN/A (*removeList.front())->readPC()); 10822292SN/A 10832292SN/A instList.erase(removeList.front()); 10842292SN/A 10852292SN/A removeList.pop(); 10861062SN/A } 10871062SN/A 10882292SN/A removeInstsThisCycle = false; 10891062SN/A} 10902325SN/A/* 10911062SN/Atemplate <class Impl> 10921062SN/Avoid 10931755SN/AFullO3CPU<Impl>::removeAllInsts() 10941060SN/A{ 10951060SN/A instList.clear(); 10961060SN/A} 10972325SN/A*/ 10981060SN/Atemplate <class Impl> 10991060SN/Avoid 11001755SN/AFullO3CPU<Impl>::dumpInsts() 11011060SN/A{ 11021060SN/A int num = 0; 11031060SN/A 11042292SN/A ListIt inst_list_it = instList.begin(); 11052292SN/A 11062292SN/A cprintf("Dumping Instruction List\n"); 11072292SN/A 11082292SN/A while (inst_list_it != instList.end()) { 11092292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 11102292SN/A "Squashed:%i\n\n", 11112292SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber, 11122292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 11132292SN/A (*inst_list_it)->isSquashed()); 11141060SN/A inst_list_it++; 11151060SN/A ++num; 11161060SN/A } 11171060SN/A} 11182325SN/A/* 11191060SN/Atemplate <class Impl> 11201060SN/Avoid 11211755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 11221060SN/A{ 11231060SN/A iew.wakeDependents(inst); 11241060SN/A} 11252325SN/A*/ 11262292SN/Atemplate <class Impl> 11272292SN/Avoid 11282292SN/AFullO3CPU<Impl>::wakeCPU() 11292292SN/A{ 11302325SN/A if (activityRec.active() || tickEvent.scheduled()) { 11312325SN/A DPRINTF(Activity, "CPU already running.\n"); 11322292SN/A return; 11332292SN/A } 11342292SN/A 11352325SN/A DPRINTF(Activity, "Waking up CPU\n"); 11362325SN/A 11372325SN/A idleCycles += (curTick - 1) - lastRunningCycle; 11382292SN/A 11392292SN/A tickEvent.schedule(curTick); 11402292SN/A} 11412292SN/A 11422292SN/Atemplate <class Impl> 11432292SN/Aint 11442292SN/AFullO3CPU<Impl>::getFreeTid() 11452292SN/A{ 11462292SN/A for (int i=0; i < numThreads; i++) { 11472292SN/A if (!tids[i]) { 11482292SN/A tids[i] = true; 11492292SN/A return i; 11502292SN/A } 11512292SN/A } 11522292SN/A 11532292SN/A return -1; 11542292SN/A} 11552292SN/A 11562292SN/Atemplate <class Impl> 11572292SN/Avoid 11582292SN/AFullO3CPU<Impl>::doContextSwitch() 11592292SN/A{ 11602292SN/A if (contextSwitch) { 11612292SN/A 11622292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 11632292SN/A 11642292SN/A for (int tid=0; tid < cpuWaitList.size(); tid++) { 11652292SN/A activateWhenReady(tid); 11662292SN/A } 11672292SN/A 11682292SN/A if (cpuWaitList.size() == 0) 11692292SN/A contextSwitch = true; 11702292SN/A } 11712292SN/A} 11722292SN/A 11732292SN/Atemplate <class Impl> 11742292SN/Avoid 11752292SN/AFullO3CPU<Impl>::updateThreadPriority() 11762292SN/A{ 11772292SN/A if (activeThreads.size() > 1) 11782292SN/A { 11792292SN/A //DEFAULT TO ROUND ROBIN SCHEME 11802292SN/A //e.g. Move highest priority to end of thread list 11812292SN/A list<unsigned>::iterator list_begin = activeThreads.begin(); 11822292SN/A list<unsigned>::iterator list_end = activeThreads.end(); 11832292SN/A 11842292SN/A unsigned high_thread = *list_begin; 11852292SN/A 11862292SN/A activeThreads.erase(list_begin); 11872292SN/A 11882292SN/A activeThreads.push_back(high_thread); 11892292SN/A } 11902292SN/A} 11911060SN/A 11921755SN/A// Forward declaration of FullO3CPU. 11931755SN/Atemplate class FullO3CPU<AlphaSimpleImpl>; 1194