cpu.cc revision 2455
12623SN/A/* 22623SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292623SN/A#include "config/full_system.hh" 302623SN/A 313170Sstever@eecs.umich.edu#if FULL_SYSTEM 322623SN/A#include "sim/system.hh" 334040Ssaidi@eecs.umich.edu#else 342623SN/A#include "sim/process.hh" 352623SN/A#endif 363348Sbinkertn@umich.edu#include "sim/root.hh" 373348Sbinkertn@umich.edu 382623SN/A#include "cpu/cpu_exec_context.hh" 392901Ssaidi@eecs.umich.edu#include "cpu/exec_context.hh" 402623SN/A#include "cpu/o3/alpha_dyn_inst.hh" 412623SN/A#include "cpu/o3/alpha_impl.hh" 422623SN/A#include "cpu/o3/cpu.hh" 432623SN/A 442856Srdreslin@umich.eduusing namespace std; 452856Srdreslin@umich.edu 462856Srdreslin@umich.eduBaseFullCPU::BaseFullCPU(Params ¶ms) 472856Srdreslin@umich.edu : BaseCPU(¶ms), cpu_id(0) 482856Srdreslin@umich.edu{ 492856Srdreslin@umich.edu} 502856Srdreslin@umich.edu 512856Srdreslin@umich.edutemplate <class Impl> 522856Srdreslin@umich.eduFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 532856Srdreslin@umich.edu : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 542623SN/A{ 552623SN/A} 562623SN/A 572623SN/Atemplate <class Impl> 582623SN/Avoid 592623SN/AFullO3CPU<Impl>::TickEvent::process() 602680Sktlim@umich.edu{ 612680Sktlim@umich.edu cpu->tick(); 622623SN/A} 632623SN/A 642680Sktlim@umich.edutemplate <class Impl> 652623SN/Aconst char * 662623SN/AFullO3CPU<Impl>::TickEvent::description() 672623SN/A{ 682623SN/A return "FullO3CPU tick event"; 692623SN/A} 703349Sbinkertn@umich.edu 712623SN/A//Call constructor to all the pipeline stages here 722623SN/Atemplate <class Impl> 732623SN/AFullO3CPU<Impl>::FullO3CPU(Params ¶ms) 742623SN/A#if FULL_SYSTEM 752623SN/A : BaseFullCPU(params), 762623SN/A#else 773349Sbinkertn@umich.edu : BaseFullCPU(params), 782623SN/A#endif // FULL_SYSTEM 793184Srdreslin@umich.edu tickEvent(this), 803184Srdreslin@umich.edu fetch(params), 812623SN/A decode(params), 822623SN/A rename(params), 832623SN/A iew(params), 842623SN/A commit(params), 852623SN/A 863647Srdreslin@umich.edu regFile(params.numPhysIntRegs, params.numPhysFloatRegs), 873647Srdreslin@umich.edu 883647Srdreslin@umich.edu freeList(TheISA::NumIntRegs, params.numPhysIntRegs, 893647Srdreslin@umich.edu TheISA::NumFloatRegs, params.numPhysFloatRegs), 903647Srdreslin@umich.edu 912631SN/A renameMap(TheISA::NumIntRegs, params.numPhysIntRegs, 923647Srdreslin@umich.edu TheISA::NumFloatRegs, params.numPhysFloatRegs, 932631SN/A TheISA::NumMiscRegs, 942623SN/A TheISA::ZeroReg, 952623SN/A TheISA::ZeroReg + TheISA::NumIntRegs), 962623SN/A 972948Ssaidi@eecs.umich.edu rob(params.numROBEntries, params.squashWidth), 982948Ssaidi@eecs.umich.edu 993349Sbinkertn@umich.edu // What to pass to these time buffers? 1002948Ssaidi@eecs.umich.edu // For now just have these time buffers be pretty big. 1012948Ssaidi@eecs.umich.edu timeBuffer(5, 5), 1022948Ssaidi@eecs.umich.edu fetchQueue(5, 5), 1032948Ssaidi@eecs.umich.edu decodeQueue(5, 5), 1042948Ssaidi@eecs.umich.edu renameQueue(5, 5), 1052623SN/A iewQueue(5, 5), 1063170Sstever@eecs.umich.edu 1073170Sstever@eecs.umich.edu cpuXC(NULL), 1082623SN/A 1092623SN/A globalSeqNum(1), 1103647Srdreslin@umich.edu 1113647Srdreslin@umich.edu#if FULL_SYSTEM 1123647Srdreslin@umich.edu system(params.system), 1133647Srdreslin@umich.edu memCtrl(system->memctrl), 1142623SN/A physmem(system->physmem), 1152839Sktlim@umich.edu itb(params.itb), 1162867Sktlim@umich.edu dtb(params.dtb), 1173222Sktlim@umich.edu mem(params.mem), 1182901Ssaidi@eecs.umich.edu#else 1192623SN/A // Hardcoded for a single thread!! 1202623SN/A mem(params.workload[0]->getMemory()), 1212623SN/A#endif // FULL_SYSTEM 1222623SN/A 1232623SN/A icacheInterface(params.icacheInterface), 1242623SN/A dcacheInterface(params.dcacheInterface), 1252623SN/A deferRegistration(params.defReg), 1262623SN/A numInsts(0), 1272623SN/A funcExeInst(0) 1282623SN/A{ 1292915Sktlim@umich.edu _status = Idle; 1302915Sktlim@umich.edu 1312623SN/A#if !FULL_SYSTEM 1322623SN/A thread.resize(this->number_of_threads); 1332623SN/A#endif 1342623SN/A 1352623SN/A for (int i = 0; i < this->number_of_threads; ++i) { 1362623SN/A#if FULL_SYSTEM 1372915Sktlim@umich.edu assert(i == 0); 1382915Sktlim@umich.edu thread[i] = new CPUExecContext(this, 0, system, itb, dtb, mem); 1392623SN/A system->execContexts[i] = thread[i]->getProxy(); 1402798Sktlim@umich.edu 1412798Sktlim@umich.edu execContexts.push_back(system->execContexts[i]); 1422901Ssaidi@eecs.umich.edu#else 1432839Sktlim@umich.edu if (i < params.workload.size()) { 1442798Sktlim@umich.edu DPRINTF(FullCPU, "FullCPU: Workload[%i]'s starting PC is %#x, " 1452839Sktlim@umich.edu "process is %#x", 1462798Sktlim@umich.edu i, params.workload[i]->prog_entry, thread[i]); 1472798Sktlim@umich.edu thread[i] = new CPUExecContext(this, i, params.workload[i], i); 1482901Ssaidi@eecs.umich.edu } 1492901Ssaidi@eecs.umich.edu assert(params.workload[i]->getMemory() != NULL); 1502798Sktlim@umich.edu assert(mem != NULL); 1512839Sktlim@umich.edu execContexts.push_back(thread[i]->getProxy()); 1522839Sktlim@umich.edu#endif // !FULL_SYSTEM 1532901Ssaidi@eecs.umich.edu } 1542798Sktlim@umich.edu 1552623SN/A // Note that this is a hack so that my code which still uses xc-> will 1562623SN/A // still work. I should remove this eventually 1572623SN/A cpuXC = thread[0]; 1582798Sktlim@umich.edu 1592623SN/A // The stages also need their CPU pointer setup. However this must be 1602798Sktlim@umich.edu // done at the upper level CPU because they have pointers to the upper 1613201Shsul@eecs.umich.edu // level CPU, and not this FullO3CPU. 1623201Shsul@eecs.umich.edu 1632867Sktlim@umich.edu // Give each of the stages the time buffer they will use. 1642867Sktlim@umich.edu fetch.setTimeBuffer(&timeBuffer); 1652915Sktlim@umich.edu decode.setTimeBuffer(&timeBuffer); 1662915Sktlim@umich.edu rename.setTimeBuffer(&timeBuffer); 1672915Sktlim@umich.edu iew.setTimeBuffer(&timeBuffer); 1682867Sktlim@umich.edu commit.setTimeBuffer(&timeBuffer); 1692867Sktlim@umich.edu 1702867Sktlim@umich.edu // Also setup each of the stages' queues. 1714471Sstever@eecs.umich.edu fetch.setFetchQueue(&fetchQueue); 1722623SN/A decode.setFetchQueue(&fetchQueue); 1732798Sktlim@umich.edu decode.setDecodeQueue(&decodeQueue); 1742901Ssaidi@eecs.umich.edu rename.setDecodeQueue(&decodeQueue); 1753222Sktlim@umich.edu rename.setRenameQueue(&renameQueue); 1762798Sktlim@umich.edu iew.setRenameQueue(&renameQueue); 1772798Sktlim@umich.edu iew.setIEWQueue(&iewQueue); 1782798Sktlim@umich.edu commit.setIEWQueue(&iewQueue); 1792798Sktlim@umich.edu commit.setRenameQueue(&renameQueue); 1802798Sktlim@umich.edu 1812798Sktlim@umich.edu // Setup the rename map for whichever stages need it. 1822798Sktlim@umich.edu rename.setRenameMap(&renameMap); 1833222Sktlim@umich.edu iew.setRenameMap(&renameMap); 1842867Sktlim@umich.edu 1852867Sktlim@umich.edu // Setup the free list for whichever stages need it. 1862867Sktlim@umich.edu rename.setFreeList(&freeList); 1872867Sktlim@umich.edu renameMap.setFreeList(&freeList); 1882867Sktlim@umich.edu 1892623SN/A // Setup the ROB for whichever stages need it. 1902623SN/A commit.setROB(&rob); 1912623SN/A} 1922623SN/A 1932623SN/Atemplate <class Impl> 1942623SN/AFullO3CPU<Impl>::~FullO3CPU() 1954192Sktlim@umich.edu{ 1962623SN/A} 1972680Sktlim@umich.edu 1982623SN/Atemplate <class Impl> 1992680Sktlim@umich.eduvoid 2002680Sktlim@umich.eduFullO3CPU<Impl>::fullCPURegStats() 2012680Sktlim@umich.edu{ 2022623SN/A // Register any of the FullCPU's stats here. 2032623SN/A} 2042623SN/A 2052623SN/Atemplate <class Impl> 2063201Shsul@eecs.umich.eduvoid 2073201Shsul@eecs.umich.eduFullO3CPU<Impl>::tick() 2083201Shsul@eecs.umich.edu{ 2093201Shsul@eecs.umich.edu DPRINTF(FullCPU, "\n\nFullCPU: Ticking main, FullO3CPU.\n"); 2102623SN/A 2112623SN/A //Tick each of the stages if they're actually running. 2122623SN/A //Will want to figure out a way to unschedule itself if they're all 2132623SN/A //going to be idle for a long time. 2142623SN/A fetch.tick(); 2152623SN/A 2162623SN/A decode.tick(); 2172683Sktlim@umich.edu 2182623SN/A rename.tick(); 2192623SN/A 2202623SN/A iew.tick(); 2212623SN/A 2222623SN/A commit.tick(); 2233686Sktlim@umich.edu 2242623SN/A // Now advance the time buffers, unless the stage is stalled. 2254471Sstever@eecs.umich.edu timeBuffer.advance(); 2262623SN/A 2272623SN/A fetchQueue.advance(); 2282623SN/A decodeQueue.advance(); 2292623SN/A renameQueue.advance(); 2302623SN/A iewQueue.advance(); 2312623SN/A 2322623SN/A if (_status == Running && !tickEvent.scheduled()) 2332683Sktlim@umich.edu tickEvent.schedule(curTick + 1); 2342623SN/A} 2352644Sstever@eecs.umich.edu 2362623SN/Atemplate <class Impl> 2372644Sstever@eecs.umich.eduvoid 2382644Sstever@eecs.umich.eduFullO3CPU<Impl>::init() 2392623SN/A{ 2402623SN/A if(!deferRegistration) 2412623SN/A { 2422623SN/A this->registerExecContexts(); 2432623SN/A 2442623SN/A // Need to do a copy of the xc->regs into the CPU's regfile so 2452623SN/A // that it can start properly. 2462623SN/A#if FULL_SYSTEM 2472623SN/A ExecContext *src_xc = system->execContexts[0]; 2482623SN/A TheISA::initCPU(src_xc, src_xc->readCpuId()); 2493169Sstever@eecs.umich.edu#else 2503169Sstever@eecs.umich.edu ExecContext *src_xc = thread[0]->getProxy(); 2513170Sstever@eecs.umich.edu#endif 2522623SN/A // First loop through the integer registers. 2532623SN/A for (int i = 0; i < TheISA::NumIntRegs; ++i) 2543169Sstever@eecs.umich.edu { 2552623SN/A regFile.intRegFile[i] = src_xc->readIntReg(i); 2562623SN/A } 2572623SN/A 2583169Sstever@eecs.umich.edu // Then loop through the floating point registers. 2592623SN/A for (int i = 0; i < TheISA::NumFloatRegs; ++i) 2602623SN/A { 2612623SN/A regFile.floatRegFile.setRegBits(i, src_xc->readRegBits(i)) 2623349Sbinkertn@umich.edu } 2634022Sstever@eecs.umich.edu/* 2643169Sstever@eecs.umich.edu // Then loop through the misc registers. 2652623SN/A regFile.miscRegs.fpcr = src_xc->regs.miscRegs.fpcr; 2663169Sstever@eecs.umich.edu regFile.miscRegs.uniq = src_xc->regs.miscRegs.uniq; 2672623SN/A regFile.miscRegs.lock_flag = src_xc->regs.miscRegs.lock_flag; 2683169Sstever@eecs.umich.edu regFile.miscRegs.lock_addr = src_xc->regs.miscRegs.lock_addr; 2692623SN/A*/ 2702623SN/A // Then finally set the PC and the next PC. 2713169Sstever@eecs.umich.edu regFile.pc = src_xc->readPC(); 2722623SN/A regFile.npc = src_xc->readNextPC(); 2732623SN/A } 2744200Ssaidi@eecs.umich.edu} 2754200Ssaidi@eecs.umich.edu 2764200Ssaidi@eecs.umich.edutemplate <class Impl> 2774200Ssaidi@eecs.umich.eduvoid 2783658Sktlim@umich.eduFullO3CPU<Impl>::activateContext(int thread_num, int delay) 2793658Sktlim@umich.edu{ 2802623SN/A // Needs to set each stage to running as well. 2812623SN/A 2822623SN/A scheduleTickEvent(delay); 2832623SN/A 2842623SN/A _status = Running; 2852623SN/A} 2862623SN/A 2872623SN/Atemplate <class Impl> 2882623SN/Avoid 2894040Ssaidi@eecs.umich.eduFullO3CPU<Impl>::suspendContext(int thread_num) 2904040Ssaidi@eecs.umich.edu{ 2914040Ssaidi@eecs.umich.edu panic("suspendContext unimplemented!"); 2924040Ssaidi@eecs.umich.edu} 2934115Ssaidi@eecs.umich.edu 2944115Ssaidi@eecs.umich.edutemplate <class Impl> 2954115Ssaidi@eecs.umich.eduvoid 2964115Ssaidi@eecs.umich.eduFullO3CPU<Impl>::deallocateContext(int thread_num) 2972623SN/A{ 2982623SN/A panic("deallocateContext unimplemented!"); 2992623SN/A} 3002623SN/A 3012623SN/Atemplate <class Impl> 3022623SN/Avoid 3032623SN/AFullO3CPU<Impl>::haltContext(int thread_num) 3042623SN/A{ 3052623SN/A panic("haltContext unimplemented!"); 3062623SN/A} 3072623SN/A 3082623SN/Atemplate <class Impl> 3092623SN/Avoid 3102623SN/AFullO3CPU<Impl>::switchOut() 3112623SN/A{ 3122623SN/A panic("FullO3CPU does not have a switch out function.\n"); 3132623SN/A} 3142623SN/A 3152623SN/Atemplate <class Impl> 3162623SN/Avoid 3172623SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 3182623SN/A{ 3192623SN/A BaseCPU::takeOverFrom(oldCPU); 3202623SN/A 3212623SN/A assert(!tickEvent.scheduled()); 3222623SN/A 3232623SN/A // Set all status's to active, schedule the 3242623SN/A // CPU's tick event. 3252623SN/A for (int i = 0; i < execContexts.size(); ++i) { 3262623SN/A ExecContext *xc = execContexts[i]; 3272623SN/A if (xc->status() == ExecContext::Active && _status != Running) { 3282623SN/A _status = Running; 3292623SN/A tickEvent.schedule(curTick); 3302623SN/A } 3312623SN/A } 3322623SN/A} 3332623SN/A 3342623SN/Atemplate <class Impl> 3352623SN/AInstSeqNum 3362623SN/AFullO3CPU<Impl>::getAndIncrementInstSeq() 3372623SN/A{ 3382623SN/A // Hopefully this works right. 3392623SN/A return globalSeqNum++; 3403169Sstever@eecs.umich.edu} 3413169Sstever@eecs.umich.edu 3423170Sstever@eecs.umich.edutemplate <class Impl> 3432623SN/Auint64_t 3444040Ssaidi@eecs.umich.eduFullO3CPU<Impl>::readIntReg(int reg_idx) 3454040Ssaidi@eecs.umich.edu{ 3464040Ssaidi@eecs.umich.edu return regFile.readIntReg(reg_idx); 3474040Ssaidi@eecs.umich.edu} 3482623SN/A 3493169Sstever@eecs.umich.edutemplate <class Impl> 3503169Sstever@eecs.umich.eduFloatReg 3512623SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx, int width) 3522623SN/A{ 3533169Sstever@eecs.umich.edu return regFile.readFloatReg(reg_idx, width); 3544040Ssaidi@eecs.umich.edu} 3554040Ssaidi@eecs.umich.edu 3564040Ssaidi@eecs.umich.edutemplate <class Impl> 3574040Ssaidi@eecs.umich.eduFloatReg 3583169Sstever@eecs.umich.eduFullO3CPU<Impl>::readFloatReg(int reg_idx) 3593169Sstever@eecs.umich.edu{ 3602623SN/A return regFile.readFloatReg(reg_idx); 3613170Sstever@eecs.umich.edu} 3623170Sstever@eecs.umich.edu 3633170Sstever@eecs.umich.edutemplate <class Impl> 3643170Sstever@eecs.umich.eduFloatRegBits 3653170Sstever@eecs.umich.eduFullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width) 3664040Ssaidi@eecs.umich.edu{ 3674040Ssaidi@eecs.umich.edu return regFile.readFloatRegBits(reg_idx, width); 3684040Ssaidi@eecs.umich.edu} 3694040Ssaidi@eecs.umich.edu 3703170Sstever@eecs.umich.edutemplate <class Impl> 3713170Sstever@eecs.umich.eduFloatRegBits 3723170Sstever@eecs.umich.eduFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 3733170Sstever@eecs.umich.edu{ 3743170Sstever@eecs.umich.edu return regFile.readFloatRegBits(reg_idx); 3753170Sstever@eecs.umich.edu} 3763170Sstever@eecs.umich.edu 3773170Sstever@eecs.umich.edutemplate <class Impl> 3783170Sstever@eecs.umich.eduvoid 3792623SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 3804200Ssaidi@eecs.umich.edu{ 3814200Ssaidi@eecs.umich.edu regFile.setIntReg(reg_idx, val); 3824200Ssaidi@eecs.umich.edu} 3833658Sktlim@umich.edu 3843658Sktlim@umich.edutemplate <class Impl> 3852623SN/Avoid 3862623SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) 3872623SN/A{ 3882623SN/A regFile.setFloatReg(reg_idx, val, width); 3892623SN/A} 3902623SN/A 3912623SN/Atemplate <class Impl> 3922623SN/Avoid 3932623SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 3942623SN/A{ 3952623SN/A regFile.setFloatReg(reg_idx, val); 3962623SN/A} 3974224Sgblack@eecs.umich.edu 3984224Sgblack@eecs.umich.edutemplate <class Impl> 3994224Sgblack@eecs.umich.eduvoid 4004224Sgblack@eecs.umich.eduFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) 4014224Sgblack@eecs.umich.edu{ 4024224Sgblack@eecs.umich.edu regFile.setFloatRegBits(reg_idx, val, width); 4034224Sgblack@eecs.umich.edu} 4044224Sgblack@eecs.umich.edu 4054224Sgblack@eecs.umich.edutemplate <class Impl> 4064224Sgblack@eecs.umich.eduvoid 4072623SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 4082623SN/A{ 4092623SN/A regFile.setFloatRegBits(reg_idx, val); 4102623SN/A} 4112623SN/A 4122623SN/Atemplate <class Impl> 4132623SN/Auint64_t 4142623SN/AFullO3CPU<Impl>::readPC() 4152623SN/A{ 4162623SN/A return regFile.readPC(); 4172623SN/A} 4182623SN/A 4192623SN/Atemplate <class Impl> 4202623SN/Avoid 4212623SN/AFullO3CPU<Impl>::setNextPC(uint64_t val) 4222623SN/A{ 4232623SN/A regFile.setNextPC(val); 4242623SN/A} 4252623SN/A 4262623SN/Atemplate <class Impl> 4272623SN/Avoid 4282623SN/AFullO3CPU<Impl>::setPC(Addr new_PC) 4292623SN/A{ 4302623SN/A regFile.setPC(new_PC); 4312623SN/A} 4322623SN/A 4332623SN/Atemplate <class Impl> 4342623SN/Avoid 4352623SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 4362623SN/A{ 4372623SN/A instList.push_back(inst); 4382623SN/A} 4392623SN/A 4402623SN/Atemplate <class Impl> 4412623SN/Avoid 4422623SN/AFullO3CPU<Impl>::instDone() 4432623SN/A{ 4442623SN/A // Keep an instruction count. 4452623SN/A numInsts++; 4462623SN/A 4472623SN/A // Check for instruction-count-based events. 4482623SN/A comInstEventQueue[0]->serviceEvents(numInsts); 4492623SN/A} 4502623SN/A 4512623SN/Atemplate <class Impl> 4522623SN/Avoid 4533387Sgblack@eecs.umich.eduFullO3CPU<Impl>::removeBackInst(DynInstPtr &inst) 4543387Sgblack@eecs.umich.edu{ 4552631SN/A DynInstPtr inst_to_delete; 4562663Sstever@eecs.umich.edu 4573170Sstever@eecs.umich.edu // Walk through the instruction list, removing any instructions 4582662Sstever@eecs.umich.edu // that were inserted after the given instruction, inst. 4592623SN/A while (instList.back() != inst) 4604022Sstever@eecs.umich.edu { 4612623SN/A assert(!instList.empty()); 4622623SN/A 4632623SN/A // Obtain the pointer to the instruction. 4642630SN/A inst_to_delete = instList.back(); 4652623SN/A 4662623SN/A DPRINTF(FullCPU, "FullCPU: Removing instruction %i, PC %#x\n", 4672623SN/A inst_to_delete->seqNum, inst_to_delete->readPC()); 4682623SN/A 4692623SN/A // Remove the instruction from the list. 4702623SN/A instList.pop_back(); 4712623SN/A 4722623SN/A // Mark it as squashed. 4732623SN/A inst_to_delete->setSquashed(); 4743658Sktlim@umich.edu } 4753658Sktlim@umich.edu} 4762644Sstever@eecs.umich.edu 4772644Sstever@eecs.umich.edutemplate <class Impl> 4782623SN/Avoid 4793222Sktlim@umich.eduFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 4803222Sktlim@umich.edu{ 4813222Sktlim@umich.edu DynInstPtr inst_to_remove; 4822623SN/A 4832623SN/A // The front instruction should be the same one being asked to be removed. 4842623SN/A assert(instList.front() == inst); 4852623SN/A 4862644Sstever@eecs.umich.edu // Remove the front instruction. 4872623SN/A inst_to_remove = inst; 4882623SN/A instList.pop_front(); 4892623SN/A 4902631SN/A DPRINTF(FullCPU, "FullCPU: Removing committed instruction %#x, PC %#x\n", 4912631SN/A inst_to_remove, inst_to_remove->readPC()); 4922631SN/A} 4932631SN/A 4942631SN/Atemplate <class Impl> 4952631SN/Avoid 4962623SN/AFullO3CPU<Impl>::removeInstsNotInROB() 4972623SN/A{ 4982623SN/A DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction " 4992623SN/A "list.\n"); 5003349Sbinkertn@umich.edu 5012623SN/A DynInstPtr rob_tail = rob.readTailInst(); 5022623SN/A 5032623SN/A removeBackInst(rob_tail); 5044870Sstever@eecs.umich.edu} 5052623SN/A 5062798Sktlim@umich.edutemplate <class Impl> 5072623SN/Avoid 5082644Sstever@eecs.umich.eduFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num) 5093222Sktlim@umich.edu{ 5103222Sktlim@umich.edu DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction " 5113222Sktlim@umich.edu "list.\n"); 5122839Sktlim@umich.edu 5133658Sktlim@umich.edu DynInstPtr inst_to_delete; 5143658Sktlim@umich.edu 5153658Sktlim@umich.edu while (instList.back()->seqNum > seq_num) { 5162839Sktlim@umich.edu assert(!instList.empty()); 5172798Sktlim@umich.edu 5182798Sktlim@umich.edu // Obtain the pointer to the instruction. 5192798Sktlim@umich.edu inst_to_delete = instList.back(); 5202623SN/A 5212644Sstever@eecs.umich.edu DPRINTF(FullCPU, "FullCPU: Removing instruction %i, PC %#x\n", 5222623SN/A inst_to_delete->seqNum, inst_to_delete->readPC()); 5232623SN/A 5243170Sstever@eecs.umich.edu // Remove the instruction from the list. 5253170Sstever@eecs.umich.edu instList.back() = NULL; 5263170Sstever@eecs.umich.edu instList.pop_back(); 5273170Sstever@eecs.umich.edu 5282644Sstever@eecs.umich.edu // Mark it as squashed. 5293170Sstever@eecs.umich.edu inst_to_delete->setSquashed(); 5303170Sstever@eecs.umich.edu } 5313170Sstever@eecs.umich.edu 5323170Sstever@eecs.umich.edu} 5333170Sstever@eecs.umich.edu 5343170Sstever@eecs.umich.edutemplate <class Impl> 5353170Sstever@eecs.umich.eduvoid 5363170Sstever@eecs.umich.eduFullO3CPU<Impl>::removeAllInsts() 5373170Sstever@eecs.umich.edu{ 5382644Sstever@eecs.umich.edu instList.clear(); 5392644Sstever@eecs.umich.edu} 5402644Sstever@eecs.umich.edu 5412623SN/Atemplate <class Impl> 5422623SN/Avoid 5432623SN/AFullO3CPU<Impl>::dumpInsts() 5442644Sstever@eecs.umich.edu{ 5452644Sstever@eecs.umich.edu int num = 0; 5462623SN/A typename list<DynInstPtr>::iterator inst_list_it = instList.begin(); 5473658Sktlim@umich.edu 5483658Sktlim@umich.edu while (inst_list_it != instList.end()) 5493658Sktlim@umich.edu { 5502623SN/A cprintf("Instruction:%i\nPC:%#x\nSN:%lli\nIssued:%i\nSquashed:%i\n\n", 5512623SN/A num, (*inst_list_it)->readPC(), (*inst_list_it)->seqNum, 5522948Ssaidi@eecs.umich.edu (*inst_list_it)->isIssued(), (*inst_list_it)->isSquashed()); 5532948Ssaidi@eecs.umich.edu inst_list_it++; 5542948Ssaidi@eecs.umich.edu ++num; 5552948Ssaidi@eecs.umich.edu } 5562948Ssaidi@eecs.umich.edu} 5572623SN/A 5582623SN/Atemplate <class Impl> 5593349Sbinkertn@umich.eduvoid 5602623SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 5613310Srdreslin@umich.edu{ 5623310Srdreslin@umich.edu iew.wakeDependents(inst); 5634584Ssaidi@eecs.umich.edu} 5642948Ssaidi@eecs.umich.edu 5653495Sktlim@umich.edu// Forward declaration of FullO3CPU. 5663310Srdreslin@umich.edutemplate class FullO3CPU<AlphaSimpleImpl>; 5673310Srdreslin@umich.edu