cpu.cc revision 13644
11689SN/A/* 213601Sgiacomo.travaglini@arm.com * Copyright (c) 2011-2012, 2014, 2016, 2017, 2019 ARM Limited 39916Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48707Sandreas.hansson@arm.com * All rights reserved 58707Sandreas.hansson@arm.com * 68707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148707Sandreas.hansson@arm.com * 152325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 167897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 171689SN/A * All rights reserved. 181689SN/A * 191689SN/A * Redistribution and use in source and binary forms, with or without 201689SN/A * modification, are permitted provided that the following conditions are 211689SN/A * met: redistributions of source code must retain the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer; 231689SN/A * redistributions in binary form must reproduce the above copyright 241689SN/A * notice, this list of conditions and the following disclaimer in the 251689SN/A * documentation and/or other materials provided with the distribution; 261689SN/A * neither the name of the copyright holders nor the names of its 271689SN/A * contributors may be used to endorse or promote products derived from 281689SN/A * this software without specific prior written permission. 291689SN/A * 301689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 432756Sksewell@umich.edu * Korey Sewell 447897Shestness@cs.utexas.edu * Rick Strong 451689SN/A */ 461689SN/A 4711793Sbrandon.potter@amd.com#include "cpu/o3/cpu.hh" 4811793Sbrandon.potter@amd.com 4912109SRekai.GonzalezAlberquilla@arm.com#include "arch/generic/traits.hh" 508779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 516658Snate@binkert.org#include "config/the_isa.hh" 5211793Sbrandon.potter@amd.com#include "cpu/activity.hh" 538887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 548887Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 558229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 568229Snate@binkert.org#include "cpu/o3/thread_context.hh" 578779Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 584762Snate@binkert.org#include "cpu/simple_thread.hh" 594762Snate@binkert.org#include "cpu/thread_context.hh" 608232Snate@binkert.org#include "debug/Activity.hh" 619152Satgutier@umich.edu#include "debug/Drain.hh" 628232Snate@binkert.org#include "debug/O3CPU.hh" 638232Snate@binkert.org#include "debug/Quiesce.hh" 644762Snate@binkert.org#include "enums/MemoryMode.hh" 654762Snate@binkert.org#include "sim/core.hh" 668793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 678779Sgblack@eecs.umich.edu#include "sim/process.hh" 684762Snate@binkert.org#include "sim/stat_control.hh" 698460SAli.Saidi@ARM.com#include "sim/system.hh" 704762Snate@binkert.org 715702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 725702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 738232Snate@binkert.org#include "debug/Activity.hh" 7411793Sbrandon.potter@amd.com 755702Ssaidi@eecs.umich.edu#endif 765702Ssaidi@eecs.umich.edu 778737Skoansin.tan@gmail.comstruct BaseCPUParams; 785529Snate@binkert.org 792669Sktlim@umich.eduusing namespace TheISA; 806221Snate@binkert.orgusing namespace std; 811060SN/A 825529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 835712Shsul@eecs.umich.edu : BaseCPU(params) 841060SN/A{ 851060SN/A} 861060SN/A 872292SN/Avoid 882733Sktlim@umich.eduBaseO3CPU::regStats() 892292SN/A{ 902292SN/A BaseCPU::regStats(); 912292SN/A} 922292SN/A 938707Sandreas.hansson@arm.comtemplate<class Impl> 948707Sandreas.hansson@arm.combool 958975Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt) 968707Sandreas.hansson@arm.com{ 978707Sandreas.hansson@arm.com DPRINTF(O3CPU, "Fetch unit received timing\n"); 9811284Sandreas.hansson@arm.com // We shouldn't ever get a cacheable block in Modified state 9910821Sandreas.hansson@arm.com assert(pkt->req->isUncacheable() || 10011284Sandreas.hansson@arm.com !(pkt->cacheResponding() && !pkt->hasSharers())); 1018948Sandreas.hansson@arm.com fetch->processCacheCompletion(pkt); 1028707Sandreas.hansson@arm.com 1038707Sandreas.hansson@arm.com return true; 1048707Sandreas.hansson@arm.com} 1058707Sandreas.hansson@arm.com 1068707Sandreas.hansson@arm.comtemplate<class Impl> 1078707Sandreas.hansson@arm.comvoid 10810713Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvReqRetry() 1098707Sandreas.hansson@arm.com{ 11010713Sandreas.hansson@arm.com fetch->recvReqRetry(); 1118707Sandreas.hansson@arm.com} 1128707Sandreas.hansson@arm.com 1138707Sandreas.hansson@arm.comtemplate <class Impl> 1148707Sandreas.hansson@arm.combool 1158975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt) 1168707Sandreas.hansson@arm.com{ 1178975Sandreas.hansson@arm.com return lsq->recvTimingResp(pkt); 1188707Sandreas.hansson@arm.com} 1198707Sandreas.hansson@arm.com 1208707Sandreas.hansson@arm.comtemplate <class Impl> 1218975Sandreas.hansson@arm.comvoid 1228975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 1238948Sandreas.hansson@arm.com{ 12411148Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { 12511148Smitch.hayenga@arm.com if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { 12611151Smitch.hayenga@arm.com cpu->wakeup(tid); 12711148Smitch.hayenga@arm.com } 12810529Smorr@cs.wisc.edu } 1298975Sandreas.hansson@arm.com lsq->recvTimingSnoopReq(pkt); 1308948Sandreas.hansson@arm.com} 1318948Sandreas.hansson@arm.com 1328948Sandreas.hansson@arm.comtemplate <class Impl> 1338707Sandreas.hansson@arm.comvoid 13410713Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvReqRetry() 1358707Sandreas.hansson@arm.com{ 13610713Sandreas.hansson@arm.com lsq->recvReqRetry(); 1378707Sandreas.hansson@arm.com} 1388707Sandreas.hansson@arm.com 1391060SN/Atemplate <class Impl> 1405595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 1412733Sktlim@umich.edu : BaseO3CPU(params), 1423781Sgblack@eecs.umich.edu itb(params->itb), 1433781Sgblack@eecs.umich.edu dtb(params->dtb), 14412127Sspwilson2@wisc.edu tickEvent([this]{ tick(); }, "FullO3CPU tick", 14512127Sspwilson2@wisc.edu false, Event::CPU_Tick_Pri), 14613641Sqtt2@cornell.edu threadExitEvent([this]{ exitThreads(); }, "FullO3CPU exit threads", 14713641Sqtt2@cornell.edu false, Event::CPU_Exit_Pri), 1485737Scws3k@cs.virginia.edu#ifndef NDEBUG 1495737Scws3k@cs.virginia.edu instcount(0), 1505737Scws3k@cs.virginia.edu#endif 1512292SN/A removeInstsThisCycle(false), 1525595Sgblack@eecs.umich.edu fetch(this, params), 1535595Sgblack@eecs.umich.edu decode(this, params), 1545595Sgblack@eecs.umich.edu rename(this, params), 1555595Sgblack@eecs.umich.edu iew(this, params), 1565595Sgblack@eecs.umich.edu commit(this, params), 1571060SN/A 15812109SRekai.GonzalezAlberquilla@arm.com /* It is mandatory that all SMT threads use the same renaming mode as 15912109SRekai.GonzalezAlberquilla@arm.com * they are sharing registers and rename */ 16013601Sgiacomo.travaglini@arm.com vecMode(RenameMode<TheISA::ISA>::init(params->isa[0])), 1619915Ssteve.reinhardt@amd.com regFile(params->numPhysIntRegs, 1629920Syasuko.eckert@amd.com params->numPhysFloatRegs, 16312109SRekai.GonzalezAlberquilla@arm.com params->numPhysVecRegs, 16413610Sgiacomo.gabrielli@arm.com params->numPhysVecPredRegs, 16512109SRekai.GonzalezAlberquilla@arm.com params->numPhysCCRegs, 16612109SRekai.GonzalezAlberquilla@arm.com vecMode), 1671060SN/A 1689919Ssteve.reinhardt@amd.com freeList(name() + ".freelist", ®File), 1691060SN/A 1709954SFaissal.Sleiman@arm.com rob(this, params), 1711060SN/A 1729916Ssteve.reinhardt@amd.com scoreboard(name() + ".scoreboard", 17312105Snathanael.premillieu@arm.com regFile.totalNumPhysRegs()), 1741060SN/A 1759384SAndreas.Sandberg@arm.com isa(numThreads, NULL), 1769384SAndreas.Sandberg@arm.com 1778707Sandreas.hansson@arm.com icachePort(&fetch, this), 1788707Sandreas.hansson@arm.com dcachePort(&iew.ldstQueue, this), 1798707Sandreas.hansson@arm.com 1802873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1812873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1822873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1832873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1842873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1855804Snate@binkert.org activityRec(name(), NumStages, 1862873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1872873Sktlim@umich.edu params->activity), 1881060SN/A 1891060SN/A globalSeqNum(1), 1902292SN/A system(params->system), 1919180Sandreas.hansson@arm.com lastRunningCycle(curCycle()) 1921060SN/A{ 1939433SAndreas.Sandberg@ARM.com if (!params->switched_out) { 1943221Sktlim@umich.edu _status = Running; 1953221Sktlim@umich.edu } else { 1969152Satgutier@umich.edu _status = SwitchedOut; 1973221Sktlim@umich.edu } 1981681SN/A 1992794Sktlim@umich.edu if (params->checker) { 2002316SN/A BaseCPU *temp_checker = params->checker; 2018733Sgeoffrey.blake@arm.com checker = dynamic_cast<Checker<Impl> *>(temp_checker); 2028707Sandreas.hansson@arm.com checker->setIcachePort(&icachePort); 2032316SN/A checker->setSystem(params->system); 2044598Sbinkertn@umich.edu } else { 2054598Sbinkertn@umich.edu checker = NULL; 2064598Sbinkertn@umich.edu } 2072316SN/A 2088793Sgblack@eecs.umich.edu if (!FullSystem) { 2098793Sgblack@eecs.umich.edu thread.resize(numThreads); 2108793Sgblack@eecs.umich.edu tids.resize(numThreads); 2118793Sgblack@eecs.umich.edu } 2121681SN/A 2132325SN/A // The stages also need their CPU pointer setup. However this 2142325SN/A // must be done at the upper level CPU because they have pointers 2152325SN/A // to the upper level CPU, and not this FullO3CPU. 2161060SN/A 2172292SN/A // Set up Pointers to the activeThreads list for each stage 2182292SN/A fetch.setActiveThreads(&activeThreads); 2192292SN/A decode.setActiveThreads(&activeThreads); 2202292SN/A rename.setActiveThreads(&activeThreads); 2212292SN/A iew.setActiveThreads(&activeThreads); 2222292SN/A commit.setActiveThreads(&activeThreads); 2231060SN/A 2241060SN/A // Give each of the stages the time buffer they will use. 2251060SN/A fetch.setTimeBuffer(&timeBuffer); 2261060SN/A decode.setTimeBuffer(&timeBuffer); 2271060SN/A rename.setTimeBuffer(&timeBuffer); 2281060SN/A iew.setTimeBuffer(&timeBuffer); 2291060SN/A commit.setTimeBuffer(&timeBuffer); 2301060SN/A 2311060SN/A // Also setup each of the stages' queues. 2321060SN/A fetch.setFetchQueue(&fetchQueue); 2331060SN/A decode.setFetchQueue(&fetchQueue); 2342292SN/A commit.setFetchQueue(&fetchQueue); 2351060SN/A decode.setDecodeQueue(&decodeQueue); 2361060SN/A rename.setDecodeQueue(&decodeQueue); 2371060SN/A rename.setRenameQueue(&renameQueue); 2381060SN/A iew.setRenameQueue(&renameQueue); 2391060SN/A iew.setIEWQueue(&iewQueue); 2401060SN/A commit.setIEWQueue(&iewQueue); 2411060SN/A commit.setRenameQueue(&renameQueue); 2421060SN/A 2432292SN/A commit.setIEWStage(&iew); 2442292SN/A rename.setIEWStage(&iew); 2452292SN/A rename.setCommitStage(&commit); 2462292SN/A 2478793Sgblack@eecs.umich.edu ThreadID active_threads; 2488793Sgblack@eecs.umich.edu if (FullSystem) { 2498793Sgblack@eecs.umich.edu active_threads = 1; 2508793Sgblack@eecs.umich.edu } else { 2518793Sgblack@eecs.umich.edu active_threads = params->workload.size(); 2522831Sksewell@umich.edu 2538793Sgblack@eecs.umich.edu if (active_threads > Impl::MaxThreads) { 2548793Sgblack@eecs.umich.edu panic("Workload Size too large. Increase the 'MaxThreads' " 2558793Sgblack@eecs.umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 2568793Sgblack@eecs.umich.edu "or edit your workload size."); 2578793Sgblack@eecs.umich.edu } 2582831Sksewell@umich.edu } 2592292SN/A 2602316SN/A //Make Sure That this a Valid Architeture 2612292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2622292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 26312109SRekai.GonzalezAlberquilla@arm.com assert(params->numPhysVecRegs >= numThreads * TheISA::NumVecRegs); 26413610Sgiacomo.gabrielli@arm.com assert(params->numPhysVecPredRegs >= numThreads * TheISA::NumVecPredRegs); 2659920Syasuko.eckert@amd.com assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs); 2662292SN/A 2672292SN/A rename.setScoreboard(&scoreboard); 2682292SN/A iew.setScoreboard(&scoreboard); 2692292SN/A 2701060SN/A // Setup the rename map for whichever stages need it. 2716221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2729384SAndreas.Sandberg@arm.com isa[tid] = params->isa[tid]; 27313601Sgiacomo.travaglini@arm.com assert(RenameMode<TheISA::ISA>::equalsInit(isa[tid], isa[0])); 2749384SAndreas.Sandberg@arm.com 2759919Ssteve.reinhardt@amd.com // Only Alpha has an FP zero register, so for other ISAs we 2769919Ssteve.reinhardt@amd.com // use an invalid FP register index to avoid special treatment 2779919Ssteve.reinhardt@amd.com // of any valid FP reg. 2789919Ssteve.reinhardt@amd.com RegIndex invalidFPReg = TheISA::NumFloatRegs + 1; 2799919Ssteve.reinhardt@amd.com RegIndex fpZeroReg = 2809919Ssteve.reinhardt@amd.com (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg; 2812292SN/A 2829919Ssteve.reinhardt@amd.com commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 28312109SRekai.GonzalezAlberquilla@arm.com &freeList, 28412109SRekai.GonzalezAlberquilla@arm.com vecMode); 2852292SN/A 2869919Ssteve.reinhardt@amd.com renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 28712109SRekai.GonzalezAlberquilla@arm.com &freeList, vecMode); 2882292SN/A } 2892292SN/A 2909919Ssteve.reinhardt@amd.com // Initialize rename map to assign physical registers to the 2919919Ssteve.reinhardt@amd.com // architectural registers for active threads only. 2929919Ssteve.reinhardt@amd.com for (ThreadID tid = 0; tid < active_threads; tid++) { 2939919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) { 2949919Ssteve.reinhardt@amd.com // Note that we can't use the rename() method because we don't 2959919Ssteve.reinhardt@amd.com // want special treatment for the zero register at this point 29612105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getIntReg(); 29712106SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg); 29812106SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg); 2999919Ssteve.reinhardt@amd.com } 3009919Ssteve.reinhardt@amd.com 3019919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) { 30212105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getFloatReg(); 30312106SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg); 30412106SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry( 30512106SRekai.GonzalezAlberquilla@arm.com RegId(FloatRegClass, ridx), phys_reg); 3069919Ssteve.reinhardt@amd.com } 3079920Syasuko.eckert@amd.com 30812109SRekai.GonzalezAlberquilla@arm.com /* Here we need two 'interfaces' the 'whole register' and the 30912109SRekai.GonzalezAlberquilla@arm.com * 'register element'. At any point only one of them will be 31012109SRekai.GonzalezAlberquilla@arm.com * active. */ 31112109SRekai.GonzalezAlberquilla@arm.com if (vecMode == Enums::Full) { 31212109SRekai.GonzalezAlberquilla@arm.com /* Initialize the full-vector interface */ 31312109SRekai.GonzalezAlberquilla@arm.com for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) { 31412109SRekai.GonzalezAlberquilla@arm.com RegId rid = RegId(VecRegClass, ridx); 31512109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = freeList.getVecReg(); 31612109SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(rid, phys_reg); 31712109SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry(rid, phys_reg); 31812109SRekai.GonzalezAlberquilla@arm.com } 31912109SRekai.GonzalezAlberquilla@arm.com } else { 32012109SRekai.GonzalezAlberquilla@arm.com /* Initialize the vector-element interface */ 32112109SRekai.GonzalezAlberquilla@arm.com for (RegIndex ridx = 0; ridx < TheISA::NumVecRegs; ++ridx) { 32212109SRekai.GonzalezAlberquilla@arm.com for (ElemIndex ldx = 0; ldx < TheISA::NumVecElemPerVecReg; 32312109SRekai.GonzalezAlberquilla@arm.com ++ldx) { 32412109SRekai.GonzalezAlberquilla@arm.com RegId lrid = RegId(VecElemClass, ridx, ldx); 32512109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_elem = freeList.getVecElem(); 32612109SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(lrid, phys_elem); 32712109SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry(lrid, phys_elem); 32812109SRekai.GonzalezAlberquilla@arm.com } 32912109SRekai.GonzalezAlberquilla@arm.com } 33012109SRekai.GonzalezAlberquilla@arm.com } 33112109SRekai.GonzalezAlberquilla@arm.com 33213610Sgiacomo.gabrielli@arm.com for (RegIndex ridx = 0; ridx < TheISA::NumVecPredRegs; ++ridx) { 33313610Sgiacomo.gabrielli@arm.com PhysRegIdPtr phys_reg = freeList.getVecPredReg(); 33413610Sgiacomo.gabrielli@arm.com renameMap[tid].setEntry(RegId(VecPredRegClass, ridx), phys_reg); 33513610Sgiacomo.gabrielli@arm.com commitRenameMap[tid].setEntry( 33613610Sgiacomo.gabrielli@arm.com RegId(VecPredRegClass, ridx), phys_reg); 33713610Sgiacomo.gabrielli@arm.com } 33813610Sgiacomo.gabrielli@arm.com 3399920Syasuko.eckert@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) { 34012105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getCCReg(); 34112106SRekai.GonzalezAlberquilla@arm.com renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg); 34212106SRekai.GonzalezAlberquilla@arm.com commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg); 3439920Syasuko.eckert@amd.com } 3449919Ssteve.reinhardt@amd.com } 3459919Ssteve.reinhardt@amd.com 3462292SN/A rename.setRenameMap(renameMap); 3472292SN/A commit.setRenameMap(commitRenameMap); 3481060SN/A rename.setFreeList(&freeList); 3492292SN/A 3501060SN/A // Setup the ROB for whichever stages need it. 3511060SN/A commit.setROB(&rob); 3522292SN/A 3539158Sandreas.hansson@arm.com lastActivatedCycle = 0; 3546221Snate@binkert.org#if 0 3553093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3566221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3576221Snate@binkert.org globalSeqNum[tid] = 1; 3586221Snate@binkert.org#endif 3593093Sksewell@umich.edu 3605595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3615595Sgblack@eecs.umich.edu 3625595Sgblack@eecs.umich.edu // Setup any thread state. 3635595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 3645595Sgblack@eecs.umich.edu 3656221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 3668793Sgblack@eecs.umich.edu if (FullSystem) { 3678793Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 3688793Sgblack@eecs.umich.edu assert(this->numThreads == 1); 3698793Sgblack@eecs.umich.edu this->thread[tid] = new Thread(this, 0, NULL); 3708793Sgblack@eecs.umich.edu } else { 3718793Sgblack@eecs.umich.edu if (tid < params->workload.size()) { 3728793Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 3738793Sgblack@eecs.umich.edu tid, this->thread[tid]); 3748793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3758793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3768793Sgblack@eecs.umich.edu tid, params->workload[tid]); 3775595Sgblack@eecs.umich.edu 3788793Sgblack@eecs.umich.edu //usedTids[tid] = true; 3798793Sgblack@eecs.umich.edu //threadMap[tid] = tid; 3808793Sgblack@eecs.umich.edu } else { 3818793Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 3828793Sgblack@eecs.umich.edu //when scheduling threads to CPU 3838793Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 3845595Sgblack@eecs.umich.edu 3858793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3868793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3878793Sgblack@eecs.umich.edu tid, dummy_proc); 3888793Sgblack@eecs.umich.edu //usedTids[tid] = false; 3898793Sgblack@eecs.umich.edu } 3905595Sgblack@eecs.umich.edu } 3915595Sgblack@eecs.umich.edu 3925595Sgblack@eecs.umich.edu ThreadContext *tc; 3935595Sgblack@eecs.umich.edu 3945595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 3955595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 3965595Sgblack@eecs.umich.edu 3975595Sgblack@eecs.umich.edu tc = o3_tc; 3985595Sgblack@eecs.umich.edu 3995595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 4005595Sgblack@eecs.umich.edu // CheckerThreadContext. 4015595Sgblack@eecs.umich.edu if (params->checker) { 4025595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 4035595Sgblack@eecs.umich.edu o3_tc, this->checker); 4045595Sgblack@eecs.umich.edu } 4055595Sgblack@eecs.umich.edu 4065595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 4075595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 4086221Snate@binkert.org o3_tc->thread = this->thread[tid]; 4095595Sgblack@eecs.umich.edu 41011627Smichael.lebeane@amd.com // Setup quiesce event. 41111627Smichael.lebeane@amd.com this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 41211627Smichael.lebeane@amd.com 4135595Sgblack@eecs.umich.edu // Give the thread the TC. 4146221Snate@binkert.org this->thread[tid]->tc = tc; 4155595Sgblack@eecs.umich.edu 4165595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4175595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4185595Sgblack@eecs.umich.edu } 4195595Sgblack@eecs.umich.edu 4208876Sandreas.hansson@arm.com // FullO3CPU always requires an interrupt controller. 42111150Smitch.hayenga@arm.com if (!params->switched_out && interrupts.empty()) { 4228876Sandreas.hansson@arm.com fatal("FullO3CPU %s has no interrupt controller.\n" 4238876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 4248876Sandreas.hansson@arm.com } 4258876Sandreas.hansson@arm.com 4266221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4276221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4281060SN/A} 4291060SN/A 4301060SN/Atemplate <class Impl> 4311755SN/AFullO3CPU<Impl>::~FullO3CPU() 4321060SN/A{ 4331060SN/A} 4341060SN/A 4351060SN/Atemplate <class Impl> 4361060SN/Avoid 43710023Smatt.horsnell@ARM.comFullO3CPU<Impl>::regProbePoints() 43810023Smatt.horsnell@ARM.com{ 43910464SAndreas.Sandberg@ARM.com BaseCPU::regProbePoints(); 44010464SAndreas.Sandberg@ARM.com 44110023Smatt.horsnell@ARM.com ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete"); 44210023Smatt.horsnell@ARM.com ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete"); 44310464SAndreas.Sandberg@ARM.com 44410023Smatt.horsnell@ARM.com fetch.regProbePoints(); 44511246Sradhika.jagtap@ARM.com rename.regProbePoints(); 44610023Smatt.horsnell@ARM.com iew.regProbePoints(); 44710023Smatt.horsnell@ARM.com commit.regProbePoints(); 44810023Smatt.horsnell@ARM.com} 44910023Smatt.horsnell@ARM.com 45010023Smatt.horsnell@ARM.comtemplate <class Impl> 45110023Smatt.horsnell@ARM.comvoid 4525595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4531062SN/A{ 4542733Sktlim@umich.edu BaseO3CPU::regStats(); 4552292SN/A 4562733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4572292SN/A timesIdled 4582292SN/A .name(name() + ".timesIdled") 4592292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4602292SN/A " unscheduled itself") 4612292SN/A .prereq(timesIdled); 4622292SN/A 4632292SN/A idleCycles 4642292SN/A .name(name() + ".idleCycles") 4652292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4662292SN/A "to idling") 4672292SN/A .prereq(idleCycles); 4682292SN/A 4698627SAli.Saidi@ARM.com quiesceCycles 4708627SAli.Saidi@ARM.com .name(name() + ".quiesceCycles") 4718627SAli.Saidi@ARM.com .desc("Total number of cycles that CPU has spent quiesced or waiting " 4728627SAli.Saidi@ARM.com "for an interrupt") 4738627SAli.Saidi@ARM.com .prereq(quiesceCycles); 4748627SAli.Saidi@ARM.com 4752292SN/A // Number of Instructions simulated 4762292SN/A // -------------------------------- 4772292SN/A // Should probably be in Base CPU but need templated 4782292SN/A // MaxThreads so put in here instead 4792292SN/A committedInsts 4802292SN/A .init(numThreads) 4812292SN/A .name(name() + ".committedInsts") 48210225Snilay@cs.wisc.edu .desc("Number of Instructions Simulated") 48310225Snilay@cs.wisc.edu .flags(Stats::total); 4842292SN/A 4858834Satgutier@umich.edu committedOps 4868834Satgutier@umich.edu .init(numThreads) 4878834Satgutier@umich.edu .name(name() + ".committedOps") 48810225Snilay@cs.wisc.edu .desc("Number of Ops (including micro ops) Simulated") 48910225Snilay@cs.wisc.edu .flags(Stats::total); 4902292SN/A 4912292SN/A cpi 4922292SN/A .name(name() + ".cpi") 4932292SN/A .desc("CPI: Cycles Per Instruction") 4942292SN/A .precision(6); 4954392Sktlim@umich.edu cpi = numCycles / committedInsts; 4962292SN/A 4972292SN/A totalCpi 4982292SN/A .name(name() + ".cpi_total") 4992292SN/A .desc("CPI: Total CPI of All Threads") 5002292SN/A .precision(6); 50110225Snilay@cs.wisc.edu totalCpi = numCycles / sum(committedInsts); 5022292SN/A 5032292SN/A ipc 5042292SN/A .name(name() + ".ipc") 5052292SN/A .desc("IPC: Instructions Per Cycle") 5062292SN/A .precision(6); 5074392Sktlim@umich.edu ipc = committedInsts / numCycles; 5082292SN/A 5092292SN/A totalIpc 5102292SN/A .name(name() + ".ipc_total") 5112292SN/A .desc("IPC: Total IPC of All Threads") 5122292SN/A .precision(6); 51310225Snilay@cs.wisc.edu totalIpc = sum(committedInsts) / numCycles; 5142292SN/A 5155595Sgblack@eecs.umich.edu this->fetch.regStats(); 5165595Sgblack@eecs.umich.edu this->decode.regStats(); 5175595Sgblack@eecs.umich.edu this->rename.regStats(); 5185595Sgblack@eecs.umich.edu this->iew.regStats(); 5195595Sgblack@eecs.umich.edu this->commit.regStats(); 5207897Shestness@cs.utexas.edu this->rob.regStats(); 5217897Shestness@cs.utexas.edu 5227897Shestness@cs.utexas.edu intRegfileReads 5237897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 5247897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 5257897Shestness@cs.utexas.edu .prereq(intRegfileReads); 5267897Shestness@cs.utexas.edu 5277897Shestness@cs.utexas.edu intRegfileWrites 5287897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 5297897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 5307897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 5317897Shestness@cs.utexas.edu 5327897Shestness@cs.utexas.edu fpRegfileReads 5337897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 5347897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 5357897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 5367897Shestness@cs.utexas.edu 5377897Shestness@cs.utexas.edu fpRegfileWrites 5387897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 5397897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 5407897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 5417897Shestness@cs.utexas.edu 54212109SRekai.GonzalezAlberquilla@arm.com vecRegfileReads 54312109SRekai.GonzalezAlberquilla@arm.com .name(name() + ".vec_regfile_reads") 54412109SRekai.GonzalezAlberquilla@arm.com .desc("number of vector regfile reads") 54512109SRekai.GonzalezAlberquilla@arm.com .prereq(vecRegfileReads); 54612109SRekai.GonzalezAlberquilla@arm.com 54712109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites 54812109SRekai.GonzalezAlberquilla@arm.com .name(name() + ".vec_regfile_writes") 54912109SRekai.GonzalezAlberquilla@arm.com .desc("number of vector regfile writes") 55012109SRekai.GonzalezAlberquilla@arm.com .prereq(vecRegfileWrites); 55112109SRekai.GonzalezAlberquilla@arm.com 55213610Sgiacomo.gabrielli@arm.com vecPredRegfileReads 55313610Sgiacomo.gabrielli@arm.com .name(name() + ".pred_regfile_reads") 55413610Sgiacomo.gabrielli@arm.com .desc("number of predicate regfile reads") 55513610Sgiacomo.gabrielli@arm.com .prereq(vecPredRegfileReads); 55613610Sgiacomo.gabrielli@arm.com 55713610Sgiacomo.gabrielli@arm.com vecPredRegfileWrites 55813610Sgiacomo.gabrielli@arm.com .name(name() + ".pred_regfile_writes") 55913610Sgiacomo.gabrielli@arm.com .desc("number of predicate regfile writes") 56013610Sgiacomo.gabrielli@arm.com .prereq(vecPredRegfileWrites); 56113610Sgiacomo.gabrielli@arm.com 5629920Syasuko.eckert@amd.com ccRegfileReads 5639920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_reads") 5649920Syasuko.eckert@amd.com .desc("number of cc regfile reads") 5659920Syasuko.eckert@amd.com .prereq(ccRegfileReads); 5669920Syasuko.eckert@amd.com 5679920Syasuko.eckert@amd.com ccRegfileWrites 5689920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_writes") 5699920Syasuko.eckert@amd.com .desc("number of cc regfile writes") 5709920Syasuko.eckert@amd.com .prereq(ccRegfileWrites); 5719920Syasuko.eckert@amd.com 5727897Shestness@cs.utexas.edu miscRegfileReads 5737897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5747897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5757897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5767897Shestness@cs.utexas.edu 5777897Shestness@cs.utexas.edu miscRegfileWrites 5787897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5797897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5807897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5811062SN/A} 5821062SN/A 5831062SN/Atemplate <class Impl> 5841062SN/Avoid 5851755SN/AFullO3CPU<Impl>::tick() 5861060SN/A{ 5872733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5889444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 58910913Sandreas.sandberg@arm.com assert(drainState() != DrainState::Drained); 5901060SN/A 5912292SN/A ++numCycles; 59212284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_ON); 5932292SN/A 5942325SN/A// activity = false; 5952292SN/A 5962292SN/A //Tick each of the stages 5971060SN/A fetch.tick(); 5981060SN/A 5991060SN/A decode.tick(); 6001060SN/A 6011060SN/A rename.tick(); 6021060SN/A 6031060SN/A iew.tick(); 6041060SN/A 6051060SN/A commit.tick(); 6061060SN/A 6072292SN/A // Now advance the time buffers 6081060SN/A timeBuffer.advance(); 6091060SN/A 6101060SN/A fetchQueue.advance(); 6111060SN/A decodeQueue.advance(); 6121060SN/A renameQueue.advance(); 6131060SN/A iewQueue.advance(); 6141060SN/A 6152325SN/A activityRec.advance(); 6162292SN/A 6172292SN/A if (removeInstsThisCycle) { 6182292SN/A cleanUpRemovedInsts(); 6192292SN/A } 6202292SN/A 6212325SN/A if (!tickEvent.scheduled()) { 6229444SAndreas.Sandberg@ARM.com if (_status == SwitchedOut) { 6233226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 6242325SN/A // increment stat 6259179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 6263221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 6273226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 6289179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 6292325SN/A timesIdled++; 6302325SN/A } else { 6319180Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(Cycles(1))); 6323226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 6332325SN/A } 6342292SN/A } 6352292SN/A 6368793Sgblack@eecs.umich.edu if (!FullSystem) 6378793Sgblack@eecs.umich.edu updateThreadPriority(); 6389444SAndreas.Sandberg@ARM.com 6399444SAndreas.Sandberg@ARM.com tryDrain(); 6401060SN/A} 6411060SN/A 6421060SN/Atemplate <class Impl> 6431060SN/Avoid 6441755SN/AFullO3CPU<Impl>::init() 6451060SN/A{ 6465714Shsul@eecs.umich.edu BaseCPU::init(); 6471060SN/A 6488921Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 6499382SAli.Saidi@ARM.com // Set noSquashFromTC so that the CPU doesn't squash when initially 6508921Sandreas.hansson@arm.com // setting up registers. 6519382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = true; 6528921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 6538921Sandreas.hansson@arm.com thread[tid]->initMemProxies(thread[tid]->getTC()); 6548921Sandreas.hansson@arm.com } 6552292SN/A 6569433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 6578793Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 6588793Sgblack@eecs.umich.edu ThreadContext *src_tc = threadContexts[tid]; 6598793Sgblack@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 6608793Sgblack@eecs.umich.edu } 6616034Ssteve.reinhardt@amd.com } 6622292SN/A 6639382SAli.Saidi@ARM.com // Clear noSquashFromTC. 6646221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6659382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6662292SN/A 6679427SAndreas.Sandberg@ARM.com commit.setThreads(thread); 6689427SAndreas.Sandberg@ARM.com} 6692292SN/A 6709427SAndreas.Sandberg@ARM.comtemplate <class Impl> 6719427SAndreas.Sandberg@ARM.comvoid 6729427SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::startup() 6739427SAndreas.Sandberg@ARM.com{ 6749992Snilay@cs.wisc.edu BaseCPU::startup(); 6759461Snilay@cs.wisc.edu for (int tid = 0; tid < numThreads; ++tid) 6769461Snilay@cs.wisc.edu isa[tid]->startup(threadContexts[tid]); 6779461Snilay@cs.wisc.edu 6789427SAndreas.Sandberg@ARM.com fetch.startupStage(); 6799444SAndreas.Sandberg@ARM.com decode.startupStage(); 6809427SAndreas.Sandberg@ARM.com iew.startupStage(); 6819427SAndreas.Sandberg@ARM.com rename.startupStage(); 6829427SAndreas.Sandberg@ARM.com commit.startupStage(); 6832292SN/A} 6842292SN/A 6852292SN/Atemplate <class Impl> 6862292SN/Avoid 6876221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 6882875Sksewell@umich.edu{ 6896221Snate@binkert.org list<ThreadID>::iterator isActive = 6905314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6912875Sksewell@umich.edu 6923226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6939444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 6943226Sktlim@umich.edu 6952875Sksewell@umich.edu if (isActive == activeThreads.end()) { 6962875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6972875Sksewell@umich.edu tid); 6982875Sksewell@umich.edu 6992875Sksewell@umich.edu activeThreads.push_back(tid); 7002875Sksewell@umich.edu } 7012875Sksewell@umich.edu} 7022875Sksewell@umich.edu 7032875Sksewell@umich.edutemplate <class Impl> 7042875Sksewell@umich.eduvoid 7056221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 7062875Sksewell@umich.edu{ 7072875Sksewell@umich.edu //Remove From Active List, if Active 7086221Snate@binkert.org list<ThreadID>::iterator thread_it = 7095314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 7102875Sksewell@umich.edu 7113226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 7129444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 7133226Sktlim@umich.edu 7142875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 7152875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 7162875Sksewell@umich.edu tid); 7172875Sksewell@umich.edu activeThreads.erase(thread_it); 7182875Sksewell@umich.edu } 71910331Smitch.hayenga@arm.com 72010331Smitch.hayenga@arm.com fetch.deactivateThread(tid); 72110331Smitch.hayenga@arm.com commit.deactivateThread(tid); 7222875Sksewell@umich.edu} 7232875Sksewell@umich.edu 7242875Sksewell@umich.edutemplate <class Impl> 7256221Snate@binkert.orgCounter 7268834Satgutier@umich.eduFullO3CPU<Impl>::totalInsts() const 7276221Snate@binkert.org{ 7286221Snate@binkert.org Counter total(0); 7296221Snate@binkert.org 7306221Snate@binkert.org ThreadID size = thread.size(); 7316221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 7326221Snate@binkert.org total += thread[i]->numInst; 7336221Snate@binkert.org 7346221Snate@binkert.org return total; 7356221Snate@binkert.org} 7366221Snate@binkert.org 7376221Snate@binkert.orgtemplate <class Impl> 7388834Satgutier@umich.eduCounter 7398834Satgutier@umich.eduFullO3CPU<Impl>::totalOps() const 7408834Satgutier@umich.edu{ 7418834Satgutier@umich.edu Counter total(0); 7428834Satgutier@umich.edu 7438834Satgutier@umich.edu ThreadID size = thread.size(); 7448834Satgutier@umich.edu for (ThreadID i = 0; i < size; i++) 7458834Satgutier@umich.edu total += thread[i]->numOp; 7468834Satgutier@umich.edu 7478834Satgutier@umich.edu return total; 7488834Satgutier@umich.edu} 7498834Satgutier@umich.edu 7508834Satgutier@umich.edutemplate <class Impl> 7512875Sksewell@umich.eduvoid 75210407Smitch.hayenga@arm.comFullO3CPU<Impl>::activateContext(ThreadID tid) 7532875Sksewell@umich.edu{ 7549444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 7559444SAndreas.Sandberg@ARM.com 7562875Sksewell@umich.edu // Needs to set each stage to running as well. 75710407Smitch.hayenga@arm.com activateThread(tid); 7582875Sksewell@umich.edu 7599444SAndreas.Sandberg@ARM.com // We don't want to wake the CPU if it is drained. In that case, 7609444SAndreas.Sandberg@ARM.com // we just want to flag the thread as active and schedule the tick 7619444SAndreas.Sandberg@ARM.com // event from drainResume() instead. 76210913Sandreas.sandberg@arm.com if (drainState() == DrainState::Drained) 7639444SAndreas.Sandberg@ARM.com return; 7649444SAndreas.Sandberg@ARM.com 7659158Sandreas.hansson@arm.com // If we are time 0 or if the last activation time is in the past, 7669158Sandreas.hansson@arm.com // schedule the next tick and wake up the fetch unit 7679158Sandreas.hansson@arm.com if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) { 76810407Smitch.hayenga@arm.com scheduleTickEvent(Cycles(0)); 7692875Sksewell@umich.edu 7702875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 7712875Sksewell@umich.edu // deschedule itself. 7722875Sksewell@umich.edu activityRec.activity(); 7732875Sksewell@umich.edu fetch.wakeFromQuiesce(); 7742875Sksewell@umich.edu 7759180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 7769180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 7779179Sandreas.hansson@arm.com if (cycles != 0) 7789179Sandreas.hansson@arm.com --cycles; 7799179Sandreas.hansson@arm.com quiesceCycles += cycles; 7808627SAli.Saidi@ARM.com 7817823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 7822875Sksewell@umich.edu 7832875Sksewell@umich.edu _status = Running; 78411526Sdavid.guillen@arm.com 78511526Sdavid.guillen@arm.com BaseCPU::activateContext(tid); 7862875Sksewell@umich.edu } 7872875Sksewell@umich.edu} 7882875Sksewell@umich.edu 7892875Sksewell@umich.edutemplate <class Impl> 79010407Smitch.hayenga@arm.comvoid 7916221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 7922875Sksewell@umich.edu{ 7932875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 7949444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 79510408Smitch.hayenga@arm.com 79610408Smitch.hayenga@arm.com deactivateThread(tid); 79710407Smitch.hayenga@arm.com 7983221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 79910683Salexandru.dutu@amd.com if (activeThreads.size() == 0) { 8002910Sksewell@umich.edu unscheduleTickEvent(); 80110683Salexandru.dutu@amd.com lastRunningCycle = curCycle(); 80210683Salexandru.dutu@amd.com _status = Idle; 80310683Salexandru.dutu@amd.com } 8048627SAli.Saidi@ARM.com 8058627SAli.Saidi@ARM.com DPRINTF(Quiesce, "Suspending Context\n"); 80611526Sdavid.guillen@arm.com 80711526Sdavid.guillen@arm.com BaseCPU::suspendContext(tid); 8082875Sksewell@umich.edu} 8092875Sksewell@umich.edu 8102875Sksewell@umich.edutemplate <class Impl> 8112875Sksewell@umich.eduvoid 8126221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 8132875Sksewell@umich.edu{ 8142910Sksewell@umich.edu //For now, this is the same as deallocate 81513641Sqtt2@cornell.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating\n", tid); 8169444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 81710408Smitch.hayenga@arm.com 81810408Smitch.hayenga@arm.com deactivateThread(tid); 81910408Smitch.hayenga@arm.com removeThread(tid); 82012284Sjose.marinho@arm.com 82112284Sjose.marinho@arm.com updateCycleCounters(BaseCPU::CPU_STATE_SLEEP); 8222875Sksewell@umich.edu} 8232875Sksewell@umich.edu 8242875Sksewell@umich.edutemplate <class Impl> 8252875Sksewell@umich.eduvoid 8266221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 8272292SN/A{ 8282847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 8292292SN/A // Will change now that the PC and thread state is internal to the CPU 8302683Sktlim@umich.edu // and not in the ThreadContext. 8318793Sgblack@eecs.umich.edu ThreadContext *src_tc; 8328793Sgblack@eecs.umich.edu if (FullSystem) 8338793Sgblack@eecs.umich.edu src_tc = system->threadContexts[tid]; 8348793Sgblack@eecs.umich.edu else 8358793Sgblack@eecs.umich.edu src_tc = tcBase(tid); 8362292SN/A 8372292SN/A //Bind Int Regs to Rename Map 83812104Snathanael.premillieu@arm.com 83912106SRekai.GonzalezAlberquilla@arm.com for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs; 84012106SRekai.GonzalezAlberquilla@arm.com reg_id.index()++) { 84112105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getIntReg(); 84212104Snathanael.premillieu@arm.com renameMap[tid].setEntry(reg_id, phys_reg); 8432292SN/A scoreboard.setReg(phys_reg); 8442292SN/A } 8452292SN/A 8462292SN/A //Bind Float Regs to Rename Map 84712106SRekai.GonzalezAlberquilla@arm.com for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs; 84812106SRekai.GonzalezAlberquilla@arm.com reg_id.index()++) { 84912105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getFloatReg(); 85012104Snathanael.premillieu@arm.com renameMap[tid].setEntry(reg_id, phys_reg); 8512292SN/A scoreboard.setReg(phys_reg); 8522292SN/A } 8532292SN/A 8549920Syasuko.eckert@amd.com //Bind condition-code Regs to Rename Map 85512106SRekai.GonzalezAlberquilla@arm.com for (RegId reg_id(CCRegClass, 0); reg_id.index() < TheISA::NumCCRegs; 85612106SRekai.GonzalezAlberquilla@arm.com reg_id.index()++) { 85712105Snathanael.premillieu@arm.com PhysRegIdPtr phys_reg = freeList.getCCReg(); 85812104Snathanael.premillieu@arm.com renameMap[tid].setEntry(reg_id, phys_reg); 8599920Syasuko.eckert@amd.com scoreboard.setReg(phys_reg); 8609920Syasuko.eckert@amd.com } 8619920Syasuko.eckert@amd.com 8622292SN/A //Copy Thread Data Into RegFile 8632847Sksewell@umich.edu //this->copyFromTC(tid); 8642292SN/A 8652847Sksewell@umich.edu //Set PC/NPC/NNPC 8667720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 8672292SN/A 8682680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 8692292SN/A 87010407Smitch.hayenga@arm.com activateContext(tid); 8712292SN/A 8722292SN/A //Reset ROB/IQ/LSQ Entries 8732292SN/A commit.rob->resetEntries(); 8742292SN/A} 8752292SN/A 8762292SN/Atemplate <class Impl> 8772292SN/Avoid 8786221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 8792292SN/A{ 8802877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 8812847Sksewell@umich.edu 8822847Sksewell@umich.edu // Copy Thread Data From RegFile 8832847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 8845364Sksewell@umich.edu // this->copyToTC(tid); 8855364Sksewell@umich.edu 8865364Sksewell@umich.edu 8875364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 8885364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 8895364Sksewell@umich.edu // in SMT workloads. 8902847Sksewell@umich.edu 89113641Sqtt2@cornell.edu // clear all thread-specific states in each stage of the pipeline 89213641Sqtt2@cornell.edu // since this thread is going to be completely removed from the CPU 89313641Sqtt2@cornell.edu commit.clearStates(tid); 89413641Sqtt2@cornell.edu fetch.clearStates(tid); 89513641Sqtt2@cornell.edu decode.clearStates(tid); 89613641Sqtt2@cornell.edu rename.clearStates(tid); 89713641Sqtt2@cornell.edu iew.clearStates(tid); 8982292SN/A 89913641Sqtt2@cornell.edu // at this step, all instructions in the pipeline should be already 90013641Sqtt2@cornell.edu // either committed successfully or squashed. All thread-specific 90113641Sqtt2@cornell.edu // queues in the pipeline must be empty. 9025362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 9032292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 90413641Sqtt2@cornell.edu assert(commit.rob->isEmpty(tid)); 9052292SN/A 9062847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 9073229Sktlim@umich.edu 9083229Sktlim@umich.edu // Commented out for now. This should be possible to do by 9093229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 9103229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 9113229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 9123229Sktlim@umich.edu/* 9132292SN/A if (activeThreads.size() >= 1) { 9142292SN/A commit.rob->resetEntries(); 9152292SN/A iew.resetEntries(); 9162292SN/A } 9173229Sktlim@umich.edu*/ 9182292SN/A} 9192292SN/A 9204192Sktlim@umich.edutemplate <class Impl> 9215595Sgblack@eecs.umich.eduFault 9226221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 9235702Ssaidi@eecs.umich.edu{ 9245702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9255702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 9265702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 9275702Ssaidi@eecs.umich.edu 9285702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 9295702Ssaidi@eecs.umich.edu 9305702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 9315702Ssaidi@eecs.umich.edu#endif 9325702Ssaidi@eecs.umich.edu return NoFault; 9335702Ssaidi@eecs.umich.edu} 9345702Ssaidi@eecs.umich.edu 9355702Ssaidi@eecs.umich.edutemplate <class Impl> 9365702Ssaidi@eecs.umich.edubool 9376221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 9385702Ssaidi@eecs.umich.edu{ 9395702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9405702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 9415702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 9425702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 9435702Ssaidi@eecs.umich.edu 9445702Ssaidi@eecs.umich.edu switch (palFunc) { 9455702Ssaidi@eecs.umich.edu case PAL::halt: 9465702Ssaidi@eecs.umich.edu halt(); 9475702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 9485702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 9495702Ssaidi@eecs.umich.edu break; 9505702Ssaidi@eecs.umich.edu 9515702Ssaidi@eecs.umich.edu case PAL::bpt: 9525702Ssaidi@eecs.umich.edu case PAL::bugchk: 9535702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 9545702Ssaidi@eecs.umich.edu return false; 9555702Ssaidi@eecs.umich.edu break; 9565702Ssaidi@eecs.umich.edu } 9575702Ssaidi@eecs.umich.edu#endif 9585702Ssaidi@eecs.umich.edu return true; 9595702Ssaidi@eecs.umich.edu} 9605702Ssaidi@eecs.umich.edu 9615702Ssaidi@eecs.umich.edutemplate <class Impl> 96213601Sgiacomo.travaglini@arm.comvoid 96313601Sgiacomo.travaglini@arm.comFullO3CPU<Impl>::switchRenameMode(ThreadID tid, UnifiedFreeList* freelist) 96413601Sgiacomo.travaglini@arm.com{ 96513601Sgiacomo.travaglini@arm.com auto pc = this->pcState(tid); 96613601Sgiacomo.travaglini@arm.com 96713601Sgiacomo.travaglini@arm.com // new_mode is the new vector renaming mode 96813601Sgiacomo.travaglini@arm.com auto new_mode = RenameMode<TheISA::ISA>::mode(pc); 96913601Sgiacomo.travaglini@arm.com 97013601Sgiacomo.travaglini@arm.com // We update vecMode only if there has been a change 97113601Sgiacomo.travaglini@arm.com if (new_mode != vecMode) { 97213601Sgiacomo.travaglini@arm.com vecMode = new_mode; 97313601Sgiacomo.travaglini@arm.com 97413601Sgiacomo.travaglini@arm.com renameMap[tid].switchMode(vecMode); 97513601Sgiacomo.travaglini@arm.com commitRenameMap[tid].switchMode(vecMode); 97613601Sgiacomo.travaglini@arm.com renameMap[tid].switchFreeList(freelist); 97713601Sgiacomo.travaglini@arm.com } 97813601Sgiacomo.travaglini@arm.com} 97913601Sgiacomo.travaglini@arm.com 98013601Sgiacomo.travaglini@arm.comtemplate <class Impl> 9815702Ssaidi@eecs.umich.eduFault 9825595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 9835595Sgblack@eecs.umich.edu{ 9845595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 98511150Smitch.hayenga@arm.com return this->interrupts[0]->getInterrupt(this->threadContexts[0]); 9865595Sgblack@eecs.umich.edu} 9875595Sgblack@eecs.umich.edu 9885595Sgblack@eecs.umich.edutemplate <class Impl> 9895595Sgblack@eecs.umich.eduvoid 99010379Sandreas.hansson@arm.comFullO3CPU<Impl>::processInterrupts(const Fault &interrupt) 9915595Sgblack@eecs.umich.edu{ 9925595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 9935595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 9945595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 9955595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 9965595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 9975595Sgblack@eecs.umich.edu 9985595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 99911150Smitch.hayenga@arm.com this->interrupts[0]->updateIntrInfo(this->threadContexts[0]); 10005595Sgblack@eecs.umich.edu 10015595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 100210417Sandreas.hansson@arm.com this->trap(interrupt, 0, nullptr); 10035595Sgblack@eecs.umich.edu} 10045595Sgblack@eecs.umich.edu 10051060SN/Atemplate <class Impl> 10062852Sktlim@umich.eduvoid 100710417Sandreas.hansson@arm.comFullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid, 100810417Sandreas.hansson@arm.com const StaticInstPtr &inst) 10095595Sgblack@eecs.umich.edu{ 10105595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 10117684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 10125595Sgblack@eecs.umich.edu} 10135595Sgblack@eecs.umich.edu 10145595Sgblack@eecs.umich.edutemplate <class Impl> 10155595Sgblack@eecs.umich.eduvoid 101611877Sbrandon.potter@amd.comFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid, Fault *fault) 10175595Sgblack@eecs.umich.edu{ 10185595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 10195595Sgblack@eecs.umich.edu 10205595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 10215595Sgblack@eecs.umich.edu 10225595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 10235595Sgblack@eecs.umich.edu // instruction. 10245595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 10255595Sgblack@eecs.umich.edu 10265595Sgblack@eecs.umich.edu // Execute the actual syscall. 102711877Sbrandon.potter@amd.com this->thread[tid]->syscall(callnum, fault); 10285595Sgblack@eecs.umich.edu 10295595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 10305595Sgblack@eecs.umich.edu // incrementing it. 10315595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 10325595Sgblack@eecs.umich.edu} 10335595Sgblack@eecs.umich.edu 10345595Sgblack@eecs.umich.edutemplate <class Impl> 10355595Sgblack@eecs.umich.eduvoid 103610905Sandreas.sandberg@arm.comFullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const 10372864Sktlim@umich.edu{ 103810905Sandreas.sandberg@arm.com thread[tid]->serialize(cp); 10392864Sktlim@umich.edu} 10402864Sktlim@umich.edu 10412864Sktlim@umich.edutemplate <class Impl> 10422864Sktlim@umich.eduvoid 104310905Sandreas.sandberg@arm.comFullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid) 10442864Sktlim@umich.edu{ 104510905Sandreas.sandberg@arm.com thread[tid]->unserialize(cp); 10462864Sktlim@umich.edu} 10472864Sktlim@umich.edu 10482864Sktlim@umich.edutemplate <class Impl> 104910913Sandreas.sandberg@arm.comDrainState 105010913Sandreas.sandberg@arm.comFullO3CPU<Impl>::drain() 10511060SN/A{ 105212276Sanouk.vanlaer@arm.com // Deschedule any power gating event (if any) 105312276Sanouk.vanlaer@arm.com deschedulePowerGatingEvent(); 105412276Sanouk.vanlaer@arm.com 10559444SAndreas.Sandberg@ARM.com // If the CPU isn't doing anything, then return immediately. 105610913Sandreas.sandberg@arm.com if (switchedOut()) 105710913Sandreas.sandberg@arm.com return DrainState::Drained; 10583512Sktlim@umich.edu 10599444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Draining...\n"); 10603512Sktlim@umich.edu 10619444SAndreas.Sandberg@ARM.com // We only need to signal a drain to the commit stage as this 10629444SAndreas.Sandberg@ARM.com // initiates squashing controls the draining. Once the commit 10639444SAndreas.Sandberg@ARM.com // stage commits an instruction where it is safe to stop, it'll 10649444SAndreas.Sandberg@ARM.com // squash the rest of the instructions in the pipeline and force 10659444SAndreas.Sandberg@ARM.com // the fetch stage to stall. The pipeline will be drained once all 10669444SAndreas.Sandberg@ARM.com // in-flight instructions have retired. 10672843Sktlim@umich.edu commit.drain(); 10682325SN/A 10692325SN/A // Wake the CPU and record activity so everything can drain out if 10702863Sktlim@umich.edu // the CPU was not able to immediately drain. 10719444SAndreas.Sandberg@ARM.com if (!isDrained()) { 107212143Sanouk.vanlaer@arm.com // If a thread is suspended, wake it up so it can be drained 107312143Sanouk.vanlaer@arm.com for (auto t : threadContexts) { 107412143Sanouk.vanlaer@arm.com if (t->status() == ThreadContext::Suspended){ 107512143Sanouk.vanlaer@arm.com DPRINTF(Drain, "Currently suspended so activate %i \n", 107612143Sanouk.vanlaer@arm.com t->threadId()); 107712143Sanouk.vanlaer@arm.com t->activate(); 107812143Sanouk.vanlaer@arm.com // As the thread is now active, change the power state as well 107912143Sanouk.vanlaer@arm.com activateContext(t->threadId()); 108012143Sanouk.vanlaer@arm.com } 108112143Sanouk.vanlaer@arm.com } 108212143Sanouk.vanlaer@arm.com 10832863Sktlim@umich.edu wakeCPU(); 10842863Sktlim@umich.edu activityRec.activity(); 10852852Sktlim@umich.edu 10869152Satgutier@umich.edu DPRINTF(Drain, "CPU not drained\n"); 10879152Satgutier@umich.edu 108810913Sandreas.sandberg@arm.com return DrainState::Draining; 10892863Sktlim@umich.edu } else { 10909444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU is already drained\n"); 10919444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 10929444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 10939444SAndreas.Sandberg@ARM.com 10949444SAndreas.Sandberg@ARM.com // Flush out any old data from the time buffers. In 10959444SAndreas.Sandberg@ARM.com // particular, there might be some data in flight from the 10969444SAndreas.Sandberg@ARM.com // fetch stage that isn't visible in any of the CPU buffers we 10979444SAndreas.Sandberg@ARM.com // test in isDrained(). 10989444SAndreas.Sandberg@ARM.com for (int i = 0; i < timeBuffer.getSize(); ++i) { 10999444SAndreas.Sandberg@ARM.com timeBuffer.advance(); 11009444SAndreas.Sandberg@ARM.com fetchQueue.advance(); 11019444SAndreas.Sandberg@ARM.com decodeQueue.advance(); 11029444SAndreas.Sandberg@ARM.com renameQueue.advance(); 11039444SAndreas.Sandberg@ARM.com iewQueue.advance(); 11049444SAndreas.Sandberg@ARM.com } 11059444SAndreas.Sandberg@ARM.com 11069444SAndreas.Sandberg@ARM.com drainSanityCheck(); 110710913Sandreas.sandberg@arm.com return DrainState::Drained; 11082863Sktlim@umich.edu } 11092316SN/A} 11102310SN/A 11112316SN/Atemplate <class Impl> 11129444SAndreas.Sandberg@ARM.combool 11139444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::tryDrain() 11149444SAndreas.Sandberg@ARM.com{ 111510913Sandreas.sandberg@arm.com if (drainState() != DrainState::Draining || !isDrained()) 11169444SAndreas.Sandberg@ARM.com return false; 11179444SAndreas.Sandberg@ARM.com 11189444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 11199444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 11209444SAndreas.Sandberg@ARM.com 11219444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 112210913Sandreas.sandberg@arm.com signalDrainDone(); 11239444SAndreas.Sandberg@ARM.com 11249444SAndreas.Sandberg@ARM.com return true; 11259444SAndreas.Sandberg@ARM.com} 11269444SAndreas.Sandberg@ARM.com 11279444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11289444SAndreas.Sandberg@ARM.comvoid 11299444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::drainSanityCheck() const 11309444SAndreas.Sandberg@ARM.com{ 11319444SAndreas.Sandberg@ARM.com assert(isDrained()); 11329444SAndreas.Sandberg@ARM.com fetch.drainSanityCheck(); 11339444SAndreas.Sandberg@ARM.com decode.drainSanityCheck(); 11349444SAndreas.Sandberg@ARM.com rename.drainSanityCheck(); 11359444SAndreas.Sandberg@ARM.com iew.drainSanityCheck(); 11369444SAndreas.Sandberg@ARM.com commit.drainSanityCheck(); 11379444SAndreas.Sandberg@ARM.com} 11389444SAndreas.Sandberg@ARM.com 11399444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11409444SAndreas.Sandberg@ARM.combool 11419444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::isDrained() const 11429444SAndreas.Sandberg@ARM.com{ 11439444SAndreas.Sandberg@ARM.com bool drained(true); 11449444SAndreas.Sandberg@ARM.com 11459444SAndreas.Sandberg@ARM.com if (!instList.empty() || !removeList.empty()) { 11469444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Main CPU structures not drained.\n"); 11479444SAndreas.Sandberg@ARM.com drained = false; 11489444SAndreas.Sandberg@ARM.com } 11499444SAndreas.Sandberg@ARM.com 11509444SAndreas.Sandberg@ARM.com if (!fetch.isDrained()) { 11519444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Fetch not drained.\n"); 11529444SAndreas.Sandberg@ARM.com drained = false; 11539444SAndreas.Sandberg@ARM.com } 11549444SAndreas.Sandberg@ARM.com 11559444SAndreas.Sandberg@ARM.com if (!decode.isDrained()) { 11569444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Decode not drained.\n"); 11579444SAndreas.Sandberg@ARM.com drained = false; 11589444SAndreas.Sandberg@ARM.com } 11599444SAndreas.Sandberg@ARM.com 11609444SAndreas.Sandberg@ARM.com if (!rename.isDrained()) { 11619444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Rename not drained.\n"); 11629444SAndreas.Sandberg@ARM.com drained = false; 11639444SAndreas.Sandberg@ARM.com } 11649444SAndreas.Sandberg@ARM.com 11659444SAndreas.Sandberg@ARM.com if (!iew.isDrained()) { 11669444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "IEW not drained.\n"); 11679444SAndreas.Sandberg@ARM.com drained = false; 11689444SAndreas.Sandberg@ARM.com } 11699444SAndreas.Sandberg@ARM.com 11709444SAndreas.Sandberg@ARM.com if (!commit.isDrained()) { 11719444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Commit not drained.\n"); 11729444SAndreas.Sandberg@ARM.com drained = false; 11739444SAndreas.Sandberg@ARM.com } 11749444SAndreas.Sandberg@ARM.com 11759444SAndreas.Sandberg@ARM.com return drained; 11769444SAndreas.Sandberg@ARM.com} 11779444SAndreas.Sandberg@ARM.com 11789444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11799444SAndreas.Sandberg@ARM.comvoid 11809444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::commitDrained(ThreadID tid) 11819444SAndreas.Sandberg@ARM.com{ 11829444SAndreas.Sandberg@ARM.com fetch.drainStall(tid); 11839444SAndreas.Sandberg@ARM.com} 11849444SAndreas.Sandberg@ARM.com 11859444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11862316SN/Avoid 11879342SAndreas.Sandberg@arm.comFullO3CPU<Impl>::drainResume() 11882316SN/A{ 11899444SAndreas.Sandberg@ARM.com if (switchedOut()) 11909444SAndreas.Sandberg@ARM.com return; 11912316SN/A 11929444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Resuming...\n"); 11939523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 11943319Shsul@eecs.umich.edu 11959444SAndreas.Sandberg@ARM.com fetch.drainResume(); 11969444SAndreas.Sandberg@ARM.com commit.drainResume(); 11972316SN/A 11989444SAndreas.Sandberg@ARM.com _status = Idle; 11999444SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < thread.size(); i++) { 12009444SAndreas.Sandberg@ARM.com if (thread[i]->status() == ThreadContext::Active) { 12019444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Activating thread: %i\n", i); 12029444SAndreas.Sandberg@ARM.com activateThread(i); 12039444SAndreas.Sandberg@ARM.com _status = Running; 12042863Sktlim@umich.edu } 12052310SN/A } 12069444SAndreas.Sandberg@ARM.com 12079444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 12089444SAndreas.Sandberg@ARM.com if (_status == Running) 12099444SAndreas.Sandberg@ARM.com schedule(tickEvent, nextCycle()); 121012276Sanouk.vanlaer@arm.com 121112276Sanouk.vanlaer@arm.com // Reschedule any power gating event (if any) 121212276Sanouk.vanlaer@arm.com schedulePowerGatingEvent(); 12132843Sktlim@umich.edu} 12142843Sktlim@umich.edu 12152843Sktlim@umich.edutemplate <class Impl> 12162843Sktlim@umich.eduvoid 12172843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 12182843Sktlim@umich.edu{ 12199444SAndreas.Sandberg@ARM.com DPRINTF(O3CPU, "Switching out\n"); 12209429SAndreas.Sandberg@ARM.com BaseCPU::switchOut(); 12219429SAndreas.Sandberg@ARM.com 12229444SAndreas.Sandberg@ARM.com activityRec.reset(); 12232843Sktlim@umich.edu 12242843Sktlim@umich.edu _status = SwitchedOut; 12258887Sgeoffrey.blake@arm.com 12262843Sktlim@umich.edu if (checker) 12272843Sktlim@umich.edu checker->switchOut(); 12281060SN/A} 12291060SN/A 12301060SN/Atemplate <class Impl> 12311060SN/Avoid 12321755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 12331060SN/A{ 12348737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 12351060SN/A 12362307SN/A fetch.takeOverFrom(); 12372307SN/A decode.takeOverFrom(); 12382307SN/A rename.takeOverFrom(); 12392307SN/A iew.takeOverFrom(); 12402307SN/A commit.takeOverFrom(); 12412307SN/A 12429444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 12431060SN/A 12449152Satgutier@umich.edu FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU); 12459152Satgutier@umich.edu if (oldO3CPU) 12469152Satgutier@umich.edu globalSeqNum = oldO3CPU->globalSeqNum; 12479152Satgutier@umich.edu 12489179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 12499444SAndreas.Sandberg@ARM.com _status = Idle; 12501060SN/A} 12511060SN/A 12521060SN/Atemplate <class Impl> 12539523SAndreas.Sandberg@ARM.comvoid 12549523SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::verifyMemoryMode() const 12559523SAndreas.Sandberg@ARM.com{ 12569524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 12579523SAndreas.Sandberg@ARM.com fatal("The O3 CPU requires the memory system to be in " 12589523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 12599523SAndreas.Sandberg@ARM.com } 12609523SAndreas.Sandberg@ARM.com} 12619523SAndreas.Sandberg@ARM.com 12629523SAndreas.Sandberg@ARM.comtemplate <class Impl> 126313557Sgabeblack@google.comRegVal 126410698Sandreas.hansson@arm.comFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const 12655595Sgblack@eecs.umich.edu{ 12669384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscRegNoEffect(misc_reg); 12675595Sgblack@eecs.umich.edu} 12685595Sgblack@eecs.umich.edu 12695595Sgblack@eecs.umich.edutemplate <class Impl> 127013557Sgabeblack@google.comRegVal 12716221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 12725595Sgblack@eecs.umich.edu{ 12737897Shestness@cs.utexas.edu miscRegfileReads++; 12749384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); 12755595Sgblack@eecs.umich.edu} 12765595Sgblack@eecs.umich.edu 12775595Sgblack@eecs.umich.edutemplate <class Impl> 12785595Sgblack@eecs.umich.eduvoid 127913582Sgabeblack@google.comFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) 12805595Sgblack@eecs.umich.edu{ 12819384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscRegNoEffect(misc_reg, val); 12825595Sgblack@eecs.umich.edu} 12835595Sgblack@eecs.umich.edu 12845595Sgblack@eecs.umich.edutemplate <class Impl> 12855595Sgblack@eecs.umich.eduvoid 128613582Sgabeblack@google.comFullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid) 12875595Sgblack@eecs.umich.edu{ 12887897Shestness@cs.utexas.edu miscRegfileWrites++; 12899384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); 12905595Sgblack@eecs.umich.edu} 12915595Sgblack@eecs.umich.edu 12925595Sgblack@eecs.umich.edutemplate <class Impl> 129313557Sgabeblack@google.comRegVal 129412105Snathanael.premillieu@arm.comFullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg) 12951060SN/A{ 12967897Shestness@cs.utexas.edu intRegfileReads++; 129712105Snathanael.premillieu@arm.com return regFile.readIntReg(phys_reg); 12981060SN/A} 12991060SN/A 13001060SN/Atemplate <class Impl> 130113557Sgabeblack@google.comRegVal 130213611Sgabeblack@google.comFullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg) 13032455SN/A{ 13047897Shestness@cs.utexas.edu fpRegfileReads++; 130513611Sgabeblack@google.com return regFile.readFloatReg(phys_reg); 13061060SN/A} 13071060SN/A 13081060SN/Atemplate <class Impl> 130912109SRekai.GonzalezAlberquilla@arm.comauto 131012109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::readVecReg(PhysRegIdPtr phys_reg) const 131112109SRekai.GonzalezAlberquilla@arm.com -> const VecRegContainer& 131212109SRekai.GonzalezAlberquilla@arm.com{ 131312109SRekai.GonzalezAlberquilla@arm.com vecRegfileReads++; 131412109SRekai.GonzalezAlberquilla@arm.com return regFile.readVecReg(phys_reg); 131512109SRekai.GonzalezAlberquilla@arm.com} 131612109SRekai.GonzalezAlberquilla@arm.com 131712109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 131812109SRekai.GonzalezAlberquilla@arm.comauto 131912109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::getWritableVecReg(PhysRegIdPtr phys_reg) 132012109SRekai.GonzalezAlberquilla@arm.com -> VecRegContainer& 132112109SRekai.GonzalezAlberquilla@arm.com{ 132212109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites++; 132312109SRekai.GonzalezAlberquilla@arm.com return regFile.getWritableVecReg(phys_reg); 132412109SRekai.GonzalezAlberquilla@arm.com} 132512109SRekai.GonzalezAlberquilla@arm.com 132612109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 132712109SRekai.GonzalezAlberquilla@arm.comauto 132812109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::readVecElem(PhysRegIdPtr phys_reg) const -> const VecElem& 132912109SRekai.GonzalezAlberquilla@arm.com{ 133012109SRekai.GonzalezAlberquilla@arm.com vecRegfileReads++; 133112109SRekai.GonzalezAlberquilla@arm.com return regFile.readVecElem(phys_reg); 133212109SRekai.GonzalezAlberquilla@arm.com} 133312109SRekai.GonzalezAlberquilla@arm.com 133412109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 133513610Sgiacomo.gabrielli@arm.comauto 133613610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::readVecPredReg(PhysRegIdPtr phys_reg) const 133713610Sgiacomo.gabrielli@arm.com -> const VecPredRegContainer& 133813610Sgiacomo.gabrielli@arm.com{ 133913610Sgiacomo.gabrielli@arm.com vecPredRegfileReads++; 134013610Sgiacomo.gabrielli@arm.com return regFile.readVecPredReg(phys_reg); 134113610Sgiacomo.gabrielli@arm.com} 134213610Sgiacomo.gabrielli@arm.com 134313610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 134413610Sgiacomo.gabrielli@arm.comauto 134513610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::getWritableVecPredReg(PhysRegIdPtr phys_reg) 134613610Sgiacomo.gabrielli@arm.com -> VecPredRegContainer& 134713610Sgiacomo.gabrielli@arm.com{ 134813610Sgiacomo.gabrielli@arm.com vecPredRegfileWrites++; 134913610Sgiacomo.gabrielli@arm.com return regFile.getWritableVecPredReg(phys_reg); 135013610Sgiacomo.gabrielli@arm.com} 135113610Sgiacomo.gabrielli@arm.com 135213610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 135313622Sgabeblack@google.comRegVal 135412105Snathanael.premillieu@arm.comFullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg) 13559920Syasuko.eckert@amd.com{ 13569920Syasuko.eckert@amd.com ccRegfileReads++; 135712105Snathanael.premillieu@arm.com return regFile.readCCReg(phys_reg); 13589920Syasuko.eckert@amd.com} 13599920Syasuko.eckert@amd.com 13609920Syasuko.eckert@amd.comtemplate <class Impl> 13611060SN/Avoid 136213557Sgabeblack@google.comFullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, RegVal val) 13631060SN/A{ 13647897Shestness@cs.utexas.edu intRegfileWrites++; 136512105Snathanael.premillieu@arm.com regFile.setIntReg(phys_reg, val); 13661060SN/A} 13671060SN/A 13681060SN/Atemplate <class Impl> 13691060SN/Avoid 137013611Sgabeblack@google.comFullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, RegVal val) 13712455SN/A{ 13727897Shestness@cs.utexas.edu fpRegfileWrites++; 137313611Sgabeblack@google.com regFile.setFloatReg(phys_reg, val); 13741060SN/A} 13751060SN/A 13761060SN/Atemplate <class Impl> 13779920Syasuko.eckert@amd.comvoid 137812109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val) 137912109SRekai.GonzalezAlberquilla@arm.com{ 138012109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites++; 138112109SRekai.GonzalezAlberquilla@arm.com regFile.setVecReg(phys_reg, val); 138212109SRekai.GonzalezAlberquilla@arm.com} 138312109SRekai.GonzalezAlberquilla@arm.com 138412109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 138512109SRekai.GonzalezAlberquilla@arm.comvoid 138612109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::setVecElem(PhysRegIdPtr phys_reg, const VecElem& val) 138712109SRekai.GonzalezAlberquilla@arm.com{ 138812109SRekai.GonzalezAlberquilla@arm.com vecRegfileWrites++; 138912109SRekai.GonzalezAlberquilla@arm.com regFile.setVecElem(phys_reg, val); 139012109SRekai.GonzalezAlberquilla@arm.com} 139112109SRekai.GonzalezAlberquilla@arm.com 139212109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 139312109SRekai.GonzalezAlberquilla@arm.comvoid 139413610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::setVecPredReg(PhysRegIdPtr phys_reg, 139513610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& val) 139613610Sgiacomo.gabrielli@arm.com{ 139713610Sgiacomo.gabrielli@arm.com vecPredRegfileWrites++; 139813610Sgiacomo.gabrielli@arm.com regFile.setVecPredReg(phys_reg, val); 139913610Sgiacomo.gabrielli@arm.com} 140013610Sgiacomo.gabrielli@arm.com 140113610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 140213610Sgiacomo.gabrielli@arm.comvoid 140313622Sgabeblack@google.comFullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, RegVal val) 14049920Syasuko.eckert@amd.com{ 14059920Syasuko.eckert@amd.com ccRegfileWrites++; 140612105Snathanael.premillieu@arm.com regFile.setCCReg(phys_reg, val); 14079920Syasuko.eckert@amd.com} 14089920Syasuko.eckert@amd.com 14099920Syasuko.eckert@amd.comtemplate <class Impl> 141013557Sgabeblack@google.comRegVal 14116221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 14121060SN/A{ 14137897Shestness@cs.utexas.edu intRegfileReads++; 141412106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 141512106SRekai.GonzalezAlberquilla@arm.com RegId(IntRegClass, reg_idx)); 14162292SN/A 14172292SN/A return regFile.readIntReg(phys_reg); 14182292SN/A} 14192292SN/A 14202292SN/Atemplate <class Impl> 142113557Sgabeblack@google.comRegVal 142213611Sgabeblack@google.comFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 14232292SN/A{ 14247897Shestness@cs.utexas.edu fpRegfileReads++; 142512106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 142612106SRekai.GonzalezAlberquilla@arm.com RegId(FloatRegClass, reg_idx)); 14272292SN/A 142813611Sgabeblack@google.com return regFile.readFloatReg(phys_reg); 14291060SN/A} 14301060SN/A 14311060SN/Atemplate <class Impl> 143212109SRekai.GonzalezAlberquilla@arm.comauto 143312109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::readArchVecReg(int reg_idx, ThreadID tid) const 143412109SRekai.GonzalezAlberquilla@arm.com -> const VecRegContainer& 143512109SRekai.GonzalezAlberquilla@arm.com{ 143612109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 143712109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx)); 143812109SRekai.GonzalezAlberquilla@arm.com return readVecReg(phys_reg); 143912109SRekai.GonzalezAlberquilla@arm.com} 144012109SRekai.GonzalezAlberquilla@arm.com 144112109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 144212109SRekai.GonzalezAlberquilla@arm.comauto 144312109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::getWritableArchVecReg(int reg_idx, ThreadID tid) 144412109SRekai.GonzalezAlberquilla@arm.com -> VecRegContainer& 144512109SRekai.GonzalezAlberquilla@arm.com{ 144612109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 144712109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx)); 144812109SRekai.GonzalezAlberquilla@arm.com return getWritableVecReg(phys_reg); 144912109SRekai.GonzalezAlberquilla@arm.com} 145012109SRekai.GonzalezAlberquilla@arm.com 145112109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 145212109SRekai.GonzalezAlberquilla@arm.comauto 145312109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::readArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 145412109SRekai.GonzalezAlberquilla@arm.com ThreadID tid) const -> const VecElem& 145512109SRekai.GonzalezAlberquilla@arm.com{ 145612109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 145713598Sgiacomo.travaglini@arm.com RegId(VecElemClass, reg_idx, ldx)); 145812109SRekai.GonzalezAlberquilla@arm.com return readVecElem(phys_reg); 145912109SRekai.GonzalezAlberquilla@arm.com} 146012109SRekai.GonzalezAlberquilla@arm.com 146112109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 146213610Sgiacomo.gabrielli@arm.comauto 146313610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::readArchVecPredReg(int reg_idx, ThreadID tid) const 146413610Sgiacomo.gabrielli@arm.com -> const VecPredRegContainer& 146513610Sgiacomo.gabrielli@arm.com{ 146613610Sgiacomo.gabrielli@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 146713610Sgiacomo.gabrielli@arm.com RegId(VecPredRegClass, reg_idx)); 146813610Sgiacomo.gabrielli@arm.com return readVecPredReg(phys_reg); 146913610Sgiacomo.gabrielli@arm.com} 147013610Sgiacomo.gabrielli@arm.com 147113610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 147213610Sgiacomo.gabrielli@arm.comauto 147313610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::getWritableArchVecPredReg(int reg_idx, ThreadID tid) 147413610Sgiacomo.gabrielli@arm.com -> VecPredRegContainer& 147513610Sgiacomo.gabrielli@arm.com{ 147613610Sgiacomo.gabrielli@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 147713610Sgiacomo.gabrielli@arm.com RegId(VecPredRegClass, reg_idx)); 147813610Sgiacomo.gabrielli@arm.com return getWritableVecPredReg(phys_reg); 147913610Sgiacomo.gabrielli@arm.com} 148013610Sgiacomo.gabrielli@arm.com 148113610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 148213622Sgabeblack@google.comRegVal 14839920Syasuko.eckert@amd.comFullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid) 14849920Syasuko.eckert@amd.com{ 14859920Syasuko.eckert@amd.com ccRegfileReads++; 148612106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 148712106SRekai.GonzalezAlberquilla@arm.com RegId(CCRegClass, reg_idx)); 14889920Syasuko.eckert@amd.com 14899920Syasuko.eckert@amd.com return regFile.readCCReg(phys_reg); 14909920Syasuko.eckert@amd.com} 14919920Syasuko.eckert@amd.com 14929920Syasuko.eckert@amd.comtemplate <class Impl> 14931060SN/Avoid 149413557Sgabeblack@google.comFullO3CPU<Impl>::setArchIntReg(int reg_idx, RegVal val, ThreadID tid) 14951060SN/A{ 14967897Shestness@cs.utexas.edu intRegfileWrites++; 149712106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 149812106SRekai.GonzalezAlberquilla@arm.com RegId(IntRegClass, reg_idx)); 14992292SN/A 15002292SN/A regFile.setIntReg(phys_reg, val); 15011060SN/A} 15021060SN/A 15031060SN/Atemplate <class Impl> 15041060SN/Avoid 150513611Sgabeblack@google.comFullO3CPU<Impl>::setArchFloatReg(int reg_idx, RegVal val, ThreadID tid) 15061060SN/A{ 15077897Shestness@cs.utexas.edu fpRegfileWrites++; 150812106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 150912106SRekai.GonzalezAlberquilla@arm.com RegId(FloatRegClass, reg_idx)); 15101060SN/A 151113611Sgabeblack@google.com regFile.setFloatReg(phys_reg, val); 15122292SN/A} 15132292SN/A 15142292SN/Atemplate <class Impl> 15159920Syasuko.eckert@amd.comvoid 151612109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::setArchVecReg(int reg_idx, const VecRegContainer& val, 151712109SRekai.GonzalezAlberquilla@arm.com ThreadID tid) 151812109SRekai.GonzalezAlberquilla@arm.com{ 151912109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 152012109SRekai.GonzalezAlberquilla@arm.com RegId(VecRegClass, reg_idx)); 152112109SRekai.GonzalezAlberquilla@arm.com setVecReg(phys_reg, val); 152212109SRekai.GonzalezAlberquilla@arm.com} 152312109SRekai.GonzalezAlberquilla@arm.com 152412109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 152512109SRekai.GonzalezAlberquilla@arm.comvoid 152612109SRekai.GonzalezAlberquilla@arm.comFullO3CPU<Impl>::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 152712109SRekai.GonzalezAlberquilla@arm.com const VecElem& val, ThreadID tid) 152812109SRekai.GonzalezAlberquilla@arm.com{ 152912109SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 153013546Sgiacomo.travaglini@arm.com RegId(VecElemClass, reg_idx, ldx)); 153112109SRekai.GonzalezAlberquilla@arm.com setVecElem(phys_reg, val); 153212109SRekai.GonzalezAlberquilla@arm.com} 153312109SRekai.GonzalezAlberquilla@arm.com 153412109SRekai.GonzalezAlberquilla@arm.comtemplate <class Impl> 153512109SRekai.GonzalezAlberquilla@arm.comvoid 153613610Sgiacomo.gabrielli@arm.comFullO3CPU<Impl>::setArchVecPredReg(int reg_idx, const VecPredRegContainer& val, 153713610Sgiacomo.gabrielli@arm.com ThreadID tid) 153813610Sgiacomo.gabrielli@arm.com{ 153913610Sgiacomo.gabrielli@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 154013610Sgiacomo.gabrielli@arm.com RegId(VecPredRegClass, reg_idx)); 154113610Sgiacomo.gabrielli@arm.com setVecPredReg(phys_reg, val); 154213610Sgiacomo.gabrielli@arm.com} 154313610Sgiacomo.gabrielli@arm.com 154413610Sgiacomo.gabrielli@arm.comtemplate <class Impl> 154513610Sgiacomo.gabrielli@arm.comvoid 154613622Sgabeblack@google.comFullO3CPU<Impl>::setArchCCReg(int reg_idx, RegVal val, ThreadID tid) 15479920Syasuko.eckert@amd.com{ 15489920Syasuko.eckert@amd.com ccRegfileWrites++; 154912106SRekai.GonzalezAlberquilla@arm.com PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( 155012106SRekai.GonzalezAlberquilla@arm.com RegId(CCRegClass, reg_idx)); 15519920Syasuko.eckert@amd.com 15529920Syasuko.eckert@amd.com regFile.setCCReg(phys_reg, val); 15539920Syasuko.eckert@amd.com} 15549920Syasuko.eckert@amd.com 15559920Syasuko.eckert@amd.comtemplate <class Impl> 15567720Sgblack@eecs.umich.eduTheISA::PCState 15577720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 15582292SN/A{ 15597720Sgblack@eecs.umich.edu return commit.pcState(tid); 15601060SN/A} 15611060SN/A 15621060SN/Atemplate <class Impl> 15631060SN/Avoid 15647720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 15651060SN/A{ 15667720Sgblack@eecs.umich.edu commit.pcState(val, tid); 15672292SN/A} 15681060SN/A 15692292SN/Atemplate <class Impl> 15707720Sgblack@eecs.umich.eduAddr 15717720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 15724636Sgblack@eecs.umich.edu{ 15737720Sgblack@eecs.umich.edu return commit.instAddr(tid); 15744636Sgblack@eecs.umich.edu} 15754636Sgblack@eecs.umich.edu 15764636Sgblack@eecs.umich.edutemplate <class Impl> 15777720Sgblack@eecs.umich.eduAddr 15787720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 15794636Sgblack@eecs.umich.edu{ 15807720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 15814636Sgblack@eecs.umich.edu} 15824636Sgblack@eecs.umich.edu 15834636Sgblack@eecs.umich.edutemplate <class Impl> 15847720Sgblack@eecs.umich.eduMicroPC 15857720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 15862292SN/A{ 15877720Sgblack@eecs.umich.edu return commit.microPC(tid); 15884636Sgblack@eecs.umich.edu} 15894636Sgblack@eecs.umich.edu 15904636Sgblack@eecs.umich.edutemplate <class Impl> 15915595Sgblack@eecs.umich.eduvoid 15926221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 15935595Sgblack@eecs.umich.edu{ 15949382SAli.Saidi@ARM.com this->thread[tid]->noSquashFromTC = true; 15955595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 15965595Sgblack@eecs.umich.edu} 15975595Sgblack@eecs.umich.edu 15985595Sgblack@eecs.umich.edutemplate <class Impl> 15992292SN/Atypename FullO3CPU<Impl>::ListIt 160013429Srekai.gonzalezalberquilla@arm.comFullO3CPU<Impl>::addInst(const DynInstPtr &inst) 16012292SN/A{ 16022292SN/A instList.push_back(inst); 16031060SN/A 16042292SN/A return --(instList.end()); 16052292SN/A} 16061060SN/A 16072292SN/Atemplate <class Impl> 16082292SN/Avoid 160913429Srekai.gonzalezalberquilla@arm.comFullO3CPU<Impl>::instDone(ThreadID tid, const DynInstPtr &inst) 16102292SN/A{ 16112292SN/A // Keep an instruction count. 16128834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) { 16138834Satgutier@umich.edu thread[tid]->numInst++; 16148834Satgutier@umich.edu thread[tid]->numInsts++; 16158834Satgutier@umich.edu committedInsts[tid]++; 161610774Snikos.nikoleris@gmail.com system->totalNumInsts++; 161710774Snikos.nikoleris@gmail.com 161810774Snikos.nikoleris@gmail.com // Check for instruction-count-based events. 161910774Snikos.nikoleris@gmail.com comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 162010774Snikos.nikoleris@gmail.com system->instEventQueue.serviceEvents(system->totalNumInsts); 16218834Satgutier@umich.edu } 16228834Satgutier@umich.edu thread[tid]->numOp++; 16238834Satgutier@umich.edu thread[tid]->numOps++; 16248834Satgutier@umich.edu committedOps[tid]++; 16258834Satgutier@umich.edu 162610464SAndreas.Sandberg@ARM.com probeInstCommit(inst->staticInst); 16272292SN/A} 16282292SN/A 16292292SN/Atemplate <class Impl> 16302292SN/Avoid 163113429Srekai.gonzalezalberquilla@arm.comFullO3CPU<Impl>::removeFrontInst(const DynInstPtr &inst) 16321060SN/A{ 16337720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 16342292SN/A "[sn:%lli]\n", 16357720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 16361060SN/A 16372292SN/A removeInstsThisCycle = true; 16381060SN/A 16391060SN/A // Remove the front instruction. 16402292SN/A removeList.push(inst->getInstListIt()); 16411060SN/A} 16421060SN/A 16431060SN/Atemplate <class Impl> 16441060SN/Avoid 16456221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 16461060SN/A{ 16472733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 16482292SN/A " list.\n", tid); 16491060SN/A 16502292SN/A ListIt end_it; 16511060SN/A 16522292SN/A bool rob_empty = false; 16532292SN/A 16542292SN/A if (instList.empty()) { 16552292SN/A return; 165610164Ssleimanf@umich.edu } else if (rob.isEmpty(tid)) { 16572733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 16582292SN/A end_it = instList.begin(); 16592292SN/A rob_empty = true; 16602292SN/A } else { 16612292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 16622733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 16632292SN/A } 16642292SN/A 16652292SN/A removeInstsThisCycle = true; 16662292SN/A 16672292SN/A ListIt inst_it = instList.end(); 16682292SN/A 16692292SN/A inst_it--; 16702292SN/A 16712292SN/A // Walk through the instruction list, removing any instructions 16722292SN/A // that were inserted after the given instruction iterator, end_it. 16732292SN/A while (inst_it != end_it) { 16742292SN/A assert(!instList.empty()); 16752292SN/A 16762292SN/A squashInstIt(inst_it, tid); 16772292SN/A 16782292SN/A inst_it--; 16792292SN/A } 16802292SN/A 16812292SN/A // If the ROB was empty, then we actually need to remove the first 16822292SN/A // instruction as well. 16832292SN/A if (rob_empty) { 16842292SN/A squashInstIt(inst_it, tid); 16852292SN/A } 16861060SN/A} 16871060SN/A 16881060SN/Atemplate <class Impl> 16891060SN/Avoid 16906221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 16911062SN/A{ 16922292SN/A assert(!instList.empty()); 16932292SN/A 16942292SN/A removeInstsThisCycle = true; 16952292SN/A 16962292SN/A ListIt inst_iter = instList.end(); 16972292SN/A 16982292SN/A inst_iter--; 16992292SN/A 17002733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 17012292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 17022292SN/A tid, seq_num, (*inst_iter)->seqNum); 17031062SN/A 17042292SN/A while ((*inst_iter)->seqNum > seq_num) { 17051062SN/A 17062292SN/A bool break_loop = (inst_iter == instList.begin()); 17071062SN/A 17082292SN/A squashInstIt(inst_iter, tid); 17091062SN/A 17102292SN/A inst_iter--; 17111062SN/A 17122292SN/A if (break_loop) 17132292SN/A break; 17142292SN/A } 17152292SN/A} 17162292SN/A 17172292SN/Atemplate <class Impl> 17182292SN/Ainline void 17196221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 17202292SN/A{ 17212292SN/A if ((*instIt)->threadNumber == tid) { 17222733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 17237720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 17242292SN/A (*instIt)->threadNumber, 17252292SN/A (*instIt)->seqNum, 17267720Sgblack@eecs.umich.edu (*instIt)->pcState()); 17271062SN/A 17281062SN/A // Mark it as squashed. 17292292SN/A (*instIt)->setSquashed(); 17302292SN/A 17312325SN/A // @todo: Formulate a consistent method for deleting 17322325SN/A // instructions from the instruction list 17332292SN/A // Remove the instruction from the list. 17342292SN/A removeList.push(instIt); 17352292SN/A } 17362292SN/A} 17372292SN/A 17382292SN/Atemplate <class Impl> 17392292SN/Avoid 17402292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 17412292SN/A{ 17422292SN/A while (!removeList.empty()) { 17432733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 17447720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 17452292SN/A (*removeList.front())->threadNumber, 17462292SN/A (*removeList.front())->seqNum, 17477720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 17482292SN/A 17492292SN/A instList.erase(removeList.front()); 17502292SN/A 17512292SN/A removeList.pop(); 17521062SN/A } 17531062SN/A 17542292SN/A removeInstsThisCycle = false; 17551062SN/A} 17562325SN/A/* 17571062SN/Atemplate <class Impl> 17581062SN/Avoid 17591755SN/AFullO3CPU<Impl>::removeAllInsts() 17601060SN/A{ 17611060SN/A instList.clear(); 17621060SN/A} 17632325SN/A*/ 17641060SN/Atemplate <class Impl> 17651060SN/Avoid 17661755SN/AFullO3CPU<Impl>::dumpInsts() 17671060SN/A{ 17681060SN/A int num = 0; 17691060SN/A 17702292SN/A ListIt inst_list_it = instList.begin(); 17712292SN/A 17722292SN/A cprintf("Dumping Instruction List\n"); 17732292SN/A 17742292SN/A while (inst_list_it != instList.end()) { 17752292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 17762292SN/A "Squashed:%i\n\n", 17777720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 17782292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 17792292SN/A (*inst_list_it)->isSquashed()); 17801060SN/A inst_list_it++; 17811060SN/A ++num; 17821060SN/A } 17831060SN/A} 17842325SN/A/* 17851060SN/Atemplate <class Impl> 17861060SN/Avoid 178713429Srekai.gonzalezalberquilla@arm.comFullO3CPU<Impl>::wakeDependents(const DynInstPtr &inst) 17881060SN/A{ 17891060SN/A iew.wakeDependents(inst); 17901060SN/A} 17912325SN/A*/ 17922292SN/Atemplate <class Impl> 17932292SN/Avoid 17942292SN/AFullO3CPU<Impl>::wakeCPU() 17952292SN/A{ 17962325SN/A if (activityRec.active() || tickEvent.scheduled()) { 17972325SN/A DPRINTF(Activity, "CPU already running.\n"); 17982292SN/A return; 17992292SN/A } 18002292SN/A 18012325SN/A DPRINTF(Activity, "Waking up CPU\n"); 18022325SN/A 18039180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 18049180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 180510464SAndreas.Sandberg@ARM.com if (cycles > 1) { 18069179Sandreas.hansson@arm.com --cycles; 180710464SAndreas.Sandberg@ARM.com idleCycles += cycles; 180810464SAndreas.Sandberg@ARM.com numCycles += cycles; 180910464SAndreas.Sandberg@ARM.com } 18102292SN/A 18119648Sdam.sunwoo@arm.com schedule(tickEvent, clockEdge()); 18122292SN/A} 18132292SN/A 18145807Snate@binkert.orgtemplate <class Impl> 18155807Snate@binkert.orgvoid 181611151Smitch.hayenga@arm.comFullO3CPU<Impl>::wakeup(ThreadID tid) 18175807Snate@binkert.org{ 181811151Smitch.hayenga@arm.com if (this->thread[tid]->status() != ThreadContext::Suspended) 18195807Snate@binkert.org return; 18205807Snate@binkert.org 18215807Snate@binkert.org this->wakeCPU(); 18225807Snate@binkert.org 18235807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 182411151Smitch.hayenga@arm.com this->threadContexts[tid]->activate(); 18255807Snate@binkert.org} 18265807Snate@binkert.org 18272292SN/Atemplate <class Impl> 18286221Snate@binkert.orgThreadID 18292292SN/AFullO3CPU<Impl>::getFreeTid() 18302292SN/A{ 18316221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 18326221Snate@binkert.org if (!tids[tid]) { 18336221Snate@binkert.org tids[tid] = true; 18346221Snate@binkert.org return tid; 18352292SN/A } 18362292SN/A } 18372292SN/A 18386221Snate@binkert.org return InvalidThreadID; 18392292SN/A} 18402292SN/A 18412292SN/Atemplate <class Impl> 18422292SN/Avoid 18432292SN/AFullO3CPU<Impl>::updateThreadPriority() 18442292SN/A{ 18456221Snate@binkert.org if (activeThreads.size() > 1) { 18462292SN/A //DEFAULT TO ROUND ROBIN SCHEME 18472292SN/A //e.g. Move highest priority to end of thread list 18486221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 18492292SN/A 18502292SN/A unsigned high_thread = *list_begin; 18512292SN/A 18522292SN/A activeThreads.erase(list_begin); 18532292SN/A 18542292SN/A activeThreads.push_back(high_thread); 18552292SN/A } 18562292SN/A} 18571060SN/A 185813641Sqtt2@cornell.edutemplate <class Impl> 185913641Sqtt2@cornell.eduvoid 186013641Sqtt2@cornell.eduFullO3CPU<Impl>::addThreadToExitingList(ThreadID tid) 186113641Sqtt2@cornell.edu{ 186213641Sqtt2@cornell.edu DPRINTF(O3CPU, "Thread %d is inserted to exitingThreads list\n", tid); 186313641Sqtt2@cornell.edu 186413644Sqtt2@cornell.edu // the thread trying to exit can't be already halted 186513644Sqtt2@cornell.edu assert(tcBase(tid)->status() != ThreadContext::Halted); 186613641Sqtt2@cornell.edu 186713641Sqtt2@cornell.edu // make sure the thread has not been added to the list yet 186813641Sqtt2@cornell.edu assert(exitingThreads.count(tid) == 0); 186913641Sqtt2@cornell.edu 187013641Sqtt2@cornell.edu // add the thread to exitingThreads list to mark that this thread is 187113641Sqtt2@cornell.edu // trying to exit. The boolean value in the pair denotes if a thread is 187213641Sqtt2@cornell.edu // ready to exit. The thread is not ready to exit until the corresponding 187313641Sqtt2@cornell.edu // exit trap event is processed in the future. Until then, it'll be still 187413641Sqtt2@cornell.edu // an active thread that is trying to exit. 187513641Sqtt2@cornell.edu exitingThreads.emplace(std::make_pair(tid, false)); 187613641Sqtt2@cornell.edu} 187713641Sqtt2@cornell.edu 187813641Sqtt2@cornell.edutemplate <class Impl> 187913641Sqtt2@cornell.edubool 188013641Sqtt2@cornell.eduFullO3CPU<Impl>::isThreadExiting(ThreadID tid) const 188113641Sqtt2@cornell.edu{ 188213641Sqtt2@cornell.edu return exitingThreads.count(tid) == 1; 188313641Sqtt2@cornell.edu} 188413641Sqtt2@cornell.edu 188513641Sqtt2@cornell.edutemplate <class Impl> 188613641Sqtt2@cornell.eduvoid 188713641Sqtt2@cornell.eduFullO3CPU<Impl>::scheduleThreadExitEvent(ThreadID tid) 188813641Sqtt2@cornell.edu{ 188913641Sqtt2@cornell.edu assert(exitingThreads.count(tid) == 1); 189013641Sqtt2@cornell.edu 189113641Sqtt2@cornell.edu // exit trap event has been processed. Now, the thread is ready to exit 189213641Sqtt2@cornell.edu // and be removed from the CPU. 189313641Sqtt2@cornell.edu exitingThreads[tid] = true; 189413641Sqtt2@cornell.edu 189513641Sqtt2@cornell.edu // we schedule a threadExitEvent in the next cycle to properly clean 189613641Sqtt2@cornell.edu // up the thread's states in the pipeline. threadExitEvent has lower 189713641Sqtt2@cornell.edu // priority than tickEvent, so the cleanup will happen at the very end 189813641Sqtt2@cornell.edu // of the next cycle after all pipeline stages complete their operations. 189913641Sqtt2@cornell.edu // We want all stages to complete squashing instructions before doing 190013641Sqtt2@cornell.edu // the cleanup. 190113641Sqtt2@cornell.edu if (!threadExitEvent.scheduled()) { 190213641Sqtt2@cornell.edu schedule(threadExitEvent, nextCycle()); 190313641Sqtt2@cornell.edu } 190413641Sqtt2@cornell.edu} 190513641Sqtt2@cornell.edu 190613641Sqtt2@cornell.edutemplate <class Impl> 190713641Sqtt2@cornell.eduvoid 190813641Sqtt2@cornell.eduFullO3CPU<Impl>::exitThreads() 190913641Sqtt2@cornell.edu{ 191013641Sqtt2@cornell.edu // there must be at least one thread trying to exit 191113641Sqtt2@cornell.edu assert(exitingThreads.size() > 0); 191213641Sqtt2@cornell.edu 191313641Sqtt2@cornell.edu // terminate all threads that are ready to exit 191413641Sqtt2@cornell.edu auto it = exitingThreads.begin(); 191513641Sqtt2@cornell.edu while (it != exitingThreads.end()) { 191613641Sqtt2@cornell.edu ThreadID thread_id = it->first; 191713641Sqtt2@cornell.edu bool readyToExit = it->second; 191813641Sqtt2@cornell.edu 191913641Sqtt2@cornell.edu if (readyToExit) { 192013641Sqtt2@cornell.edu DPRINTF(O3CPU, "Exiting thread %d\n", thread_id); 192113641Sqtt2@cornell.edu haltContext(thread_id); 192213641Sqtt2@cornell.edu tcBase(thread_id)->setStatus(ThreadContext::Halted); 192313641Sqtt2@cornell.edu it = exitingThreads.erase(it); 192413641Sqtt2@cornell.edu } else { 192513641Sqtt2@cornell.edu it++; 192613641Sqtt2@cornell.edu } 192713641Sqtt2@cornell.edu } 192813641Sqtt2@cornell.edu} 192913641Sqtt2@cornell.edu 19301755SN/A// Forward declaration of FullO3CPU. 19312818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1932