cpu.cc revision 10529
11689SN/A/* 210331Smitch.hayenga@arm.com * Copyright (c) 2011-2012, 2014 ARM Limited 39916Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48707Sandreas.hansson@arm.com * All rights reserved 58707Sandreas.hansson@arm.com * 68707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148707Sandreas.hansson@arm.com * 152325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 167897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 171689SN/A * All rights reserved. 181689SN/A * 191689SN/A * Redistribution and use in source and binary forms, with or without 201689SN/A * modification, are permitted provided that the following conditions are 211689SN/A * met: redistributions of source code must retain the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer; 231689SN/A * redistributions in binary form must reproduce the above copyright 241689SN/A * notice, this list of conditions and the following disclaimer in the 251689SN/A * documentation and/or other materials provided with the distribution; 261689SN/A * neither the name of the copyright holders nor the names of its 271689SN/A * contributors may be used to endorse or promote products derived from 281689SN/A * this software without specific prior written permission. 291689SN/A * 301689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 432756Sksewell@umich.edu * Korey Sewell 447897Shestness@cs.utexas.edu * Rick Strong 451689SN/A */ 461689SN/A 478779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 498887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 508887Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 518229Snate@binkert.org#include "cpu/o3/cpu.hh" 528229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 538229Snate@binkert.org#include "cpu/o3/thread_context.hh" 544762Snate@binkert.org#include "cpu/activity.hh" 558779Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 564762Snate@binkert.org#include "cpu/simple_thread.hh" 574762Snate@binkert.org#include "cpu/thread_context.hh" 588232Snate@binkert.org#include "debug/Activity.hh" 599152Satgutier@umich.edu#include "debug/Drain.hh" 608232Snate@binkert.org#include "debug/O3CPU.hh" 618232Snate@binkert.org#include "debug/Quiesce.hh" 624762Snate@binkert.org#include "enums/MemoryMode.hh" 634762Snate@binkert.org#include "sim/core.hh" 648793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 658779Sgblack@eecs.umich.edu#include "sim/process.hh" 664762Snate@binkert.org#include "sim/stat_control.hh" 678460SAli.Saidi@ARM.com#include "sim/system.hh" 684762Snate@binkert.org 695702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 705702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 718232Snate@binkert.org#include "debug/Activity.hh" 725702Ssaidi@eecs.umich.edu#endif 735702Ssaidi@eecs.umich.edu 748737Skoansin.tan@gmail.comstruct BaseCPUParams; 755529Snate@binkert.org 762669Sktlim@umich.eduusing namespace TheISA; 776221Snate@binkert.orgusing namespace std; 781060SN/A 795529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 805712Shsul@eecs.umich.edu : BaseCPU(params) 811060SN/A{ 821060SN/A} 831060SN/A 842292SN/Avoid 852733Sktlim@umich.eduBaseO3CPU::regStats() 862292SN/A{ 872292SN/A BaseCPU::regStats(); 882292SN/A} 892292SN/A 908707Sandreas.hansson@arm.comtemplate<class Impl> 918707Sandreas.hansson@arm.combool 928975Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt) 938707Sandreas.hansson@arm.com{ 948707Sandreas.hansson@arm.com DPRINTF(O3CPU, "Fetch unit received timing\n"); 958948Sandreas.hansson@arm.com // We shouldn't ever get a block in ownership state 968948Sandreas.hansson@arm.com assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); 978948Sandreas.hansson@arm.com fetch->processCacheCompletion(pkt); 988707Sandreas.hansson@arm.com 998707Sandreas.hansson@arm.com return true; 1008707Sandreas.hansson@arm.com} 1018707Sandreas.hansson@arm.com 1028707Sandreas.hansson@arm.comtemplate<class Impl> 1038707Sandreas.hansson@arm.comvoid 1048707Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvRetry() 1058707Sandreas.hansson@arm.com{ 1068707Sandreas.hansson@arm.com fetch->recvRetry(); 1078707Sandreas.hansson@arm.com} 1088707Sandreas.hansson@arm.com 1098707Sandreas.hansson@arm.comtemplate <class Impl> 1108707Sandreas.hansson@arm.combool 1118975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt) 1128707Sandreas.hansson@arm.com{ 1138975Sandreas.hansson@arm.com return lsq->recvTimingResp(pkt); 1148707Sandreas.hansson@arm.com} 1158707Sandreas.hansson@arm.com 1168707Sandreas.hansson@arm.comtemplate <class Impl> 1178975Sandreas.hansson@arm.comvoid 1188975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 1198948Sandreas.hansson@arm.com{ 12010529Smorr@cs.wisc.edu // X86 ISA: Snooping an invalidation for monitor/mwait 12110529Smorr@cs.wisc.edu if(cpu->getCpuAddrMonitor()->doMonitor(pkt)) { 12210529Smorr@cs.wisc.edu cpu->wakeup(); 12310529Smorr@cs.wisc.edu } 1248975Sandreas.hansson@arm.com lsq->recvTimingSnoopReq(pkt); 1258948Sandreas.hansson@arm.com} 1268948Sandreas.hansson@arm.com 1278948Sandreas.hansson@arm.comtemplate <class Impl> 1288707Sandreas.hansson@arm.comvoid 1298707Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvRetry() 1308707Sandreas.hansson@arm.com{ 1318707Sandreas.hansson@arm.com lsq->recvRetry(); 1328707Sandreas.hansson@arm.com} 1338707Sandreas.hansson@arm.com 1341060SN/Atemplate <class Impl> 1351755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 1365606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 1371060SN/A{ 1381060SN/A} 1391060SN/A 1401060SN/Atemplate <class Impl> 1411060SN/Avoid 1421755SN/AFullO3CPU<Impl>::TickEvent::process() 1431060SN/A{ 1441060SN/A cpu->tick(); 1451060SN/A} 1461060SN/A 1471060SN/Atemplate <class Impl> 1481060SN/Aconst char * 1495336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 1501060SN/A{ 1514873Sstever@eecs.umich.edu return "FullO3CPU tick"; 1521060SN/A} 1531060SN/A 1541060SN/Atemplate <class Impl> 1555595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 1562733Sktlim@umich.edu : BaseO3CPU(params), 1573781Sgblack@eecs.umich.edu itb(params->itb), 1583781Sgblack@eecs.umich.edu dtb(params->dtb), 1591060SN/A tickEvent(this), 1605737Scws3k@cs.virginia.edu#ifndef NDEBUG 1615737Scws3k@cs.virginia.edu instcount(0), 1625737Scws3k@cs.virginia.edu#endif 1632292SN/A removeInstsThisCycle(false), 1645595Sgblack@eecs.umich.edu fetch(this, params), 1655595Sgblack@eecs.umich.edu decode(this, params), 1665595Sgblack@eecs.umich.edu rename(this, params), 1675595Sgblack@eecs.umich.edu iew(this, params), 1685595Sgblack@eecs.umich.edu commit(this, params), 1691060SN/A 1709915Ssteve.reinhardt@amd.com regFile(params->numPhysIntRegs, 1719920Syasuko.eckert@amd.com params->numPhysFloatRegs, 1729920Syasuko.eckert@amd.com params->numPhysCCRegs), 1731060SN/A 1749919Ssteve.reinhardt@amd.com freeList(name() + ".freelist", ®File), 1751060SN/A 1769954SFaissal.Sleiman@arm.com rob(this, params), 1771060SN/A 1789916Ssteve.reinhardt@amd.com scoreboard(name() + ".scoreboard", 1799916Ssteve.reinhardt@amd.com regFile.totalNumPhysRegs(), TheISA::NumMiscRegs, 1809916Ssteve.reinhardt@amd.com TheISA::ZeroReg, TheISA::ZeroReg), 1811060SN/A 1829384SAndreas.Sandberg@arm.com isa(numThreads, NULL), 1839384SAndreas.Sandberg@arm.com 1848707Sandreas.hansson@arm.com icachePort(&fetch, this), 1858707Sandreas.hansson@arm.com dcachePort(&iew.ldstQueue, this), 1868707Sandreas.hansson@arm.com 1872873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 1882873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 1892873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 1902873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 1912873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 1925804Snate@binkert.org activityRec(name(), NumStages, 1932873Sktlim@umich.edu params->backComSize + params->forwardComSize, 1942873Sktlim@umich.edu params->activity), 1951060SN/A 1961060SN/A globalSeqNum(1), 1972292SN/A system(params->system), 1989444SAndreas.Sandberg@ARM.com drainManager(NULL), 1999180Sandreas.hansson@arm.com lastRunningCycle(curCycle()) 2001060SN/A{ 2019433SAndreas.Sandberg@ARM.com if (!params->switched_out) { 2023221Sktlim@umich.edu _status = Running; 2033221Sktlim@umich.edu } else { 2049152Satgutier@umich.edu _status = SwitchedOut; 2053221Sktlim@umich.edu } 2061681SN/A 2072794Sktlim@umich.edu if (params->checker) { 2082316SN/A BaseCPU *temp_checker = params->checker; 2098733Sgeoffrey.blake@arm.com checker = dynamic_cast<Checker<Impl> *>(temp_checker); 2108707Sandreas.hansson@arm.com checker->setIcachePort(&icachePort); 2112316SN/A checker->setSystem(params->system); 2124598Sbinkertn@umich.edu } else { 2134598Sbinkertn@umich.edu checker = NULL; 2144598Sbinkertn@umich.edu } 2152316SN/A 2168793Sgblack@eecs.umich.edu if (!FullSystem) { 2178793Sgblack@eecs.umich.edu thread.resize(numThreads); 2188793Sgblack@eecs.umich.edu tids.resize(numThreads); 2198793Sgblack@eecs.umich.edu } 2201681SN/A 2212325SN/A // The stages also need their CPU pointer setup. However this 2222325SN/A // must be done at the upper level CPU because they have pointers 2232325SN/A // to the upper level CPU, and not this FullO3CPU. 2241060SN/A 2252292SN/A // Set up Pointers to the activeThreads list for each stage 2262292SN/A fetch.setActiveThreads(&activeThreads); 2272292SN/A decode.setActiveThreads(&activeThreads); 2282292SN/A rename.setActiveThreads(&activeThreads); 2292292SN/A iew.setActiveThreads(&activeThreads); 2302292SN/A commit.setActiveThreads(&activeThreads); 2311060SN/A 2321060SN/A // Give each of the stages the time buffer they will use. 2331060SN/A fetch.setTimeBuffer(&timeBuffer); 2341060SN/A decode.setTimeBuffer(&timeBuffer); 2351060SN/A rename.setTimeBuffer(&timeBuffer); 2361060SN/A iew.setTimeBuffer(&timeBuffer); 2371060SN/A commit.setTimeBuffer(&timeBuffer); 2381060SN/A 2391060SN/A // Also setup each of the stages' queues. 2401060SN/A fetch.setFetchQueue(&fetchQueue); 2411060SN/A decode.setFetchQueue(&fetchQueue); 2422292SN/A commit.setFetchQueue(&fetchQueue); 2431060SN/A decode.setDecodeQueue(&decodeQueue); 2441060SN/A rename.setDecodeQueue(&decodeQueue); 2451060SN/A rename.setRenameQueue(&renameQueue); 2461060SN/A iew.setRenameQueue(&renameQueue); 2471060SN/A iew.setIEWQueue(&iewQueue); 2481060SN/A commit.setIEWQueue(&iewQueue); 2491060SN/A commit.setRenameQueue(&renameQueue); 2501060SN/A 2512292SN/A commit.setIEWStage(&iew); 2522292SN/A rename.setIEWStage(&iew); 2532292SN/A rename.setCommitStage(&commit); 2542292SN/A 2558793Sgblack@eecs.umich.edu ThreadID active_threads; 2568793Sgblack@eecs.umich.edu if (FullSystem) { 2578793Sgblack@eecs.umich.edu active_threads = 1; 2588793Sgblack@eecs.umich.edu } else { 2598793Sgblack@eecs.umich.edu active_threads = params->workload.size(); 2602831Sksewell@umich.edu 2618793Sgblack@eecs.umich.edu if (active_threads > Impl::MaxThreads) { 2628793Sgblack@eecs.umich.edu panic("Workload Size too large. Increase the 'MaxThreads' " 2638793Sgblack@eecs.umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 2648793Sgblack@eecs.umich.edu "or edit your workload size."); 2658793Sgblack@eecs.umich.edu } 2662831Sksewell@umich.edu } 2672292SN/A 2682316SN/A //Make Sure That this a Valid Architeture 2692292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 2702292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 2719920Syasuko.eckert@amd.com assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs); 2722292SN/A 2732292SN/A rename.setScoreboard(&scoreboard); 2742292SN/A iew.setScoreboard(&scoreboard); 2752292SN/A 2761060SN/A // Setup the rename map for whichever stages need it. 2776221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2789384SAndreas.Sandberg@arm.com isa[tid] = params->isa[tid]; 2799384SAndreas.Sandberg@arm.com 2809919Ssteve.reinhardt@amd.com // Only Alpha has an FP zero register, so for other ISAs we 2819919Ssteve.reinhardt@amd.com // use an invalid FP register index to avoid special treatment 2829919Ssteve.reinhardt@amd.com // of any valid FP reg. 2839919Ssteve.reinhardt@amd.com RegIndex invalidFPReg = TheISA::NumFloatRegs + 1; 2849919Ssteve.reinhardt@amd.com RegIndex fpZeroReg = 2859919Ssteve.reinhardt@amd.com (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg; 2862292SN/A 2879919Ssteve.reinhardt@amd.com commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 2889919Ssteve.reinhardt@amd.com &freeList); 2892292SN/A 2909919Ssteve.reinhardt@amd.com renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 2919919Ssteve.reinhardt@amd.com &freeList); 2922292SN/A } 2932292SN/A 2949919Ssteve.reinhardt@amd.com // Initialize rename map to assign physical registers to the 2959919Ssteve.reinhardt@amd.com // architectural registers for active threads only. 2969919Ssteve.reinhardt@amd.com for (ThreadID tid = 0; tid < active_threads; tid++) { 2979919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) { 2989919Ssteve.reinhardt@amd.com // Note that we can't use the rename() method because we don't 2999919Ssteve.reinhardt@amd.com // want special treatment for the zero register at this point 3009919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = freeList.getIntReg(); 3019919Ssteve.reinhardt@amd.com renameMap[tid].setIntEntry(ridx, phys_reg); 3029919Ssteve.reinhardt@amd.com commitRenameMap[tid].setIntEntry(ridx, phys_reg); 3039919Ssteve.reinhardt@amd.com } 3049919Ssteve.reinhardt@amd.com 3059919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) { 3069919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = freeList.getFloatReg(); 3079919Ssteve.reinhardt@amd.com renameMap[tid].setFloatEntry(ridx, phys_reg); 3089919Ssteve.reinhardt@amd.com commitRenameMap[tid].setFloatEntry(ridx, phys_reg); 3099919Ssteve.reinhardt@amd.com } 3109920Syasuko.eckert@amd.com 3119920Syasuko.eckert@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) { 3129920Syasuko.eckert@amd.com PhysRegIndex phys_reg = freeList.getCCReg(); 3139920Syasuko.eckert@amd.com renameMap[tid].setCCEntry(ridx, phys_reg); 3149920Syasuko.eckert@amd.com commitRenameMap[tid].setCCEntry(ridx, phys_reg); 3159920Syasuko.eckert@amd.com } 3169919Ssteve.reinhardt@amd.com } 3179919Ssteve.reinhardt@amd.com 3182292SN/A rename.setRenameMap(renameMap); 3192292SN/A commit.setRenameMap(commitRenameMap); 3201060SN/A rename.setFreeList(&freeList); 3212292SN/A 3221060SN/A // Setup the ROB for whichever stages need it. 3231060SN/A commit.setROB(&rob); 3242292SN/A 3259158Sandreas.hansson@arm.com lastActivatedCycle = 0; 3266221Snate@binkert.org#if 0 3273093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3286221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3296221Snate@binkert.org globalSeqNum[tid] = 1; 3306221Snate@binkert.org#endif 3313093Sksewell@umich.edu 3325595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3335595Sgblack@eecs.umich.edu 3345595Sgblack@eecs.umich.edu // Setup any thread state. 3355595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 3365595Sgblack@eecs.umich.edu 3376221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 3388793Sgblack@eecs.umich.edu if (FullSystem) { 3398793Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 3408793Sgblack@eecs.umich.edu assert(this->numThreads == 1); 3418793Sgblack@eecs.umich.edu this->thread[tid] = new Thread(this, 0, NULL); 3428793Sgblack@eecs.umich.edu } else { 3438793Sgblack@eecs.umich.edu if (tid < params->workload.size()) { 3448793Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 3458793Sgblack@eecs.umich.edu tid, this->thread[tid]); 3468793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3478793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3488793Sgblack@eecs.umich.edu tid, params->workload[tid]); 3495595Sgblack@eecs.umich.edu 3508793Sgblack@eecs.umich.edu //usedTids[tid] = true; 3518793Sgblack@eecs.umich.edu //threadMap[tid] = tid; 3528793Sgblack@eecs.umich.edu } else { 3538793Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 3548793Sgblack@eecs.umich.edu //when scheduling threads to CPU 3558793Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 3565595Sgblack@eecs.umich.edu 3578793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 3588793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 3598793Sgblack@eecs.umich.edu tid, dummy_proc); 3608793Sgblack@eecs.umich.edu //usedTids[tid] = false; 3618793Sgblack@eecs.umich.edu } 3625595Sgblack@eecs.umich.edu } 3635595Sgblack@eecs.umich.edu 3645595Sgblack@eecs.umich.edu ThreadContext *tc; 3655595Sgblack@eecs.umich.edu 3665595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 3675595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 3685595Sgblack@eecs.umich.edu 3695595Sgblack@eecs.umich.edu tc = o3_tc; 3705595Sgblack@eecs.umich.edu 3715595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 3725595Sgblack@eecs.umich.edu // CheckerThreadContext. 3735595Sgblack@eecs.umich.edu if (params->checker) { 3745595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 3755595Sgblack@eecs.umich.edu o3_tc, this->checker); 3765595Sgblack@eecs.umich.edu } 3775595Sgblack@eecs.umich.edu 3785595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 3795595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 3806221Snate@binkert.org o3_tc->thread = this->thread[tid]; 3815595Sgblack@eecs.umich.edu 3828793Sgblack@eecs.umich.edu if (FullSystem) { 3838793Sgblack@eecs.umich.edu // Setup quiesce event. 3848793Sgblack@eecs.umich.edu this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 3858793Sgblack@eecs.umich.edu } 3865595Sgblack@eecs.umich.edu // Give the thread the TC. 3876221Snate@binkert.org this->thread[tid]->tc = tc; 3885595Sgblack@eecs.umich.edu 3895595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 3905595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 3915595Sgblack@eecs.umich.edu } 3925595Sgblack@eecs.umich.edu 3938876Sandreas.hansson@arm.com // FullO3CPU always requires an interrupt controller. 3949433SAndreas.Sandberg@ARM.com if (!params->switched_out && !interrupts) { 3958876Sandreas.hansson@arm.com fatal("FullO3CPU %s has no interrupt controller.\n" 3968876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 3978876Sandreas.hansson@arm.com } 3988876Sandreas.hansson@arm.com 3996221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4006221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4011060SN/A} 4021060SN/A 4031060SN/Atemplate <class Impl> 4041755SN/AFullO3CPU<Impl>::~FullO3CPU() 4051060SN/A{ 4061060SN/A} 4071060SN/A 4081060SN/Atemplate <class Impl> 4091060SN/Avoid 41010023Smatt.horsnell@ARM.comFullO3CPU<Impl>::regProbePoints() 41110023Smatt.horsnell@ARM.com{ 41210464SAndreas.Sandberg@ARM.com BaseCPU::regProbePoints(); 41310464SAndreas.Sandberg@ARM.com 41410023Smatt.horsnell@ARM.com ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete"); 41510023Smatt.horsnell@ARM.com ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete"); 41610464SAndreas.Sandberg@ARM.com 41710023Smatt.horsnell@ARM.com fetch.regProbePoints(); 41810023Smatt.horsnell@ARM.com iew.regProbePoints(); 41910023Smatt.horsnell@ARM.com commit.regProbePoints(); 42010023Smatt.horsnell@ARM.com} 42110023Smatt.horsnell@ARM.com 42210023Smatt.horsnell@ARM.comtemplate <class Impl> 42310023Smatt.horsnell@ARM.comvoid 4245595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4251062SN/A{ 4262733Sktlim@umich.edu BaseO3CPU::regStats(); 4272292SN/A 4282733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4292292SN/A timesIdled 4302292SN/A .name(name() + ".timesIdled") 4312292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4322292SN/A " unscheduled itself") 4332292SN/A .prereq(timesIdled); 4342292SN/A 4352292SN/A idleCycles 4362292SN/A .name(name() + ".idleCycles") 4372292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4382292SN/A "to idling") 4392292SN/A .prereq(idleCycles); 4402292SN/A 4418627SAli.Saidi@ARM.com quiesceCycles 4428627SAli.Saidi@ARM.com .name(name() + ".quiesceCycles") 4438627SAli.Saidi@ARM.com .desc("Total number of cycles that CPU has spent quiesced or waiting " 4448627SAli.Saidi@ARM.com "for an interrupt") 4458627SAli.Saidi@ARM.com .prereq(quiesceCycles); 4468627SAli.Saidi@ARM.com 4472292SN/A // Number of Instructions simulated 4482292SN/A // -------------------------------- 4492292SN/A // Should probably be in Base CPU but need templated 4502292SN/A // MaxThreads so put in here instead 4512292SN/A committedInsts 4522292SN/A .init(numThreads) 4532292SN/A .name(name() + ".committedInsts") 45410225Snilay@cs.wisc.edu .desc("Number of Instructions Simulated") 45510225Snilay@cs.wisc.edu .flags(Stats::total); 4562292SN/A 4578834Satgutier@umich.edu committedOps 4588834Satgutier@umich.edu .init(numThreads) 4598834Satgutier@umich.edu .name(name() + ".committedOps") 46010225Snilay@cs.wisc.edu .desc("Number of Ops (including micro ops) Simulated") 46110225Snilay@cs.wisc.edu .flags(Stats::total); 4622292SN/A 4632292SN/A cpi 4642292SN/A .name(name() + ".cpi") 4652292SN/A .desc("CPI: Cycles Per Instruction") 4662292SN/A .precision(6); 4674392Sktlim@umich.edu cpi = numCycles / committedInsts; 4682292SN/A 4692292SN/A totalCpi 4702292SN/A .name(name() + ".cpi_total") 4712292SN/A .desc("CPI: Total CPI of All Threads") 4722292SN/A .precision(6); 47310225Snilay@cs.wisc.edu totalCpi = numCycles / sum(committedInsts); 4742292SN/A 4752292SN/A ipc 4762292SN/A .name(name() + ".ipc") 4772292SN/A .desc("IPC: Instructions Per Cycle") 4782292SN/A .precision(6); 4794392Sktlim@umich.edu ipc = committedInsts / numCycles; 4802292SN/A 4812292SN/A totalIpc 4822292SN/A .name(name() + ".ipc_total") 4832292SN/A .desc("IPC: Total IPC of All Threads") 4842292SN/A .precision(6); 48510225Snilay@cs.wisc.edu totalIpc = sum(committedInsts) / numCycles; 4862292SN/A 4875595Sgblack@eecs.umich.edu this->fetch.regStats(); 4885595Sgblack@eecs.umich.edu this->decode.regStats(); 4895595Sgblack@eecs.umich.edu this->rename.regStats(); 4905595Sgblack@eecs.umich.edu this->iew.regStats(); 4915595Sgblack@eecs.umich.edu this->commit.regStats(); 4927897Shestness@cs.utexas.edu this->rob.regStats(); 4937897Shestness@cs.utexas.edu 4947897Shestness@cs.utexas.edu intRegfileReads 4957897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 4967897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 4977897Shestness@cs.utexas.edu .prereq(intRegfileReads); 4987897Shestness@cs.utexas.edu 4997897Shestness@cs.utexas.edu intRegfileWrites 5007897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 5017897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 5027897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 5037897Shestness@cs.utexas.edu 5047897Shestness@cs.utexas.edu fpRegfileReads 5057897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 5067897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 5077897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 5087897Shestness@cs.utexas.edu 5097897Shestness@cs.utexas.edu fpRegfileWrites 5107897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 5117897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 5127897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 5137897Shestness@cs.utexas.edu 5149920Syasuko.eckert@amd.com ccRegfileReads 5159920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_reads") 5169920Syasuko.eckert@amd.com .desc("number of cc regfile reads") 5179920Syasuko.eckert@amd.com .prereq(ccRegfileReads); 5189920Syasuko.eckert@amd.com 5199920Syasuko.eckert@amd.com ccRegfileWrites 5209920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_writes") 5219920Syasuko.eckert@amd.com .desc("number of cc regfile writes") 5229920Syasuko.eckert@amd.com .prereq(ccRegfileWrites); 5239920Syasuko.eckert@amd.com 5247897Shestness@cs.utexas.edu miscRegfileReads 5257897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5267897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5277897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5287897Shestness@cs.utexas.edu 5297897Shestness@cs.utexas.edu miscRegfileWrites 5307897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5317897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5327897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5331062SN/A} 5341062SN/A 5351062SN/Atemplate <class Impl> 5361062SN/Avoid 5371755SN/AFullO3CPU<Impl>::tick() 5381060SN/A{ 5392733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5409444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 5419444SAndreas.Sandberg@ARM.com assert(getDrainState() != Drainable::Drained); 5421060SN/A 5432292SN/A ++numCycles; 54410464SAndreas.Sandberg@ARM.com ppCycles->notify(1); 5452292SN/A 5462325SN/A// activity = false; 5472292SN/A 5482292SN/A //Tick each of the stages 5491060SN/A fetch.tick(); 5501060SN/A 5511060SN/A decode.tick(); 5521060SN/A 5531060SN/A rename.tick(); 5541060SN/A 5551060SN/A iew.tick(); 5561060SN/A 5571060SN/A commit.tick(); 5581060SN/A 5592292SN/A // Now advance the time buffers 5601060SN/A timeBuffer.advance(); 5611060SN/A 5621060SN/A fetchQueue.advance(); 5631060SN/A decodeQueue.advance(); 5641060SN/A renameQueue.advance(); 5651060SN/A iewQueue.advance(); 5661060SN/A 5672325SN/A activityRec.advance(); 5682292SN/A 5692292SN/A if (removeInstsThisCycle) { 5702292SN/A cleanUpRemovedInsts(); 5712292SN/A } 5722292SN/A 5732325SN/A if (!tickEvent.scheduled()) { 5749444SAndreas.Sandberg@ARM.com if (_status == SwitchedOut) { 5753226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 5762325SN/A // increment stat 5779179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 5783221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 5793226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 5809179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 5812325SN/A timesIdled++; 5822325SN/A } else { 5839180Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(Cycles(1))); 5843226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 5852325SN/A } 5862292SN/A } 5872292SN/A 5888793Sgblack@eecs.umich.edu if (!FullSystem) 5898793Sgblack@eecs.umich.edu updateThreadPriority(); 5909444SAndreas.Sandberg@ARM.com 5919444SAndreas.Sandberg@ARM.com tryDrain(); 5921060SN/A} 5931060SN/A 5941060SN/Atemplate <class Impl> 5951060SN/Avoid 5961755SN/AFullO3CPU<Impl>::init() 5971060SN/A{ 5985714Shsul@eecs.umich.edu BaseCPU::init(); 5991060SN/A 6008921Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 6019382SAli.Saidi@ARM.com // Set noSquashFromTC so that the CPU doesn't squash when initially 6028921Sandreas.hansson@arm.com // setting up registers. 6039382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = true; 6048921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 6058921Sandreas.hansson@arm.com thread[tid]->initMemProxies(thread[tid]->getTC()); 6068921Sandreas.hansson@arm.com } 6072292SN/A 6089433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 6098793Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 6108793Sgblack@eecs.umich.edu ThreadContext *src_tc = threadContexts[tid]; 6118793Sgblack@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 6128793Sgblack@eecs.umich.edu } 6136034Ssteve.reinhardt@amd.com } 6142292SN/A 6159382SAli.Saidi@ARM.com // Clear noSquashFromTC. 6166221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6179382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6182292SN/A 6199427SAndreas.Sandberg@ARM.com commit.setThreads(thread); 6209427SAndreas.Sandberg@ARM.com} 6212292SN/A 6229427SAndreas.Sandberg@ARM.comtemplate <class Impl> 6239427SAndreas.Sandberg@ARM.comvoid 6249427SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::startup() 6259427SAndreas.Sandberg@ARM.com{ 6269992Snilay@cs.wisc.edu BaseCPU::startup(); 6279461Snilay@cs.wisc.edu for (int tid = 0; tid < numThreads; ++tid) 6289461Snilay@cs.wisc.edu isa[tid]->startup(threadContexts[tid]); 6299461Snilay@cs.wisc.edu 6309427SAndreas.Sandberg@ARM.com fetch.startupStage(); 6319444SAndreas.Sandberg@ARM.com decode.startupStage(); 6329427SAndreas.Sandberg@ARM.com iew.startupStage(); 6339427SAndreas.Sandberg@ARM.com rename.startupStage(); 6349427SAndreas.Sandberg@ARM.com commit.startupStage(); 6352292SN/A} 6362292SN/A 6372292SN/Atemplate <class Impl> 6382292SN/Avoid 6396221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 6402875Sksewell@umich.edu{ 6416221Snate@binkert.org list<ThreadID>::iterator isActive = 6425314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6432875Sksewell@umich.edu 6443226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 6459444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 6463226Sktlim@umich.edu 6472875Sksewell@umich.edu if (isActive == activeThreads.end()) { 6482875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 6492875Sksewell@umich.edu tid); 6502875Sksewell@umich.edu 6512875Sksewell@umich.edu activeThreads.push_back(tid); 6522875Sksewell@umich.edu } 6532875Sksewell@umich.edu} 6542875Sksewell@umich.edu 6552875Sksewell@umich.edutemplate <class Impl> 6562875Sksewell@umich.eduvoid 6576221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 6582875Sksewell@umich.edu{ 6592875Sksewell@umich.edu //Remove From Active List, if Active 6606221Snate@binkert.org list<ThreadID>::iterator thread_it = 6615314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 6622875Sksewell@umich.edu 6633226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 6649444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 6653226Sktlim@umich.edu 6662875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 6672875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 6682875Sksewell@umich.edu tid); 6692875Sksewell@umich.edu activeThreads.erase(thread_it); 6702875Sksewell@umich.edu } 67110331Smitch.hayenga@arm.com 67210331Smitch.hayenga@arm.com fetch.deactivateThread(tid); 67310331Smitch.hayenga@arm.com commit.deactivateThread(tid); 6742875Sksewell@umich.edu} 6752875Sksewell@umich.edu 6762875Sksewell@umich.edutemplate <class Impl> 6776221Snate@binkert.orgCounter 6788834Satgutier@umich.eduFullO3CPU<Impl>::totalInsts() const 6796221Snate@binkert.org{ 6806221Snate@binkert.org Counter total(0); 6816221Snate@binkert.org 6826221Snate@binkert.org ThreadID size = thread.size(); 6836221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 6846221Snate@binkert.org total += thread[i]->numInst; 6856221Snate@binkert.org 6866221Snate@binkert.org return total; 6876221Snate@binkert.org} 6886221Snate@binkert.org 6896221Snate@binkert.orgtemplate <class Impl> 6908834Satgutier@umich.eduCounter 6918834Satgutier@umich.eduFullO3CPU<Impl>::totalOps() const 6928834Satgutier@umich.edu{ 6938834Satgutier@umich.edu Counter total(0); 6948834Satgutier@umich.edu 6958834Satgutier@umich.edu ThreadID size = thread.size(); 6968834Satgutier@umich.edu for (ThreadID i = 0; i < size; i++) 6978834Satgutier@umich.edu total += thread[i]->numOp; 6988834Satgutier@umich.edu 6998834Satgutier@umich.edu return total; 7008834Satgutier@umich.edu} 7018834Satgutier@umich.edu 7028834Satgutier@umich.edutemplate <class Impl> 7032875Sksewell@umich.eduvoid 70410407Smitch.hayenga@arm.comFullO3CPU<Impl>::activateContext(ThreadID tid) 7052875Sksewell@umich.edu{ 7069444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 7079444SAndreas.Sandberg@ARM.com 7082875Sksewell@umich.edu // Needs to set each stage to running as well. 70910407Smitch.hayenga@arm.com activateThread(tid); 7102875Sksewell@umich.edu 7119444SAndreas.Sandberg@ARM.com // We don't want to wake the CPU if it is drained. In that case, 7129444SAndreas.Sandberg@ARM.com // we just want to flag the thread as active and schedule the tick 7139444SAndreas.Sandberg@ARM.com // event from drainResume() instead. 7149444SAndreas.Sandberg@ARM.com if (getDrainState() == Drainable::Drained) 7159444SAndreas.Sandberg@ARM.com return; 7169444SAndreas.Sandberg@ARM.com 7179158Sandreas.hansson@arm.com // If we are time 0 or if the last activation time is in the past, 7189158Sandreas.hansson@arm.com // schedule the next tick and wake up the fetch unit 7199158Sandreas.hansson@arm.com if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) { 72010407Smitch.hayenga@arm.com scheduleTickEvent(Cycles(0)); 7212875Sksewell@umich.edu 7222875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 7232875Sksewell@umich.edu // deschedule itself. 7242875Sksewell@umich.edu activityRec.activity(); 7252875Sksewell@umich.edu fetch.wakeFromQuiesce(); 7262875Sksewell@umich.edu 7279180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 7289180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 7299179Sandreas.hansson@arm.com if (cycles != 0) 7309179Sandreas.hansson@arm.com --cycles; 7319179Sandreas.hansson@arm.com quiesceCycles += cycles; 7328627SAli.Saidi@ARM.com 7337823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 7342875Sksewell@umich.edu 7352875Sksewell@umich.edu _status = Running; 7362875Sksewell@umich.edu } 7372875Sksewell@umich.edu} 7382875Sksewell@umich.edu 7392875Sksewell@umich.edutemplate <class Impl> 74010407Smitch.hayenga@arm.comvoid 7416221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 7422875Sksewell@umich.edu{ 7432875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 7449444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 74510408Smitch.hayenga@arm.com 74610408Smitch.hayenga@arm.com deactivateThread(tid); 74710407Smitch.hayenga@arm.com 7483221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 74910407Smitch.hayenga@arm.com if (activeThreads.size() == 0) 7502910Sksewell@umich.edu unscheduleTickEvent(); 7518627SAli.Saidi@ARM.com 7528627SAli.Saidi@ARM.com DPRINTF(Quiesce, "Suspending Context\n"); 7539179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 7542875Sksewell@umich.edu _status = Idle; 7552875Sksewell@umich.edu} 7562875Sksewell@umich.edu 7572875Sksewell@umich.edutemplate <class Impl> 7582875Sksewell@umich.eduvoid 7596221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 7602875Sksewell@umich.edu{ 7612910Sksewell@umich.edu //For now, this is the same as deallocate 7622910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 7639444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 76410408Smitch.hayenga@arm.com 76510408Smitch.hayenga@arm.com deactivateThread(tid); 76610408Smitch.hayenga@arm.com removeThread(tid); 7672875Sksewell@umich.edu} 7682875Sksewell@umich.edu 7692875Sksewell@umich.edutemplate <class Impl> 7702875Sksewell@umich.eduvoid 7716221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 7722292SN/A{ 7732847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 7742292SN/A // Will change now that the PC and thread state is internal to the CPU 7752683Sktlim@umich.edu // and not in the ThreadContext. 7768793Sgblack@eecs.umich.edu ThreadContext *src_tc; 7778793Sgblack@eecs.umich.edu if (FullSystem) 7788793Sgblack@eecs.umich.edu src_tc = system->threadContexts[tid]; 7798793Sgblack@eecs.umich.edu else 7808793Sgblack@eecs.umich.edu src_tc = tcBase(tid); 7812292SN/A 7822292SN/A //Bind Int Regs to Rename Map 7832292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 7842292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 7852292SN/A 7862292SN/A renameMap[tid].setEntry(ireg,phys_reg); 7872292SN/A scoreboard.setReg(phys_reg); 7882292SN/A } 7892292SN/A 7902292SN/A //Bind Float Regs to Rename Map 7919920Syasuko.eckert@amd.com int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs; 7929920Syasuko.eckert@amd.com for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) { 7932292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 7942292SN/A 7952292SN/A renameMap[tid].setEntry(freg,phys_reg); 7962292SN/A scoreboard.setReg(phys_reg); 7972292SN/A } 7982292SN/A 7999920Syasuko.eckert@amd.com //Bind condition-code Regs to Rename Map 8009920Syasuko.eckert@amd.com max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs; 8019920Syasuko.eckert@amd.com for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs; 8029920Syasuko.eckert@amd.com creg < max_reg; creg++) { 8039920Syasuko.eckert@amd.com PhysRegIndex phys_reg = freeList.getCCReg(); 8049920Syasuko.eckert@amd.com 8059920Syasuko.eckert@amd.com renameMap[tid].setEntry(creg,phys_reg); 8069920Syasuko.eckert@amd.com scoreboard.setReg(phys_reg); 8079920Syasuko.eckert@amd.com } 8089920Syasuko.eckert@amd.com 8092292SN/A //Copy Thread Data Into RegFile 8102847Sksewell@umich.edu //this->copyFromTC(tid); 8112292SN/A 8122847Sksewell@umich.edu //Set PC/NPC/NNPC 8137720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 8142292SN/A 8152680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 8162292SN/A 81710407Smitch.hayenga@arm.com activateContext(tid); 8182292SN/A 8192292SN/A //Reset ROB/IQ/LSQ Entries 8202292SN/A commit.rob->resetEntries(); 8212292SN/A iew.resetEntries(); 8222292SN/A} 8232292SN/A 8242292SN/Atemplate <class Impl> 8252292SN/Avoid 8266221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 8272292SN/A{ 8282877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 8292847Sksewell@umich.edu 8302847Sksewell@umich.edu // Copy Thread Data From RegFile 8312847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 8325364Sksewell@umich.edu // this->copyToTC(tid); 8335364Sksewell@umich.edu 8345364Sksewell@umich.edu 8355364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 8365364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 8375364Sksewell@umich.edu // in SMT workloads. 8382847Sksewell@umich.edu 8392847Sksewell@umich.edu // Unbind Int Regs from Rename Map 8402292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 8412292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 8422292SN/A scoreboard.unsetReg(phys_reg); 8432292SN/A freeList.addReg(phys_reg); 8442292SN/A } 8452292SN/A 8462847Sksewell@umich.edu // Unbind Float Regs from Rename Map 84710487Snilay@cs.wisc.edu int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs; 84810487Snilay@cs.wisc.edu for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) { 8492292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 8502292SN/A scoreboard.unsetReg(phys_reg); 8512292SN/A freeList.addReg(phys_reg); 8522292SN/A } 8532292SN/A 8549920Syasuko.eckert@amd.com // Unbind condition-code Regs from Rename Map 85510487Snilay@cs.wisc.edu max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs; 85610487Snilay@cs.wisc.edu for (int creg = TheISA::CC_Reg_Base; creg < max_reg; creg++) { 8579920Syasuko.eckert@amd.com PhysRegIndex phys_reg = renameMap[tid].lookup(creg); 8589920Syasuko.eckert@amd.com scoreboard.unsetReg(phys_reg); 8599920Syasuko.eckert@amd.com freeList.addReg(phys_reg); 8609920Syasuko.eckert@amd.com } 8619920Syasuko.eckert@amd.com 8622847Sksewell@umich.edu // Squash Throughout Pipeline 8638138SAli.Saidi@ARM.com DynInstPtr inst = commit.rob->readHeadInst(tid); 8648138SAli.Saidi@ARM.com InstSeqNum squash_seq_num = inst->seqNum; 8658138SAli.Saidi@ARM.com fetch.squash(0, squash_seq_num, inst, tid); 8662292SN/A decode.squash(tid); 8672935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 8682875Sksewell@umich.edu iew.squash(tid); 8695363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 8702935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 8712292SN/A 8725362Sksewell@umich.edu 8735362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 8742292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 8752292SN/A 8762847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 8773229Sktlim@umich.edu 8783229Sktlim@umich.edu // Commented out for now. This should be possible to do by 8793229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 8803229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 8813229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 8823229Sktlim@umich.edu/* 8832292SN/A if (activeThreads.size() >= 1) { 8842292SN/A commit.rob->resetEntries(); 8852292SN/A iew.resetEntries(); 8862292SN/A } 8873229Sktlim@umich.edu*/ 8882292SN/A} 8892292SN/A 8904192Sktlim@umich.edutemplate <class Impl> 8915595Sgblack@eecs.umich.eduFault 8926221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 8935702Ssaidi@eecs.umich.edu{ 8945702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 8955702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 8965702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 8975702Ssaidi@eecs.umich.edu 8985702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 8995702Ssaidi@eecs.umich.edu 9005702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 9015702Ssaidi@eecs.umich.edu#endif 9025702Ssaidi@eecs.umich.edu return NoFault; 9035702Ssaidi@eecs.umich.edu} 9045702Ssaidi@eecs.umich.edu 9055702Ssaidi@eecs.umich.edutemplate <class Impl> 9065702Ssaidi@eecs.umich.edubool 9076221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 9085702Ssaidi@eecs.umich.edu{ 9095702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 9105702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 9115702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 9125702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 9135702Ssaidi@eecs.umich.edu 9145702Ssaidi@eecs.umich.edu switch (palFunc) { 9155702Ssaidi@eecs.umich.edu case PAL::halt: 9165702Ssaidi@eecs.umich.edu halt(); 9175702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 9185702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 9195702Ssaidi@eecs.umich.edu break; 9205702Ssaidi@eecs.umich.edu 9215702Ssaidi@eecs.umich.edu case PAL::bpt: 9225702Ssaidi@eecs.umich.edu case PAL::bugchk: 9235702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 9245702Ssaidi@eecs.umich.edu return false; 9255702Ssaidi@eecs.umich.edu break; 9265702Ssaidi@eecs.umich.edu } 9275702Ssaidi@eecs.umich.edu#endif 9285702Ssaidi@eecs.umich.edu return true; 9295702Ssaidi@eecs.umich.edu} 9305702Ssaidi@eecs.umich.edu 9315702Ssaidi@eecs.umich.edutemplate <class Impl> 9325702Ssaidi@eecs.umich.eduFault 9335595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 9345595Sgblack@eecs.umich.edu{ 9355595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 9365647Sgblack@eecs.umich.edu return this->interrupts->getInterrupt(this->threadContexts[0]); 9375595Sgblack@eecs.umich.edu} 9385595Sgblack@eecs.umich.edu 9395595Sgblack@eecs.umich.edutemplate <class Impl> 9405595Sgblack@eecs.umich.eduvoid 94110379Sandreas.hansson@arm.comFullO3CPU<Impl>::processInterrupts(const Fault &interrupt) 9425595Sgblack@eecs.umich.edu{ 9435595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 9445595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 9455595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 9465595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 9475595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 9485595Sgblack@eecs.umich.edu 9495595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 9505647Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 9515595Sgblack@eecs.umich.edu 9525595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 95310417Sandreas.hansson@arm.com this->trap(interrupt, 0, nullptr); 9545595Sgblack@eecs.umich.edu} 9555595Sgblack@eecs.umich.edu 9561060SN/Atemplate <class Impl> 9572852Sktlim@umich.eduvoid 95810417Sandreas.hansson@arm.comFullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid, 95910417Sandreas.hansson@arm.com const StaticInstPtr &inst) 9605595Sgblack@eecs.umich.edu{ 9615595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 9627684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 9635595Sgblack@eecs.umich.edu} 9645595Sgblack@eecs.umich.edu 9655595Sgblack@eecs.umich.edutemplate <class Impl> 9665595Sgblack@eecs.umich.eduvoid 9676221Snate@binkert.orgFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 9685595Sgblack@eecs.umich.edu{ 9695595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 9705595Sgblack@eecs.umich.edu 9715595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 9725595Sgblack@eecs.umich.edu 9735595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 9745595Sgblack@eecs.umich.edu // instruction. 9755595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 9765595Sgblack@eecs.umich.edu 9775595Sgblack@eecs.umich.edu // Execute the actual syscall. 9785595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 9795595Sgblack@eecs.umich.edu 9805595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 9815595Sgblack@eecs.umich.edu // incrementing it. 9825595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 9835595Sgblack@eecs.umich.edu} 9845595Sgblack@eecs.umich.edu 9855595Sgblack@eecs.umich.edutemplate <class Impl> 9865595Sgblack@eecs.umich.eduvoid 9879448SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::serializeThread(std::ostream &os, ThreadID tid) 9882864Sktlim@umich.edu{ 9899448SAndreas.Sandberg@ARM.com thread[tid]->serialize(os); 9902864Sktlim@umich.edu} 9912864Sktlim@umich.edu 9922864Sktlim@umich.edutemplate <class Impl> 9932864Sktlim@umich.eduvoid 9949448SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::unserializeThread(Checkpoint *cp, const std::string §ion, 9959448SAndreas.Sandberg@ARM.com ThreadID tid) 9962864Sktlim@umich.edu{ 9979448SAndreas.Sandberg@ARM.com thread[tid]->unserialize(cp, section); 9982864Sktlim@umich.edu} 9992864Sktlim@umich.edu 10002864Sktlim@umich.edutemplate <class Impl> 10012905Sktlim@umich.eduunsigned int 10029342SAndreas.Sandberg@arm.comFullO3CPU<Impl>::drain(DrainManager *drain_manager) 10031060SN/A{ 10049444SAndreas.Sandberg@ARM.com // If the CPU isn't doing anything, then return immediately. 10059444SAndreas.Sandberg@ARM.com if (switchedOut()) { 10069444SAndreas.Sandberg@ARM.com setDrainState(Drainable::Drained); 10079444SAndreas.Sandberg@ARM.com return 0; 10089444SAndreas.Sandberg@ARM.com } 10093512Sktlim@umich.edu 10109444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Draining...\n"); 10119444SAndreas.Sandberg@ARM.com setDrainState(Drainable::Draining); 10123512Sktlim@umich.edu 10139444SAndreas.Sandberg@ARM.com // We only need to signal a drain to the commit stage as this 10149444SAndreas.Sandberg@ARM.com // initiates squashing controls the draining. Once the commit 10159444SAndreas.Sandberg@ARM.com // stage commits an instruction where it is safe to stop, it'll 10169444SAndreas.Sandberg@ARM.com // squash the rest of the instructions in the pipeline and force 10179444SAndreas.Sandberg@ARM.com // the fetch stage to stall. The pipeline will be drained once all 10189444SAndreas.Sandberg@ARM.com // in-flight instructions have retired. 10192843Sktlim@umich.edu commit.drain(); 10202325SN/A 10212325SN/A // Wake the CPU and record activity so everything can drain out if 10222863Sktlim@umich.edu // the CPU was not able to immediately drain. 10239444SAndreas.Sandberg@ARM.com if (!isDrained()) { 10249342SAndreas.Sandberg@arm.com drainManager = drain_manager; 10252843Sktlim@umich.edu 10262863Sktlim@umich.edu wakeCPU(); 10272863Sktlim@umich.edu activityRec.activity(); 10282852Sktlim@umich.edu 10299152Satgutier@umich.edu DPRINTF(Drain, "CPU not drained\n"); 10309152Satgutier@umich.edu 10312905Sktlim@umich.edu return 1; 10322863Sktlim@umich.edu } else { 10339444SAndreas.Sandberg@ARM.com setDrainState(Drainable::Drained); 10349444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU is already drained\n"); 10359444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 10369444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 10379444SAndreas.Sandberg@ARM.com 10389444SAndreas.Sandberg@ARM.com // Flush out any old data from the time buffers. In 10399444SAndreas.Sandberg@ARM.com // particular, there might be some data in flight from the 10409444SAndreas.Sandberg@ARM.com // fetch stage that isn't visible in any of the CPU buffers we 10419444SAndreas.Sandberg@ARM.com // test in isDrained(). 10429444SAndreas.Sandberg@ARM.com for (int i = 0; i < timeBuffer.getSize(); ++i) { 10439444SAndreas.Sandberg@ARM.com timeBuffer.advance(); 10449444SAndreas.Sandberg@ARM.com fetchQueue.advance(); 10459444SAndreas.Sandberg@ARM.com decodeQueue.advance(); 10469444SAndreas.Sandberg@ARM.com renameQueue.advance(); 10479444SAndreas.Sandberg@ARM.com iewQueue.advance(); 10489444SAndreas.Sandberg@ARM.com } 10499444SAndreas.Sandberg@ARM.com 10509444SAndreas.Sandberg@ARM.com drainSanityCheck(); 10512905Sktlim@umich.edu return 0; 10522863Sktlim@umich.edu } 10532316SN/A} 10542310SN/A 10552316SN/Atemplate <class Impl> 10569444SAndreas.Sandberg@ARM.combool 10579444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::tryDrain() 10589444SAndreas.Sandberg@ARM.com{ 10599444SAndreas.Sandberg@ARM.com if (!drainManager || !isDrained()) 10609444SAndreas.Sandberg@ARM.com return false; 10619444SAndreas.Sandberg@ARM.com 10629444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 10639444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 10649444SAndreas.Sandberg@ARM.com 10659444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 10669444SAndreas.Sandberg@ARM.com drainManager->signalDrainDone(); 10679444SAndreas.Sandberg@ARM.com drainManager = NULL; 10689444SAndreas.Sandberg@ARM.com 10699444SAndreas.Sandberg@ARM.com return true; 10709444SAndreas.Sandberg@ARM.com} 10719444SAndreas.Sandberg@ARM.com 10729444SAndreas.Sandberg@ARM.comtemplate <class Impl> 10739444SAndreas.Sandberg@ARM.comvoid 10749444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::drainSanityCheck() const 10759444SAndreas.Sandberg@ARM.com{ 10769444SAndreas.Sandberg@ARM.com assert(isDrained()); 10779444SAndreas.Sandberg@ARM.com fetch.drainSanityCheck(); 10789444SAndreas.Sandberg@ARM.com decode.drainSanityCheck(); 10799444SAndreas.Sandberg@ARM.com rename.drainSanityCheck(); 10809444SAndreas.Sandberg@ARM.com iew.drainSanityCheck(); 10819444SAndreas.Sandberg@ARM.com commit.drainSanityCheck(); 10829444SAndreas.Sandberg@ARM.com} 10839444SAndreas.Sandberg@ARM.com 10849444SAndreas.Sandberg@ARM.comtemplate <class Impl> 10859444SAndreas.Sandberg@ARM.combool 10869444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::isDrained() const 10879444SAndreas.Sandberg@ARM.com{ 10889444SAndreas.Sandberg@ARM.com bool drained(true); 10899444SAndreas.Sandberg@ARM.com 10909444SAndreas.Sandberg@ARM.com if (!instList.empty() || !removeList.empty()) { 10919444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Main CPU structures not drained.\n"); 10929444SAndreas.Sandberg@ARM.com drained = false; 10939444SAndreas.Sandberg@ARM.com } 10949444SAndreas.Sandberg@ARM.com 10959444SAndreas.Sandberg@ARM.com if (!fetch.isDrained()) { 10969444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Fetch not drained.\n"); 10979444SAndreas.Sandberg@ARM.com drained = false; 10989444SAndreas.Sandberg@ARM.com } 10999444SAndreas.Sandberg@ARM.com 11009444SAndreas.Sandberg@ARM.com if (!decode.isDrained()) { 11019444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Decode not drained.\n"); 11029444SAndreas.Sandberg@ARM.com drained = false; 11039444SAndreas.Sandberg@ARM.com } 11049444SAndreas.Sandberg@ARM.com 11059444SAndreas.Sandberg@ARM.com if (!rename.isDrained()) { 11069444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Rename not drained.\n"); 11079444SAndreas.Sandberg@ARM.com drained = false; 11089444SAndreas.Sandberg@ARM.com } 11099444SAndreas.Sandberg@ARM.com 11109444SAndreas.Sandberg@ARM.com if (!iew.isDrained()) { 11119444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "IEW not drained.\n"); 11129444SAndreas.Sandberg@ARM.com drained = false; 11139444SAndreas.Sandberg@ARM.com } 11149444SAndreas.Sandberg@ARM.com 11159444SAndreas.Sandberg@ARM.com if (!commit.isDrained()) { 11169444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Commit not drained.\n"); 11179444SAndreas.Sandberg@ARM.com drained = false; 11189444SAndreas.Sandberg@ARM.com } 11199444SAndreas.Sandberg@ARM.com 11209444SAndreas.Sandberg@ARM.com return drained; 11219444SAndreas.Sandberg@ARM.com} 11229444SAndreas.Sandberg@ARM.com 11239444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11249444SAndreas.Sandberg@ARM.comvoid 11259444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::commitDrained(ThreadID tid) 11269444SAndreas.Sandberg@ARM.com{ 11279444SAndreas.Sandberg@ARM.com fetch.drainStall(tid); 11289444SAndreas.Sandberg@ARM.com} 11299444SAndreas.Sandberg@ARM.com 11309444SAndreas.Sandberg@ARM.comtemplate <class Impl> 11312316SN/Avoid 11329342SAndreas.Sandberg@arm.comFullO3CPU<Impl>::drainResume() 11332316SN/A{ 11349444SAndreas.Sandberg@ARM.com setDrainState(Drainable::Running); 11359444SAndreas.Sandberg@ARM.com if (switchedOut()) 11369444SAndreas.Sandberg@ARM.com return; 11372316SN/A 11389444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Resuming...\n"); 11399523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 11403319Shsul@eecs.umich.edu 11419444SAndreas.Sandberg@ARM.com fetch.drainResume(); 11429444SAndreas.Sandberg@ARM.com commit.drainResume(); 11432316SN/A 11449444SAndreas.Sandberg@ARM.com _status = Idle; 11459444SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < thread.size(); i++) { 11469444SAndreas.Sandberg@ARM.com if (thread[i]->status() == ThreadContext::Active) { 11479444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Activating thread: %i\n", i); 11489444SAndreas.Sandberg@ARM.com activateThread(i); 11499444SAndreas.Sandberg@ARM.com _status = Running; 11502863Sktlim@umich.edu } 11512310SN/A } 11529444SAndreas.Sandberg@ARM.com 11539444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 11549444SAndreas.Sandberg@ARM.com if (_status == Running) 11559444SAndreas.Sandberg@ARM.com schedule(tickEvent, nextCycle()); 11562843Sktlim@umich.edu} 11572843Sktlim@umich.edu 11582843Sktlim@umich.edutemplate <class Impl> 11592843Sktlim@umich.eduvoid 11602843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 11612843Sktlim@umich.edu{ 11629444SAndreas.Sandberg@ARM.com DPRINTF(O3CPU, "Switching out\n"); 11639429SAndreas.Sandberg@ARM.com BaseCPU::switchOut(); 11649429SAndreas.Sandberg@ARM.com 11659444SAndreas.Sandberg@ARM.com activityRec.reset(); 11662843Sktlim@umich.edu 11672843Sktlim@umich.edu _status = SwitchedOut; 11688887Sgeoffrey.blake@arm.com 11692843Sktlim@umich.edu if (checker) 11702843Sktlim@umich.edu checker->switchOut(); 11711060SN/A} 11721060SN/A 11731060SN/Atemplate <class Impl> 11741060SN/Avoid 11751755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 11761060SN/A{ 11778737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 11781060SN/A 11792307SN/A fetch.takeOverFrom(); 11802307SN/A decode.takeOverFrom(); 11812307SN/A rename.takeOverFrom(); 11822307SN/A iew.takeOverFrom(); 11832307SN/A commit.takeOverFrom(); 11842307SN/A 11859444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 11861060SN/A 11879152Satgutier@umich.edu FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU); 11889152Satgutier@umich.edu if (oldO3CPU) 11899152Satgutier@umich.edu globalSeqNum = oldO3CPU->globalSeqNum; 11909152Satgutier@umich.edu 11919179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 11929444SAndreas.Sandberg@ARM.com _status = Idle; 11931060SN/A} 11941060SN/A 11951060SN/Atemplate <class Impl> 11969523SAndreas.Sandberg@ARM.comvoid 11979523SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::verifyMemoryMode() const 11989523SAndreas.Sandberg@ARM.com{ 11999524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 12009523SAndreas.Sandberg@ARM.com fatal("The O3 CPU requires the memory system to be in " 12019523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 12029523SAndreas.Sandberg@ARM.com } 12039523SAndreas.Sandberg@ARM.com} 12049523SAndreas.Sandberg@ARM.com 12059523SAndreas.Sandberg@ARM.comtemplate <class Impl> 12065595Sgblack@eecs.umich.eduTheISA::MiscReg 12076221Snate@binkert.orgFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) 12085595Sgblack@eecs.umich.edu{ 12099384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscRegNoEffect(misc_reg); 12105595Sgblack@eecs.umich.edu} 12115595Sgblack@eecs.umich.edu 12125595Sgblack@eecs.umich.edutemplate <class Impl> 12135595Sgblack@eecs.umich.eduTheISA::MiscReg 12146221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 12155595Sgblack@eecs.umich.edu{ 12167897Shestness@cs.utexas.edu miscRegfileReads++; 12179384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); 12185595Sgblack@eecs.umich.edu} 12195595Sgblack@eecs.umich.edu 12205595Sgblack@eecs.umich.edutemplate <class Impl> 12215595Sgblack@eecs.umich.eduvoid 12225595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 12236221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12245595Sgblack@eecs.umich.edu{ 12259384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscRegNoEffect(misc_reg, val); 12265595Sgblack@eecs.umich.edu} 12275595Sgblack@eecs.umich.edu 12285595Sgblack@eecs.umich.edutemplate <class Impl> 12295595Sgblack@eecs.umich.eduvoid 12305595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 12316221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 12325595Sgblack@eecs.umich.edu{ 12337897Shestness@cs.utexas.edu miscRegfileWrites++; 12349384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); 12355595Sgblack@eecs.umich.edu} 12365595Sgblack@eecs.umich.edu 12375595Sgblack@eecs.umich.edutemplate <class Impl> 12381060SN/Auint64_t 12391755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 12401060SN/A{ 12417897Shestness@cs.utexas.edu intRegfileReads++; 12421060SN/A return regFile.readIntReg(reg_idx); 12431060SN/A} 12441060SN/A 12451060SN/Atemplate <class Impl> 12462455SN/AFloatReg 12472455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 12481060SN/A{ 12497897Shestness@cs.utexas.edu fpRegfileReads++; 12502455SN/A return regFile.readFloatReg(reg_idx); 12511060SN/A} 12521060SN/A 12531060SN/Atemplate <class Impl> 12542455SN/AFloatRegBits 12552455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 12562455SN/A{ 12577897Shestness@cs.utexas.edu fpRegfileReads++; 12582455SN/A return regFile.readFloatRegBits(reg_idx); 12591060SN/A} 12601060SN/A 12611060SN/Atemplate <class Impl> 12629920Syasuko.eckert@amd.comCCReg 12639920Syasuko.eckert@amd.comFullO3CPU<Impl>::readCCReg(int reg_idx) 12649920Syasuko.eckert@amd.com{ 12659920Syasuko.eckert@amd.com ccRegfileReads++; 12669920Syasuko.eckert@amd.com return regFile.readCCReg(reg_idx); 12679920Syasuko.eckert@amd.com} 12689920Syasuko.eckert@amd.com 12699920Syasuko.eckert@amd.comtemplate <class Impl> 12701060SN/Avoid 12711755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 12721060SN/A{ 12737897Shestness@cs.utexas.edu intRegfileWrites++; 12741060SN/A regFile.setIntReg(reg_idx, val); 12751060SN/A} 12761060SN/A 12771060SN/Atemplate <class Impl> 12781060SN/Avoid 12792455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 12801060SN/A{ 12817897Shestness@cs.utexas.edu fpRegfileWrites++; 12822455SN/A regFile.setFloatReg(reg_idx, val); 12831060SN/A} 12841060SN/A 12851060SN/Atemplate <class Impl> 12861060SN/Avoid 12872455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 12882455SN/A{ 12897897Shestness@cs.utexas.edu fpRegfileWrites++; 12902455SN/A regFile.setFloatRegBits(reg_idx, val); 12911060SN/A} 12921060SN/A 12931060SN/Atemplate <class Impl> 12949920Syasuko.eckert@amd.comvoid 12959920Syasuko.eckert@amd.comFullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val) 12969920Syasuko.eckert@amd.com{ 12979920Syasuko.eckert@amd.com ccRegfileWrites++; 12989920Syasuko.eckert@amd.com regFile.setCCReg(reg_idx, val); 12999920Syasuko.eckert@amd.com} 13009920Syasuko.eckert@amd.com 13019920Syasuko.eckert@amd.comtemplate <class Impl> 13021060SN/Auint64_t 13036221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 13041060SN/A{ 13057897Shestness@cs.utexas.edu intRegfileReads++; 13069919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx); 13072292SN/A 13082292SN/A return regFile.readIntReg(phys_reg); 13092292SN/A} 13102292SN/A 13112292SN/Atemplate <class Impl> 13122292SN/Afloat 13136314Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 13142292SN/A{ 13157897Shestness@cs.utexas.edu fpRegfileReads++; 13169919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 13172292SN/A 13182669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 13192292SN/A} 13202292SN/A 13212292SN/Atemplate <class Impl> 13222292SN/Auint64_t 13236221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 13242292SN/A{ 13257897Shestness@cs.utexas.edu fpRegfileReads++; 13269919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 13272292SN/A 13282669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 13291060SN/A} 13301060SN/A 13311060SN/Atemplate <class Impl> 13329920Syasuko.eckert@amd.comCCReg 13339920Syasuko.eckert@amd.comFullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid) 13349920Syasuko.eckert@amd.com{ 13359920Syasuko.eckert@amd.com ccRegfileReads++; 13369920Syasuko.eckert@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx); 13379920Syasuko.eckert@amd.com 13389920Syasuko.eckert@amd.com return regFile.readCCReg(phys_reg); 13399920Syasuko.eckert@amd.com} 13409920Syasuko.eckert@amd.com 13419920Syasuko.eckert@amd.comtemplate <class Impl> 13421060SN/Avoid 13436221Snate@binkert.orgFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 13441060SN/A{ 13457897Shestness@cs.utexas.edu intRegfileWrites++; 13469919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx); 13472292SN/A 13482292SN/A regFile.setIntReg(phys_reg, val); 13491060SN/A} 13501060SN/A 13511060SN/Atemplate <class Impl> 13521060SN/Avoid 13536314Sgblack@eecs.umich.eduFullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 13541060SN/A{ 13557897Shestness@cs.utexas.edu fpRegfileWrites++; 13569919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 13572292SN/A 13582669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 13591060SN/A} 13601060SN/A 13611060SN/Atemplate <class Impl> 13621060SN/Avoid 13636221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 13641060SN/A{ 13657897Shestness@cs.utexas.edu fpRegfileWrites++; 13669919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 13671060SN/A 13682669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 13692292SN/A} 13702292SN/A 13712292SN/Atemplate <class Impl> 13729920Syasuko.eckert@amd.comvoid 13739920Syasuko.eckert@amd.comFullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid) 13749920Syasuko.eckert@amd.com{ 13759920Syasuko.eckert@amd.com ccRegfileWrites++; 13769920Syasuko.eckert@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx); 13779920Syasuko.eckert@amd.com 13789920Syasuko.eckert@amd.com regFile.setCCReg(phys_reg, val); 13799920Syasuko.eckert@amd.com} 13809920Syasuko.eckert@amd.com 13819920Syasuko.eckert@amd.comtemplate <class Impl> 13827720Sgblack@eecs.umich.eduTheISA::PCState 13837720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 13842292SN/A{ 13857720Sgblack@eecs.umich.edu return commit.pcState(tid); 13861060SN/A} 13871060SN/A 13881060SN/Atemplate <class Impl> 13891060SN/Avoid 13907720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 13911060SN/A{ 13927720Sgblack@eecs.umich.edu commit.pcState(val, tid); 13932292SN/A} 13941060SN/A 13952292SN/Atemplate <class Impl> 13967720Sgblack@eecs.umich.eduAddr 13977720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 13984636Sgblack@eecs.umich.edu{ 13997720Sgblack@eecs.umich.edu return commit.instAddr(tid); 14004636Sgblack@eecs.umich.edu} 14014636Sgblack@eecs.umich.edu 14024636Sgblack@eecs.umich.edutemplate <class Impl> 14037720Sgblack@eecs.umich.eduAddr 14047720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 14054636Sgblack@eecs.umich.edu{ 14067720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 14074636Sgblack@eecs.umich.edu} 14084636Sgblack@eecs.umich.edu 14094636Sgblack@eecs.umich.edutemplate <class Impl> 14107720Sgblack@eecs.umich.eduMicroPC 14117720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 14122292SN/A{ 14137720Sgblack@eecs.umich.edu return commit.microPC(tid); 14144636Sgblack@eecs.umich.edu} 14154636Sgblack@eecs.umich.edu 14164636Sgblack@eecs.umich.edutemplate <class Impl> 14175595Sgblack@eecs.umich.eduvoid 14186221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 14195595Sgblack@eecs.umich.edu{ 14209382SAli.Saidi@ARM.com this->thread[tid]->noSquashFromTC = true; 14215595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 14225595Sgblack@eecs.umich.edu} 14235595Sgblack@eecs.umich.edu 14245595Sgblack@eecs.umich.edutemplate <class Impl> 14252292SN/Atypename FullO3CPU<Impl>::ListIt 14262292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 14272292SN/A{ 14282292SN/A instList.push_back(inst); 14291060SN/A 14302292SN/A return --(instList.end()); 14312292SN/A} 14321060SN/A 14332292SN/Atemplate <class Impl> 14342292SN/Avoid 14358834Satgutier@umich.eduFullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst) 14362292SN/A{ 14372292SN/A // Keep an instruction count. 14388834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) { 14398834Satgutier@umich.edu thread[tid]->numInst++; 14408834Satgutier@umich.edu thread[tid]->numInsts++; 14418834Satgutier@umich.edu committedInsts[tid]++; 14428834Satgutier@umich.edu } 14438834Satgutier@umich.edu thread[tid]->numOp++; 14448834Satgutier@umich.edu thread[tid]->numOps++; 14458834Satgutier@umich.edu committedOps[tid]++; 14468834Satgutier@umich.edu 14477897Shestness@cs.utexas.edu system->totalNumInsts++; 14482292SN/A // Check for instruction-count-based events. 14492292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 14507897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 145110464SAndreas.Sandberg@ARM.com 145210464SAndreas.Sandberg@ARM.com probeInstCommit(inst->staticInst); 14532292SN/A} 14542292SN/A 14552292SN/Atemplate <class Impl> 14562292SN/Avoid 14571755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 14581060SN/A{ 14597720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 14602292SN/A "[sn:%lli]\n", 14617720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 14621060SN/A 14632292SN/A removeInstsThisCycle = true; 14641060SN/A 14651060SN/A // Remove the front instruction. 14662292SN/A removeList.push(inst->getInstListIt()); 14671060SN/A} 14681060SN/A 14691060SN/Atemplate <class Impl> 14701060SN/Avoid 14716221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 14721060SN/A{ 14732733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 14742292SN/A " list.\n", tid); 14751060SN/A 14762292SN/A ListIt end_it; 14771060SN/A 14782292SN/A bool rob_empty = false; 14792292SN/A 14802292SN/A if (instList.empty()) { 14812292SN/A return; 148210164Ssleimanf@umich.edu } else if (rob.isEmpty(tid)) { 14832733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 14842292SN/A end_it = instList.begin(); 14852292SN/A rob_empty = true; 14862292SN/A } else { 14872292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 14882733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 14892292SN/A } 14902292SN/A 14912292SN/A removeInstsThisCycle = true; 14922292SN/A 14932292SN/A ListIt inst_it = instList.end(); 14942292SN/A 14952292SN/A inst_it--; 14962292SN/A 14972292SN/A // Walk through the instruction list, removing any instructions 14982292SN/A // that were inserted after the given instruction iterator, end_it. 14992292SN/A while (inst_it != end_it) { 15002292SN/A assert(!instList.empty()); 15012292SN/A 15022292SN/A squashInstIt(inst_it, tid); 15032292SN/A 15042292SN/A inst_it--; 15052292SN/A } 15062292SN/A 15072292SN/A // If the ROB was empty, then we actually need to remove the first 15082292SN/A // instruction as well. 15092292SN/A if (rob_empty) { 15102292SN/A squashInstIt(inst_it, tid); 15112292SN/A } 15121060SN/A} 15131060SN/A 15141060SN/Atemplate <class Impl> 15151060SN/Avoid 15166221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 15171062SN/A{ 15182292SN/A assert(!instList.empty()); 15192292SN/A 15202292SN/A removeInstsThisCycle = true; 15212292SN/A 15222292SN/A ListIt inst_iter = instList.end(); 15232292SN/A 15242292SN/A inst_iter--; 15252292SN/A 15262733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 15272292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 15282292SN/A tid, seq_num, (*inst_iter)->seqNum); 15291062SN/A 15302292SN/A while ((*inst_iter)->seqNum > seq_num) { 15311062SN/A 15322292SN/A bool break_loop = (inst_iter == instList.begin()); 15331062SN/A 15342292SN/A squashInstIt(inst_iter, tid); 15351062SN/A 15362292SN/A inst_iter--; 15371062SN/A 15382292SN/A if (break_loop) 15392292SN/A break; 15402292SN/A } 15412292SN/A} 15422292SN/A 15432292SN/Atemplate <class Impl> 15442292SN/Ainline void 15456221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 15462292SN/A{ 15472292SN/A if ((*instIt)->threadNumber == tid) { 15482733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 15497720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 15502292SN/A (*instIt)->threadNumber, 15512292SN/A (*instIt)->seqNum, 15527720Sgblack@eecs.umich.edu (*instIt)->pcState()); 15531062SN/A 15541062SN/A // Mark it as squashed. 15552292SN/A (*instIt)->setSquashed(); 15562292SN/A 15572325SN/A // @todo: Formulate a consistent method for deleting 15582325SN/A // instructions from the instruction list 15592292SN/A // Remove the instruction from the list. 15602292SN/A removeList.push(instIt); 15612292SN/A } 15622292SN/A} 15632292SN/A 15642292SN/Atemplate <class Impl> 15652292SN/Avoid 15662292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 15672292SN/A{ 15682292SN/A while (!removeList.empty()) { 15692733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 15707720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 15712292SN/A (*removeList.front())->threadNumber, 15722292SN/A (*removeList.front())->seqNum, 15737720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 15742292SN/A 15752292SN/A instList.erase(removeList.front()); 15762292SN/A 15772292SN/A removeList.pop(); 15781062SN/A } 15791062SN/A 15802292SN/A removeInstsThisCycle = false; 15811062SN/A} 15822325SN/A/* 15831062SN/Atemplate <class Impl> 15841062SN/Avoid 15851755SN/AFullO3CPU<Impl>::removeAllInsts() 15861060SN/A{ 15871060SN/A instList.clear(); 15881060SN/A} 15892325SN/A*/ 15901060SN/Atemplate <class Impl> 15911060SN/Avoid 15921755SN/AFullO3CPU<Impl>::dumpInsts() 15931060SN/A{ 15941060SN/A int num = 0; 15951060SN/A 15962292SN/A ListIt inst_list_it = instList.begin(); 15972292SN/A 15982292SN/A cprintf("Dumping Instruction List\n"); 15992292SN/A 16002292SN/A while (inst_list_it != instList.end()) { 16012292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 16022292SN/A "Squashed:%i\n\n", 16037720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 16042292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 16052292SN/A (*inst_list_it)->isSquashed()); 16061060SN/A inst_list_it++; 16071060SN/A ++num; 16081060SN/A } 16091060SN/A} 16102325SN/A/* 16111060SN/Atemplate <class Impl> 16121060SN/Avoid 16131755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 16141060SN/A{ 16151060SN/A iew.wakeDependents(inst); 16161060SN/A} 16172325SN/A*/ 16182292SN/Atemplate <class Impl> 16192292SN/Avoid 16202292SN/AFullO3CPU<Impl>::wakeCPU() 16212292SN/A{ 16222325SN/A if (activityRec.active() || tickEvent.scheduled()) { 16232325SN/A DPRINTF(Activity, "CPU already running.\n"); 16242292SN/A return; 16252292SN/A } 16262292SN/A 16272325SN/A DPRINTF(Activity, "Waking up CPU\n"); 16282325SN/A 16299180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 16309180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 163110464SAndreas.Sandberg@ARM.com if (cycles > 1) { 16329179Sandreas.hansson@arm.com --cycles; 163310464SAndreas.Sandberg@ARM.com idleCycles += cycles; 163410464SAndreas.Sandberg@ARM.com numCycles += cycles; 163510464SAndreas.Sandberg@ARM.com ppCycles->notify(cycles); 163610464SAndreas.Sandberg@ARM.com } 16372292SN/A 16389648Sdam.sunwoo@arm.com schedule(tickEvent, clockEdge()); 16392292SN/A} 16402292SN/A 16415807Snate@binkert.orgtemplate <class Impl> 16425807Snate@binkert.orgvoid 16435807Snate@binkert.orgFullO3CPU<Impl>::wakeup() 16445807Snate@binkert.org{ 16455807Snate@binkert.org if (this->thread[0]->status() != ThreadContext::Suspended) 16465807Snate@binkert.org return; 16475807Snate@binkert.org 16485807Snate@binkert.org this->wakeCPU(); 16495807Snate@binkert.org 16505807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 16515807Snate@binkert.org this->threadContexts[0]->activate(); 16525807Snate@binkert.org} 16535807Snate@binkert.org 16542292SN/Atemplate <class Impl> 16556221Snate@binkert.orgThreadID 16562292SN/AFullO3CPU<Impl>::getFreeTid() 16572292SN/A{ 16586221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 16596221Snate@binkert.org if (!tids[tid]) { 16606221Snate@binkert.org tids[tid] = true; 16616221Snate@binkert.org return tid; 16622292SN/A } 16632292SN/A } 16642292SN/A 16656221Snate@binkert.org return InvalidThreadID; 16662292SN/A} 16672292SN/A 16682292SN/Atemplate <class Impl> 16692292SN/Avoid 16702292SN/AFullO3CPU<Impl>::updateThreadPriority() 16712292SN/A{ 16726221Snate@binkert.org if (activeThreads.size() > 1) { 16732292SN/A //DEFAULT TO ROUND ROBIN SCHEME 16742292SN/A //e.g. Move highest priority to end of thread list 16756221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 16762292SN/A 16772292SN/A unsigned high_thread = *list_begin; 16782292SN/A 16792292SN/A activeThreads.erase(list_begin); 16802292SN/A 16812292SN/A activeThreads.push_back(high_thread); 16822292SN/A } 16832292SN/A} 16841060SN/A 16851755SN/A// Forward declaration of FullO3CPU. 16862818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1687