cpu.cc revision 10225
11689SN/A/* 28948Sandreas.hansson@arm.com * Copyright (c) 2011-2012 ARM Limited 39916Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48707Sandreas.hansson@arm.com * All rights reserved 58707Sandreas.hansson@arm.com * 68707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148707Sandreas.hansson@arm.com * 152325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 167897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 171689SN/A * All rights reserved. 181689SN/A * 191689SN/A * Redistribution and use in source and binary forms, with or without 201689SN/A * modification, are permitted provided that the following conditions are 211689SN/A * met: redistributions of source code must retain the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer; 231689SN/A * redistributions in binary form must reproduce the above copyright 241689SN/A * notice, this list of conditions and the following disclaimer in the 251689SN/A * documentation and/or other materials provided with the distribution; 261689SN/A * neither the name of the copyright holders nor the names of its 271689SN/A * contributors may be used to endorse or promote products derived from 281689SN/A * this software without specific prior written permission. 291689SN/A * 301689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 432756Sksewell@umich.edu * Korey Sewell 447897Shestness@cs.utexas.edu * Rick Strong 451689SN/A */ 461689SN/A 478779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 498887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 508887Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 518229Snate@binkert.org#include "cpu/o3/cpu.hh" 528229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 538229Snate@binkert.org#include "cpu/o3/thread_context.hh" 544762Snate@binkert.org#include "cpu/activity.hh" 558779Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 564762Snate@binkert.org#include "cpu/simple_thread.hh" 574762Snate@binkert.org#include "cpu/thread_context.hh" 588232Snate@binkert.org#include "debug/Activity.hh" 599152Satgutier@umich.edu#include "debug/Drain.hh" 608232Snate@binkert.org#include "debug/O3CPU.hh" 618232Snate@binkert.org#include "debug/Quiesce.hh" 624762Snate@binkert.org#include "enums/MemoryMode.hh" 634762Snate@binkert.org#include "sim/core.hh" 648793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 658779Sgblack@eecs.umich.edu#include "sim/process.hh" 664762Snate@binkert.org#include "sim/stat_control.hh" 678460SAli.Saidi@ARM.com#include "sim/system.hh" 684762Snate@binkert.org 695702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 705702Ssaidi@eecs.umich.edu#include "arch/alpha/osfpal.hh" 718232Snate@binkert.org#include "debug/Activity.hh" 725702Ssaidi@eecs.umich.edu#endif 735702Ssaidi@eecs.umich.edu 748737Skoansin.tan@gmail.comstruct BaseCPUParams; 755529Snate@binkert.org 762669Sktlim@umich.eduusing namespace TheISA; 776221Snate@binkert.orgusing namespace std; 781060SN/A 795529Snate@binkert.orgBaseO3CPU::BaseO3CPU(BaseCPUParams *params) 805712Shsul@eecs.umich.edu : BaseCPU(params) 811060SN/A{ 821060SN/A} 831060SN/A 842292SN/Avoid 852733Sktlim@umich.eduBaseO3CPU::regStats() 862292SN/A{ 872292SN/A BaseCPU::regStats(); 882292SN/A} 892292SN/A 908707Sandreas.hansson@arm.comtemplate<class Impl> 918707Sandreas.hansson@arm.combool 928975Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvTimingResp(PacketPtr pkt) 938707Sandreas.hansson@arm.com{ 948707Sandreas.hansson@arm.com DPRINTF(O3CPU, "Fetch unit received timing\n"); 958948Sandreas.hansson@arm.com // We shouldn't ever get a block in ownership state 968948Sandreas.hansson@arm.com assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); 978948Sandreas.hansson@arm.com fetch->processCacheCompletion(pkt); 988707Sandreas.hansson@arm.com 998707Sandreas.hansson@arm.com return true; 1008707Sandreas.hansson@arm.com} 1018707Sandreas.hansson@arm.com 1028707Sandreas.hansson@arm.comtemplate<class Impl> 1038707Sandreas.hansson@arm.comvoid 1048707Sandreas.hansson@arm.comFullO3CPU<Impl>::IcachePort::recvRetry() 1058707Sandreas.hansson@arm.com{ 1068707Sandreas.hansson@arm.com fetch->recvRetry(); 1078707Sandreas.hansson@arm.com} 1088707Sandreas.hansson@arm.com 1098707Sandreas.hansson@arm.comtemplate <class Impl> 1108707Sandreas.hansson@arm.combool 1118975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingResp(PacketPtr pkt) 1128707Sandreas.hansson@arm.com{ 1138975Sandreas.hansson@arm.com return lsq->recvTimingResp(pkt); 1148707Sandreas.hansson@arm.com} 1158707Sandreas.hansson@arm.com 1168707Sandreas.hansson@arm.comtemplate <class Impl> 1178975Sandreas.hansson@arm.comvoid 1188975Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvTimingSnoopReq(PacketPtr pkt) 1198948Sandreas.hansson@arm.com{ 1208975Sandreas.hansson@arm.com lsq->recvTimingSnoopReq(pkt); 1218948Sandreas.hansson@arm.com} 1228948Sandreas.hansson@arm.com 1238948Sandreas.hansson@arm.comtemplate <class Impl> 1248707Sandreas.hansson@arm.comvoid 1258707Sandreas.hansson@arm.comFullO3CPU<Impl>::DcachePort::recvRetry() 1268707Sandreas.hansson@arm.com{ 1278707Sandreas.hansson@arm.com lsq->recvRetry(); 1288707Sandreas.hansson@arm.com} 1298707Sandreas.hansson@arm.com 1301060SN/Atemplate <class Impl> 1311755SN/AFullO3CPU<Impl>::TickEvent::TickEvent(FullO3CPU<Impl> *c) 1325606Snate@binkert.org : Event(CPU_Tick_Pri), cpu(c) 1331060SN/A{ 1341060SN/A} 1351060SN/A 1361060SN/Atemplate <class Impl> 1371060SN/Avoid 1381755SN/AFullO3CPU<Impl>::TickEvent::process() 1391060SN/A{ 1401060SN/A cpu->tick(); 1411060SN/A} 1421060SN/A 1431060SN/Atemplate <class Impl> 1441060SN/Aconst char * 1455336Shines@cs.fsu.eduFullO3CPU<Impl>::TickEvent::description() const 1461060SN/A{ 1474873Sstever@eecs.umich.edu return "FullO3CPU tick"; 1481060SN/A} 1491060SN/A 1501060SN/Atemplate <class Impl> 1512829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::ActivateThreadEvent() 1525606Snate@binkert.org : Event(CPU_Switch_Pri) 1532829Sksewell@umich.edu{ 1542829Sksewell@umich.edu} 1552829Sksewell@umich.edu 1562829Sksewell@umich.edutemplate <class Impl> 1572829Sksewell@umich.eduvoid 1582829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::init(int thread_num, 1592829Sksewell@umich.edu FullO3CPU<Impl> *thread_cpu) 1602829Sksewell@umich.edu{ 1612829Sksewell@umich.edu tid = thread_num; 1622829Sksewell@umich.edu cpu = thread_cpu; 1632829Sksewell@umich.edu} 1642829Sksewell@umich.edu 1652829Sksewell@umich.edutemplate <class Impl> 1662829Sksewell@umich.eduvoid 1672829Sksewell@umich.eduFullO3CPU<Impl>::ActivateThreadEvent::process() 1682829Sksewell@umich.edu{ 1692829Sksewell@umich.edu cpu->activateThread(tid); 1702829Sksewell@umich.edu} 1712829Sksewell@umich.edu 1722829Sksewell@umich.edutemplate <class Impl> 1732829Sksewell@umich.educonst char * 1745336Shines@cs.fsu.eduFullO3CPU<Impl>::ActivateThreadEvent::description() const 1752829Sksewell@umich.edu{ 1764873Sstever@eecs.umich.edu return "FullO3CPU \"Activate Thread\""; 1772829Sksewell@umich.edu} 1782829Sksewell@umich.edu 1792829Sksewell@umich.edutemplate <class Impl> 1802875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::DeallocateContextEvent() 1815606Snate@binkert.org : Event(CPU_Tick_Pri), tid(0), remove(false), cpu(NULL) 1822875Sksewell@umich.edu{ 1832875Sksewell@umich.edu} 1842875Sksewell@umich.edu 1852875Sksewell@umich.edutemplate <class Impl> 1862875Sksewell@umich.eduvoid 1872875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::init(int thread_num, 1883859Sbinkertn@umich.edu FullO3CPU<Impl> *thread_cpu) 1892875Sksewell@umich.edu{ 1902875Sksewell@umich.edu tid = thread_num; 1912875Sksewell@umich.edu cpu = thread_cpu; 1923859Sbinkertn@umich.edu remove = false; 1932875Sksewell@umich.edu} 1942875Sksewell@umich.edu 1952875Sksewell@umich.edutemplate <class Impl> 1962875Sksewell@umich.eduvoid 1972875Sksewell@umich.eduFullO3CPU<Impl>::DeallocateContextEvent::process() 1982875Sksewell@umich.edu{ 1992875Sksewell@umich.edu cpu->deactivateThread(tid); 2003221Sktlim@umich.edu if (remove) 2013221Sktlim@umich.edu cpu->removeThread(tid); 2022875Sksewell@umich.edu} 2032875Sksewell@umich.edu 2042875Sksewell@umich.edutemplate <class Impl> 2052875Sksewell@umich.educonst char * 2065336Shines@cs.fsu.eduFullO3CPU<Impl>::DeallocateContextEvent::description() const 2072875Sksewell@umich.edu{ 2084873Sstever@eecs.umich.edu return "FullO3CPU \"Deallocate Context\""; 2092875Sksewell@umich.edu} 2102875Sksewell@umich.edu 2112875Sksewell@umich.edutemplate <class Impl> 2125595Sgblack@eecs.umich.eduFullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params) 2132733Sktlim@umich.edu : BaseO3CPU(params), 2143781Sgblack@eecs.umich.edu itb(params->itb), 2153781Sgblack@eecs.umich.edu dtb(params->dtb), 2161060SN/A tickEvent(this), 2175737Scws3k@cs.virginia.edu#ifndef NDEBUG 2185737Scws3k@cs.virginia.edu instcount(0), 2195737Scws3k@cs.virginia.edu#endif 2202292SN/A removeInstsThisCycle(false), 2215595Sgblack@eecs.umich.edu fetch(this, params), 2225595Sgblack@eecs.umich.edu decode(this, params), 2235595Sgblack@eecs.umich.edu rename(this, params), 2245595Sgblack@eecs.umich.edu iew(this, params), 2255595Sgblack@eecs.umich.edu commit(this, params), 2261060SN/A 2279915Ssteve.reinhardt@amd.com regFile(params->numPhysIntRegs, 2289920Syasuko.eckert@amd.com params->numPhysFloatRegs, 2299920Syasuko.eckert@amd.com params->numPhysCCRegs), 2301060SN/A 2319919Ssteve.reinhardt@amd.com freeList(name() + ".freelist", ®File), 2321060SN/A 2339954SFaissal.Sleiman@arm.com rob(this, params), 2341060SN/A 2359916Ssteve.reinhardt@amd.com scoreboard(name() + ".scoreboard", 2369916Ssteve.reinhardt@amd.com regFile.totalNumPhysRegs(), TheISA::NumMiscRegs, 2379916Ssteve.reinhardt@amd.com TheISA::ZeroReg, TheISA::ZeroReg), 2381060SN/A 2399384SAndreas.Sandberg@arm.com isa(numThreads, NULL), 2409384SAndreas.Sandberg@arm.com 2418707Sandreas.hansson@arm.com icachePort(&fetch, this), 2428707Sandreas.hansson@arm.com dcachePort(&iew.ldstQueue, this), 2438707Sandreas.hansson@arm.com 2442873Sktlim@umich.edu timeBuffer(params->backComSize, params->forwardComSize), 2452873Sktlim@umich.edu fetchQueue(params->backComSize, params->forwardComSize), 2462873Sktlim@umich.edu decodeQueue(params->backComSize, params->forwardComSize), 2472873Sktlim@umich.edu renameQueue(params->backComSize, params->forwardComSize), 2482873Sktlim@umich.edu iewQueue(params->backComSize, params->forwardComSize), 2495804Snate@binkert.org activityRec(name(), NumStages, 2502873Sktlim@umich.edu params->backComSize + params->forwardComSize, 2512873Sktlim@umich.edu params->activity), 2521060SN/A 2531060SN/A globalSeqNum(1), 2542292SN/A system(params->system), 2559444SAndreas.Sandberg@ARM.com drainManager(NULL), 2569180Sandreas.hansson@arm.com lastRunningCycle(curCycle()) 2571060SN/A{ 2589433SAndreas.Sandberg@ARM.com if (!params->switched_out) { 2593221Sktlim@umich.edu _status = Running; 2603221Sktlim@umich.edu } else { 2619152Satgutier@umich.edu _status = SwitchedOut; 2623221Sktlim@umich.edu } 2631681SN/A 2642794Sktlim@umich.edu if (params->checker) { 2652316SN/A BaseCPU *temp_checker = params->checker; 2668733Sgeoffrey.blake@arm.com checker = dynamic_cast<Checker<Impl> *>(temp_checker); 2678707Sandreas.hansson@arm.com checker->setIcachePort(&icachePort); 2682316SN/A checker->setSystem(params->system); 2694598Sbinkertn@umich.edu } else { 2704598Sbinkertn@umich.edu checker = NULL; 2714598Sbinkertn@umich.edu } 2722316SN/A 2738793Sgblack@eecs.umich.edu if (!FullSystem) { 2748793Sgblack@eecs.umich.edu thread.resize(numThreads); 2758793Sgblack@eecs.umich.edu tids.resize(numThreads); 2768793Sgblack@eecs.umich.edu } 2771681SN/A 2782325SN/A // The stages also need their CPU pointer setup. However this 2792325SN/A // must be done at the upper level CPU because they have pointers 2802325SN/A // to the upper level CPU, and not this FullO3CPU. 2811060SN/A 2822292SN/A // Set up Pointers to the activeThreads list for each stage 2832292SN/A fetch.setActiveThreads(&activeThreads); 2842292SN/A decode.setActiveThreads(&activeThreads); 2852292SN/A rename.setActiveThreads(&activeThreads); 2862292SN/A iew.setActiveThreads(&activeThreads); 2872292SN/A commit.setActiveThreads(&activeThreads); 2881060SN/A 2891060SN/A // Give each of the stages the time buffer they will use. 2901060SN/A fetch.setTimeBuffer(&timeBuffer); 2911060SN/A decode.setTimeBuffer(&timeBuffer); 2921060SN/A rename.setTimeBuffer(&timeBuffer); 2931060SN/A iew.setTimeBuffer(&timeBuffer); 2941060SN/A commit.setTimeBuffer(&timeBuffer); 2951060SN/A 2961060SN/A // Also setup each of the stages' queues. 2971060SN/A fetch.setFetchQueue(&fetchQueue); 2981060SN/A decode.setFetchQueue(&fetchQueue); 2992292SN/A commit.setFetchQueue(&fetchQueue); 3001060SN/A decode.setDecodeQueue(&decodeQueue); 3011060SN/A rename.setDecodeQueue(&decodeQueue); 3021060SN/A rename.setRenameQueue(&renameQueue); 3031060SN/A iew.setRenameQueue(&renameQueue); 3041060SN/A iew.setIEWQueue(&iewQueue); 3051060SN/A commit.setIEWQueue(&iewQueue); 3061060SN/A commit.setRenameQueue(&renameQueue); 3071060SN/A 3082292SN/A commit.setIEWStage(&iew); 3092292SN/A rename.setIEWStage(&iew); 3102292SN/A rename.setCommitStage(&commit); 3112292SN/A 3128793Sgblack@eecs.umich.edu ThreadID active_threads; 3138793Sgblack@eecs.umich.edu if (FullSystem) { 3148793Sgblack@eecs.umich.edu active_threads = 1; 3158793Sgblack@eecs.umich.edu } else { 3168793Sgblack@eecs.umich.edu active_threads = params->workload.size(); 3172831Sksewell@umich.edu 3188793Sgblack@eecs.umich.edu if (active_threads > Impl::MaxThreads) { 3198793Sgblack@eecs.umich.edu panic("Workload Size too large. Increase the 'MaxThreads' " 3208793Sgblack@eecs.umich.edu "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " 3218793Sgblack@eecs.umich.edu "or edit your workload size."); 3228793Sgblack@eecs.umich.edu } 3232831Sksewell@umich.edu } 3242292SN/A 3252316SN/A //Make Sure That this a Valid Architeture 3262292SN/A assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs); 3272292SN/A assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 3289920Syasuko.eckert@amd.com assert(params->numPhysCCRegs >= numThreads * TheISA::NumCCRegs); 3292292SN/A 3302292SN/A rename.setScoreboard(&scoreboard); 3312292SN/A iew.setScoreboard(&scoreboard); 3322292SN/A 3331060SN/A // Setup the rename map for whichever stages need it. 3346221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3359384SAndreas.Sandberg@arm.com isa[tid] = params->isa[tid]; 3369384SAndreas.Sandberg@arm.com 3379919Ssteve.reinhardt@amd.com // Only Alpha has an FP zero register, so for other ISAs we 3389919Ssteve.reinhardt@amd.com // use an invalid FP register index to avoid special treatment 3399919Ssteve.reinhardt@amd.com // of any valid FP reg. 3409919Ssteve.reinhardt@amd.com RegIndex invalidFPReg = TheISA::NumFloatRegs + 1; 3419919Ssteve.reinhardt@amd.com RegIndex fpZeroReg = 3429919Ssteve.reinhardt@amd.com (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg; 3432292SN/A 3449919Ssteve.reinhardt@amd.com commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 3459919Ssteve.reinhardt@amd.com &freeList); 3462292SN/A 3479919Ssteve.reinhardt@amd.com renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, 3489919Ssteve.reinhardt@amd.com &freeList); 3493221Sktlim@umich.edu 3503221Sktlim@umich.edu activateThreadEvent[tid].init(tid, this); 3513221Sktlim@umich.edu deallocateContextEvent[tid].init(tid, this); 3522292SN/A } 3532292SN/A 3549919Ssteve.reinhardt@amd.com // Initialize rename map to assign physical registers to the 3559919Ssteve.reinhardt@amd.com // architectural registers for active threads only. 3569919Ssteve.reinhardt@amd.com for (ThreadID tid = 0; tid < active_threads; tid++) { 3579919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) { 3589919Ssteve.reinhardt@amd.com // Note that we can't use the rename() method because we don't 3599919Ssteve.reinhardt@amd.com // want special treatment for the zero register at this point 3609919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = freeList.getIntReg(); 3619919Ssteve.reinhardt@amd.com renameMap[tid].setIntEntry(ridx, phys_reg); 3629919Ssteve.reinhardt@amd.com commitRenameMap[tid].setIntEntry(ridx, phys_reg); 3639919Ssteve.reinhardt@amd.com } 3649919Ssteve.reinhardt@amd.com 3659919Ssteve.reinhardt@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) { 3669919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = freeList.getFloatReg(); 3679919Ssteve.reinhardt@amd.com renameMap[tid].setFloatEntry(ridx, phys_reg); 3689919Ssteve.reinhardt@amd.com commitRenameMap[tid].setFloatEntry(ridx, phys_reg); 3699919Ssteve.reinhardt@amd.com } 3709920Syasuko.eckert@amd.com 3719920Syasuko.eckert@amd.com for (RegIndex ridx = 0; ridx < TheISA::NumCCRegs; ++ridx) { 3729920Syasuko.eckert@amd.com PhysRegIndex phys_reg = freeList.getCCReg(); 3739920Syasuko.eckert@amd.com renameMap[tid].setCCEntry(ridx, phys_reg); 3749920Syasuko.eckert@amd.com commitRenameMap[tid].setCCEntry(ridx, phys_reg); 3759920Syasuko.eckert@amd.com } 3769919Ssteve.reinhardt@amd.com } 3779919Ssteve.reinhardt@amd.com 3782292SN/A rename.setRenameMap(renameMap); 3792292SN/A commit.setRenameMap(commitRenameMap); 3801060SN/A rename.setFreeList(&freeList); 3812292SN/A 3821060SN/A // Setup the ROB for whichever stages need it. 3831060SN/A commit.setROB(&rob); 3842292SN/A 3859158Sandreas.hansson@arm.com lastActivatedCycle = 0; 3866221Snate@binkert.org#if 0 3873093Sksewell@umich.edu // Give renameMap & rename stage access to the freeList; 3886221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3896221Snate@binkert.org globalSeqNum[tid] = 1; 3906221Snate@binkert.org#endif 3913093Sksewell@umich.edu 3922292SN/A contextSwitch = false; 3935595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Creating O3CPU object.\n"); 3945595Sgblack@eecs.umich.edu 3955595Sgblack@eecs.umich.edu // Setup any thread state. 3965595Sgblack@eecs.umich.edu this->thread.resize(this->numThreads); 3975595Sgblack@eecs.umich.edu 3986221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; ++tid) { 3998793Sgblack@eecs.umich.edu if (FullSystem) { 4008793Sgblack@eecs.umich.edu // SMT is not supported in FS mode yet. 4018793Sgblack@eecs.umich.edu assert(this->numThreads == 1); 4028793Sgblack@eecs.umich.edu this->thread[tid] = new Thread(this, 0, NULL); 4038793Sgblack@eecs.umich.edu } else { 4048793Sgblack@eecs.umich.edu if (tid < params->workload.size()) { 4058793Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Workload[%i] process is %#x", 4068793Sgblack@eecs.umich.edu tid, this->thread[tid]); 4078793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 4088793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 4098793Sgblack@eecs.umich.edu tid, params->workload[tid]); 4105595Sgblack@eecs.umich.edu 4118793Sgblack@eecs.umich.edu //usedTids[tid] = true; 4128793Sgblack@eecs.umich.edu //threadMap[tid] = tid; 4138793Sgblack@eecs.umich.edu } else { 4148793Sgblack@eecs.umich.edu //Allocate Empty thread so M5 can use later 4158793Sgblack@eecs.umich.edu //when scheduling threads to CPU 4168793Sgblack@eecs.umich.edu Process* dummy_proc = NULL; 4175595Sgblack@eecs.umich.edu 4188793Sgblack@eecs.umich.edu this->thread[tid] = new typename FullO3CPU<Impl>::Thread( 4198793Sgblack@eecs.umich.edu (typename Impl::O3CPU *)(this), 4208793Sgblack@eecs.umich.edu tid, dummy_proc); 4218793Sgblack@eecs.umich.edu //usedTids[tid] = false; 4228793Sgblack@eecs.umich.edu } 4235595Sgblack@eecs.umich.edu } 4245595Sgblack@eecs.umich.edu 4255595Sgblack@eecs.umich.edu ThreadContext *tc; 4265595Sgblack@eecs.umich.edu 4275595Sgblack@eecs.umich.edu // Setup the TC that will serve as the interface to the threads/CPU. 4285595Sgblack@eecs.umich.edu O3ThreadContext<Impl> *o3_tc = new O3ThreadContext<Impl>; 4295595Sgblack@eecs.umich.edu 4305595Sgblack@eecs.umich.edu tc = o3_tc; 4315595Sgblack@eecs.umich.edu 4325595Sgblack@eecs.umich.edu // If we're using a checker, then the TC should be the 4335595Sgblack@eecs.umich.edu // CheckerThreadContext. 4345595Sgblack@eecs.umich.edu if (params->checker) { 4355595Sgblack@eecs.umich.edu tc = new CheckerThreadContext<O3ThreadContext<Impl> >( 4365595Sgblack@eecs.umich.edu o3_tc, this->checker); 4375595Sgblack@eecs.umich.edu } 4385595Sgblack@eecs.umich.edu 4395595Sgblack@eecs.umich.edu o3_tc->cpu = (typename Impl::O3CPU *)(this); 4405595Sgblack@eecs.umich.edu assert(o3_tc->cpu); 4416221Snate@binkert.org o3_tc->thread = this->thread[tid]; 4425595Sgblack@eecs.umich.edu 4438793Sgblack@eecs.umich.edu if (FullSystem) { 4448793Sgblack@eecs.umich.edu // Setup quiesce event. 4458793Sgblack@eecs.umich.edu this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc); 4468793Sgblack@eecs.umich.edu } 4475595Sgblack@eecs.umich.edu // Give the thread the TC. 4486221Snate@binkert.org this->thread[tid]->tc = tc; 4495595Sgblack@eecs.umich.edu 4505595Sgblack@eecs.umich.edu // Add the TC to the CPU's list of TC's. 4515595Sgblack@eecs.umich.edu this->threadContexts.push_back(tc); 4525595Sgblack@eecs.umich.edu } 4535595Sgblack@eecs.umich.edu 4548876Sandreas.hansson@arm.com // FullO3CPU always requires an interrupt controller. 4559433SAndreas.Sandberg@ARM.com if (!params->switched_out && !interrupts) { 4568876Sandreas.hansson@arm.com fatal("FullO3CPU %s has no interrupt controller.\n" 4578876Sandreas.hansson@arm.com "Ensure createInterruptController() is called.\n", name()); 4588876Sandreas.hansson@arm.com } 4598876Sandreas.hansson@arm.com 4606221Snate@binkert.org for (ThreadID tid = 0; tid < this->numThreads; tid++) 4616221Snate@binkert.org this->thread[tid]->setFuncExeInst(0); 4621060SN/A} 4631060SN/A 4641060SN/Atemplate <class Impl> 4651755SN/AFullO3CPU<Impl>::~FullO3CPU() 4661060SN/A{ 4671060SN/A} 4681060SN/A 4691060SN/Atemplate <class Impl> 4701060SN/Avoid 47110023Smatt.horsnell@ARM.comFullO3CPU<Impl>::regProbePoints() 47210023Smatt.horsnell@ARM.com{ 47310023Smatt.horsnell@ARM.com ppInstAccessComplete = new ProbePointArg<PacketPtr>(getProbeManager(), "InstAccessComplete"); 47410023Smatt.horsnell@ARM.com ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete"); 47510023Smatt.horsnell@ARM.com fetch.regProbePoints(); 47610023Smatt.horsnell@ARM.com iew.regProbePoints(); 47710023Smatt.horsnell@ARM.com commit.regProbePoints(); 47810023Smatt.horsnell@ARM.com} 47910023Smatt.horsnell@ARM.com 48010023Smatt.horsnell@ARM.comtemplate <class Impl> 48110023Smatt.horsnell@ARM.comvoid 4825595Sgblack@eecs.umich.eduFullO3CPU<Impl>::regStats() 4831062SN/A{ 4842733Sktlim@umich.edu BaseO3CPU::regStats(); 4852292SN/A 4862733Sktlim@umich.edu // Register any of the O3CPU's stats here. 4872292SN/A timesIdled 4882292SN/A .name(name() + ".timesIdled") 4892292SN/A .desc("Number of times that the entire CPU went into an idle state and" 4902292SN/A " unscheduled itself") 4912292SN/A .prereq(timesIdled); 4922292SN/A 4932292SN/A idleCycles 4942292SN/A .name(name() + ".idleCycles") 4952292SN/A .desc("Total number of cycles that the CPU has spent unscheduled due " 4962292SN/A "to idling") 4972292SN/A .prereq(idleCycles); 4982292SN/A 4998627SAli.Saidi@ARM.com quiesceCycles 5008627SAli.Saidi@ARM.com .name(name() + ".quiesceCycles") 5018627SAli.Saidi@ARM.com .desc("Total number of cycles that CPU has spent quiesced or waiting " 5028627SAli.Saidi@ARM.com "for an interrupt") 5038627SAli.Saidi@ARM.com .prereq(quiesceCycles); 5048627SAli.Saidi@ARM.com 5052292SN/A // Number of Instructions simulated 5062292SN/A // -------------------------------- 5072292SN/A // Should probably be in Base CPU but need templated 5082292SN/A // MaxThreads so put in here instead 5092292SN/A committedInsts 5102292SN/A .init(numThreads) 5112292SN/A .name(name() + ".committedInsts") 51210225Snilay@cs.wisc.edu .desc("Number of Instructions Simulated") 51310225Snilay@cs.wisc.edu .flags(Stats::total); 5142292SN/A 5158834Satgutier@umich.edu committedOps 5168834Satgutier@umich.edu .init(numThreads) 5178834Satgutier@umich.edu .name(name() + ".committedOps") 51810225Snilay@cs.wisc.edu .desc("Number of Ops (including micro ops) Simulated") 51910225Snilay@cs.wisc.edu .flags(Stats::total); 5202292SN/A 5212292SN/A cpi 5222292SN/A .name(name() + ".cpi") 5232292SN/A .desc("CPI: Cycles Per Instruction") 5242292SN/A .precision(6); 5254392Sktlim@umich.edu cpi = numCycles / committedInsts; 5262292SN/A 5272292SN/A totalCpi 5282292SN/A .name(name() + ".cpi_total") 5292292SN/A .desc("CPI: Total CPI of All Threads") 5302292SN/A .precision(6); 53110225Snilay@cs.wisc.edu totalCpi = numCycles / sum(committedInsts); 5322292SN/A 5332292SN/A ipc 5342292SN/A .name(name() + ".ipc") 5352292SN/A .desc("IPC: Instructions Per Cycle") 5362292SN/A .precision(6); 5374392Sktlim@umich.edu ipc = committedInsts / numCycles; 5382292SN/A 5392292SN/A totalIpc 5402292SN/A .name(name() + ".ipc_total") 5412292SN/A .desc("IPC: Total IPC of All Threads") 5422292SN/A .precision(6); 54310225Snilay@cs.wisc.edu totalIpc = sum(committedInsts) / numCycles; 5442292SN/A 5455595Sgblack@eecs.umich.edu this->fetch.regStats(); 5465595Sgblack@eecs.umich.edu this->decode.regStats(); 5475595Sgblack@eecs.umich.edu this->rename.regStats(); 5485595Sgblack@eecs.umich.edu this->iew.regStats(); 5495595Sgblack@eecs.umich.edu this->commit.regStats(); 5507897Shestness@cs.utexas.edu this->rob.regStats(); 5517897Shestness@cs.utexas.edu 5527897Shestness@cs.utexas.edu intRegfileReads 5537897Shestness@cs.utexas.edu .name(name() + ".int_regfile_reads") 5547897Shestness@cs.utexas.edu .desc("number of integer regfile reads") 5557897Shestness@cs.utexas.edu .prereq(intRegfileReads); 5567897Shestness@cs.utexas.edu 5577897Shestness@cs.utexas.edu intRegfileWrites 5587897Shestness@cs.utexas.edu .name(name() + ".int_regfile_writes") 5597897Shestness@cs.utexas.edu .desc("number of integer regfile writes") 5607897Shestness@cs.utexas.edu .prereq(intRegfileWrites); 5617897Shestness@cs.utexas.edu 5627897Shestness@cs.utexas.edu fpRegfileReads 5637897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_reads") 5647897Shestness@cs.utexas.edu .desc("number of floating regfile reads") 5657897Shestness@cs.utexas.edu .prereq(fpRegfileReads); 5667897Shestness@cs.utexas.edu 5677897Shestness@cs.utexas.edu fpRegfileWrites 5687897Shestness@cs.utexas.edu .name(name() + ".fp_regfile_writes") 5697897Shestness@cs.utexas.edu .desc("number of floating regfile writes") 5707897Shestness@cs.utexas.edu .prereq(fpRegfileWrites); 5717897Shestness@cs.utexas.edu 5729920Syasuko.eckert@amd.com ccRegfileReads 5739920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_reads") 5749920Syasuko.eckert@amd.com .desc("number of cc regfile reads") 5759920Syasuko.eckert@amd.com .prereq(ccRegfileReads); 5769920Syasuko.eckert@amd.com 5779920Syasuko.eckert@amd.com ccRegfileWrites 5789920Syasuko.eckert@amd.com .name(name() + ".cc_regfile_writes") 5799920Syasuko.eckert@amd.com .desc("number of cc regfile writes") 5809920Syasuko.eckert@amd.com .prereq(ccRegfileWrites); 5819920Syasuko.eckert@amd.com 5827897Shestness@cs.utexas.edu miscRegfileReads 5837897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_reads") 5847897Shestness@cs.utexas.edu .desc("number of misc regfile reads") 5857897Shestness@cs.utexas.edu .prereq(miscRegfileReads); 5867897Shestness@cs.utexas.edu 5877897Shestness@cs.utexas.edu miscRegfileWrites 5887897Shestness@cs.utexas.edu .name(name() + ".misc_regfile_writes") 5897897Shestness@cs.utexas.edu .desc("number of misc regfile writes") 5907897Shestness@cs.utexas.edu .prereq(miscRegfileWrites); 5911062SN/A} 5921062SN/A 5931062SN/Atemplate <class Impl> 5941062SN/Avoid 5951755SN/AFullO3CPU<Impl>::tick() 5961060SN/A{ 5972733Sktlim@umich.edu DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); 5989444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 5999444SAndreas.Sandberg@ARM.com assert(getDrainState() != Drainable::Drained); 6001060SN/A 6012292SN/A ++numCycles; 6022292SN/A 6032325SN/A// activity = false; 6042292SN/A 6052292SN/A //Tick each of the stages 6061060SN/A fetch.tick(); 6071060SN/A 6081060SN/A decode.tick(); 6091060SN/A 6101060SN/A rename.tick(); 6111060SN/A 6121060SN/A iew.tick(); 6131060SN/A 6141060SN/A commit.tick(); 6151060SN/A 6168793Sgblack@eecs.umich.edu if (!FullSystem) 6178793Sgblack@eecs.umich.edu doContextSwitch(); 6182292SN/A 6192292SN/A // Now advance the time buffers 6201060SN/A timeBuffer.advance(); 6211060SN/A 6221060SN/A fetchQueue.advance(); 6231060SN/A decodeQueue.advance(); 6241060SN/A renameQueue.advance(); 6251060SN/A iewQueue.advance(); 6261060SN/A 6272325SN/A activityRec.advance(); 6282292SN/A 6292292SN/A if (removeInstsThisCycle) { 6302292SN/A cleanUpRemovedInsts(); 6312292SN/A } 6322292SN/A 6332325SN/A if (!tickEvent.scheduled()) { 6349444SAndreas.Sandberg@ARM.com if (_status == SwitchedOut) { 6353226Sktlim@umich.edu DPRINTF(O3CPU, "Switched out!\n"); 6362325SN/A // increment stat 6379179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 6383221Sktlim@umich.edu } else if (!activityRec.active() || _status == Idle) { 6393226Sktlim@umich.edu DPRINTF(O3CPU, "Idle!\n"); 6409179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 6412325SN/A timesIdled++; 6422325SN/A } else { 6439180Sandreas.hansson@arm.com schedule(tickEvent, clockEdge(Cycles(1))); 6443226Sktlim@umich.edu DPRINTF(O3CPU, "Scheduling next tick!\n"); 6452325SN/A } 6462292SN/A } 6472292SN/A 6488793Sgblack@eecs.umich.edu if (!FullSystem) 6498793Sgblack@eecs.umich.edu updateThreadPriority(); 6509444SAndreas.Sandberg@ARM.com 6519444SAndreas.Sandberg@ARM.com tryDrain(); 6521060SN/A} 6531060SN/A 6541060SN/Atemplate <class Impl> 6551060SN/Avoid 6561755SN/AFullO3CPU<Impl>::init() 6571060SN/A{ 6585714Shsul@eecs.umich.edu BaseCPU::init(); 6591060SN/A 6608921Sandreas.hansson@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) { 6619382SAli.Saidi@ARM.com // Set noSquashFromTC so that the CPU doesn't squash when initially 6628921Sandreas.hansson@arm.com // setting up registers. 6639382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = true; 6648921Sandreas.hansson@arm.com // Initialise the ThreadContext's memory proxies 6658921Sandreas.hansson@arm.com thread[tid]->initMemProxies(thread[tid]->getTC()); 6668921Sandreas.hansson@arm.com } 6672292SN/A 6689433SAndreas.Sandberg@ARM.com if (FullSystem && !params()->switched_out) { 6698793Sgblack@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 6708793Sgblack@eecs.umich.edu ThreadContext *src_tc = threadContexts[tid]; 6718793Sgblack@eecs.umich.edu TheISA::initCPU(src_tc, src_tc->contextId()); 6728793Sgblack@eecs.umich.edu } 6736034Ssteve.reinhardt@amd.com } 6742292SN/A 6759382SAli.Saidi@ARM.com // Clear noSquashFromTC. 6766221Snate@binkert.org for (int tid = 0; tid < numThreads; ++tid) 6779382SAli.Saidi@ARM.com thread[tid]->noSquashFromTC = false; 6782292SN/A 6799427SAndreas.Sandberg@ARM.com commit.setThreads(thread); 6809427SAndreas.Sandberg@ARM.com} 6812292SN/A 6829427SAndreas.Sandberg@ARM.comtemplate <class Impl> 6839427SAndreas.Sandberg@ARM.comvoid 6849427SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::startup() 6859427SAndreas.Sandberg@ARM.com{ 6869992Snilay@cs.wisc.edu BaseCPU::startup(); 6879461Snilay@cs.wisc.edu for (int tid = 0; tid < numThreads; ++tid) 6889461Snilay@cs.wisc.edu isa[tid]->startup(threadContexts[tid]); 6899461Snilay@cs.wisc.edu 6909427SAndreas.Sandberg@ARM.com fetch.startupStage(); 6919444SAndreas.Sandberg@ARM.com decode.startupStage(); 6929427SAndreas.Sandberg@ARM.com iew.startupStage(); 6939427SAndreas.Sandberg@ARM.com rename.startupStage(); 6949427SAndreas.Sandberg@ARM.com commit.startupStage(); 6952292SN/A} 6962292SN/A 6972292SN/Atemplate <class Impl> 6982292SN/Avoid 6996221Snate@binkert.orgFullO3CPU<Impl>::activateThread(ThreadID tid) 7002875Sksewell@umich.edu{ 7016221Snate@binkert.org list<ThreadID>::iterator isActive = 7025314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 7032875Sksewell@umich.edu 7043226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid); 7059444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 7063226Sktlim@umich.edu 7072875Sksewell@umich.edu if (isActive == activeThreads.end()) { 7082875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n", 7092875Sksewell@umich.edu tid); 7102875Sksewell@umich.edu 7112875Sksewell@umich.edu activeThreads.push_back(tid); 7122875Sksewell@umich.edu } 7132875Sksewell@umich.edu} 7142875Sksewell@umich.edu 7152875Sksewell@umich.edutemplate <class Impl> 7162875Sksewell@umich.eduvoid 7176221Snate@binkert.orgFullO3CPU<Impl>::deactivateThread(ThreadID tid) 7182875Sksewell@umich.edu{ 7192875Sksewell@umich.edu //Remove From Active List, if Active 7206221Snate@binkert.org list<ThreadID>::iterator thread_it = 7215314Sstever@gmail.com std::find(activeThreads.begin(), activeThreads.end(), tid); 7222875Sksewell@umich.edu 7233226Sktlim@umich.edu DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid); 7249444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 7253226Sktlim@umich.edu 7262875Sksewell@umich.edu if (thread_it != activeThreads.end()) { 7272875Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", 7282875Sksewell@umich.edu tid); 7292875Sksewell@umich.edu activeThreads.erase(thread_it); 7302875Sksewell@umich.edu } 7312875Sksewell@umich.edu} 7322875Sksewell@umich.edu 7332875Sksewell@umich.edutemplate <class Impl> 7346221Snate@binkert.orgCounter 7358834Satgutier@umich.eduFullO3CPU<Impl>::totalInsts() const 7366221Snate@binkert.org{ 7376221Snate@binkert.org Counter total(0); 7386221Snate@binkert.org 7396221Snate@binkert.org ThreadID size = thread.size(); 7406221Snate@binkert.org for (ThreadID i = 0; i < size; i++) 7416221Snate@binkert.org total += thread[i]->numInst; 7426221Snate@binkert.org 7436221Snate@binkert.org return total; 7446221Snate@binkert.org} 7456221Snate@binkert.org 7466221Snate@binkert.orgtemplate <class Impl> 7478834Satgutier@umich.eduCounter 7488834Satgutier@umich.eduFullO3CPU<Impl>::totalOps() const 7498834Satgutier@umich.edu{ 7508834Satgutier@umich.edu Counter total(0); 7518834Satgutier@umich.edu 7528834Satgutier@umich.edu ThreadID size = thread.size(); 7538834Satgutier@umich.edu for (ThreadID i = 0; i < size; i++) 7548834Satgutier@umich.edu total += thread[i]->numOp; 7558834Satgutier@umich.edu 7568834Satgutier@umich.edu return total; 7578834Satgutier@umich.edu} 7588834Satgutier@umich.edu 7598834Satgutier@umich.edutemplate <class Impl> 7602875Sksewell@umich.eduvoid 7619180Sandreas.hansson@arm.comFullO3CPU<Impl>::activateContext(ThreadID tid, Cycles delay) 7622875Sksewell@umich.edu{ 7639444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 7649444SAndreas.Sandberg@ARM.com 7652875Sksewell@umich.edu // Needs to set each stage to running as well. 7662875Sksewell@umich.edu if (delay){ 7672875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " 7689180Sandreas.hansson@arm.com "on cycle %d\n", tid, clockEdge(delay)); 7692875Sksewell@umich.edu scheduleActivateThreadEvent(tid, delay); 7702875Sksewell@umich.edu } else { 7712875Sksewell@umich.edu activateThread(tid); 7722875Sksewell@umich.edu } 7732875Sksewell@umich.edu 7749444SAndreas.Sandberg@ARM.com // We don't want to wake the CPU if it is drained. In that case, 7759444SAndreas.Sandberg@ARM.com // we just want to flag the thread as active and schedule the tick 7769444SAndreas.Sandberg@ARM.com // event from drainResume() instead. 7779444SAndreas.Sandberg@ARM.com if (getDrainState() == Drainable::Drained) 7789444SAndreas.Sandberg@ARM.com return; 7799444SAndreas.Sandberg@ARM.com 7809158Sandreas.hansson@arm.com // If we are time 0 or if the last activation time is in the past, 7819158Sandreas.hansson@arm.com // schedule the next tick and wake up the fetch unit 7829158Sandreas.hansson@arm.com if (lastActivatedCycle == 0 || lastActivatedCycle < curTick()) { 7832875Sksewell@umich.edu scheduleTickEvent(delay); 7842875Sksewell@umich.edu 7852875Sksewell@umich.edu // Be sure to signal that there's some activity so the CPU doesn't 7862875Sksewell@umich.edu // deschedule itself. 7872875Sksewell@umich.edu activityRec.activity(); 7882875Sksewell@umich.edu fetch.wakeFromQuiesce(); 7892875Sksewell@umich.edu 7909180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 7919180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 7929179Sandreas.hansson@arm.com if (cycles != 0) 7939179Sandreas.hansson@arm.com --cycles; 7949179Sandreas.hansson@arm.com quiesceCycles += cycles; 7958627SAli.Saidi@ARM.com 7967823Ssteve.reinhardt@amd.com lastActivatedCycle = curTick(); 7972875Sksewell@umich.edu 7982875Sksewell@umich.edu _status = Running; 7992875Sksewell@umich.edu } 8002875Sksewell@umich.edu} 8012875Sksewell@umich.edu 8022875Sksewell@umich.edutemplate <class Impl> 8033221Sktlim@umich.edubool 8048737Skoansin.tan@gmail.comFullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove, 8059180Sandreas.hansson@arm.com Cycles delay) 8062875Sksewell@umich.edu{ 8072875Sksewell@umich.edu // Schedule removal of thread data from CPU 8082875Sksewell@umich.edu if (delay){ 8092875Sksewell@umich.edu DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " 8109180Sandreas.hansson@arm.com "on tick %d\n", tid, clockEdge(delay)); 8113221Sktlim@umich.edu scheduleDeallocateContextEvent(tid, remove, delay); 8123221Sktlim@umich.edu return false; 8132875Sksewell@umich.edu } else { 8142875Sksewell@umich.edu deactivateThread(tid); 8153221Sktlim@umich.edu if (remove) 8163221Sktlim@umich.edu removeThread(tid); 8173221Sktlim@umich.edu return true; 8182875Sksewell@umich.edu } 8192875Sksewell@umich.edu} 8202875Sksewell@umich.edu 8212875Sksewell@umich.edutemplate <class Impl> 8222875Sksewell@umich.eduvoid 8236221Snate@binkert.orgFullO3CPU<Impl>::suspendContext(ThreadID tid) 8242875Sksewell@umich.edu{ 8252875Sksewell@umich.edu DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid); 8269444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 8279180Sandreas.hansson@arm.com bool deallocated = scheduleDeallocateContext(tid, false, Cycles(1)); 8283221Sktlim@umich.edu // If this was the last thread then unschedule the tick event. 8295570Snate@binkert.org if ((activeThreads.size() == 1 && !deallocated) || 8303859Sbinkertn@umich.edu activeThreads.size() == 0) 8312910Sksewell@umich.edu unscheduleTickEvent(); 8328627SAli.Saidi@ARM.com 8338627SAli.Saidi@ARM.com DPRINTF(Quiesce, "Suspending Context\n"); 8349179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 8352875Sksewell@umich.edu _status = Idle; 8362875Sksewell@umich.edu} 8372875Sksewell@umich.edu 8382875Sksewell@umich.edutemplate <class Impl> 8392875Sksewell@umich.eduvoid 8406221Snate@binkert.orgFullO3CPU<Impl>::haltContext(ThreadID tid) 8412875Sksewell@umich.edu{ 8422910Sksewell@umich.edu //For now, this is the same as deallocate 8432910Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid); 8449444SAndreas.Sandberg@ARM.com assert(!switchedOut()); 8459180Sandreas.hansson@arm.com scheduleDeallocateContext(tid, true, Cycles(1)); 8462875Sksewell@umich.edu} 8472875Sksewell@umich.edu 8482875Sksewell@umich.edutemplate <class Impl> 8492875Sksewell@umich.eduvoid 8506221Snate@binkert.orgFullO3CPU<Impl>::insertThread(ThreadID tid) 8512292SN/A{ 8522847Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU"); 8532292SN/A // Will change now that the PC and thread state is internal to the CPU 8542683Sktlim@umich.edu // and not in the ThreadContext. 8558793Sgblack@eecs.umich.edu ThreadContext *src_tc; 8568793Sgblack@eecs.umich.edu if (FullSystem) 8578793Sgblack@eecs.umich.edu src_tc = system->threadContexts[tid]; 8588793Sgblack@eecs.umich.edu else 8598793Sgblack@eecs.umich.edu src_tc = tcBase(tid); 8602292SN/A 8612292SN/A //Bind Int Regs to Rename Map 8622292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 8632292SN/A PhysRegIndex phys_reg = freeList.getIntReg(); 8642292SN/A 8652292SN/A renameMap[tid].setEntry(ireg,phys_reg); 8662292SN/A scoreboard.setReg(phys_reg); 8672292SN/A } 8682292SN/A 8692292SN/A //Bind Float Regs to Rename Map 8709920Syasuko.eckert@amd.com int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs; 8719920Syasuko.eckert@amd.com for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) { 8722292SN/A PhysRegIndex phys_reg = freeList.getFloatReg(); 8732292SN/A 8742292SN/A renameMap[tid].setEntry(freg,phys_reg); 8752292SN/A scoreboard.setReg(phys_reg); 8762292SN/A } 8772292SN/A 8789920Syasuko.eckert@amd.com //Bind condition-code Regs to Rename Map 8799920Syasuko.eckert@amd.com max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs; 8809920Syasuko.eckert@amd.com for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs; 8819920Syasuko.eckert@amd.com creg < max_reg; creg++) { 8829920Syasuko.eckert@amd.com PhysRegIndex phys_reg = freeList.getCCReg(); 8839920Syasuko.eckert@amd.com 8849920Syasuko.eckert@amd.com renameMap[tid].setEntry(creg,phys_reg); 8859920Syasuko.eckert@amd.com scoreboard.setReg(phys_reg); 8869920Syasuko.eckert@amd.com } 8879920Syasuko.eckert@amd.com 8882292SN/A //Copy Thread Data Into RegFile 8892847Sksewell@umich.edu //this->copyFromTC(tid); 8902292SN/A 8912847Sksewell@umich.edu //Set PC/NPC/NNPC 8927720Sgblack@eecs.umich.edu pcState(src_tc->pcState(), tid); 8932292SN/A 8942680Sktlim@umich.edu src_tc->setStatus(ThreadContext::Active); 8952292SN/A 8969180Sandreas.hansson@arm.com activateContext(tid, Cycles(1)); 8972292SN/A 8982292SN/A //Reset ROB/IQ/LSQ Entries 8992292SN/A commit.rob->resetEntries(); 9002292SN/A iew.resetEntries(); 9012292SN/A} 9022292SN/A 9032292SN/Atemplate <class Impl> 9042292SN/Avoid 9056221Snate@binkert.orgFullO3CPU<Impl>::removeThread(ThreadID tid) 9062292SN/A{ 9072877Sksewell@umich.edu DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid); 9082847Sksewell@umich.edu 9092847Sksewell@umich.edu // Copy Thread Data From RegFile 9102847Sksewell@umich.edu // If thread is suspended, it might be re-allocated 9115364Sksewell@umich.edu // this->copyToTC(tid); 9125364Sksewell@umich.edu 9135364Sksewell@umich.edu 9145364Sksewell@umich.edu // @todo: 2-27-2008: Fix how we free up rename mappings 9155364Sksewell@umich.edu // here to alleviate the case for double-freeing registers 9165364Sksewell@umich.edu // in SMT workloads. 9172847Sksewell@umich.edu 9182847Sksewell@umich.edu // Unbind Int Regs from Rename Map 9192292SN/A for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { 9202292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(ireg); 9212292SN/A 9222292SN/A scoreboard.unsetReg(phys_reg); 9232292SN/A freeList.addReg(phys_reg); 9242292SN/A } 9252292SN/A 9262847Sksewell@umich.edu // Unbind Float Regs from Rename Map 9279920Syasuko.eckert@amd.com int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs; 9289920Syasuko.eckert@amd.com for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) { 9292292SN/A PhysRegIndex phys_reg = renameMap[tid].lookup(freg); 9302292SN/A 9312292SN/A scoreboard.unsetReg(phys_reg); 9322292SN/A freeList.addReg(phys_reg); 9332292SN/A } 9342292SN/A 9359920Syasuko.eckert@amd.com // Unbind condition-code Regs from Rename Map 9369920Syasuko.eckert@amd.com max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs; 9379920Syasuko.eckert@amd.com for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs; 9389920Syasuko.eckert@amd.com creg < max_reg; creg++) { 9399920Syasuko.eckert@amd.com PhysRegIndex phys_reg = renameMap[tid].lookup(creg); 9409920Syasuko.eckert@amd.com 9419920Syasuko.eckert@amd.com scoreboard.unsetReg(phys_reg); 9429920Syasuko.eckert@amd.com freeList.addReg(phys_reg); 9439920Syasuko.eckert@amd.com } 9449920Syasuko.eckert@amd.com 9452847Sksewell@umich.edu // Squash Throughout Pipeline 9468138SAli.Saidi@ARM.com DynInstPtr inst = commit.rob->readHeadInst(tid); 9478138SAli.Saidi@ARM.com InstSeqNum squash_seq_num = inst->seqNum; 9488138SAli.Saidi@ARM.com fetch.squash(0, squash_seq_num, inst, tid); 9492292SN/A decode.squash(tid); 9502935Sksewell@umich.edu rename.squash(squash_seq_num, tid); 9512875Sksewell@umich.edu iew.squash(tid); 9525363Sksewell@umich.edu iew.ldstQueue.squash(squash_seq_num, tid); 9532935Sksewell@umich.edu commit.rob->squash(squash_seq_num, tid); 9542292SN/A 9555362Sksewell@umich.edu 9565362Sksewell@umich.edu assert(iew.instQueue.getCount(tid) == 0); 9572292SN/A assert(iew.ldstQueue.getCount(tid) == 0); 9582292SN/A 9592847Sksewell@umich.edu // Reset ROB/IQ/LSQ Entries 9603229Sktlim@umich.edu 9613229Sktlim@umich.edu // Commented out for now. This should be possible to do by 9623229Sktlim@umich.edu // telling all the pipeline stages to drain first, and then 9633229Sktlim@umich.edu // checking until the drain completes. Once the pipeline is 9643229Sktlim@umich.edu // drained, call resetEntries(). - 10-09-06 ktlim 9653229Sktlim@umich.edu/* 9662292SN/A if (activeThreads.size() >= 1) { 9672292SN/A commit.rob->resetEntries(); 9682292SN/A iew.resetEntries(); 9692292SN/A } 9703229Sktlim@umich.edu*/ 9712292SN/A} 9722292SN/A 9732292SN/A 9742292SN/Atemplate <class Impl> 9752292SN/Avoid 9766221Snate@binkert.orgFullO3CPU<Impl>::activateWhenReady(ThreadID tid) 9772292SN/A{ 9782733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" 9792292SN/A "(e.g. PhysRegs/ROB/IQ/LSQ) \n", 9802292SN/A tid); 9812292SN/A 9822292SN/A bool ready = true; 9832292SN/A 9849920Syasuko.eckert@amd.com // Should these all be '<' not '>='? This seems backwards... 9852292SN/A if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { 9862733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9872292SN/A "Phys. Int. Regs.\n", 9882292SN/A tid); 9892292SN/A ready = false; 9902292SN/A } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { 9912733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9922292SN/A "Phys. Float. Regs.\n", 9932292SN/A tid); 9942292SN/A ready = false; 9959920Syasuko.eckert@amd.com } else if (freeList.numFreeCCRegs() >= TheISA::NumCCRegs) { 9969920Syasuko.eckert@amd.com DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 9979920Syasuko.eckert@amd.com "Phys. CC. Regs.\n", 9989920Syasuko.eckert@amd.com tid); 9999920Syasuko.eckert@amd.com ready = false; 10002292SN/A } else if (commit.rob->numFreeEntries() >= 10012292SN/A commit.rob->entryAmount(activeThreads.size() + 1)) { 10022733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 10032292SN/A "ROB entries.\n", 10042292SN/A tid); 10052292SN/A ready = false; 10062292SN/A } else if (iew.instQueue.numFreeEntries() >= 10072292SN/A iew.instQueue.entryAmount(activeThreads.size() + 1)) { 10082733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 10092292SN/A "IQ entries.\n", 10102292SN/A tid); 10112292SN/A ready = false; 10122292SN/A } else if (iew.ldstQueue.numFreeEntries() >= 10132292SN/A iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { 10142733Sktlim@umich.edu DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " 10152292SN/A "LSQ entries.\n", 10162292SN/A tid); 10172292SN/A ready = false; 10182292SN/A } 10192292SN/A 10202292SN/A if (ready) { 10212292SN/A insertThread(tid); 10222292SN/A 10232292SN/A contextSwitch = false; 10242292SN/A 10252292SN/A cpuWaitList.remove(tid); 10262292SN/A } else { 10272292SN/A suspendContext(tid); 10282292SN/A 10292292SN/A //blocks fetch 10302292SN/A contextSwitch = true; 10312292SN/A 10322875Sksewell@umich.edu //@todo: dont always add to waitlist 10332292SN/A //do waitlist 10342292SN/A cpuWaitList.push_back(tid); 10351060SN/A } 10361060SN/A} 10371060SN/A 10384192Sktlim@umich.edutemplate <class Impl> 10395595Sgblack@eecs.umich.eduFault 10406221Snate@binkert.orgFullO3CPU<Impl>::hwrei(ThreadID tid) 10415702Ssaidi@eecs.umich.edu{ 10425702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 10435702Ssaidi@eecs.umich.edu // Need to clear the lock flag upon returning from an interrupt. 10445702Ssaidi@eecs.umich.edu this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); 10455702Ssaidi@eecs.umich.edu 10465702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->hwrei(); 10475702Ssaidi@eecs.umich.edu 10485702Ssaidi@eecs.umich.edu // FIXME: XXX check for interrupts? XXX 10495702Ssaidi@eecs.umich.edu#endif 10505702Ssaidi@eecs.umich.edu return NoFault; 10515702Ssaidi@eecs.umich.edu} 10525702Ssaidi@eecs.umich.edu 10535702Ssaidi@eecs.umich.edutemplate <class Impl> 10545702Ssaidi@eecs.umich.edubool 10556221Snate@binkert.orgFullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid) 10565702Ssaidi@eecs.umich.edu{ 10575702Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 10585702Ssaidi@eecs.umich.edu if (this->thread[tid]->kernelStats) 10595702Ssaidi@eecs.umich.edu this->thread[tid]->kernelStats->callpal(palFunc, 10605702Ssaidi@eecs.umich.edu this->threadContexts[tid]); 10615702Ssaidi@eecs.umich.edu 10625702Ssaidi@eecs.umich.edu switch (palFunc) { 10635702Ssaidi@eecs.umich.edu case PAL::halt: 10645702Ssaidi@eecs.umich.edu halt(); 10655702Ssaidi@eecs.umich.edu if (--System::numSystemsRunning == 0) 10665702Ssaidi@eecs.umich.edu exitSimLoop("all cpus halted"); 10675702Ssaidi@eecs.umich.edu break; 10685702Ssaidi@eecs.umich.edu 10695702Ssaidi@eecs.umich.edu case PAL::bpt: 10705702Ssaidi@eecs.umich.edu case PAL::bugchk: 10715702Ssaidi@eecs.umich.edu if (this->system->breakpoint()) 10725702Ssaidi@eecs.umich.edu return false; 10735702Ssaidi@eecs.umich.edu break; 10745702Ssaidi@eecs.umich.edu } 10755702Ssaidi@eecs.umich.edu#endif 10765702Ssaidi@eecs.umich.edu return true; 10775702Ssaidi@eecs.umich.edu} 10785702Ssaidi@eecs.umich.edu 10795702Ssaidi@eecs.umich.edutemplate <class Impl> 10805702Ssaidi@eecs.umich.eduFault 10815595Sgblack@eecs.umich.eduFullO3CPU<Impl>::getInterrupts() 10825595Sgblack@eecs.umich.edu{ 10835595Sgblack@eecs.umich.edu // Check if there are any outstanding interrupts 10845647Sgblack@eecs.umich.edu return this->interrupts->getInterrupt(this->threadContexts[0]); 10855595Sgblack@eecs.umich.edu} 10865595Sgblack@eecs.umich.edu 10875595Sgblack@eecs.umich.edutemplate <class Impl> 10885595Sgblack@eecs.umich.eduvoid 10895595Sgblack@eecs.umich.eduFullO3CPU<Impl>::processInterrupts(Fault interrupt) 10905595Sgblack@eecs.umich.edu{ 10915595Sgblack@eecs.umich.edu // Check for interrupts here. For now can copy the code that 10925595Sgblack@eecs.umich.edu // exists within isa_fullsys_traits.hh. Also assume that thread 0 10935595Sgblack@eecs.umich.edu // is the one that handles the interrupts. 10945595Sgblack@eecs.umich.edu // @todo: Possibly consolidate the interrupt checking code. 10955595Sgblack@eecs.umich.edu // @todo: Allow other threads to handle interrupts. 10965595Sgblack@eecs.umich.edu 10975595Sgblack@eecs.umich.edu assert(interrupt != NoFault); 10985647Sgblack@eecs.umich.edu this->interrupts->updateIntrInfo(this->threadContexts[0]); 10995595Sgblack@eecs.umich.edu 11005595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); 11017684Sgblack@eecs.umich.edu this->trap(interrupt, 0, NULL); 11025595Sgblack@eecs.umich.edu} 11035595Sgblack@eecs.umich.edu 11041060SN/Atemplate <class Impl> 11052852Sktlim@umich.eduvoid 11067684Sgblack@eecs.umich.eduFullO3CPU<Impl>::trap(Fault fault, ThreadID tid, StaticInstPtr inst) 11075595Sgblack@eecs.umich.edu{ 11085595Sgblack@eecs.umich.edu // Pass the thread's TC into the invoke method. 11097684Sgblack@eecs.umich.edu fault->invoke(this->threadContexts[tid], inst); 11105595Sgblack@eecs.umich.edu} 11115595Sgblack@eecs.umich.edu 11125595Sgblack@eecs.umich.edutemplate <class Impl> 11135595Sgblack@eecs.umich.eduvoid 11146221Snate@binkert.orgFullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid) 11155595Sgblack@eecs.umich.edu{ 11165595Sgblack@eecs.umich.edu DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); 11175595Sgblack@eecs.umich.edu 11185595Sgblack@eecs.umich.edu DPRINTF(Activity,"Activity: syscall() called.\n"); 11195595Sgblack@eecs.umich.edu 11205595Sgblack@eecs.umich.edu // Temporarily increase this by one to account for the syscall 11215595Sgblack@eecs.umich.edu // instruction. 11225595Sgblack@eecs.umich.edu ++(this->thread[tid]->funcExeInst); 11235595Sgblack@eecs.umich.edu 11245595Sgblack@eecs.umich.edu // Execute the actual syscall. 11255595Sgblack@eecs.umich.edu this->thread[tid]->syscall(callnum); 11265595Sgblack@eecs.umich.edu 11275595Sgblack@eecs.umich.edu // Decrease funcExeInst by one as the normal commit will handle 11285595Sgblack@eecs.umich.edu // incrementing it. 11295595Sgblack@eecs.umich.edu --(this->thread[tid]->funcExeInst); 11305595Sgblack@eecs.umich.edu} 11315595Sgblack@eecs.umich.edu 11325595Sgblack@eecs.umich.edutemplate <class Impl> 11335595Sgblack@eecs.umich.eduvoid 11349448SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::serializeThread(std::ostream &os, ThreadID tid) 11352864Sktlim@umich.edu{ 11369448SAndreas.Sandberg@ARM.com thread[tid]->serialize(os); 11372864Sktlim@umich.edu} 11382864Sktlim@umich.edu 11392864Sktlim@umich.edutemplate <class Impl> 11402864Sktlim@umich.eduvoid 11419448SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::unserializeThread(Checkpoint *cp, const std::string §ion, 11429448SAndreas.Sandberg@ARM.com ThreadID tid) 11432864Sktlim@umich.edu{ 11449448SAndreas.Sandberg@ARM.com thread[tid]->unserialize(cp, section); 11452864Sktlim@umich.edu} 11462864Sktlim@umich.edu 11472864Sktlim@umich.edutemplate <class Impl> 11482905Sktlim@umich.eduunsigned int 11499342SAndreas.Sandberg@arm.comFullO3CPU<Impl>::drain(DrainManager *drain_manager) 11501060SN/A{ 11519444SAndreas.Sandberg@ARM.com // If the CPU isn't doing anything, then return immediately. 11529444SAndreas.Sandberg@ARM.com if (switchedOut()) { 11539444SAndreas.Sandberg@ARM.com setDrainState(Drainable::Drained); 11549444SAndreas.Sandberg@ARM.com return 0; 11559444SAndreas.Sandberg@ARM.com } 11563512Sktlim@umich.edu 11579444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Draining...\n"); 11589444SAndreas.Sandberg@ARM.com setDrainState(Drainable::Draining); 11593512Sktlim@umich.edu 11609444SAndreas.Sandberg@ARM.com // We only need to signal a drain to the commit stage as this 11619444SAndreas.Sandberg@ARM.com // initiates squashing controls the draining. Once the commit 11629444SAndreas.Sandberg@ARM.com // stage commits an instruction where it is safe to stop, it'll 11639444SAndreas.Sandberg@ARM.com // squash the rest of the instructions in the pipeline and force 11649444SAndreas.Sandberg@ARM.com // the fetch stage to stall. The pipeline will be drained once all 11659444SAndreas.Sandberg@ARM.com // in-flight instructions have retired. 11662843Sktlim@umich.edu commit.drain(); 11672325SN/A 11682325SN/A // Wake the CPU and record activity so everything can drain out if 11692863Sktlim@umich.edu // the CPU was not able to immediately drain. 11709444SAndreas.Sandberg@ARM.com if (!isDrained()) { 11719342SAndreas.Sandberg@arm.com drainManager = drain_manager; 11722843Sktlim@umich.edu 11732863Sktlim@umich.edu wakeCPU(); 11742863Sktlim@umich.edu activityRec.activity(); 11752852Sktlim@umich.edu 11769152Satgutier@umich.edu DPRINTF(Drain, "CPU not drained\n"); 11779152Satgutier@umich.edu 11782905Sktlim@umich.edu return 1; 11792863Sktlim@umich.edu } else { 11809444SAndreas.Sandberg@ARM.com setDrainState(Drainable::Drained); 11819444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU is already drained\n"); 11829444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 11839444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 11849444SAndreas.Sandberg@ARM.com 11859444SAndreas.Sandberg@ARM.com // Flush out any old data from the time buffers. In 11869444SAndreas.Sandberg@ARM.com // particular, there might be some data in flight from the 11879444SAndreas.Sandberg@ARM.com // fetch stage that isn't visible in any of the CPU buffers we 11889444SAndreas.Sandberg@ARM.com // test in isDrained(). 11899444SAndreas.Sandberg@ARM.com for (int i = 0; i < timeBuffer.getSize(); ++i) { 11909444SAndreas.Sandberg@ARM.com timeBuffer.advance(); 11919444SAndreas.Sandberg@ARM.com fetchQueue.advance(); 11929444SAndreas.Sandberg@ARM.com decodeQueue.advance(); 11939444SAndreas.Sandberg@ARM.com renameQueue.advance(); 11949444SAndreas.Sandberg@ARM.com iewQueue.advance(); 11959444SAndreas.Sandberg@ARM.com } 11969444SAndreas.Sandberg@ARM.com 11979444SAndreas.Sandberg@ARM.com drainSanityCheck(); 11982905Sktlim@umich.edu return 0; 11992863Sktlim@umich.edu } 12002316SN/A} 12012310SN/A 12022316SN/Atemplate <class Impl> 12039444SAndreas.Sandberg@ARM.combool 12049444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::tryDrain() 12059444SAndreas.Sandberg@ARM.com{ 12069444SAndreas.Sandberg@ARM.com if (!drainManager || !isDrained()) 12079444SAndreas.Sandberg@ARM.com return false; 12089444SAndreas.Sandberg@ARM.com 12099444SAndreas.Sandberg@ARM.com if (tickEvent.scheduled()) 12109444SAndreas.Sandberg@ARM.com deschedule(tickEvent); 12119444SAndreas.Sandberg@ARM.com 12129444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU done draining, processing drain event\n"); 12139444SAndreas.Sandberg@ARM.com drainManager->signalDrainDone(); 12149444SAndreas.Sandberg@ARM.com drainManager = NULL; 12159444SAndreas.Sandberg@ARM.com 12169444SAndreas.Sandberg@ARM.com return true; 12179444SAndreas.Sandberg@ARM.com} 12189444SAndreas.Sandberg@ARM.com 12199444SAndreas.Sandberg@ARM.comtemplate <class Impl> 12209444SAndreas.Sandberg@ARM.comvoid 12219444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::drainSanityCheck() const 12229444SAndreas.Sandberg@ARM.com{ 12239444SAndreas.Sandberg@ARM.com assert(isDrained()); 12249444SAndreas.Sandberg@ARM.com fetch.drainSanityCheck(); 12259444SAndreas.Sandberg@ARM.com decode.drainSanityCheck(); 12269444SAndreas.Sandberg@ARM.com rename.drainSanityCheck(); 12279444SAndreas.Sandberg@ARM.com iew.drainSanityCheck(); 12289444SAndreas.Sandberg@ARM.com commit.drainSanityCheck(); 12299444SAndreas.Sandberg@ARM.com} 12309444SAndreas.Sandberg@ARM.com 12319444SAndreas.Sandberg@ARM.comtemplate <class Impl> 12329444SAndreas.Sandberg@ARM.combool 12339444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::isDrained() const 12349444SAndreas.Sandberg@ARM.com{ 12359444SAndreas.Sandberg@ARM.com bool drained(true); 12369444SAndreas.Sandberg@ARM.com 12379444SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < thread.size(); ++i) { 12389444SAndreas.Sandberg@ARM.com if (activateThreadEvent[i].scheduled()) { 12399444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU not drained, tread %i has a " 12409444SAndreas.Sandberg@ARM.com "pending activate event\n", i); 12419444SAndreas.Sandberg@ARM.com drained = false; 12429444SAndreas.Sandberg@ARM.com } 12439444SAndreas.Sandberg@ARM.com if (deallocateContextEvent[i].scheduled()) { 12449444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "CPU not drained, tread %i has a " 12459444SAndreas.Sandberg@ARM.com "pending deallocate context event\n", i); 12469444SAndreas.Sandberg@ARM.com drained = false; 12479444SAndreas.Sandberg@ARM.com } 12489444SAndreas.Sandberg@ARM.com } 12499444SAndreas.Sandberg@ARM.com 12509444SAndreas.Sandberg@ARM.com if (!instList.empty() || !removeList.empty()) { 12519444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Main CPU structures not drained.\n"); 12529444SAndreas.Sandberg@ARM.com drained = false; 12539444SAndreas.Sandberg@ARM.com } 12549444SAndreas.Sandberg@ARM.com 12559444SAndreas.Sandberg@ARM.com if (!fetch.isDrained()) { 12569444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Fetch not drained.\n"); 12579444SAndreas.Sandberg@ARM.com drained = false; 12589444SAndreas.Sandberg@ARM.com } 12599444SAndreas.Sandberg@ARM.com 12609444SAndreas.Sandberg@ARM.com if (!decode.isDrained()) { 12619444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Decode not drained.\n"); 12629444SAndreas.Sandberg@ARM.com drained = false; 12639444SAndreas.Sandberg@ARM.com } 12649444SAndreas.Sandberg@ARM.com 12659444SAndreas.Sandberg@ARM.com if (!rename.isDrained()) { 12669444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Rename not drained.\n"); 12679444SAndreas.Sandberg@ARM.com drained = false; 12689444SAndreas.Sandberg@ARM.com } 12699444SAndreas.Sandberg@ARM.com 12709444SAndreas.Sandberg@ARM.com if (!iew.isDrained()) { 12719444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "IEW not drained.\n"); 12729444SAndreas.Sandberg@ARM.com drained = false; 12739444SAndreas.Sandberg@ARM.com } 12749444SAndreas.Sandberg@ARM.com 12759444SAndreas.Sandberg@ARM.com if (!commit.isDrained()) { 12769444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Commit not drained.\n"); 12779444SAndreas.Sandberg@ARM.com drained = false; 12789444SAndreas.Sandberg@ARM.com } 12799444SAndreas.Sandberg@ARM.com 12809444SAndreas.Sandberg@ARM.com return drained; 12819444SAndreas.Sandberg@ARM.com} 12829444SAndreas.Sandberg@ARM.com 12839444SAndreas.Sandberg@ARM.comtemplate <class Impl> 12849444SAndreas.Sandberg@ARM.comvoid 12859444SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::commitDrained(ThreadID tid) 12869444SAndreas.Sandberg@ARM.com{ 12879444SAndreas.Sandberg@ARM.com fetch.drainStall(tid); 12889444SAndreas.Sandberg@ARM.com} 12899444SAndreas.Sandberg@ARM.com 12909444SAndreas.Sandberg@ARM.comtemplate <class Impl> 12912316SN/Avoid 12929342SAndreas.Sandberg@arm.comFullO3CPU<Impl>::drainResume() 12932316SN/A{ 12949444SAndreas.Sandberg@ARM.com setDrainState(Drainable::Running); 12959444SAndreas.Sandberg@ARM.com if (switchedOut()) 12969444SAndreas.Sandberg@ARM.com return; 12972316SN/A 12989444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Resuming...\n"); 12999523SAndreas.Sandberg@ARM.com verifyMemoryMode(); 13003319Shsul@eecs.umich.edu 13019444SAndreas.Sandberg@ARM.com fetch.drainResume(); 13029444SAndreas.Sandberg@ARM.com commit.drainResume(); 13032316SN/A 13049444SAndreas.Sandberg@ARM.com _status = Idle; 13059444SAndreas.Sandberg@ARM.com for (ThreadID i = 0; i < thread.size(); i++) { 13069444SAndreas.Sandberg@ARM.com if (thread[i]->status() == ThreadContext::Active) { 13079444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "Activating thread: %i\n", i); 13089444SAndreas.Sandberg@ARM.com activateThread(i); 13099444SAndreas.Sandberg@ARM.com _status = Running; 13102863Sktlim@umich.edu } 13112310SN/A } 13129444SAndreas.Sandberg@ARM.com 13139444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 13149444SAndreas.Sandberg@ARM.com if (_status == Running) 13159444SAndreas.Sandberg@ARM.com schedule(tickEvent, nextCycle()); 13162843Sktlim@umich.edu} 13172843Sktlim@umich.edu 13182843Sktlim@umich.edutemplate <class Impl> 13192843Sktlim@umich.eduvoid 13202843Sktlim@umich.eduFullO3CPU<Impl>::switchOut() 13212843Sktlim@umich.edu{ 13229444SAndreas.Sandberg@ARM.com DPRINTF(O3CPU, "Switching out\n"); 13239429SAndreas.Sandberg@ARM.com BaseCPU::switchOut(); 13249429SAndreas.Sandberg@ARM.com 13259444SAndreas.Sandberg@ARM.com activityRec.reset(); 13262843Sktlim@umich.edu 13272843Sktlim@umich.edu _status = SwitchedOut; 13288887Sgeoffrey.blake@arm.com 13292843Sktlim@umich.edu if (checker) 13302843Sktlim@umich.edu checker->switchOut(); 13311060SN/A} 13321060SN/A 13331060SN/Atemplate <class Impl> 13341060SN/Avoid 13351755SN/AFullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) 13361060SN/A{ 13378737Skoansin.tan@gmail.com BaseCPU::takeOverFrom(oldCPU); 13381060SN/A 13392307SN/A fetch.takeOverFrom(); 13402307SN/A decode.takeOverFrom(); 13412307SN/A rename.takeOverFrom(); 13422307SN/A iew.takeOverFrom(); 13432307SN/A commit.takeOverFrom(); 13442307SN/A 13459444SAndreas.Sandberg@ARM.com assert(!tickEvent.scheduled()); 13461060SN/A 13479152Satgutier@umich.edu FullO3CPU<Impl> *oldO3CPU = dynamic_cast<FullO3CPU<Impl>*>(oldCPU); 13489152Satgutier@umich.edu if (oldO3CPU) 13499152Satgutier@umich.edu globalSeqNum = oldO3CPU->globalSeqNum; 13509152Satgutier@umich.edu 13519179Sandreas.hansson@arm.com lastRunningCycle = curCycle(); 13529444SAndreas.Sandberg@ARM.com _status = Idle; 13531060SN/A} 13541060SN/A 13551060SN/Atemplate <class Impl> 13569523SAndreas.Sandberg@ARM.comvoid 13579523SAndreas.Sandberg@ARM.comFullO3CPU<Impl>::verifyMemoryMode() const 13589523SAndreas.Sandberg@ARM.com{ 13599524SAndreas.Sandberg@ARM.com if (!system->isTimingMode()) { 13609523SAndreas.Sandberg@ARM.com fatal("The O3 CPU requires the memory system to be in " 13619523SAndreas.Sandberg@ARM.com "'timing' mode.\n"); 13629523SAndreas.Sandberg@ARM.com } 13639523SAndreas.Sandberg@ARM.com} 13649523SAndreas.Sandberg@ARM.com 13659523SAndreas.Sandberg@ARM.comtemplate <class Impl> 13665595Sgblack@eecs.umich.eduTheISA::MiscReg 13676221Snate@binkert.orgFullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) 13685595Sgblack@eecs.umich.edu{ 13699384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscRegNoEffect(misc_reg); 13705595Sgblack@eecs.umich.edu} 13715595Sgblack@eecs.umich.edu 13725595Sgblack@eecs.umich.edutemplate <class Impl> 13735595Sgblack@eecs.umich.eduTheISA::MiscReg 13746221Snate@binkert.orgFullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) 13755595Sgblack@eecs.umich.edu{ 13767897Shestness@cs.utexas.edu miscRegfileReads++; 13779384SAndreas.Sandberg@arm.com return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); 13785595Sgblack@eecs.umich.edu} 13795595Sgblack@eecs.umich.edu 13805595Sgblack@eecs.umich.edutemplate <class Impl> 13815595Sgblack@eecs.umich.eduvoid 13825595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, 13836221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 13845595Sgblack@eecs.umich.edu{ 13859384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscRegNoEffect(misc_reg, val); 13865595Sgblack@eecs.umich.edu} 13875595Sgblack@eecs.umich.edu 13885595Sgblack@eecs.umich.edutemplate <class Impl> 13895595Sgblack@eecs.umich.eduvoid 13905595Sgblack@eecs.umich.eduFullO3CPU<Impl>::setMiscReg(int misc_reg, 13916221Snate@binkert.org const TheISA::MiscReg &val, ThreadID tid) 13925595Sgblack@eecs.umich.edu{ 13937897Shestness@cs.utexas.edu miscRegfileWrites++; 13949384SAndreas.Sandberg@arm.com this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); 13955595Sgblack@eecs.umich.edu} 13965595Sgblack@eecs.umich.edu 13975595Sgblack@eecs.umich.edutemplate <class Impl> 13981060SN/Auint64_t 13991755SN/AFullO3CPU<Impl>::readIntReg(int reg_idx) 14001060SN/A{ 14017897Shestness@cs.utexas.edu intRegfileReads++; 14021060SN/A return regFile.readIntReg(reg_idx); 14031060SN/A} 14041060SN/A 14051060SN/Atemplate <class Impl> 14062455SN/AFloatReg 14072455SN/AFullO3CPU<Impl>::readFloatReg(int reg_idx) 14081060SN/A{ 14097897Shestness@cs.utexas.edu fpRegfileReads++; 14102455SN/A return regFile.readFloatReg(reg_idx); 14111060SN/A} 14121060SN/A 14131060SN/Atemplate <class Impl> 14142455SN/AFloatRegBits 14152455SN/AFullO3CPU<Impl>::readFloatRegBits(int reg_idx) 14162455SN/A{ 14177897Shestness@cs.utexas.edu fpRegfileReads++; 14182455SN/A return regFile.readFloatRegBits(reg_idx); 14191060SN/A} 14201060SN/A 14211060SN/Atemplate <class Impl> 14229920Syasuko.eckert@amd.comCCReg 14239920Syasuko.eckert@amd.comFullO3CPU<Impl>::readCCReg(int reg_idx) 14249920Syasuko.eckert@amd.com{ 14259920Syasuko.eckert@amd.com ccRegfileReads++; 14269920Syasuko.eckert@amd.com return regFile.readCCReg(reg_idx); 14279920Syasuko.eckert@amd.com} 14289920Syasuko.eckert@amd.com 14299920Syasuko.eckert@amd.comtemplate <class Impl> 14301060SN/Avoid 14311755SN/AFullO3CPU<Impl>::setIntReg(int reg_idx, uint64_t val) 14321060SN/A{ 14337897Shestness@cs.utexas.edu intRegfileWrites++; 14341060SN/A regFile.setIntReg(reg_idx, val); 14351060SN/A} 14361060SN/A 14371060SN/Atemplate <class Impl> 14381060SN/Avoid 14392455SN/AFullO3CPU<Impl>::setFloatReg(int reg_idx, FloatReg val) 14401060SN/A{ 14417897Shestness@cs.utexas.edu fpRegfileWrites++; 14422455SN/A regFile.setFloatReg(reg_idx, val); 14431060SN/A} 14441060SN/A 14451060SN/Atemplate <class Impl> 14461060SN/Avoid 14472455SN/AFullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) 14482455SN/A{ 14497897Shestness@cs.utexas.edu fpRegfileWrites++; 14502455SN/A regFile.setFloatRegBits(reg_idx, val); 14511060SN/A} 14521060SN/A 14531060SN/Atemplate <class Impl> 14549920Syasuko.eckert@amd.comvoid 14559920Syasuko.eckert@amd.comFullO3CPU<Impl>::setCCReg(int reg_idx, CCReg val) 14569920Syasuko.eckert@amd.com{ 14579920Syasuko.eckert@amd.com ccRegfileWrites++; 14589920Syasuko.eckert@amd.com regFile.setCCReg(reg_idx, val); 14599920Syasuko.eckert@amd.com} 14609920Syasuko.eckert@amd.com 14619920Syasuko.eckert@amd.comtemplate <class Impl> 14621060SN/Auint64_t 14636221Snate@binkert.orgFullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) 14641060SN/A{ 14657897Shestness@cs.utexas.edu intRegfileReads++; 14669919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx); 14672292SN/A 14682292SN/A return regFile.readIntReg(phys_reg); 14692292SN/A} 14702292SN/A 14712292SN/Atemplate <class Impl> 14722292SN/Afloat 14736314Sgblack@eecs.umich.eduFullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) 14742292SN/A{ 14757897Shestness@cs.utexas.edu fpRegfileReads++; 14769919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 14772292SN/A 14782669Sktlim@umich.edu return regFile.readFloatReg(phys_reg); 14792292SN/A} 14802292SN/A 14812292SN/Atemplate <class Impl> 14822292SN/Auint64_t 14836221Snate@binkert.orgFullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) 14842292SN/A{ 14857897Shestness@cs.utexas.edu fpRegfileReads++; 14869919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 14872292SN/A 14882669Sktlim@umich.edu return regFile.readFloatRegBits(phys_reg); 14891060SN/A} 14901060SN/A 14911060SN/Atemplate <class Impl> 14929920Syasuko.eckert@amd.comCCReg 14939920Syasuko.eckert@amd.comFullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid) 14949920Syasuko.eckert@amd.com{ 14959920Syasuko.eckert@amd.com ccRegfileReads++; 14969920Syasuko.eckert@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx); 14979920Syasuko.eckert@amd.com 14989920Syasuko.eckert@amd.com return regFile.readCCReg(phys_reg); 14999920Syasuko.eckert@amd.com} 15009920Syasuko.eckert@amd.com 15019920Syasuko.eckert@amd.comtemplate <class Impl> 15021060SN/Avoid 15036221Snate@binkert.orgFullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) 15041060SN/A{ 15057897Shestness@cs.utexas.edu intRegfileWrites++; 15069919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupInt(reg_idx); 15072292SN/A 15082292SN/A regFile.setIntReg(phys_reg, val); 15091060SN/A} 15101060SN/A 15111060SN/Atemplate <class Impl> 15121060SN/Avoid 15136314Sgblack@eecs.umich.eduFullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) 15141060SN/A{ 15157897Shestness@cs.utexas.edu fpRegfileWrites++; 15169919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 15172292SN/A 15182669Sktlim@umich.edu regFile.setFloatReg(phys_reg, val); 15191060SN/A} 15201060SN/A 15211060SN/Atemplate <class Impl> 15221060SN/Avoid 15236221Snate@binkert.orgFullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) 15241060SN/A{ 15257897Shestness@cs.utexas.edu fpRegfileWrites++; 15269919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupFloat(reg_idx); 15271060SN/A 15282669Sktlim@umich.edu regFile.setFloatRegBits(phys_reg, val); 15292292SN/A} 15302292SN/A 15312292SN/Atemplate <class Impl> 15329920Syasuko.eckert@amd.comvoid 15339920Syasuko.eckert@amd.comFullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid) 15349920Syasuko.eckert@amd.com{ 15359920Syasuko.eckert@amd.com ccRegfileWrites++; 15369920Syasuko.eckert@amd.com PhysRegIndex phys_reg = commitRenameMap[tid].lookupCC(reg_idx); 15379920Syasuko.eckert@amd.com 15389920Syasuko.eckert@amd.com regFile.setCCReg(phys_reg, val); 15399920Syasuko.eckert@amd.com} 15409920Syasuko.eckert@amd.com 15419920Syasuko.eckert@amd.comtemplate <class Impl> 15427720Sgblack@eecs.umich.eduTheISA::PCState 15437720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(ThreadID tid) 15442292SN/A{ 15457720Sgblack@eecs.umich.edu return commit.pcState(tid); 15461060SN/A} 15471060SN/A 15481060SN/Atemplate <class Impl> 15491060SN/Avoid 15507720Sgblack@eecs.umich.eduFullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid) 15511060SN/A{ 15527720Sgblack@eecs.umich.edu commit.pcState(val, tid); 15532292SN/A} 15541060SN/A 15552292SN/Atemplate <class Impl> 15567720Sgblack@eecs.umich.eduAddr 15577720Sgblack@eecs.umich.eduFullO3CPU<Impl>::instAddr(ThreadID tid) 15584636Sgblack@eecs.umich.edu{ 15597720Sgblack@eecs.umich.edu return commit.instAddr(tid); 15604636Sgblack@eecs.umich.edu} 15614636Sgblack@eecs.umich.edu 15624636Sgblack@eecs.umich.edutemplate <class Impl> 15637720Sgblack@eecs.umich.eduAddr 15647720Sgblack@eecs.umich.eduFullO3CPU<Impl>::nextInstAddr(ThreadID tid) 15654636Sgblack@eecs.umich.edu{ 15667720Sgblack@eecs.umich.edu return commit.nextInstAddr(tid); 15674636Sgblack@eecs.umich.edu} 15684636Sgblack@eecs.umich.edu 15694636Sgblack@eecs.umich.edutemplate <class Impl> 15707720Sgblack@eecs.umich.eduMicroPC 15717720Sgblack@eecs.umich.eduFullO3CPU<Impl>::microPC(ThreadID tid) 15722292SN/A{ 15737720Sgblack@eecs.umich.edu return commit.microPC(tid); 15744636Sgblack@eecs.umich.edu} 15754636Sgblack@eecs.umich.edu 15764636Sgblack@eecs.umich.edutemplate <class Impl> 15775595Sgblack@eecs.umich.eduvoid 15786221Snate@binkert.orgFullO3CPU<Impl>::squashFromTC(ThreadID tid) 15795595Sgblack@eecs.umich.edu{ 15809382SAli.Saidi@ARM.com this->thread[tid]->noSquashFromTC = true; 15815595Sgblack@eecs.umich.edu this->commit.generateTCEvent(tid); 15825595Sgblack@eecs.umich.edu} 15835595Sgblack@eecs.umich.edu 15845595Sgblack@eecs.umich.edutemplate <class Impl> 15852292SN/Atypename FullO3CPU<Impl>::ListIt 15862292SN/AFullO3CPU<Impl>::addInst(DynInstPtr &inst) 15872292SN/A{ 15882292SN/A instList.push_back(inst); 15891060SN/A 15902292SN/A return --(instList.end()); 15912292SN/A} 15921060SN/A 15932292SN/Atemplate <class Impl> 15942292SN/Avoid 15958834Satgutier@umich.eduFullO3CPU<Impl>::instDone(ThreadID tid, DynInstPtr &inst) 15962292SN/A{ 15972292SN/A // Keep an instruction count. 15988834Satgutier@umich.edu if (!inst->isMicroop() || inst->isLastMicroop()) { 15998834Satgutier@umich.edu thread[tid]->numInst++; 16008834Satgutier@umich.edu thread[tid]->numInsts++; 16018834Satgutier@umich.edu committedInsts[tid]++; 16028834Satgutier@umich.edu } 16038834Satgutier@umich.edu thread[tid]->numOp++; 16048834Satgutier@umich.edu thread[tid]->numOps++; 16058834Satgutier@umich.edu committedOps[tid]++; 16068834Satgutier@umich.edu 16077897Shestness@cs.utexas.edu system->totalNumInsts++; 16082292SN/A // Check for instruction-count-based events. 16092292SN/A comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst); 16107897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 16112292SN/A} 16122292SN/A 16132292SN/Atemplate <class Impl> 16142292SN/Avoid 16151755SN/AFullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst) 16161060SN/A{ 16177720Sgblack@eecs.umich.edu DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s " 16182292SN/A "[sn:%lli]\n", 16197720Sgblack@eecs.umich.edu inst->threadNumber, inst->pcState(), inst->seqNum); 16201060SN/A 16212292SN/A removeInstsThisCycle = true; 16221060SN/A 16231060SN/A // Remove the front instruction. 16242292SN/A removeList.push(inst->getInstListIt()); 16251060SN/A} 16261060SN/A 16271060SN/Atemplate <class Impl> 16281060SN/Avoid 16296221Snate@binkert.orgFullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid) 16301060SN/A{ 16312733Sktlim@umich.edu DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" 16322292SN/A " list.\n", tid); 16331060SN/A 16342292SN/A ListIt end_it; 16351060SN/A 16362292SN/A bool rob_empty = false; 16372292SN/A 16382292SN/A if (instList.empty()) { 16392292SN/A return; 164010164Ssleimanf@umich.edu } else if (rob.isEmpty(tid)) { 16412733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); 16422292SN/A end_it = instList.begin(); 16432292SN/A rob_empty = true; 16442292SN/A } else { 16452292SN/A end_it = (rob.readTailInst(tid))->getInstListIt(); 16462733Sktlim@umich.edu DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); 16472292SN/A } 16482292SN/A 16492292SN/A removeInstsThisCycle = true; 16502292SN/A 16512292SN/A ListIt inst_it = instList.end(); 16522292SN/A 16532292SN/A inst_it--; 16542292SN/A 16552292SN/A // Walk through the instruction list, removing any instructions 16562292SN/A // that were inserted after the given instruction iterator, end_it. 16572292SN/A while (inst_it != end_it) { 16582292SN/A assert(!instList.empty()); 16592292SN/A 16602292SN/A squashInstIt(inst_it, tid); 16612292SN/A 16622292SN/A inst_it--; 16632292SN/A } 16642292SN/A 16652292SN/A // If the ROB was empty, then we actually need to remove the first 16662292SN/A // instruction as well. 16672292SN/A if (rob_empty) { 16682292SN/A squashInstIt(inst_it, tid); 16692292SN/A } 16701060SN/A} 16711060SN/A 16721060SN/Atemplate <class Impl> 16731060SN/Avoid 16746221Snate@binkert.orgFullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) 16751062SN/A{ 16762292SN/A assert(!instList.empty()); 16772292SN/A 16782292SN/A removeInstsThisCycle = true; 16792292SN/A 16802292SN/A ListIt inst_iter = instList.end(); 16812292SN/A 16822292SN/A inst_iter--; 16832292SN/A 16842733Sktlim@umich.edu DPRINTF(O3CPU, "Deleting instructions from instruction " 16852292SN/A "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", 16862292SN/A tid, seq_num, (*inst_iter)->seqNum); 16871062SN/A 16882292SN/A while ((*inst_iter)->seqNum > seq_num) { 16891062SN/A 16902292SN/A bool break_loop = (inst_iter == instList.begin()); 16911062SN/A 16922292SN/A squashInstIt(inst_iter, tid); 16931062SN/A 16942292SN/A inst_iter--; 16951062SN/A 16962292SN/A if (break_loop) 16972292SN/A break; 16982292SN/A } 16992292SN/A} 17002292SN/A 17012292SN/Atemplate <class Impl> 17022292SN/Ainline void 17036221Snate@binkert.orgFullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid) 17042292SN/A{ 17052292SN/A if ((*instIt)->threadNumber == tid) { 17062733Sktlim@umich.edu DPRINTF(O3CPU, "Squashing instruction, " 17077720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 17082292SN/A (*instIt)->threadNumber, 17092292SN/A (*instIt)->seqNum, 17107720Sgblack@eecs.umich.edu (*instIt)->pcState()); 17111062SN/A 17121062SN/A // Mark it as squashed. 17132292SN/A (*instIt)->setSquashed(); 17142292SN/A 17152325SN/A // @todo: Formulate a consistent method for deleting 17162325SN/A // instructions from the instruction list 17172292SN/A // Remove the instruction from the list. 17182292SN/A removeList.push(instIt); 17192292SN/A } 17202292SN/A} 17212292SN/A 17222292SN/Atemplate <class Impl> 17232292SN/Avoid 17242292SN/AFullO3CPU<Impl>::cleanUpRemovedInsts() 17252292SN/A{ 17262292SN/A while (!removeList.empty()) { 17272733Sktlim@umich.edu DPRINTF(O3CPU, "Removing instruction, " 17287720Sgblack@eecs.umich.edu "[tid:%i] [sn:%lli] PC %s\n", 17292292SN/A (*removeList.front())->threadNumber, 17302292SN/A (*removeList.front())->seqNum, 17317720Sgblack@eecs.umich.edu (*removeList.front())->pcState()); 17322292SN/A 17332292SN/A instList.erase(removeList.front()); 17342292SN/A 17352292SN/A removeList.pop(); 17361062SN/A } 17371062SN/A 17382292SN/A removeInstsThisCycle = false; 17391062SN/A} 17402325SN/A/* 17411062SN/Atemplate <class Impl> 17421062SN/Avoid 17431755SN/AFullO3CPU<Impl>::removeAllInsts() 17441060SN/A{ 17451060SN/A instList.clear(); 17461060SN/A} 17472325SN/A*/ 17481060SN/Atemplate <class Impl> 17491060SN/Avoid 17501755SN/AFullO3CPU<Impl>::dumpInsts() 17511060SN/A{ 17521060SN/A int num = 0; 17531060SN/A 17542292SN/A ListIt inst_list_it = instList.begin(); 17552292SN/A 17562292SN/A cprintf("Dumping Instruction List\n"); 17572292SN/A 17582292SN/A while (inst_list_it != instList.end()) { 17592292SN/A cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n" 17602292SN/A "Squashed:%i\n\n", 17617720Sgblack@eecs.umich.edu num, (*inst_list_it)->instAddr(), (*inst_list_it)->threadNumber, 17622292SN/A (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(), 17632292SN/A (*inst_list_it)->isSquashed()); 17641060SN/A inst_list_it++; 17651060SN/A ++num; 17661060SN/A } 17671060SN/A} 17682325SN/A/* 17691060SN/Atemplate <class Impl> 17701060SN/Avoid 17711755SN/AFullO3CPU<Impl>::wakeDependents(DynInstPtr &inst) 17721060SN/A{ 17731060SN/A iew.wakeDependents(inst); 17741060SN/A} 17752325SN/A*/ 17762292SN/Atemplate <class Impl> 17772292SN/Avoid 17782292SN/AFullO3CPU<Impl>::wakeCPU() 17792292SN/A{ 17802325SN/A if (activityRec.active() || tickEvent.scheduled()) { 17812325SN/A DPRINTF(Activity, "CPU already running.\n"); 17822292SN/A return; 17832292SN/A } 17842292SN/A 17852325SN/A DPRINTF(Activity, "Waking up CPU\n"); 17862325SN/A 17879180Sandreas.hansson@arm.com Cycles cycles(curCycle() - lastRunningCycle); 17889180Sandreas.hansson@arm.com // @todo: This is an oddity that is only here to match the stats 17899179Sandreas.hansson@arm.com if (cycles != 0) 17909179Sandreas.hansson@arm.com --cycles; 17919179Sandreas.hansson@arm.com idleCycles += cycles; 17929179Sandreas.hansson@arm.com numCycles += cycles; 17932292SN/A 17949648Sdam.sunwoo@arm.com schedule(tickEvent, clockEdge()); 17952292SN/A} 17962292SN/A 17975807Snate@binkert.orgtemplate <class Impl> 17985807Snate@binkert.orgvoid 17995807Snate@binkert.orgFullO3CPU<Impl>::wakeup() 18005807Snate@binkert.org{ 18015807Snate@binkert.org if (this->thread[0]->status() != ThreadContext::Suspended) 18025807Snate@binkert.org return; 18035807Snate@binkert.org 18045807Snate@binkert.org this->wakeCPU(); 18055807Snate@binkert.org 18065807Snate@binkert.org DPRINTF(Quiesce, "Suspended Processor woken\n"); 18075807Snate@binkert.org this->threadContexts[0]->activate(); 18085807Snate@binkert.org} 18095807Snate@binkert.org 18102292SN/Atemplate <class Impl> 18116221Snate@binkert.orgThreadID 18122292SN/AFullO3CPU<Impl>::getFreeTid() 18132292SN/A{ 18146221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 18156221Snate@binkert.org if (!tids[tid]) { 18166221Snate@binkert.org tids[tid] = true; 18176221Snate@binkert.org return tid; 18182292SN/A } 18192292SN/A } 18202292SN/A 18216221Snate@binkert.org return InvalidThreadID; 18222292SN/A} 18232292SN/A 18242292SN/Atemplate <class Impl> 18252292SN/Avoid 18262292SN/AFullO3CPU<Impl>::doContextSwitch() 18272292SN/A{ 18282292SN/A if (contextSwitch) { 18292292SN/A 18302292SN/A //ADD CODE TO DEACTIVE THREAD HERE (???) 18312292SN/A 18326221Snate@binkert.org ThreadID size = cpuWaitList.size(); 18336221Snate@binkert.org for (ThreadID tid = 0; tid < size; tid++) { 18342292SN/A activateWhenReady(tid); 18352292SN/A } 18362292SN/A 18372292SN/A if (cpuWaitList.size() == 0) 18382292SN/A contextSwitch = true; 18392292SN/A } 18402292SN/A} 18412292SN/A 18422292SN/Atemplate <class Impl> 18432292SN/Avoid 18442292SN/AFullO3CPU<Impl>::updateThreadPriority() 18452292SN/A{ 18466221Snate@binkert.org if (activeThreads.size() > 1) { 18472292SN/A //DEFAULT TO ROUND ROBIN SCHEME 18482292SN/A //e.g. Move highest priority to end of thread list 18496221Snate@binkert.org list<ThreadID>::iterator list_begin = activeThreads.begin(); 18502292SN/A 18512292SN/A unsigned high_thread = *list_begin; 18522292SN/A 18532292SN/A activeThreads.erase(list_begin); 18542292SN/A 18552292SN/A activeThreads.push_back(high_thread); 18562292SN/A } 18572292SN/A} 18581060SN/A 18591755SN/A// Forward declaration of FullO3CPU. 18602818Sksewell@umich.edutemplate class FullO3CPU<O3CPUImpl>; 1861