commit_impl.hh revision 9944:4ff1c5c6dcbc 
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Korey Sewell
42 */
43#ifndef __CPU_O3_COMMIT_IMPL_HH__
44#define __CPU_O3_COMMIT_IMPL_HH__
45
46#include <algorithm>
47#include <set>
48#include <string>
49
50#include "arch/utility.hh"
51#include "base/loader/symtab.hh"
52#include "base/cp_annotate.hh"
53#include "config/the_isa.hh"
54#include "cpu/checker/cpu.hh"
55#include "cpu/o3/commit.hh"
56#include "cpu/o3/thread_state.hh"
57#include "cpu/base.hh"
58#include "cpu/exetrace.hh"
59#include "cpu/timebuf.hh"
60#include "debug/Activity.hh"
61#include "debug/Commit.hh"
62#include "debug/CommitRate.hh"
63#include "debug/Drain.hh"
64#include "debug/ExecFaulting.hh"
65#include "debug/O3PipeView.hh"
66#include "params/DerivO3CPU.hh"
67#include "sim/faults.hh"
68#include "sim/full_system.hh"
69
70using namespace std;
71
72template <class Impl>
73DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
74                                          ThreadID _tid)
75    : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid)
76{
77}
78
79template <class Impl>
80void
81DefaultCommit<Impl>::TrapEvent::process()
82{
83    // This will get reset by commit if it was switched out at the
84    // time of this event processing.
85    commit->trapSquash[tid] = true;
86}
87
88template <class Impl>
89const char *
90DefaultCommit<Impl>::TrapEvent::description() const
91{
92    return "Trap";
93}
94
95template <class Impl>
96DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
97    : cpu(_cpu),
98      squashCounter(0),
99      iewToCommitDelay(params->iewToCommitDelay),
100      commitToIEWDelay(params->commitToIEWDelay),
101      renameToROBDelay(params->renameToROBDelay),
102      fetchToCommitDelay(params->commitToFetchDelay),
103      renameWidth(params->renameWidth),
104      commitWidth(params->commitWidth),
105      numThreads(params->numThreads),
106      drainPending(false),
107      trapLatency(params->trapLatency),
108      canHandleInterrupts(true),
109      avoidQuiesceLiveLock(false)
110{
111    _status = Active;
112    _nextStatus = Inactive;
113    std::string policy = params->smtCommitPolicy;
114
115    //Convert string to lowercase
116    std::transform(policy.begin(), policy.end(), policy.begin(),
117                   (int(*)(int)) tolower);
118
119    //Assign commit policy
120    if (policy == "aggressive"){
121        commitPolicy = Aggressive;
122
123        DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
124    } else if (policy == "roundrobin"){
125        commitPolicy = RoundRobin;
126
127        //Set-Up Priority List
128        for (ThreadID tid = 0; tid < numThreads; tid++) {
129            priority_list.push_back(tid);
130        }
131
132        DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
133    } else if (policy == "oldestready"){
134        commitPolicy = OldestReady;
135
136        DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
137    } else {
138        assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
139               "RoundRobin,OldestReady}");
140    }
141
142    for (ThreadID tid = 0; tid < numThreads; tid++) {
143        commitStatus[tid] = Idle;
144        changedROBNumEntries[tid] = false;
145        checkEmptyROB[tid] = false;
146        trapInFlight[tid] = false;
147        committedStores[tid] = false;
148        trapSquash[tid] = false;
149        tcSquash[tid] = false;
150        pc[tid].set(0);
151        lastCommitedSeqNum[tid] = 0;
152        squashAfterInst[tid] = NULL;
153    }
154    interrupt = NoFault;
155}
156
157template <class Impl>
158std::string
159DefaultCommit<Impl>::name() const
160{
161    return cpu->name() + ".commit";
162}
163
164template <class Impl>
165void
166DefaultCommit<Impl>::regStats()
167{
168    using namespace Stats;
169    commitSquashedInsts
170        .name(name() + ".commitSquashedInsts")
171        .desc("The number of squashed insts skipped by commit")
172        .prereq(commitSquashedInsts);
173    commitSquashEvents
174        .name(name() + ".commitSquashEvents")
175        .desc("The number of times commit is told to squash")
176        .prereq(commitSquashEvents);
177    commitNonSpecStalls
178        .name(name() + ".commitNonSpecStalls")
179        .desc("The number of times commit has been forced to stall to "
180              "communicate backwards")
181        .prereq(commitNonSpecStalls);
182    branchMispredicts
183        .name(name() + ".branchMispredicts")
184        .desc("The number of times a branch was mispredicted")
185        .prereq(branchMispredicts);
186    numCommittedDist
187        .init(0,commitWidth,1)
188        .name(name() + ".committed_per_cycle")
189        .desc("Number of insts commited each cycle")
190        .flags(Stats::pdf)
191        ;
192
193    instsCommitted
194        .init(cpu->numThreads)
195        .name(name() + ".committedInsts")
196        .desc("Number of instructions committed")
197        .flags(total)
198        ;
199
200    opsCommitted
201        .init(cpu->numThreads)
202        .name(name() + ".committedOps")
203        .desc("Number of ops (including micro ops) committed")
204        .flags(total)
205        ;
206
207    statComSwp
208        .init(cpu->numThreads)
209        .name(name() + ".swp_count")
210        .desc("Number of s/w prefetches committed")
211        .flags(total)
212        ;
213
214    statComRefs
215        .init(cpu->numThreads)
216        .name(name() +  ".refs")
217        .desc("Number of memory references committed")
218        .flags(total)
219        ;
220
221    statComLoads
222        .init(cpu->numThreads)
223        .name(name() +  ".loads")
224        .desc("Number of loads committed")
225        .flags(total)
226        ;
227
228    statComMembars
229        .init(cpu->numThreads)
230        .name(name() +  ".membars")
231        .desc("Number of memory barriers committed")
232        .flags(total)
233        ;
234
235    statComBranches
236        .init(cpu->numThreads)
237        .name(name() + ".branches")
238        .desc("Number of branches committed")
239        .flags(total)
240        ;
241
242    statComFloating
243        .init(cpu->numThreads)
244        .name(name() + ".fp_insts")
245        .desc("Number of committed floating point instructions.")
246        .flags(total)
247        ;
248
249    statComInteger
250        .init(cpu->numThreads)
251        .name(name()+".int_insts")
252        .desc("Number of committed integer instructions.")
253        .flags(total)
254        ;
255
256    statComFunctionCalls
257        .init(cpu->numThreads)
258        .name(name()+".function_calls")
259        .desc("Number of function calls committed.")
260        .flags(total)
261        ;
262
263    commitEligible
264        .init(cpu->numThreads)
265        .name(name() + ".bw_limited")
266        .desc("number of insts not committed due to BW limits")
267        .flags(total)
268        ;
269
270    commitEligibleSamples
271        .name(name() + ".bw_lim_events")
272        .desc("number cycles where commit BW limit reached")
273        ;
274}
275
276template <class Impl>
277void
278DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
279{
280    thread = threads;
281}
282
283template <class Impl>
284void
285DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
286{
287    timeBuffer = tb_ptr;
288
289    // Setup wire to send information back to IEW.
290    toIEW = timeBuffer->getWire(0);
291
292    // Setup wire to read data from IEW (for the ROB).
293    robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
294}
295
296template <class Impl>
297void
298DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
299{
300    fetchQueue = fq_ptr;
301
302    // Setup wire to get instructions from rename (for the ROB).
303    fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
304}
305
306template <class Impl>
307void
308DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
309{
310    renameQueue = rq_ptr;
311
312    // Setup wire to get instructions from rename (for the ROB).
313    fromRename = renameQueue->getWire(-renameToROBDelay);
314}
315
316template <class Impl>
317void
318DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
319{
320    iewQueue = iq_ptr;
321
322    // Setup wire to get instructions from IEW.
323    fromIEW = iewQueue->getWire(-iewToCommitDelay);
324}
325
326template <class Impl>
327void
328DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
329{
330    iewStage = iew_stage;
331}
332
333template<class Impl>
334void
335DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
336{
337    activeThreads = at_ptr;
338}
339
340template <class Impl>
341void
342DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
343{
344    for (ThreadID tid = 0; tid < numThreads; tid++)
345        renameMap[tid] = &rm_ptr[tid];
346}
347
348template <class Impl>
349void
350DefaultCommit<Impl>::setROB(ROB *rob_ptr)
351{
352    rob = rob_ptr;
353}
354
355template <class Impl>
356void
357DefaultCommit<Impl>::startupStage()
358{
359    rob->setActiveThreads(activeThreads);
360    rob->resetEntries();
361
362    // Broadcast the number of free entries.
363    for (ThreadID tid = 0; tid < numThreads; tid++) {
364        toIEW->commitInfo[tid].usedROB = true;
365        toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
366        toIEW->commitInfo[tid].emptyROB = true;
367    }
368
369    // Commit must broadcast the number of free entries it has at the
370    // start of the simulation, so it starts as active.
371    cpu->activateStage(O3CPU::CommitIdx);
372
373    cpu->activityThisCycle();
374}
375
376template <class Impl>
377void
378DefaultCommit<Impl>::drain()
379{
380    drainPending = true;
381}
382
383template <class Impl>
384void
385DefaultCommit<Impl>::drainResume()
386{
387    drainPending = false;
388}
389
390template <class Impl>
391void
392DefaultCommit<Impl>::drainSanityCheck() const
393{
394    assert(isDrained());
395    rob->drainSanityCheck();
396}
397
398template <class Impl>
399bool
400DefaultCommit<Impl>::isDrained() const
401{
402    /* Make sure no one is executing microcode. There are two reasons
403     * for this:
404     * - Hardware virtualized CPUs can't switch into the middle of a
405     *   microcode sequence.
406     * - The current fetch implementation will most likely get very
407     *   confused if it tries to start fetching an instruction that
408     *   is executing in the middle of a ucode sequence that changes
409     *   address mappings. This can happen on for example x86.
410     */
411    for (ThreadID tid = 0; tid < numThreads; tid++) {
412        if (pc[tid].microPC() != 0)
413            return false;
414    }
415
416    /* Make sure that all instructions have finished committing before
417     * declaring the system as drained. We want the pipeline to be
418     * completely empty when we declare the CPU to be drained. This
419     * makes debugging easier since CPU handover and restoring from a
420     * checkpoint with a different CPU should have the same timing.
421     */
422    return rob->isEmpty() &&
423        interrupt == NoFault;
424}
425
426template <class Impl>
427void
428DefaultCommit<Impl>::takeOverFrom()
429{
430    _status = Active;
431    _nextStatus = Inactive;
432    for (ThreadID tid = 0; tid < numThreads; tid++) {
433        commitStatus[tid] = Idle;
434        changedROBNumEntries[tid] = false;
435        trapSquash[tid] = false;
436        tcSquash[tid] = false;
437        squashAfterInst[tid] = NULL;
438    }
439    squashCounter = 0;
440    rob->takeOverFrom();
441}
442
443template <class Impl>
444void
445DefaultCommit<Impl>::updateStatus()
446{
447    // reset ROB changed variable
448    list<ThreadID>::iterator threads = activeThreads->begin();
449    list<ThreadID>::iterator end = activeThreads->end();
450
451    while (threads != end) {
452        ThreadID tid = *threads++;
453
454        changedROBNumEntries[tid] = false;
455
456        // Also check if any of the threads has a trap pending
457        if (commitStatus[tid] == TrapPending ||
458            commitStatus[tid] == FetchTrapPending) {
459            _nextStatus = Active;
460        }
461    }
462
463    if (_nextStatus == Inactive && _status == Active) {
464        DPRINTF(Activity, "Deactivating stage.\n");
465        cpu->deactivateStage(O3CPU::CommitIdx);
466    } else if (_nextStatus == Active && _status == Inactive) {
467        DPRINTF(Activity, "Activating stage.\n");
468        cpu->activateStage(O3CPU::CommitIdx);
469    }
470
471    _status = _nextStatus;
472}
473
474template <class Impl>
475void
476DefaultCommit<Impl>::setNextStatus()
477{
478    int squashes = 0;
479
480    list<ThreadID>::iterator threads = activeThreads->begin();
481    list<ThreadID>::iterator end = activeThreads->end();
482
483    while (threads != end) {
484        ThreadID tid = *threads++;
485
486        if (commitStatus[tid] == ROBSquashing) {
487            squashes++;
488        }
489    }
490
491    squashCounter = squashes;
492
493    // If commit is currently squashing, then it will have activity for the
494    // next cycle. Set its next status as active.
495    if (squashCounter) {
496        _nextStatus = Active;
497    }
498}
499
500template <class Impl>
501bool
502DefaultCommit<Impl>::changedROBEntries()
503{
504    list<ThreadID>::iterator threads = activeThreads->begin();
505    list<ThreadID>::iterator end = activeThreads->end();
506
507    while (threads != end) {
508        ThreadID tid = *threads++;
509
510        if (changedROBNumEntries[tid]) {
511            return true;
512        }
513    }
514
515    return false;
516}
517
518template <class Impl>
519size_t
520DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
521{
522    return rob->numFreeEntries(tid);
523}
524
525template <class Impl>
526void
527DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
528{
529    DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
530
531    TrapEvent *trap = new TrapEvent(this, tid);
532
533    cpu->schedule(trap, cpu->clockEdge(trapLatency));
534    trapInFlight[tid] = true;
535    thread[tid]->trapPending = true;
536}
537
538template <class Impl>
539void
540DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
541{
542    assert(!trapInFlight[tid]);
543    DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
544
545    tcSquash[tid] = true;
546}
547
548template <class Impl>
549void
550DefaultCommit<Impl>::squashAll(ThreadID tid)
551{
552    // If we want to include the squashing instruction in the squash,
553    // then use one older sequence number.
554    // Hopefully this doesn't mess things up.  Basically I want to squash
555    // all instructions of this thread.
556    InstSeqNum squashed_inst = rob->isEmpty() ?
557        lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
558
559    // All younger instructions will be squashed. Set the sequence
560    // number as the youngest instruction in the ROB (0 in this case.
561    // Hopefully nothing breaks.)
562    youngestSeqNum[tid] = lastCommitedSeqNum[tid];
563
564    rob->squash(squashed_inst, tid);
565    changedROBNumEntries[tid] = true;
566
567    // Send back the sequence number of the squashed instruction.
568    toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
569
570    // Send back the squash signal to tell stages that they should
571    // squash.
572    toIEW->commitInfo[tid].squash = true;
573
574    // Send back the rob squashing signal so other stages know that
575    // the ROB is in the process of squashing.
576    toIEW->commitInfo[tid].robSquashing = true;
577
578    toIEW->commitInfo[tid].mispredictInst = NULL;
579    toIEW->commitInfo[tid].squashInst = NULL;
580
581    toIEW->commitInfo[tid].pc = pc[tid];
582}
583
584template <class Impl>
585void
586DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
587{
588    squashAll(tid);
589
590    DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
591
592    thread[tid]->trapPending = false;
593    thread[tid]->noSquashFromTC = false;
594    trapInFlight[tid] = false;
595
596    trapSquash[tid] = false;
597
598    commitStatus[tid] = ROBSquashing;
599    cpu->activityThisCycle();
600}
601
602template <class Impl>
603void
604DefaultCommit<Impl>::squashFromTC(ThreadID tid)
605{
606    squashAll(tid);
607
608    DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
609
610    thread[tid]->noSquashFromTC = false;
611    assert(!thread[tid]->trapPending);
612
613    commitStatus[tid] = ROBSquashing;
614    cpu->activityThisCycle();
615
616    tcSquash[tid] = false;
617}
618
619template <class Impl>
620void
621DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid)
622{
623    DPRINTF(Commit, "Squashing after squash after request, "
624            "restarting at PC %s\n", pc[tid]);
625
626    squashAll(tid);
627    // Make sure to inform the fetch stage of which instruction caused
628    // the squash. It'll try to re-fetch an instruction executing in
629    // microcode unless this is set.
630    toIEW->commitInfo[tid].squashInst = squashAfterInst[tid];
631    squashAfterInst[tid] = NULL;
632
633    commitStatus[tid] = ROBSquashing;
634    cpu->activityThisCycle();
635}
636
637template <class Impl>
638void
639DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst)
640{
641    DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
642            tid, head_inst->seqNum);
643
644    assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst);
645    commitStatus[tid] = SquashAfterPending;
646    squashAfterInst[tid] = head_inst;
647}
648
649template <class Impl>
650void
651DefaultCommit<Impl>::tick()
652{
653    wroteToTimeBuffer = false;
654    _nextStatus = Inactive;
655
656    if (activeThreads->empty())
657        return;
658
659    list<ThreadID>::iterator threads = activeThreads->begin();
660    list<ThreadID>::iterator end = activeThreads->end();
661
662    // Check if any of the threads are done squashing.  Change the
663    // status if they are done.
664    while (threads != end) {
665        ThreadID tid = *threads++;
666
667        // Clear the bit saying if the thread has committed stores
668        // this cycle.
669        committedStores[tid] = false;
670
671        if (commitStatus[tid] == ROBSquashing) {
672
673            if (rob->isDoneSquashing(tid)) {
674                commitStatus[tid] = Running;
675            } else {
676                DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
677                        " insts this cycle.\n", tid);
678                rob->doSquash(tid);
679                toIEW->commitInfo[tid].robSquashing = true;
680                wroteToTimeBuffer = true;
681            }
682        }
683    }
684
685    commit();
686
687    markCompletedInsts();
688
689    threads = activeThreads->begin();
690
691    while (threads != end) {
692        ThreadID tid = *threads++;
693
694        if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
695            // The ROB has more instructions it can commit. Its next status
696            // will be active.
697            _nextStatus = Active;
698
699            DynInstPtr inst = rob->readHeadInst(tid);
700
701            DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
702                    " ROB and ready to commit\n",
703                    tid, inst->seqNum, inst->pcState());
704
705        } else if (!rob->isEmpty(tid)) {
706            DynInstPtr inst = rob->readHeadInst(tid);
707
708            DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
709                    "%s is head of ROB and not ready\n",
710                    tid, inst->seqNum, inst->pcState());
711        }
712
713        DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
714                tid, rob->countInsts(tid), rob->numFreeEntries(tid));
715    }
716
717
718    if (wroteToTimeBuffer) {
719        DPRINTF(Activity, "Activity This Cycle.\n");
720        cpu->activityThisCycle();
721    }
722
723    updateStatus();
724}
725
726template <class Impl>
727void
728DefaultCommit<Impl>::handleInterrupt()
729{
730    // Verify that we still have an interrupt to handle
731    if (!cpu->checkInterrupts(cpu->tcBase(0))) {
732        DPRINTF(Commit, "Pending interrupt is cleared by master before "
733                "it got handled. Restart fetching from the orig path.\n");
734        toIEW->commitInfo[0].clearInterrupt = true;
735        interrupt = NoFault;
736        avoidQuiesceLiveLock = true;
737        return;
738    }
739
740    // Wait until all in flight instructions are finished before enterring
741    // the interrupt.
742    if (canHandleInterrupts && cpu->instList.empty()) {
743        // Squash or record that I need to squash this cycle if
744        // an interrupt needed to be handled.
745        DPRINTF(Commit, "Interrupt detected.\n");
746
747        // Clear the interrupt now that it's going to be handled
748        toIEW->commitInfo[0].clearInterrupt = true;
749
750        assert(!thread[0]->noSquashFromTC);
751        thread[0]->noSquashFromTC = true;
752
753        if (cpu->checker) {
754            cpu->checker->handlePendingInt();
755        }
756
757        // CPU will handle interrupt. Note that we ignore the local copy of
758        // interrupt. This is because the local copy may no longer be the
759        // interrupt that the interrupt controller thinks is being handled.
760        cpu->processInterrupts(cpu->getInterrupts());
761
762        thread[0]->noSquashFromTC = false;
763
764        commitStatus[0] = TrapPending;
765
766        // Generate trap squash event.
767        generateTrapEvent(0);
768
769        interrupt = NoFault;
770        avoidQuiesceLiveLock = false;
771    } else {
772        DPRINTF(Commit, "Interrupt pending: instruction is %sin "
773                "flight, ROB is %sempty\n",
774                canHandleInterrupts ? "not " : "",
775                cpu->instList.empty() ? "" : "not " );
776    }
777}
778
779template <class Impl>
780void
781DefaultCommit<Impl>::propagateInterrupt()
782{
783    if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
784            tcSquash[0])
785        return;
786
787    // Process interrupts if interrupts are enabled, not in PAL
788    // mode, and no other traps or external squashes are currently
789    // pending.
790    // @todo: Allow other threads to handle interrupts.
791
792    // Get any interrupt that happened
793    interrupt = cpu->getInterrupts();
794
795    // Tell fetch that there is an interrupt pending.  This
796    // will make fetch wait until it sees a non PAL-mode PC,
797    // at which point it stops fetching instructions.
798    if (interrupt != NoFault)
799        toIEW->commitInfo[0].interruptPending = true;
800}
801
802template <class Impl>
803void
804DefaultCommit<Impl>::commit()
805{
806    if (FullSystem) {
807        // Check if we have a interrupt and get read to handle it
808        if (cpu->checkInterrupts(cpu->tcBase(0)))
809            propagateInterrupt();
810    }
811
812    ////////////////////////////////////
813    // Check for any possible squashes, handle them first
814    ////////////////////////////////////
815    list<ThreadID>::iterator threads = activeThreads->begin();
816    list<ThreadID>::iterator end = activeThreads->end();
817
818    while (threads != end) {
819        ThreadID tid = *threads++;
820
821        // Not sure which one takes priority.  I think if we have
822        // both, that's a bad sign.
823        if (trapSquash[tid] == true) {
824            assert(!tcSquash[tid]);
825            squashFromTrap(tid);
826        } else if (tcSquash[tid] == true) {
827            assert(commitStatus[tid] != TrapPending);
828            squashFromTC(tid);
829        } else if (commitStatus[tid] == SquashAfterPending) {
830            // A squash from the previous cycle of the commit stage (i.e.,
831            // commitInsts() called squashAfter) is pending. Squash the
832            // thread now.
833            squashFromSquashAfter(tid);
834        }
835
836        // Squashed sequence number must be older than youngest valid
837        // instruction in the ROB. This prevents squashes from younger
838        // instructions overriding squashes from older instructions.
839        if (fromIEW->squash[tid] &&
840            commitStatus[tid] != TrapPending &&
841            fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
842
843            if (fromIEW->mispredictInst[tid]) {
844                DPRINTF(Commit,
845                    "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
846                    tid,
847                    fromIEW->mispredictInst[tid]->instAddr(),
848                    fromIEW->squashedSeqNum[tid]);
849            } else {
850                DPRINTF(Commit,
851                    "[tid:%i]: Squashing due to order violation [sn:%i]\n",
852                    tid, fromIEW->squashedSeqNum[tid]);
853            }
854
855            DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
856                    tid,
857                    fromIEW->pc[tid].nextInstAddr());
858
859            commitStatus[tid] = ROBSquashing;
860
861            // If we want to include the squashing instruction in the squash,
862            // then use one older sequence number.
863            InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
864
865            if (fromIEW->includeSquashInst[tid] == true) {
866                squashed_inst--;
867            }
868
869            // All younger instructions will be squashed. Set the sequence
870            // number as the youngest instruction in the ROB.
871            youngestSeqNum[tid] = squashed_inst;
872
873            rob->squash(squashed_inst, tid);
874            changedROBNumEntries[tid] = true;
875
876            toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
877
878            toIEW->commitInfo[tid].squash = true;
879
880            // Send back the rob squashing signal so other stages know that
881            // the ROB is in the process of squashing.
882            toIEW->commitInfo[tid].robSquashing = true;
883
884            toIEW->commitInfo[tid].mispredictInst =
885                fromIEW->mispredictInst[tid];
886            toIEW->commitInfo[tid].branchTaken =
887                fromIEW->branchTaken[tid];
888            toIEW->commitInfo[tid].squashInst =
889                                    rob->findInst(tid, squashed_inst);
890            if (toIEW->commitInfo[tid].mispredictInst) {
891                if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
892                     toIEW->commitInfo[tid].branchTaken = true;
893                }
894            }
895
896            toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
897
898            if (toIEW->commitInfo[tid].mispredictInst) {
899                ++branchMispredicts;
900            }
901        }
902
903    }
904
905    setNextStatus();
906
907    if (squashCounter != numThreads) {
908        // If we're not currently squashing, then get instructions.
909        getInsts();
910
911        // Try to commit any instructions.
912        commitInsts();
913    }
914
915    //Check for any activity
916    threads = activeThreads->begin();
917
918    while (threads != end) {
919        ThreadID tid = *threads++;
920
921        if (changedROBNumEntries[tid]) {
922            toIEW->commitInfo[tid].usedROB = true;
923            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
924
925            wroteToTimeBuffer = true;
926            changedROBNumEntries[tid] = false;
927            if (rob->isEmpty(tid))
928                checkEmptyROB[tid] = true;
929        }
930
931        // ROB is only considered "empty" for previous stages if: a)
932        // ROB is empty, b) there are no outstanding stores, c) IEW
933        // stage has received any information regarding stores that
934        // committed.
935        // c) is checked by making sure to not consider the ROB empty
936        // on the same cycle as when stores have been committed.
937        // @todo: Make this handle multi-cycle communication between
938        // commit and IEW.
939        if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
940            !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
941            checkEmptyROB[tid] = false;
942            toIEW->commitInfo[tid].usedROB = true;
943            toIEW->commitInfo[tid].emptyROB = true;
944            toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
945            wroteToTimeBuffer = true;
946        }
947
948    }
949}
950
951template <class Impl>
952void
953DefaultCommit<Impl>::commitInsts()
954{
955    ////////////////////////////////////
956    // Handle commit
957    // Note that commit will be handled prior to putting new
958    // instructions in the ROB so that the ROB only tries to commit
959    // instructions it has in this current cycle, and not instructions
960    // it is writing in during this cycle.  Can't commit and squash
961    // things at the same time...
962    ////////////////////////////////////
963
964    DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
965
966    unsigned num_committed = 0;
967
968    DynInstPtr head_inst;
969
970    // Commit as many instructions as possible until the commit bandwidth
971    // limit is reached, or it becomes impossible to commit any more.
972    while (num_committed < commitWidth) {
973        // Check for any interrupt that we've already squashed for
974        // and start processing it.
975        if (interrupt != NoFault)
976            handleInterrupt();
977
978        int commit_thread = getCommittingThread();
979
980        if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
981            break;
982
983        head_inst = rob->readHeadInst(commit_thread);
984
985        ThreadID tid = head_inst->threadNumber;
986
987        assert(tid == commit_thread);
988
989        DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
990                head_inst->seqNum, tid);
991
992        // If the head instruction is squashed, it is ready to retire
993        // (be removed from the ROB) at any time.
994        if (head_inst->isSquashed()) {
995
996            DPRINTF(Commit, "Retiring squashed instruction from "
997                    "ROB.\n");
998
999            rob->retireHead(commit_thread);
1000
1001            ++commitSquashedInsts;
1002
1003            // Record that the number of ROB entries has changed.
1004            changedROBNumEntries[tid] = true;
1005        } else {
1006            pc[tid] = head_inst->pcState();
1007
1008            // Increment the total number of non-speculative instructions
1009            // executed.
1010            // Hack for now: it really shouldn't happen until after the
1011            // commit is deemed to be successful, but this count is needed
1012            // for syscalls.
1013            thread[tid]->funcExeInst++;
1014
1015            // Try to commit the head instruction.
1016            bool commit_success = commitHead(head_inst, num_committed);
1017
1018            if (commit_success) {
1019                ++num_committed;
1020
1021                changedROBNumEntries[tid] = true;
1022
1023                // Set the doneSeqNum to the youngest committed instruction.
1024                toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1025
1026                if (tid == 0) {
1027                    canHandleInterrupts =  (!head_inst->isDelayedCommit()) &&
1028                                           ((THE_ISA != ALPHA_ISA) ||
1029                                             (!(pc[0].instAddr() & 0x3)));
1030                }
1031
1032                // Updates misc. registers.
1033                head_inst->updateMiscRegs();
1034
1035                cpu->traceFunctions(pc[tid].instAddr());
1036
1037                TheISA::advancePC(pc[tid], head_inst->staticInst);
1038
1039                // Keep track of the last sequence number commited
1040                lastCommitedSeqNum[tid] = head_inst->seqNum;
1041
1042                // If this is an instruction that doesn't play nicely with
1043                // others squash everything and restart fetch
1044                if (head_inst->isSquashAfter())
1045                    squashAfter(tid, head_inst);
1046
1047                if (drainPending) {
1048                    DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]);
1049                    if (pc[tid].microPC() == 0 && interrupt == NoFault) {
1050                        squashAfter(tid, head_inst);
1051                        cpu->commitDrained(tid);
1052                    }
1053                }
1054
1055                int count = 0;
1056                Addr oldpc;
1057                // Debug statement.  Checks to make sure we're not
1058                // currently updating state while handling PC events.
1059                assert(!thread[tid]->noSquashFromTC && !thread[tid]->trapPending);
1060                do {
1061                    oldpc = pc[tid].instAddr();
1062                    cpu->system->pcEventQueue.service(thread[tid]->getTC());
1063                    count++;
1064                } while (oldpc != pc[tid].instAddr());
1065                if (count > 1) {
1066                    DPRINTF(Commit,
1067                            "PC skip function event, stopping commit\n");
1068                    break;
1069                }
1070
1071                // Check if an instruction just enabled interrupts and we've
1072                // previously had an interrupt pending that was not handled
1073                // because interrupts were subsequently disabled before the
1074                // pipeline reached a place to handle the interrupt. In that
1075                // case squash now to make sure the interrupt is handled.
1076                //
1077                // If we don't do this, we might end up in a live lock situation
1078                if (!interrupt  && avoidQuiesceLiveLock &&
1079                   (!head_inst->isMicroop() || head_inst->isLastMicroop()) &&
1080                   cpu->checkInterrupts(cpu->tcBase(0)))
1081                    squashAfter(tid, head_inst);
1082            } else {
1083                DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1084                        "[tid:%i] [sn:%i].\n",
1085                        head_inst->pcState(), tid ,head_inst->seqNum);
1086                break;
1087            }
1088        }
1089    }
1090
1091    DPRINTF(CommitRate, "%i\n", num_committed);
1092    numCommittedDist.sample(num_committed);
1093
1094    if (num_committed == commitWidth) {
1095        commitEligibleSamples++;
1096    }
1097}
1098
1099template <class Impl>
1100bool
1101DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1102{
1103    assert(head_inst);
1104
1105    ThreadID tid = head_inst->threadNumber;
1106
1107    // If the instruction is not executed yet, then it will need extra
1108    // handling.  Signal backwards that it should be executed.
1109    if (!head_inst->isExecuted()) {
1110        // Keep this number correct.  We have not yet actually executed
1111        // and committed this instruction.
1112        thread[tid]->funcExeInst--;
1113
1114        if (head_inst->isNonSpeculative() ||
1115            head_inst->isStoreConditional() ||
1116            head_inst->isMemBarrier() ||
1117            head_inst->isWriteBarrier()) {
1118
1119            DPRINTF(Commit, "Encountered a barrier or non-speculative "
1120                    "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1121                    head_inst->seqNum, head_inst->pcState());
1122
1123            if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1124                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1125                return false;
1126            }
1127
1128            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1129
1130            // Change the instruction so it won't try to commit again until
1131            // it is executed.
1132            head_inst->clearCanCommit();
1133
1134            ++commitNonSpecStalls;
1135
1136            return false;
1137        } else if (head_inst->isLoad()) {
1138            if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1139                DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1140                return false;
1141            }
1142
1143            assert(head_inst->uncacheable());
1144            DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1145                    head_inst->seqNum, head_inst->pcState());
1146
1147            // Send back the non-speculative instruction's sequence
1148            // number.  Tell the lsq to re-execute the load.
1149            toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1150            toIEW->commitInfo[tid].uncached = true;
1151            toIEW->commitInfo[tid].uncachedLoad = head_inst;
1152
1153            head_inst->clearCanCommit();
1154
1155            return false;
1156        } else {
1157            panic("Trying to commit un-executed instruction "
1158                  "of unknown type!\n");
1159        }
1160    }
1161
1162    if (head_inst->isThreadSync()) {
1163        // Not handled for now.
1164        panic("Thread sync instructions are not handled yet.\n");
1165    }
1166
1167    // Check if the instruction caused a fault.  If so, trap.
1168    Fault inst_fault = head_inst->getFault();
1169
1170    // Stores mark themselves as completed.
1171    if (!head_inst->isStore() && inst_fault == NoFault) {
1172        head_inst->setCompleted();
1173    }
1174
1175    // Use checker prior to updating anything due to traps or PC
1176    // based events.
1177    if (cpu->checker) {
1178        cpu->checker->verify(head_inst);
1179    }
1180
1181    if (inst_fault != NoFault) {
1182        DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1183                head_inst->seqNum, head_inst->pcState());
1184
1185        if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1186            DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1187            return false;
1188        }
1189
1190        head_inst->setCompleted();
1191
1192        if (cpu->checker) {
1193            // Need to check the instruction before its fault is processed
1194            cpu->checker->verify(head_inst);
1195        }
1196
1197        assert(!thread[tid]->noSquashFromTC);
1198
1199        // Mark that we're in state update mode so that the trap's
1200        // execution doesn't generate extra squashes.
1201        thread[tid]->noSquashFromTC = true;
1202
1203        // Execute the trap.  Although it's slightly unrealistic in
1204        // terms of timing (as it doesn't wait for the full timing of
1205        // the trap event to complete before updating state), it's
1206        // needed to update the state as soon as possible.  This
1207        // prevents external agents from changing any specific state
1208        // that the trap need.
1209        cpu->trap(inst_fault, tid, head_inst->staticInst);
1210
1211        // Exit state update mode to avoid accidental updating.
1212        thread[tid]->noSquashFromTC = false;
1213
1214        commitStatus[tid] = TrapPending;
1215
1216        DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1217            head_inst->seqNum);
1218        if (head_inst->traceData) {
1219            if (DTRACE(ExecFaulting)) {
1220                head_inst->traceData->setFetchSeq(head_inst->seqNum);
1221                head_inst->traceData->setCPSeq(thread[tid]->numOp);
1222                head_inst->traceData->dump();
1223            }
1224            delete head_inst->traceData;
1225            head_inst->traceData = NULL;
1226        }
1227
1228        // Generate trap squash event.
1229        generateTrapEvent(tid);
1230        return false;
1231    }
1232
1233    updateComInstStats(head_inst);
1234
1235    if (FullSystem) {
1236        if (thread[tid]->profile) {
1237            thread[tid]->profilePC = head_inst->instAddr();
1238            ProfileNode *node = thread[tid]->profile->consume(
1239                    thread[tid]->getTC(), head_inst->staticInst);
1240
1241            if (node)
1242                thread[tid]->profileNode = node;
1243        }
1244        if (CPA::available()) {
1245            if (head_inst->isControl()) {
1246                ThreadContext *tc = thread[tid]->getTC();
1247                CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1248            }
1249        }
1250    }
1251    DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1252            head_inst->seqNum, head_inst->pcState());
1253    if (head_inst->traceData) {
1254        head_inst->traceData->setFetchSeq(head_inst->seqNum);
1255        head_inst->traceData->setCPSeq(thread[tid]->numOp);
1256        head_inst->traceData->dump();
1257        delete head_inst->traceData;
1258        head_inst->traceData = NULL;
1259    }
1260    if (head_inst->isReturn()) {
1261        DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n",
1262                        head_inst->seqNum, head_inst->pcState());
1263    }
1264
1265    // Update the commit rename map
1266    for (int i = 0; i < head_inst->numDestRegs(); i++) {
1267        renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1268                                 head_inst->renamedDestRegIdx(i));
1269    }
1270
1271    // Finally clear the head ROB entry.
1272    rob->retireHead(tid);
1273
1274#if TRACING_ON
1275    if (DTRACE(O3PipeView)) {
1276        head_inst->commitTick = curTick() - head_inst->fetchTick;
1277    }
1278#endif
1279
1280    // If this was a store, record it for this cycle.
1281    if (head_inst->isStore())
1282        committedStores[tid] = true;
1283
1284    // Return true to indicate that we have committed an instruction.
1285    return true;
1286}
1287
1288template <class Impl>
1289void
1290DefaultCommit<Impl>::getInsts()
1291{
1292    DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1293
1294    // Read any renamed instructions and place them into the ROB.
1295    int insts_to_process = std::min((int)renameWidth, fromRename->size);
1296
1297    for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1298        DynInstPtr inst;
1299
1300        inst = fromRename->insts[inst_num];
1301        ThreadID tid = inst->threadNumber;
1302
1303        if (!inst->isSquashed() &&
1304            commitStatus[tid] != ROBSquashing &&
1305            commitStatus[tid] != TrapPending) {
1306            changedROBNumEntries[tid] = true;
1307
1308            DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1309                    inst->pcState(), inst->seqNum, tid);
1310
1311            rob->insertInst(inst);
1312
1313            assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1314
1315            youngestSeqNum[tid] = inst->seqNum;
1316        } else {
1317            DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1318                    "squashed, skipping.\n",
1319                    inst->pcState(), inst->seqNum, tid);
1320        }
1321    }
1322}
1323
1324template <class Impl>
1325void
1326DefaultCommit<Impl>::skidInsert()
1327{
1328    DPRINTF(Commit, "Attempting to any instructions from rename into "
1329            "skidBuffer.\n");
1330
1331    for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1332        DynInstPtr inst = fromRename->insts[inst_num];
1333
1334        if (!inst->isSquashed()) {
1335            DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1336                    "skidBuffer.\n", inst->pcState(), inst->seqNum,
1337                    inst->threadNumber);
1338            skidBuffer.push(inst);
1339        } else {
1340            DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1341                    "squashed, skipping.\n",
1342                    inst->pcState(), inst->seqNum, inst->threadNumber);
1343        }
1344    }
1345}
1346
1347template <class Impl>
1348void
1349DefaultCommit<Impl>::markCompletedInsts()
1350{
1351    // Grab completed insts out of the IEW instruction queue, and mark
1352    // instructions completed within the ROB.
1353    for (int inst_num = 0;
1354         inst_num < fromIEW->size && fromIEW->insts[inst_num];
1355         ++inst_num)
1356    {
1357        if (!fromIEW->insts[inst_num]->isSquashed()) {
1358            DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1359                    "within ROB.\n",
1360                    fromIEW->insts[inst_num]->threadNumber,
1361                    fromIEW->insts[inst_num]->pcState(),
1362                    fromIEW->insts[inst_num]->seqNum);
1363
1364            // Mark the instruction as ready to commit.
1365            fromIEW->insts[inst_num]->setCanCommit();
1366        }
1367    }
1368}
1369
1370template <class Impl>
1371bool
1372DefaultCommit<Impl>::robDoneSquashing()
1373{
1374    list<ThreadID>::iterator threads = activeThreads->begin();
1375    list<ThreadID>::iterator end = activeThreads->end();
1376
1377    while (threads != end) {
1378        ThreadID tid = *threads++;
1379
1380        if (!rob->isDoneSquashing(tid))
1381            return false;
1382    }
1383
1384    return true;
1385}
1386
1387template <class Impl>
1388void
1389DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1390{
1391    ThreadID tid = inst->threadNumber;
1392
1393    if (!inst->isMicroop() || inst->isLastMicroop())
1394        instsCommitted[tid]++;
1395    opsCommitted[tid]++;
1396
1397    // To match the old model, don't count nops and instruction
1398    // prefetches towards the total commit count.
1399    if (!inst->isNop() && !inst->isInstPrefetch()) {
1400        cpu->instDone(tid, inst);
1401    }
1402
1403    //
1404    //  Control Instructions
1405    //
1406    if (inst->isControl())
1407        statComBranches[tid]++;
1408
1409    //
1410    //  Memory references
1411    //
1412    if (inst->isMemRef()) {
1413        statComRefs[tid]++;
1414
1415        if (inst->isLoad()) {
1416            statComLoads[tid]++;
1417        }
1418    }
1419
1420    if (inst->isMemBarrier()) {
1421        statComMembars[tid]++;
1422    }
1423
1424    // Integer Instruction
1425    if (inst->isInteger())
1426        statComInteger[tid]++;
1427
1428    // Floating Point Instruction
1429    if (inst->isFloating())
1430        statComFloating[tid]++;
1431
1432    // Function Calls
1433    if (inst->isCall())
1434        statComFunctionCalls[tid]++;
1435
1436}
1437
1438////////////////////////////////////////
1439//                                    //
1440//  SMT COMMIT POLICY MAINTAINED HERE //
1441//                                    //
1442////////////////////////////////////////
1443template <class Impl>
1444ThreadID
1445DefaultCommit<Impl>::getCommittingThread()
1446{
1447    if (numThreads > 1) {
1448        switch (commitPolicy) {
1449
1450          case Aggressive:
1451            //If Policy is Aggressive, commit will call
1452            //this function multiple times per
1453            //cycle
1454            return oldestReady();
1455
1456          case RoundRobin:
1457            return roundRobin();
1458
1459          case OldestReady:
1460            return oldestReady();
1461
1462          default:
1463            return InvalidThreadID;
1464        }
1465    } else {
1466        assert(!activeThreads->empty());
1467        ThreadID tid = activeThreads->front();
1468
1469        if (commitStatus[tid] == Running ||
1470            commitStatus[tid] == Idle ||
1471            commitStatus[tid] == FetchTrapPending) {
1472            return tid;
1473        } else {
1474            return InvalidThreadID;
1475        }
1476    }
1477}
1478
1479template<class Impl>
1480ThreadID
1481DefaultCommit<Impl>::roundRobin()
1482{
1483    list<ThreadID>::iterator pri_iter = priority_list.begin();
1484    list<ThreadID>::iterator end      = priority_list.end();
1485
1486    while (pri_iter != end) {
1487        ThreadID tid = *pri_iter;
1488
1489        if (commitStatus[tid] == Running ||
1490            commitStatus[tid] == Idle ||
1491            commitStatus[tid] == FetchTrapPending) {
1492
1493            if (rob->isHeadReady(tid)) {
1494                priority_list.erase(pri_iter);
1495                priority_list.push_back(tid);
1496
1497                return tid;
1498            }
1499        }
1500
1501        pri_iter++;
1502    }
1503
1504    return InvalidThreadID;
1505}
1506
1507template<class Impl>
1508ThreadID
1509DefaultCommit<Impl>::oldestReady()
1510{
1511    unsigned oldest = 0;
1512    bool first = true;
1513
1514    list<ThreadID>::iterator threads = activeThreads->begin();
1515    list<ThreadID>::iterator end = activeThreads->end();
1516
1517    while (threads != end) {
1518        ThreadID tid = *threads++;
1519
1520        if (!rob->isEmpty(tid) &&
1521            (commitStatus[tid] == Running ||
1522             commitStatus[tid] == Idle ||
1523             commitStatus[tid] == FetchTrapPending)) {
1524
1525            if (rob->isHeadReady(tid)) {
1526
1527                DynInstPtr head_inst = rob->readHeadInst(tid);
1528
1529                if (first) {
1530                    oldest = tid;
1531                    first = false;
1532                } else if (head_inst->seqNum < oldest) {
1533                    oldest = tid;
1534                }
1535            }
1536        }
1537    }
1538
1539    if (!first) {
1540        return oldest;
1541    } else {
1542        return InvalidThreadID;
1543    }
1544}
1545
1546#endif//__CPU_O3_COMMIT_IMPL_HH__
1547